Isolated Sigma-Delta Modulator AD7401 Data Sheet FEATURES GENERAL DESCRIPTION 20 MHz maximum external clock rate Second-order modulator 16 bits no missing codes ±2 LSB INL typical at 16 bits 3.5 μV/°C maximum offset drift On-board digital isolator On-board reference Low power operation: 20 mA maximum at 5.25 V −40°C to +105°C operating range 16-lead SOIC package Safety and regulatory approvals UL recognition 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 891 V peak The AD74011 is a second-order, sigma-delta (Σ-Δ) modulator that converts an analog input signal into a high speed, 1-bit data stream with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. The AD7401 operates from a 5 V power supply and accepts a differential input signal of ±200 mV (±320 mV full scale). The analog input is continuously sampled by the analog modulator, eliminating the need for external sampleand-hold circuitry. The input information is contained in the output stream as a density of ones with a data rate up to 20 MHz. The original information can be reconstructed with an appropriate digital filter. The serial input/output can use a 5 V or a 3 V supply (VDD2). The serial interface is digitally isolated. High speed CMOS, combined with monolithic air core transformer technology, means the on-chip isolation provides outstanding performance characteristics, superior to alternatives such as optocoupler devices. The device contains an on-chip reference. The AD7401 is offered in a 16-lead SOIC and has an operating temperature range of −40°C to +105°C. APPLICATIONS AC motor controls Data acquisition systems A/D + opto-isolator replacements An internal clock version, AD7400, is also available. 1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 AD7401 VIN+ T/H Σ-∆ ADC UPDATE ENCODE BUF REF WATCHDOG CONTROL LOGIC WATCHDOG DECODE DECODE MDAT UPDATE MCLKIN ENCODE GND2 GND1 05851-001 VIN– Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2006–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7401 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................9 Applications ....................................................................................... 1 Terminology .................................................................................... 12 General Description ......................................................................... 1 Theory of Operation ...................................................................... 13 Functional Block Diagram .............................................................. 1 Circuit Information .................................................................... 13 Revision History ............................................................................... 2 Analog Input ............................................................................... 13 Specifications..................................................................................... 3 Differential Inputs ...................................................................... 14 Timing Specifications .................................................................. 4 Digital Filter ................................................................................ 15 Insulation and Safety Related Specifications ............................ 5 Applications Information .............................................................. 17 Regulatory Information ............................................................... 5 Grounding and Layout .............................................................. 17 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics .............................................................................. 6 Evaluating the AD7401 Performance ...................................... 17 Absolute Maximum Ratings ............................................................ 7 Outline Dimensions ....................................................................... 18 ESD Caution .................................................................................. 7 Ordering Guide .......................................................................... 18 Insulation Lifetime ..................................................................... 17 Pin Configuration and Function Descriptions ............................. 8 REVISION HISTORY 12/15—Rev. D to Rev. E Changes to Ordering Guide .......................................................... 18 7/11—Rev. C to Rev. D Changes to Minimum External Air Gap (Clearance) Parameter, Table 3 and Minimum External Tracking (Creepage) Parameter, Table 3 ................................................................................................ 5 Changes to Figure 5; Pin 1 Description, Table 8; and Pin 7 Description, Table 8.......................................................................... 8 1/11—Rev. B to Rev. C Changes to Features Section............................................................ 1 Changes to Input-to-Output Momentary Withstand Voltage Parameter, Table 3, UL Column, Table 4, and Note 1, Table 4 .......... 5 Changes to Ordering Guide..................................................................... 18 9/07—Rev. A to Rev. B Updated VDE Certification Throughout ......................................1 Changes to Table 6.............................................................................7 12/06—Rev. 0 to Rev. A Changes to Features and General Description ..............................1 Changes to Table 1.............................................................................3 Changes to Table 2.............................................................................4 Changes to Table 6.............................................................................7 Changes to Table 8.............................................................................8 Changes to Circuit Information Section ..................................... 13 Changes to Figure 27...................................................................... 15 1/06—Revision 0: Initial Version Rev. E | Page 2 of 20 Data Sheet AD7401 SPECIFICATIONS VDD1 = 4.5 V to 5.25 V, VDD2 = 3 V to 5.5 V, VIN+ = −200 mV to +200 mV, and VIN− = 0 V (single-ended); TA = TMIN to TMAX, fMCLK = 16 MHz maximum, tested with Sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity 3 Differential Nonlinearity3 Offset Error3 Offset Drift vs. Temperature Offset Drift vs. VDD1 Gain Error3 Gain Error Drift vs. Temperature Gain Error Drift vs. VDD1 ANALOG INPUT Input Voltage Range Dynamic Input Current DC Leakage Current Input Capacitance DYNAMIC SPECIFICATIONS Signal-to-(Noise + Distortion) Ratio (SINAD)3 Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Effective Number of Bits (ENOB)3 Isolation Transient Immunity3 LOGIC INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Current, IIN Input Capacitance, CIN 5 Y Version 1, 2 Unit Test Conditions/Comments 16 ±15 ±25 ±55 ±0.9 Bits min LSB max LSB max LSB max LSB max ±0.6 ±50 3.5 1 120 ±1.6 ±2 ±1 23 110 mV max µV typ µV/°C max µV/°C typ µV/V typ mV max mV max mV typ µV/°C typ µV/V typ Filter output truncated to 16 bits −40°C to +85°C; ±2 LSB typical; fMCLK = 20 MHz maximum 4 >85°C to 105°C fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV Guaranteed no missed codes to 16 bits; fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV TA = 25°C −40°C to +105°C ±200 ±9 ±0.5 10 mV min/mV max µA max µA max pF typ 70 68 65 65 81 80 80 −92 −92 11.5 25 30 dB min dB min dB min dB min dB typ dB min dB min dB typ dB typ Bits kV/µs min kV/µs typ 0.8 × VDD2 0.2 × VDD2 ±0.5 10 V min V max µA max pF max Rev. E | Page 3 of 20 −40°C to +85°C >85°C to 105°C fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV −40°C to +105°C For specified performance; full range ±320 mV VIN+ = 400 mV, VIN− = 0 V VIN+ = 5 kHz, 400 mV p-p sine −40°C to +85°C; fMCLK = 9 MHz to 20 MHz4 −40°C to +85°C; fMCLK = 5 MHz to <9 MHz >85°C to 105°C fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV −40°C to +105°C; 82 dB typ fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV fMCLK = 20 MHz maximum4; VIN+ = −250 mV to +250 mV AD7401 Data Sheet Parameter LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL POWER REQUIREMENTS VDD1 VDD2 IDD16 IDD27 Y Version1, 2 Unit Test Conditions/Comments VDD2 − 0.1 0.4 V min V max IO = −200 μA IO = +200 μA 4.5/5.25 3/5.5 12 8 4 V min/V max V min/V max mA max mA max mA max VDD1 = 5.25 V VDD2 = 5.5 V VDD2 = 3.3 V 1 Temperature range is −40°C to +85°C. All voltages are relative to their respective ground. 3 See the Terminology section. 4 For fMCLK > 16 MHz to 20 MHz, mark space ratio is 48/52 to 52/48, VDD1 = VDD2 = 5 V ± 5%, and TA = −40°C to +85°C. 5 Sample tested during initial release to ensure compliance. 6 See Figure 15. 7 See Figure 17. 2 TIMING SPECIFICATIONS VDD1 = 4.5 V to 5.25 V, VDD2 = 3 V to 5.5 V, TA = TMAX to TMIN, unless otherwise noted.1 Table 2. Parameter fMCLKIN2, 3 t14 t24 t3 t4 Limit at TMIN, TMAX 20 5 25 15 0.4 × tMCLKIN 0.4 × tMCLKIN Unit MHz max MHz min ns max ns min ns min ns min Description Master clock input frequency Master clock input frequency Data access time after MCLK rising edge Data hold time after MCLK rising edge Master clock low time Master clock high time 1 Sample tested during initial release to ensure compliance Mark space ratio for clock input is 40/60 to 60/40 for fMCLKIN to 16 MHz and 48/52 to 52/48 for fMCLKIN > 16 MHz to 20 MHz. 3 VDD1 = VDD2 = 5 V ± 5% for fMCLKIN > 16 MHz to 20 MHz. 4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 2 200µA 1.6V CL 25pF 200µA 05851-002 TO OUTPUT PIN IOL IOH Figure 2. Load Circuit for Digital Output Timing Specifications t4 t1 t2 MDAT Figure 3. Data Timing Rev. E | Page 4 of 20 t3 05851-003 MCLKIN Data Sheet AD7401 INSULATION AND SAFETY RELATED SPECIFICATIONS Table 3. Parameter Input-to-Output Momentary Withstand Voltage Minimum External Air Gap (Clearance) Symbol VISO L(I01) Value 5000 min 8.1 min Unit V rms mm Minimum External Tracking (Creepage) L(I02) 7.46 min mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min >175 IIIa mm V Conditions 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table I) REGULATORY INFORMATION Table 4. UL 1 Recognized under 1577 Component Recognition Program1 5000 V rms Isolation Voltage File E214100 1 2 CSA Approved under CSA Component Acceptance Notice #5A Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 630 V rms maximum working voltage File 205078 VDE 2 Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Reinforced insulation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12, 891V peak File 2471900-4880-0001 In accordance with UL 1577, each AD7401 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 µA). In accordance with DIN V VDE V 0884-10, each AD7401 is proof tested by applying an insulation test voltage ≥ 1671 V peak for 1 second (partial discharge detection limit = 5 pC). Rev. E | Page 5 of 20 AD7401 Data Sheet DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. Table 5. Description INSTALLATION CLASSIFICATION PER DIN VDE 0110 For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 450 V rms For Rated Mains Voltage ≤ 600 V rms CLIMATIC CLASSIFICATION POLLUTION DEGREE (DIN VDE 0110, TABLE I) MAXIMUM WORKING INSULATION VOLTAGE INPUT-TO-OUTPUT TEST VOLTAGE, METHOD B1 VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC INPUT-TO-OUTPUT TEST VOLTAGE, METHOD A After Environmental Test Subgroup 1 VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC After Input and/or Safety Test Subgroup 2/3 VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 sec) SAFETY LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, ALSO SEE Figure 4) Case Temperature Side 1 Current Side 2 Current INSULATION RESISTANCE AT TS, VIO = 500 V 350 250 SIDE #2 200 150 SIDE #1 100 50 0 0 50 100 150 CASE TEMPERATURE (°C) 200 05851-004 SAFETY-LIMITING CURRENT (mA) 300 Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. E | Page 6 of 20 Symbol Characteristic Unit VIORM I–IV I–II I–II 40/105/21 2 891 V peak 1671 V peak 1426 V peak 1069 V peak VTR 6000 V peak TS IS1 IS2 RS 150 265 335 >109 °C mA mA Ω VPR VPR Data Sheet AD7401 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. All voltages are relative to their respective ground. Table 6. Parameter VDD1 to GND1 VDD2 to GND2 Analog Input Voltage to GND1 Digital Input Voltage to GND2 Output Voltage to GND2 Input Current to Any Pin Except Supplies 1 Operating Temperature Range Storage Temperature Range Junction Temperature SOIC Package θJA Thermal Impedance θJC Thermal Impedance Resistance (Input to Output), RI-O Capacitance (Input to Output), CI-O 2 Lead-Free Temperature, Soldering Reflow ESD 1 2 Rating −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to VDD1 + 0.3 V −0.3 V to VDD1 + 0.5 V −0.3 V to VDD2 + 0.3 V ±10 mA −40°C to +105°C −65°C to +150°C 150°C 89.2°C/W 55.6°C/W 1012 Ω 1.7 pF typ Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 7. Maximum Continuous Working Voltage1 Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform DC Voltage 1 Max 565 Unit VPK Constraint 50-year minimum lifetime 891 VPK 891 V Maximum CSA/VDE approved working voltage Maximum CSA/VDE approved working voltage Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. ESD CAUTION 260 (+0)°C 1.5 kV Transient currents of up to 100 mA do not cause SCR to latch-up. f = 1 MHz. Rev. E | Page 7 of 20 AD7401 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD1 1 16 GND2 VIN+ 2 15 NC VIN– 3 14 VDD2 NC 4 AD7401 NC 5 NC 6 11 MDAT VDD1 /NC 7 10 NC GND1 8 9 GND2 NC = NO CONNECT 05851-005 13 MCLKIN TOP VIEW (Not to Scale) 12 NC Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2 3 4 to 6, 10, 12, 15 7 Mnemonic VDD1 VIN+ VIN− NC Description Supply Voltage. 4.5 V to 5.25 V. This is the supply voltage for the isolated side of the AD7401 and is relative to GND1. Positive Analog Input. Specified range of ±200 mV. Negative Analog Input. Normally connected to GND1. No Connect. VDD1/NC 8 9, 16 11 GND1 GND2 MDAT 13 14 MCLKIN VDD2 Supply Voltage. 4.5 V to 5.25 V. This is the supply voltage for the isolated side of the AD7401 and is relative to GND1. No Connect (NC). If desired, Pin 7 may be allowed to float. It should not be tied to ground. The AD7401 will operate normally provided that the supply voltage is applied to Pin 1. Ground 1. This is the ground reference point for all circuitry on the isolated side. Ground 2. This is the ground reference point for all circuitry on the nonisolated side. Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream. The bits are clocked out on the rising edge of the MCLKIN input and valid on the following MCLKIN rising edge. Master Clock Logic Input. 20 MHz maximum. The bit stream from the modulator is valid on the rising edge of MCLKIN. Supply Voltage. 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2. Rev. E | Page 8 of 20 Data Sheet AD7401 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, using a 25 kHz brick wall filter, unless otherwise noted. 100 –90 VDD1 = VDD2 = 5V 90 –85 80 MCLKIN = 10MHz MCLKIN = 16MHz –80 60 SINAD (dB) PSRR (dB) 70 50 MCLKIN = 5MHz MCLKIN = 10MHz 40 MCLKIN = 16MHz –75 –70 –65 30 –60 600 700 800 900 1000 SUPPLY RIPPLE FREQUENCY (kHz) –50 0.17 0.18 0.19 0.20 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.30 0.31 0.32 0.33 ± INPUT AMPLITUDE (V) Figure 6. PSRR vs. Supply Ripple Frequency Without Supply Decoupling 05851-028 –55 05851-006 20 200mV p-p SINE WAVE ON V DD1 NO DECOUPLING 10 V = V = 5V DD1 DD2 1MHz CUTOFF FILTER 0 0 100 200 300 400 500 Figure 9. SINAD vs. VIN –90 0.4 =V = 5V VDD1 V= V DD2 = 5V DD1 DD2 0.3 –85 MCLKIN = 16MHz 0.2 DNL ERROR (LSB) –75 MCLKIN = 10MHz –70 –65 MCLKIN = 5MHz –60 0.1 0 –0.1 –0.2 0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k INPUT FREQUENCY (Hz) 05851-027 –50 –0.4 V + = –200mV TO +200mV IN VIN– = 0V –0.5 0 10k 20k 30k Figure 7. SINAD vs. Analog Input Frequency 50k 60k Figure 10. Typical DNL (±200 mV Range) 20 0.8 4096 POINT FFT fIN = 5kHz SINAD = 81.984dB THD = –96.311dB DECIMATION BY 256 0 –20 VIN+ = –200mV TO +200mV VIN– = 0V 0.6 INL ERROR (LSB) –40 –60 –80 –100 –120 –140 0.4 0.2 0 –0.2 –160 –180 0 5 10 15 20 FREQUENCY (kHz) 25 30 05851-042 (dB) 40k CODE 05851-043 –0.3 –55 –0.4 0 10k 20k 30k 40k 50k CODE Figure 11. Typical INL (±200 mV Range) Figure 8. Typical FFT (±200 mV Range) Rev. E | Page 9 of 20 60k 05851-044 SINAD (dB) –80 AD7401 Data Sheet 0.0105 250 150 0.0100 0.0095 IDD1 (A) 0 MCLKIN = 16MHz TA = –40°C 0.0085 –150 –200 15 25 35 45 55 65 75 85 95 105 TEMPERATURE (°C) MCLKIN = 10MHz TA = +105°C MCLKIN = 10MHz TA = +85°C 0.0070 VDD1 = VDD2 = 5.25V MCLKIN = 5MHz VDD1 = VDD2 = 5V MCLKIN = 10MHz 5 MCLKIN = 16MHz TA = +105°C 0.0080 0.0075 VDD1 = VDD2 = 5.25V MCLKIN = 10MHz VDD1 = VDD2 = 5.25V MCLKIN = 16MHz –250 –45 –35 –25 –15 –5 MCLKIN = 16MHz TA = +85°C MCLKIN = 10MHz TA = –40°C –50 –100 0.0065 MCLKIN = 5MHz TA = +85°C MCLKIN = 5MHz TA = –40°C MCLKIN = 5MHz TA = +105°C 0.0060 –0.33 –0.28 –0.23 –0.18 –0.13 –0.08 –0.03 0.03 0.08 0.13 0.18 0.23 0.28 0.33 VIN DC INPUT VOLTAGE (V) Figure 15. IDD1 vs. VIN at Various Temperatures Figure 12. Offset Drift vs. Temperature for Various Supply Voltages 0.0070 200.5 200.4 VDD1 = VDD2 = 4.5V MCLKIN = 16MHz VDD1 = VDD2 = 4.5V MCLKIN = 10MHz 0.0065 200.3 VDD1 = VDD2 = 4.5V MCLKIN = 5MHz VDD1 = VDD2 = 5V MCLKIN = 5MHz 0.0060 200.2 VDD1 = VDD2 = 5V MCLKIN = 16MHz VDD1 = VDD2 = 5.25V MCLKIN = 10MHz 0.0055 200.1 VDD1 = VDD2 = 5.25V MCLKIN = 16MHz VDD1 = VDD2 = 5.25V MCLKIN = 5MHz 0.0050 200.0 VDD1 = VDD2 = 5V MCLKIN = 10MHz IDD2 (A) GAIN (mV) VDD1 = VDD2 = 5V 0.0090 50 05851-029 OFFSET (µV) 100 VDD1 = VDD2 = 4.5V MCLKIN = 10MHz VDD1 = VDD2 = 5V MCLKIN = 5MHz 05851-034 200 VDD1 = VDD2 = 4.5V MCLKIN = 16MHz VDD1 = VDD2 = 4.5V MCLKIN = 5MHz VDD1 = VDD2 = 5V MCLKIN = 16MHz VDD1 = VDD2 = 5V TA = 25°C MCLKIN = 16MHz MCLKIN = 10MHz 0.0045 199.9 0.0040 199.8 0.0035 199.7 0.0030 199.6 0.0025 MCLKIN = 5MHz TEMPERATURE (°C) 0.0020 –0.225 –0.125 –0.025 0.075 0.175 0.275 –0.325 –0.275 –0.175 –0.075 0.025 0.125 0.225 0.325 VIN DC INPUT VOLTAGE (V) Figure 13. Gain Error Drift vs. Temperature for Various Supply Voltages Figure 16. IDD2 vs. VIN DC Input Voltage 0.0070 0.0105 VDD1 = VDD2 = 5V TA = 25°C 0.0100 VDD1 = VDD2 = 5V 0.0065 0.0060 0.0095 MCLKIN = 16MHz 0.0055 IDD2 (A) 0.0050 MCLKIN = 10MHz MCLKIN = 5MHz MCLKIN = 10MHz TA = –40°C 0.0025 0.0020 0.0065 VIN DC INPUT VOLTAGE (V) MCLKIN = 16MHz TA = +85°C MCLKIN = 10MHz TA = +105°C MCLKIN = 10MHz TA = +85°C MCLKIN = 5MHz TA = –40°C 0.0030 0.0070 –0.33 –0.28 –0.23 –0.18 –0.13 –0.08 –0.03 0.03 0.08 0.13 0.18 0.23 0.28 0.33 MCLKIN = 16MHz TA = +105°C 0.0045 0.0035 0.0075 MCLKIN = 16MHz TA = –40°C 0.0040 0.0080 05851-033 IDD1 (A) 0.0090 0.0085 05851-037 15 25 35 45 55 65 75 85 95 105 MCLKIN = 5MHz TA = +85°C MCLKIN = 5MHz TA = +105°C –0.225 –0.125 –0.025 0.075 0.175 0.275 –0.325 –0.275 –0.175 –0.075 0.025 0.125 0.225 0.325 VIN DC INPUT VOLTAGE (V) Figure 17. IDD2 vs. VIN at Various Temperatures Figure 14. IDD1 vs. VIN DC Input Voltage Rev. E | Page 10 of 20 05851-038 5 05851-036 199.5 –45 –35 –25 –15 –5 Data Sheet 8 AD7401 1.0 VDD1 = VDD2 = 4.5V TO 5.25V VDD1 = VDD2 = 5V 50kHz BRICK WALL FILTER MCLKIN = 16MHz 6 0.8 MCLKIN = 10MHz 4 NOISE (mV) IIN (µA) 2 MCLKIN = 5MHz 0 –2 0.6 0.4 MCLKIN = 5MHz –4 0.2 =V =5V VDD1 = VVDD2 = 5V DD1 DD2 –20 –40 MCLKIN = 5MHz –60 MCLKIN = 10MHz –80 –120 0.1 1 10 100 RIPPLE FREQUENCY (kHz) 1000 05851-031 MCLKIN = 16MHz –100 Figure 19. CMRR vs. Common-Mode Ripple Frequency Rev. E | Page 11 of 20 0.30 05851-032 0.25 0.20 0.15 0.05 0 –0.05 –0.10 –0.15 –0.20 –0.25 VIN DC INPUT (V) Figure 20. RMS Noise Voltage vs. VIN DC Input Figure 18. IIN vs. VIN− DC Input 0 –0.30 0.35 VIN– DC INPUT (V) 0 05851-030 0.30 0.25 0.20 0.15 0.10 0 0.05 –0.05 –0.10 –0.15 –0.20 –0.25 –0.30 –0.35 –8 CMRR (dB) MCLKIN = 16MHz MCLKIN = 10MHz 0.10 –6 AD7401 Data Sheet TERMINOLOGY Differential Nonlinearity Differential nonlinearity is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity Integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are specified negative full-scale, −200 mV (VIN+ − VIN−), Code 12,288 for the 16-bit level, and specified positive full-scale, +200 mV (VIN+ − VIN−), Code 53,248 for the 16-bit level. Offset Error Offset error is the deviation of the midscale code (Code 32,768 for the 16-bit level) from the ideal VIN+ − VIN− (that is, 0 V). Gain Error Gain error includes both positive full-scale gain error and negative full-scale gain error. Positive full-scale gain error is the deviation of the specified positive full-scale code (53,248 for the 16-bit level) from the ideal VIN+ − VIN− (+200 mV) after the offset error is adjusted out. Negative full-scale gain error is the deviation of the specified negative full-scale code (12,288 for the 16-bit level) from the ideal VIN+ − VIN− (−200 mV) after the offset error is adjusted out. Gain error includes reference error. Signal-to-(Noise + Distortion) Ratio This ratio is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Therefore, for a 12-bit converter, this is 74 dB. Effective Number of Bits (ENOB) The ENOB is defined by ENOB = (SINAD − 1.76)/6.02 Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7401, it is defined as THD (dB) 20 log V2 2 V3 2 V4 2 V5 2 V6 2 V1 where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at ±200 mV frequency, f, to the power of a 200 mV p-p sine wave applied to the common-mode voltage of VIN+ and VIN− of frequency fS, expressed as CMRR (dB) = 10 log(Pf/PfS) where: Pf is the power at frequency f in the ADC output. PfS is the power at frequency fS in the ADC output. Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not converter linearity. PSRR is the maximum change in the specified full-scale (±200 mV) transition point due to a change in power supply voltage from the nominal value (see Figure 6). Isolation Transient Immunity The isolation transient immunity specifies the rate of rise/fall of a transient pulse applied across the isolation boundary beyond which clock or data is corrupted. (It was tested using a transient pulse frequency of 100 kHz.) Rev. E | Page 12 of 20 Data Sheet AD7401 THEORY OF OPERATION A differential input of 320 mV results in a stream of, ideally, all 1s. This is the absolute full-scale range of the AD7401, while 200 mV is the specified full-scale range, as shown in Table 9. CIRCUIT INFORMATION The AD7401 isolated Σ-Δ modulator converts an analog input signal into a high speed (20 MHz maximum), single-bit data stream; the time average of the modulator single-bit data is directly proportional to the input signal. Figure 23 shows a typical application circuit where the AD7401 is used to provide isolation between the analog input, a current sensing resistor, and the digital output, which is then processed by a digital filter to provide an N-bit word. Table 9. Analog Input Range Analog Input Full-Scale Range Positive Full-Scale Positive Specified Input Range Zero Negative Specified Input Range Negative Full-Scale ANALOG INPUT The differential analog input of the AD7401 is implemented with a switched capacitor circuit. This circuit implements a second-order modulator stage that digitizes the input signal into a 1-bit output stream. The sample clock (MCLKIN) provides the clock signal for the conversion process as well as the output data-framing clock. This clock source is external on the AD7401. The analog input signal is continuously sampled by the modulator and compared to an internal voltage reference. A digital stream that accurately represents the analog input over time appears at the output of the converter (see Figure 21). Voltage Input +640 mV +320 mV +200 mV 0 mV −200 mV −320 mV To reconstruct the original information, this output needs to be digitally filtered and decimated. A Sinc3 filter is recommended because this is one order higher than that of the AD7401 modulator. If a 256 decimation rate is used, the resulting 16-bit word rate is 62.5 kHz, assuming a 16 MHz external clock frequency. Figure 22 shows the transfer function of the AD7401 relative to the 16-bit output. 65535 MODULATOR OUTPUT +FS ANALOG INPUT SPECIFIED RANGE ADC CODE Figure 21. Analog Input vs. Modulator Output 12288 A differential signal of 0 V results (ideally) in a stream of 1s and 0s at the MDAT output pin. This output is high 50% of the time and low 50% of the time. A differential input of 200 mV produces a stream of 1s and 0s that are high 81.25% of the time. A differential input of −200 mV produces a stream of 1s and 0s that are high 18.75% of the time. 0 –320mV –200mV +200mV +320mV ANALOG INPUT 05851-021 –FS ANALOG INPUT ANALOG INPUT 05851-020 53248 Figure 22. Filtered and Decimated 16-Bit Transfer Characteristic ISOLATED 5V + INPUT CURRENT NONISOLATED 5V/3V VDD1 AD7401 VIN+ Σ-∆ MOD/ ENCODER VDD2 VDD SINC3 FILTER DECODER VIN– MDAT MDAT MCLKIN MCLK CS SCLK SDAT RSHUNT GND1 ENCODER GND2 GND 05851-019 DECODER Figure 23. Typical Application Circuit Rev. E | Page 13 of 20 AD7401 Data Sheet DIFFERENTIAL INPUTS The analog input to the modulator is a switched capacitor design. The analog signal is converted into charge by highly linear sampling capacitors. A simplified equivalent circuit diagram of the analog input is shown in Figure 24. A signal source driving the analog input must be able to provide the charge onto the sampling capacitors every half MCLKIN cycle and settle to the required accuracy within the next half cycle. φA MCLKIN 2pF φA 2pF The recommended circuit configuration for driving the differential inputs to achieve best performance is shown in Figure 25. A capacitor between the two input pins sources or sinks charge to allow most of the charge that is needed by one input to be effectively supplied by the other input. The series resistor again isolates any operational amplifier from the current spikes created during the sampling process. Recommended values for the resistors and capacitor are 22 Ω and 47 pF, respectively. φB φA φB φA φB Figure 24. Analog Input Equivalent Circuit Because the AD7401 samples the differential voltage across its analog inputs, low noise performance is attained with an input circuit that provides low common-mode noise at each input. The amplifiers used to drive the analog inputs play a critical role in attaining the high performance available from the AD7401. Rev. E | Page 14 of 20 VIN+ R C VIN– R AD7401 05851-023 VIN– 1kΩ φB 05851-022 VIN+ 1kΩ When a capacitive load is switched onto the output of an operational amplifier, the amplitude momentarily drops. The operational amplifier tries to correct the situation and, in the process, hits its slew rate limit. This nonlinear response, which can cause excessive ringing, can lead to distortion. To remedy the situation, a low-pass RC filter can be connected between the amplifier and the input to the AD7401. The external capacitor at each input aids in supplying the current spikes created during the sampling process, and the resistor isolates the operational amplifier from the transient nature of the load. Figure 25. Differential Input RC Network Data Sheet AD7401 DIGITAL FILTER A Sinc3 filter is recommended for use with the AD7401. This filter can be implemented on an FPGA or possibly a DSP. The following Verilog code provides an example of a Sinc3 filter implementation on a Xylinx® Spartan-II 2.5 V FPGA. This code can possibly be compiled for another FPGA, such as an Altera® device. Note that the data is read on the negative clock edge in this case, although it can be read on the positive edge if preferred. Figure 29 shows the effect of using different decimation rates with various filter types. /*`Data is read on negative clk edge*/ module DEC256SINC24B(mdata1, mclk1, reset, DATA); input mclk1; input reset; input mdata1; filtered*/ /*used to clk filter*/ /*used to reset filter*/ /*ip data to be output [15:0] DATA; /*filtered op*/ integer location; integer info_file; ACC2+ ACC1+ IP_DATA1 Z Z + ACC3+ Z + + 05851-024 MCLKIN Figure 26. Accumulator Z = one sample delay MCLKIN = modulators conversion bit rate */ always @ (posedge mclk1 or posedge reset) if (reset) begin /*initialize acc registers on reset*/ acc1 <= 0; acc2 <= 0; acc3 <= 0; end else begin /*perform accumulation process*/ acc1 <= acc1 + ip_data1; acc2 <= acc2 + acc1; acc3 <= acc3 + acc2; end reg [23:0] ip_data1; reg [23:0] acc1; reg [23:0] acc2; reg [23:0] acc3; reg [23:0] acc3_d1; reg [23:0] acc3_d2; reg [23:0] diff1; reg [23:0] diff2; always @ (word_count) word_clk <= word_count[7]; reg [23:0] diff3; /*DIFFERENTIATOR (including decimation stage) reg [23:0] diff1_d; reg [23:0] diff2_d; Perform the differentiation stage (FIR) at a lower speed. reg [15:0] DATA; always @ (negedge mclk1 or posedge reset) if (reset) word_count <= 0; else word_count <= word_count + 1; + ACC3 DIFF1 + – word_count; Z–1 reg word_clk; reg init; DIFF2 Z–1 WORD_CLK Figure 27. Differentiator /*Perform the Sinc ACTION*/ always @ (mdata1) if(mdata1==0) ip_data1 <= 0; to a -1 for 2's comp */ else ip_data1 <= 1; Z = one sample delay WORD_CLK = output word rate */ /* change from a 0 /*ACCUMULATOR (INTEGRATOR) Perform the accumulation (IIR) at the speed of the modulator. Rev. E | Page 15 of 20 + – DIFF3 – Z–1 05851-025 reg [7:0] /*DECIMATION STAGE (MCLKIN/ WORD_CLK) */ AD7401 Data Sheet always @ (posedge word_clk or posedge reset) if(reset) begin acc3_d2 <= 0; diff1_d <= 0; diff2_d <= 0; diff1 <= 0; diff2 <= 0; diff3 <= 0; end DATA[9] DATA[8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] <= <= <= <= <= <= <= <= <= <= diff3[17]; diff3[16]; diff3[15]; diff3[14]; diff3[13]; diff3[12]; diff3[11]; diff3[10]; diff3[9]; diff3[8]; end endmodule else 90 SINC3 begin diff1 <= acc3 - acc3_d2; diff2 <= diff1 - diff1_d; diff3 <= diff2 - diff2_d; acc3_d2 <= acc3; diff1_d <= diff1; diff2_d <= diff2; end 80 70 SINC2 SNR (dB) 60 /* Clock the Sinc output into an output register 50 40 SINC1 30 20 WORD_CLK 10 0 1 Figure 28. Clocking Sinc Output into an Output Register 10 100 1k DECIMATION RATE WORD_CLK = output word rate */ always @ (posedge word_clk) begin DATA[15] DATA[14] DATA[13] DATA[12] DATA[11] DATA[10] <= <= <= <= <= <= diff3[23]; diff3[22]; diff3[21]; diff3[20]; diff3[19]; diff3[18]; 05851-035 DATA 05851-026 DIFF3 Figure 29. SNR vs. Decimation Rate for Different Filter Types Figure 29 shows a plot of SNR performance vs. decimation rate with different filter types. Note that, for a given bandwidth requirement, a higher MCLKIN frequency can allow higher decimation rates to be used, resulting in higher SNR performance. Rev. E | Page 16 of 20 Data Sheet AD7401 APPLICATIONS INFORMATION GROUNDING AND LAYOUT Supply decoupling with a value of 100 nF is strongly recommended on both VDD1 and VDD2. Decoupling on one or both VDD1 pins does not affect performance significantly. In applications involving high common-mode transients, care must be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout must be designed so any coupling that occurs equally affects all pins on a given component side. Failure to ensure this may cause voltage differentials between pins to exceed the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. Any decoupling used must be placed as close to the supply pins as possible. Series resistance in the analog inputs must be minimized to avoid any distortion effects, especially at high temperatures. If possible, equalize the source impedance on each analog input to minimize offset. Beware of mismatch and thermocouple effects on the analog input PCB tracks to reduce offset drift. These tests subject populations of devices to continuous cross isolation voltages. To accelerate the occurrence of failures, the selected test voltages are values exceeding those of normal use. The time to failure values of these units are recorded and used to calculate acceleration factors. These factors are then used to calculate the time to failure under normal operating conditions. The values shown in Table 7 are the lesser of the following two values: • • The value that ensures at least a 50-year lifetime of continuous use The maximum CSA/VDE approved working voltage It should also be noted that the lifetime of the AD7401 varies according to the waveform type imposed across the isolation barrier. The iCoupler insulation structure is stressed differently depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 30, Figure 31, and Figure 32 illustrate the different isolation voltage waveforms. EVALUATING THE AD7401 PERFORMANCE A simple standalone AD7401 evaluation board is available with split ground planes and a board split beneath the AD7401 package to ensure isolation. This board allows access to each pin on the device for evaluation purposes. External supplies and all other circuitry (such as a digital filter) must be provided by the user. 05851-039 RATED PEAK VOLTAGE 0V Figure 30. Bipolar AC Waveform RATED PEAK VOLTAGE 0V Figure 31. Unipolar AC Waveform RATED PEAK VOLTAGE 05851-041 All insulation structures, subjected to sufficient time and/or voltage, are vulnerable to breakdown. In addition to the testing performed by the regulatory agencies, Analog Devices has carried out an extensive set of evaluations to determine the lifetime of the insulation structure within the AD7401. 05851-040 INSULATION LIFETIME 0V Figure 32. DC Waveform Rev. E | Page 17 of 20 AD7401 Data Sheet OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 45° 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 8° 0° 0.33 (0.0130) 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 03-27-2007-B 1 Figure 33. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model1 AD7401YRWZ AD7401YRWZ-REEL AD7401YRWZ-REEL7 EVAL-AD7401EDZ EVAL-CED1Z 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 16-Lead Standard Small Outline Package [SOIC_W] 16-Lead Standard Small Outline Package [SOIC_W] 16-Lead Standard Small Outline Package [SOIC_W] Evaluation Board Development Board Z = RoHS Compliant Part. Rev. E | Page 18 of 20 Package Option RW-16 RW-16 RW-16 Data Sheet AD7401 NOTES Rev. E | Page 19 of 20 AD7401 Data Sheet NOTES ©2006–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05851-0-12/15(E) Rev. E | Page 20 of 20