18-Bit, 5 MSPS PulSAR Differential ADC AD7960 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS REFIN VIO EN0 EN1 ÷2 CLOCK LOGIC EN2 EN3 IN+ CAP DAC IN– CNV+, CNV– D+, D– SERIAL LVDS SAR AD7960 DCO+, DCO– CLK+, CLK– GND Figure 1. GENERAL DESCRIPTION The AD7960 is an 18-bit, 5 MSPS, charge redistribution successive approximation (SAR), analog-to-digital converter (ADC). The SAR architecture allows unmatched performance both in noise and in linearity. The AD7960 contains a low power, high speed, 18-bit sampling ADC, an internal conversion clock, and an internal reference buffer. On the CNV± edge, the AD7960 samples the voltage difference between the IN+ and IN− pins. The voltages on these pins swing in opposite phase between 0 V and 4.096 V and between 0 V and 5 V. The reference voltage is applied to the part externally. All conversion results are available on a single LVDS self clocked or echoed clock serial interface. The AD7960 is available in a 32-lead LFCSP (QFN) with operation specified from −40°C to +85°C. Table 1. Fast PulSAR® ADC Selection Digital imaging systems Digital X-rays Computed tomography IR cameras MRI gradient control High speed data acquisition Spectroscopy Test equipment Input Type PseudoDifferential, 16-Bit True Bipolar, 16-Bit Differential, 1 16-Bit Differential,1 18-Bit 1 Rev. C VDD1 VDD2 REF VCM 09659-001 Throughput: 5 MSPS 18-bit resolution with no missing codes Excellent ac and dc performance Dynamic range: 100 dB SNR: 99 dB THD: −117 dB INL: ±0.8 LSB (typical), ±2 LSB (maximum) DNL: ±0.5 LSB (typical), ±0.99 LSB (maximum) True differential analog input voltage range: ±4.096 V or ±5 V Low power dissipation 46.5 mW at 5 MSPS with external reference buffer (echoed clock mode) 64.5 mW at 5 MSPS with internal reference buffer (echoed clock mode) 39 mW at 5 MSPS with external reference buffer (self clocked mode, CNV± in CMOS mode) SAR architecture No latency/pipeline delay External reference options: 2.048 V buffered to 4.096 V (internal reference buffer), 4.096 V, and 5 V Serial LVDS interface Self clocked mode Echoed clock mode LVDS or CMOS option for conversion control (CNV± signal) Operating temperature range of −40°C to +85°C 32-lead, 5 mm × 5 mm LFCSP (QFN) 1 MSPS to <2 MSPS AD7653 AD7667 AD7980 AD7983 AD7671 2 MSPS to 3 MSPS AD7985 5 MSPS to 6 MSPS AD7677 AD7623 AD7643 AD7982 AD7984 AD7621 AD7622 AD7641 AD7986 AD7625 AD7961 AD7960 10 MSPS AD7626 Antiphase. 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Technical Support www.analog.com AD7960 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Information.................................................................... 14 Applications ....................................................................................... 1 Converter Information .............................................................. 14 Functional Block Diagram .............................................................. 1 Transfer Function ....................................................................... 15 General Description ......................................................................... 1 Analog Inputs ............................................................................. 15 Revision History ............................................................................... 2 Typical Applications ................................................................... 16 Specifications..................................................................................... 3 Voltage Reference Options ........................................................ 17 Timing Specifications .................................................................. 5 Power Supply............................................................................... 18 Absolute Maximum Ratings............................................................ 7 Digital Interface .............................................................................. 19 Thermal Resistance ...................................................................... 7 Conversion Control ................................................................... 19 ESD Caution .................................................................................. 7 Applications Information .............................................................. 22 Pin Configuration and Function Descriptions ............................. 8 Layout .......................................................................................... 22 Typical Performance Characteristics ............................................. 9 Evaluating AD7960 Performance............................................. 22 Terminology .................................................................................... 13 Outline Dimensions ....................................................................... 23 Theory of Operation ...................................................................... 14 Ordering Guide .......................................................................... 23 REVISION HISTORY 3/14—Rev. B to Rev. C Changes to Table 4 ............................................................................ 7 Deleted Table 6; Renumbered Sequentially .................................. 7 2/14—Rev. A to Rev. B Changes to Table 4 ............................................................................ 7 Changes to Figure 19 ...................................................................... 11 11/13—Rev. 0 to Rev. A Change to Table 1 ............................................................................. 1 Changes to Table 2 ............................................................................ 5 Change to Table 3 ............................................................................. 5 Changes to Table 4 ............................................................................ 7 Added Table 6; Renumbered Sequentially .................................... 7 Change to Figure 4 ........................................................................... 8 Changes to Figure 32 ...................................................................... 16 Change to Voltage Reference Options Section ........................... 17 8/13—Revision 0: Initial Version Rev. C | Page 2 of 24 Data Sheet AD7960 SPECIFICATIONS VDD1 = 5 V; VDD2 = 1.8 V; VIO = 1.8 V; REF = 5 V or 4.096 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Common-Mode Input Range 1 CMRR Input Leakage Current THROUGHPUT Complete Cycle Throughput Rate DC ACCURACY No Missing Codes Integral Linearity Error Differential Linearity Error Transition Noise Zero Error Zero Error Drift1 Gain Error Gain Error Drift1 Power Supply Sensitivity 2 AC ACCURACY fIN = 1 kHz, −0.5 dBFS, VREF = 5 V Dynamic Range Signal-to-Noise Ratio Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-Noise-and-Distortion Ratio fIN = 1 kHz, −0.5 dBFS, VREF = 4.096 V Dynamic Range Signal-to-Noise Ratio Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-Noise-and-Distortion Ratio −3 dB Input Bandwidth 3 Oversampled Dynamic Range 4 Aperture Delay 5 Aperture Jitter5 REFERENCE BUFFER REFIN Input Voltage Range1 REF Output Voltage Range Line Regulation Test Conditions/Comments Min 18 VIN+ − VIN− VIN+, VIN− to GND −VREF −0.1 VREF/2 − 0.05 fIN = 500 kHz Acquisition phase Typ VREF/2 70 60 200 0 18 −2 −0.99 −6 −0.25 −30 −0.5 VDD1 = 5 V ± 5% VDD2 = 1.8 V ± 5% 98 97 V V V dB nA 5 ±0.8 ±0.5 1.1 ±0.01 ±5 ±0.05 ±1 ±2 +2 +0.99 +6 +0.25 +30 +0.5 ns MSPS Bits LSB LSB LSB LSB ppm/°C LSB ppm/°C LSB LSB 94.5 98.5 97 115 −113 96.5 28 120 1.6 1 dB dB dB dB dB MHz dB ns ps 2.042 4.086 2.048 4.096 EN2 = 0 OSR = 256, REF = 5 V 2.054 4.106 ±20 −25 Rev. C | Page 3 of 24 +VREF VREF + 0.1 VREF/2 + 0.05 dB dB dB dB dB 97 95 Gain Drift1 Unit Bits 100 99 119 −117 98.5 96.5 REF at 25°C, EN3 to EN0 = XX01 or XX10 VDD1 = 5 V ± 5%, VDD2 = 1.8 V ± 5% Max ±4 V V µV +25 ppm/°C AD7960 Parameter EXTERNAL REFERENCE Voltage Range Current Drain VCM PIN VCM Output VCM Error Output Impedance LVDS I/O (ANSI-644) Data Format Differential Output Voltage, VOD Common-Mode Output Voltage, VOCM Differential Input Voltage, VID Common-Mode Input Voltage, VICM POWER SUPPLIES Specified Performance VDD1 VDD2 VIO Operating Currents 8 Static—Not Converting, Internal Reference Buffer Disabled VDD1 VDD2 VIO Static—Not Converting, Internal Reference Buffer Enabled VDD1 VDD2 VIO Converting: Internal Reference Buffer Disabled VDD1 VDD2 VIO Converting: Internal Reference Buffer Enabled VDD1 VDD2 VIO Converting: Internal Reference Buffer Disabled VDD1 VDD2 VIO Snooze Mode VDD1 VDD2 VIO Data Sheet Test Conditions/Comments Min REFIN pin, EN1 to EN0 = 01 REF pin, EN1 to EN0 = 10 6 REF pin, EN1 to EN0 = 016 5 MSPS, REF = 4.096 V 5 MSPS, REF = 5 V Typ 2.048 4.096 5 1.05 1.36 Max Unit 1.11 1.43 V V V mA mA REF/2 −0.01 +0.01 5.1 RL = 100 Ω RL = 100 Ω 245 980 7 100 800 4.75 1.71 1.71 Serial LVDS twos complement 290 454 1130 1375 650 1575 V kΩ mV mV mV mV 5 1.8 1.8 5.25 1.89 1.89 V V V 8 8 5 40 70 5.3 µA µA mA 2.6 9 4.4 2.9 72 5.3 mA µA mA 2 11.4 9 2.2 13.5 10.3 mA mA mA 5.6 11.4 9 6 13.5 10.3 mA mA mA 2 11.4 4.9 2.2 13.5 5.6 mA mA mA 2 1 0.1 4.1 40.3 4.8 µA µA µA Self clocked mode, CNV± in CMOS mode 9 Self clocked mode, CNV± in CMOS mode9 Echoed clock mode, CNV± in LVDS mode Echoed clock mode, CNV± in LVDS mode Self clocked mode, CNV± in CMOS mode9 Rev. C | Page 4 of 24 Data Sheet Parameter Power-Down VDD1 VDD2 VIO Power Dissipation Static—Not Converting, Internal Reference Buffer Disabled Static—Not Converting, Internal Reference Buffer Enabled Converting: Internal Reference Buffer Disabled Converting: Internal Reference Buffer Enabled Converting: Internal Reference Buffer Disabled Power-Down Energy per Conversion TEMPERATURE RANGE Specified Performance AD7960 Test Conditions/Comments EN3 to EN0 = X000 Min Self clocked mode, CNV± in CMOS mode9 Self clocked mode, CNV± in CMOS mode9 Echoed clock mode, CNV± in LVDS mode Echoed clock mode, CNV± in LVDS mode Self clocked mode, CNV± in CMOS mode9 EN3 to EN0 = X000 Self clocked, CNV± in CMOS mode9 TMIN to TMAX Typ Max Unit 1 1 0.2 2.8 37.8 4.6 µA µA µA 9 10.3 mW 21 25 mW 46.5 56.2 mW 64.5 76.4 mW 39 47.4 mW 7.2 7.8 94.5 9.5 µW nJ/sample +85 °C −40 The minimum and maximum values are guaranteed by characterization. Using an external reference. 3 See Table 8 for logic levels of enable pins. When EN2 = 1, the −3 dB input bandwidth is 9 MHz. Use this lower bandwidth only when the throughput rate is 2 MSPS or lower. 4 The oversampled dynamic range is the ratio of the peak signal power to the noise power (for a small input) measured in the ADC output FFT from dc up to fS/(2 × OSR), where fS is the ADC sample rate and OSR is the oversampling ratio. 5 Guaranteed by design. 6 The REFIN pin is tied to 0 V in this mode. 7 The ANSI-644 LVDS specification has a minimum common-mode output (VOCM) of 1125 mV. 8 The current dissipated in the VCM circuitry when enabled is REF/20 kΩ and is not included in the operating currents listed. 9 CNV+ works as a CMOS input when CNV− is grounded. See Table 6 for additional information. 1 2 TIMING SPECIFICATIONS VDD1 = 5 V; VDD2 = 1.8 V; VIO = 1.71 V to 1.89 V; REF = 5 V or 4.096 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Time Between Conversions Acquisition Time CNV± High Time CNV± to D± (MSB) Ready CNV± to Last CLK± (LSB) Delay CLK± Period 1 CLK± Frequency CLK± to DCO± Delay (Echoed Clock Mode) DCO± to D± Delay (Echoed Clock Mode) CLK± to D± Delay 1 Symbol tCYC tACQ tCNVH tMSB tCLKL tCLK fCLK tDCO tD tCLKD Min 200 Typ Max tCYC − 115 10 3.33 0 0 4 250 3 0 3 0.6 × tCYC 200 160 (tCYC − tMSB + tCLKL)/n 300 5 1 5 Unit ns ns ns ns ns ns MHz ns ns ns For the maximum CLK± period, the window available to read data is tCYC − tMSB + tCLKL. Divide this time by the number of bits (n) to be read, giving the maximum CLK± frequency that can be used for a given conversion CNV± frequency. In echoed clock interface mode, n = 18; in self clocked interface mode, n = 20. Rev. C | Page 5 of 24 AD7960 Data Sheet Timing Diagrams SAMPLE N SAMPLE N + 1 tCYC tCNVH CNV– CNV+ tACQ ACQUISITION ACQUISITION ACQUISITION tCLKL tCLK 17 CLK– 1 18 2 17 1 18 2 3 CLK+ tDCO 17 DCO– 18 1 2 17 1 18 2 3 DCO+ tMSB D1 N–1 D– D0 N–1 tD D1 N D16 N D17 N 0 D0 N 0 D15 N+1 D16 N+1 D17 N+1 09659-002 tCLKD D+ Figure 2. Echoed Clock Interface Mode Timing Diagram SAMPLE N SAMPLE N + 1 tCYC tCNVH CNV– CNV+ tACQ ACQUISITION ACQUISITION ACQUISITION tCLKL tCLK CLK– 19 20 1 2 4 3 19 1 20 2 3 CLK+ D+ D– D1 N–1 D0 N–1 0 1 0 D17 N D16 N D1 N Figure 3. Self Clocked Interface Mode Timing Diagram Rev. C | Page 6 of 24 D0 N 0 1 0 D17 N+1 09659-003 tMSB tCLKD Data Sheet AD7960 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Analog Inputs/Outputs IN+, IN− to GND REF1 to GND VCM to GND REFIN to GND Supply Voltages VDD1 VDD2, VIO Digital Inputs to GND Digital Outputs to GND Input Current to Any Pin Except Supplies Operating Temperature Range (Commercial) Storage Temperature Range Junction Temperature ESD Ratings Human Body Model Machine Model Field-Induced ChargedDevice Model 1 θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating −0.3 V to VDD1 −0.3 V to +6 V −0.3 V to +6 V −0.3 V to +6 V Table 5. Thermal Resistance Package Type 32-Lead LFCSP_VQ −0.3 V to +6 V −0.3 V to +2.1 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V ±10 mA ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C 4 kV 200 V 1.25 kV Transient currents of up to 100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. C | Page 7 of 24 θJA 40 θJC 4 Unit °C/W AD7960 Data Sheet 32 31 30 29 28 27 26 25 REF REF REF REF REF_GND REF_GND REF_GND VDD2 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 AD7960 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 GND IN+ IN– VCM VDD1 VDD1 VDD2 CLK+ NOTES 1. CONNECT THE EXPOSED PAD TO THE GROUND PLANE OF THE PCB USING MULTIPLE VIAS. 09659-004 CNV+ D– D+ VIO GND DCO– DCO+ CLK– 9 10 11 12 13 14 15 16 VDD1 VDD2 REFIN EN0 EN1 EN2 EN3 CNV– Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 19, 20 2, 18, 25 12 13, 24 26, 27, 28 Mnemonic VDD1 VDD2 VIO GND REF_GND Type 1 P P P P P 3 REFIN AI 4, 5, 6, 7 DI 8, 9 EN0, EN1, EN2, 2 EN3 CNV−, CNV+ DI 10, 11 14, 15 D−, D+ DCO−, DCO+ DO DO 16, 17 21 CLK−, CLK+ VCM DI AO 22 23 29, 30, 31, 32 IN− IN+ REF AI AI AI/O 33 EP 1 2 Description Analog 5 V Supply. Decouple the 5 V supply with a 100 nF capacitor. Analog 1.8 V Supply. Decouple this pin with a 100 nF capacitor. Input/Output Interface Supply. Use a 1.8 V supply and decouple this pin with a 100 nF capacitor. Ground. Reference Ground. Connect the capacitors on the REF pin between REF and REF_GND. Tie REF_GND to GND. Prebuffer Reference Voltage. It is driven with an external reference voltage of 2.048 V. When driving an external 2.048 V reference, a 100 nF capacitor is required. If using an external 5 V or 4.096 V reference (connected to REF), connect this pin to ground. Enable.2 The logic levels of these pins set the operation of the device, as described in Table 8. Convert Input. These pins act as the conversion control pin. On the rising edge of these pins, the analog inputs are sampled and a conversion cycle is initiated. CNV+ works as a CMOS input when CNV− is grounded; otherwise, CNV+ and CNV− are differential LVDS inputs. LVDS Data Outputs. The conversion data is output serially on these pins. LVDS Buffered Clock Outputs. When DCO+ is grounded, the self clocked interface mode is selected. In this mode, the 18-bit results on D± are preceded by an initial 0 (which is output at the end of the previous conversion), followed by a 2-bit header (10) to allow synchronization of the data by the digital host with extra logic. The 1 in this header provides the reference to acquire the subsequent conversion result correctly. When DCO+ is not grounded, the echoed clock interface mode is selected. In this mode, DCO± is a copy of CLK±. The data bits are output on the falling edge of DCO+ and can be captured in the digital host on the next rising edge of DCO+. LVDS Clock Inputs. This clock shifts out the conversion results on the falling edge of CLK+. Common-Mode Output. When using any reference scheme, this pin produces one-half the voltage present on the REF pin, which can be useful for driving the common mode of the input amplifiers. Differential Negative Analog Input. Referenced to and must be driven 180° out of phase with IN+. Differential Positive Analog Input. Referenced to and must be driven 180° out of phase with IN−. Buffered Reference Voltage. When using the 2.048 V external reference (REFIN input), the 4.096 V system reference is produced at this pin. When using an external reference of 4.096 V or 5 V on this pin, the internal reference buffer must be disabled. Connect the REF pins with the shortest trace possible to a single 10 μF, low ESR, low ESL capacitor. The other side of the capacitor must be placed close to GND. Exposed Pad. The exposed pad is located on the underside of the package. Connect the exposed pad to the ground plane of the PCB using multiple vias. AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DO = digital output; P = power. EN2 = 0 sets the 28 MHz of input bandwidth, and EN2 = 1 sets the 9 MHz of input bandwidth. EN3 = 1 enables the VCM reference output. Rev. C | Page 8 of 24 Data Sheet AD7960 TYPICAL PERFORMANCE CHARACTERISTICS VDD1 = 5 V; VDD2 = 1.8 V; VIO = 1.8 V; all specifications T = 25°C, unless otherwise noted. 1.00 0.50 –40°C +25°C +85°C 0.75 0.25 0.50 DNL (LSB) 0.25 INL (LSB) –40°C +25°C +85°C 0 0 –0.25 –0.25 –0.50 0 150000 100000 50000 200000 250000 CODE –0.50 09659-101 –1.00 0 50000 100000 150000 200000 250000 CODE 09659-104 –0.75 Figure 8. Differential Nonlinearity vs. Code and Temperature, REF = 5 V Figure 5. Integral Nonlinearity vs. Code and Temperature, REF = 5 V 0.50 1.00 –40°C +25°C +85°C 0.75 0.50 0.25 DNL (LSB) INL (LSB) 0.25 0 –0.25 –0.25 –1.00 –40°C +25°C +85°C 0 50000 100000 150000 200000 250000 CODE –0.50 09659-102 –0.75 0 50000 100000 200000 150000 250000 CODE Figure 6. Integral Nonlinearity vs. Code and Temperature, REF = 4.096 V 09659-105 –0.50 Figure 9. Differential Nonlinearity vs. Code and Temperature, REF = 4.096 V 800000 800000 731453 600000 574212 702042 682452 601563 600000 COUNT 417791 400000 299523 263386 200000 200000 167625 137500 76526 0 5909 8878 464 6 66DB 66DC 66DD 66DE 66DF 66E0 66E1 66E2 66E3 66E4 66E5 66E6 CODE (HEX) Figure 7. Histogram of DC Input at Code Center, REF = 5 V 0 29 29231 1254 20298 66DB 66DD 66DC 66DF 66DE 66E1 66E0 66E3 66E2 2213 64 66E5 66E4 1 66E7 66E6 CODE (HEX) Figure 10. Histogram of DC Input at Code Transition, REF = 5 V Rev. C | Page 9 of 24 09659-112 59315 203 09659-109 COUNT 460940 400000 AD7960 Data Sheet 800000 800000 612307 600000 529433 600723 600000 573335 524601 COUNT COUNT 469541 400000 322696 393411 400000 318090 251602 200000 200000 126798 176972 122502 83201 7 277 3934 3389 206 8 0 843B 843D 843F 8441 8443 8445 8447 8449 844B 843C 843E 8440 8442 8444 8446 8448 844A CODE (HEX) 0 1 47010 6982 96 513 22 1 844B 8449 8445 8447 8441 8443 843B 843D 843F 844A 8446 8448 8444 843C 843E 8440 8442 CODE (HEX) Figure 14. Histogram of DC Input at Code Transition, REF = 4.096 V Figure 11. Histogram of DC Input at Code Center, REF = 4.096 V 0 0 INPUT FREQUENCY = 20kHz SNR = 99.8dB SINAD = 99.7dB THD = –115.9dB SFDR = 118.3dB –40 –40 –60 AMPLITUDE (dB) –60 –80 –100 –120 –80 –100 –120 –140 –140 –160 –160 500 1000 1500 2000 2500 FREQUENCY (kHz) –180 09659-103 –180 0 INPUT FREQUENCY = 20kHz SNR = 98.4dB SINAD = 98.3dB THD = –113.6dB SFDR = 116.1dB –20 0 1000 500 1500 09659-106 –20 AMPLITUDE (dB) 0 16272 09659-116 0 27625 09659-113 0 1758 29567 2500 2000 FREQUENCY (kHz) Figure 12. 20 kHz, −0.5 dBFS Input Tone FFT, Wide View, REF = 5 V Figure 15. 20 kHz, −0.5 dBFS Input Tone FFT, Wide Frequency View, REF = 4.096 V 0 INPUT FREQUENCY = 20kHz SNR = 99.8dB SINAD = 99.7dB THD = –115.9dB SFDR = 118.3dB –20 –40 0 INPUT FREQUENCY = 20kHz SNR = 98.4dB SINAD = 98.3dB THD = –113.6dB SFDR = 116.1dB –20 AMPLITUDE (dB) AMPLITUDE (dB) –40 –60 –80 –100 –120 –60 –80 –100 –120 –140 –140 –160 10 20 30 40 50 60 FREQUENCY (kHz) 70 80 90 100 Figure 13. 20 kHz, −0.5 dBFS Input Tone FFT, Zoomed View, REF = 5 V –180 0 10 20 30 40 50 60 FREQUENCY (kHz) 70 80 90 100 09659-110 0 09659-107 –160 –180 Figure 16. 20 kHz, −0.5 dBFS Input Tone FFT, Zoomed View, REF = 4.096 V Rev. C | Page 10 of 24 Data Sheet AD7960 100.0 0 INPUT FREQUENCY = 20kHz SNR = 100.1dB SINAD = 100.0dB THD = –123.4dB SFDR = 120.8dB –20 –40 99.5 SNR –60 SNR, SINAD (dB) AMPLITUDE (dB) SINAD –80 –100 –120 99.0 98.5 98.0 –140 97.5 0 500 1000 2000 1500 2500 FREQUENCY (kHz) 97.0 –40 09659-108 –180 40 60 80 –110 INPUT FREQUENCY = 20kHz SNR = 98.7dB SINAD = 98.6dB THD = –121.7dB SFDR = 119.5dB –112 –60 –114 THD (dB) AMPLITUDE (dB) 20 Figure 20. SNR and SINAD vs. Temperature, REF = 5 V 0 –40 0 TEMPERATURE (°C) Figure 17. 20 kHz, −6 dBFS Input Tone FFT, Wide View, REF = 5 V –20 –20 09659-115 –160 –80 –100 –120 –116 –118 –140 –120 0 500 1000 1500 2000 2500 FREQUENCY (kHz) –122 –40 –30 –20 –10 09659-111 –180 –120 99.50 –115 99.25 30 40 50 60 70 80 70 80 126 124 –110 122 –100 SNR 120 118 98.50 –95 98.25 –90 116 98.00 –85 114 0 50 100 150 –80 200 FREQUENCY (kHz) Figure 19. SNR and THD vs. Frequency, −0.5 dBFS, REF = 5 V 112 –40 –30 –20 –10 0 10 20 30 40 50 60 TEMPERATURE (°C) Figure 22. SFDR vs. Temperature, REF = 5 V Rev. C | Page 11 of 24 09659-130 98.75 SFDR (dB) –105 THD (dB) 99.00 09659-117 SNR (dB) 20 Figure 21. THD vs. Temperature, REF = 5 V THD 97.75 10 TEMPERATURE (°C) Figure 18. 20 kHz, −6 dBFS Input Tone FFT, Wide View, REF = 4.096 V 99.75 0 09659-129 –160 Data Sheet 2.5 10 2.0 8 CURRENT (µA) GAIN ERROR 1.5 1.0 VDD2 VDD1 VIO 6 4 ZERO ERROR 0.5 0 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) 0 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 23. Zero Error and Gain Error vs. Temperature, REF = 5 V 09659-123 2 09659-121 ZERO ERROR AND GAIN ERROR (LSB) AD7960 Figure 26. Power-Down Current vs. Temperature, REF = 5 V 0.3 12 0.2 10 IN+ 0 SUPPLY CURRENT (mA) –0.1 –0.2 IN– –0.3 –0.4 –0.5 VDD2 8 6 VIO 4 2 VDD1 –0.6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 DIFFERENTIAL INPUT VOLTAGE (V) 0 09659-125 –0.7 Figure 24. Input Current (IN+, IN−) vs. Differential Input Voltage, REF = 5 V 6 VIO 4 VDD1 –20 0 20 40 TEMPERATURE (°C) 60 80 09659-120 SUPPLY CURRENT (mA) VDD2 8 0 –40 2 3 4 5 Figure 27. Supply Current vs. Throughput, Self Clocked Mode, CNV± in CMOS Mode, Internal Reference Buffer Disabled 10 2 1 THROUGHPUT (MHz) 14 12 0 09659-126 INPUT CURRENT (mA) 0.1 Figure 25. Supply Current vs. Temperature, REF = 5 V, Self Clocked Mode, CNV± in CMOS Mode, Internal Reference Buffer Disabled Rev. C | Page 12 of 24 Data Sheet AD7960 TERMINOLOGY Differential Nonlinearity (DNL) Error In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. PSRR is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value. Integral Nonlinearity (INL) Error Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the rms noise measured for an input typically at −60 dB. The value for dynamic range is expressed in decibels. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD and is expressed in bits by ENOB = [(SINADdB − 1.76)/6.02] Gain Error The first transition (from 100 … 000 to 100 …001) should occur at a level ½ LSB above nominal negative full scale (−4.0959844 V for the ±4.096 V range). The last transition (from 011 … 110 to 011 … 111) occurs for an analog voltage 1½ LSB below the nominal full scale (+4.095953 V for the ±4.096 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Gain Error Drift The ratio of the gain error change due to a temperature change of 1°C and the full-scale range (2N). It is expressed in parts per million. Signal-to-Noise-and-Distortion (SINAD) Ratio SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal (including harmonics). Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Zero Error Zero error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. Zero Error Drift The ratio of the zero error change due to a temperature change of 1°C and the full-scale code range (2N). It is expressed in parts per million. Least Significant Bit (LSB) The least significant bit, or LSB, is the smallest increment that can be represented by a converter. For a fully differential input ADC with N bits of resolution, the LSB expressed in volts is LSB (V) = V INp-p 2N Rev. C | Page 13 of 24 AD7960 Data Sheet THEORY OF OPERATION IN+ GND LSB MSB 131,072C 65,536C 4C 2C SWITCHES CONTROL SW+ C C CLK+, CLK– REF COMP CONTROL LOGIC 4C 2C C OUTPUT CODE C MSB SW– LSB CNV+, CNV– GND CONVERSION CONTROL IN– LVDS INTERFACE 09659-011 65,536C DATA TRANSFER D+, D– GND 131,072C DCO+, DCO– Figure 28. ADC Simplified Schematic CIRCUIT INFORMATION The AD7960 is a 5 MSPS, high precision, power efficient, 18-bit ADC that uses SAR-based architecture to provide performance of 99 dB SNR, ±0.8 LSB INL, and ±0.5 LSB DNL. The AD7960 does not exhibit any pipeline delay or latency, making it ideal for multiplexed channel applications. The AD7960 is capable of converting 5,000,000 samples per second (5 MSPS). The device typically consumes 46.5 mW of power. The AD7960 offers the added functionality of an onchip reference buffer. If the internal reference buffer is enabled, the AD7960 consumes approximately an additional 18 mW of power. The AD7960 is specified for use with 5 V and 1.8 V supplies (VDD1, VDD2). The interface from the digital host to the AD7960 uses 1.8 V logic only. The AD7960 uses an LVDS interface to transfer data conversions. The CNV+ and CNV− inputs to the part activate the conversion of the analog input. The CNV+ and CNV− pins can be applied using a CMOS or LVDS source. The AD7960 is housed in a space-saving, 32-lead, 5 mm × 5 mm LFCSP package. When the conversion phase begins, SW+ and SW− are opened first. The two-capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the inputs (IN+ and IN−) captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF (the reference voltage), the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 … VREF/262,144). The control logic toggles these switches, MSB first, to bring the comparator back into a balanced condition. At the completion of this process, the control logic generates the ADC output code. The AD7960 digital interface uses low voltage differential signaling (LVDS) to enable high data transfer rates. The AD7960 conversion result is available for reading after tMSB (time from the conversion start until MSB is available) elapses. The user must apply a burst LVDS CLK± signal to the AD7960 to transfer data to the digital host. The CLK± signal outputs the ADC conversion result onto the data output, D±. The bursting of the CLK± signal, illustrated in Figure 35 and Figure 36, is characterized as follows: CONVERTER INFORMATION • The AD7960 is a 5 MSPS ADC that uses SAR-based architecture based on a charge redistribution DAC. Figure 28 shows a simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 18 binary weighted capacitors that are connected to the two comparator inputs. • During the acquisition phase, the terminals of the array tied to the input of the comparator are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs. In this way, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. A conversion phase is initiated when the acquisition phase is complete and the CNV± input goes high. Note that the AD7960 can receive a CMOS or LVDS format CNV± signal. Rev. C | Page 14 of 24 Hold the differential voltage on CLK± in a steady state in the window of time between tCLKL and tMSB. The AD7960 has two data read modes. For more information about the echoed clock and self clocked interface modes, see the Digital Interface section. Data Sheet AD7960 TRANSFER FUNCTION The AD7960 uses a 5 V or a 4.096 V reference. The AD7960 converts the differential voltage of the antiphase analog inputs (IN+ and IN−) into a digital output. IN+ and IN− require a REF/2 V common-mode voltage. maximum. However, if the supplies of the input buffer amplifier are different from the VDD1/GND supply, the analog input signal may eventually exceed the supply rails by more than 0.3 V. In such a case (for example, an input buffer with a short circuit), the current limitation can be used to protect the part. VDD1 185Ω 26pF 09659-013 IN+ OR IN– Figure 30. Equivalent Analog Input Circuit 011 ... 111 011 ... 110 011 ... 101 The analog input structure allows the sampling of the true differential signal between IN+ and IN−. By using these differential inputs, signals common to both inputs are rejected. The AD7960 shows some degradation in THD with higher analog input frequencies. 100 100 ... 010 90 80 –FSR + 0.5LSB +FSR – 1LSB +FSR – 1.5LSB ANALOG INPUT 70 Figure 29. ADC Ideal Transfer Functions (FSR = Full-Scale Range) ANALOG INPUTS The analog inputs applied to the AD7960, IN+ and IN−, must be 180° out of phase with each other. Figure 30 shows an equivalent circuit of the input structure of the AD7960. The two diodes provide ESD protection for IN+ and IN−. Care must be taken to ensure that the analog input signals do not exceed the supply rails of the AD7960 by more than 0.3 V (VDD1 and GND). If the analog input signals exceed this level, the diodes become forward-biased and start conducting current. These diodes can handle a forward-biased current of 130 mA 60 50 40 30 20 10 0 100 1k 10k 100k FREQUENCY (Hz) 1M 09659-127 –FSR + 1LSB CMRR (dB) 100 ... 001 100 ... 000 –FSR 09659-012 ADC CODE (TWOS COMPLEMENT) The 18-bit conversion result is in MSB first, twos complement format. The ideal transfer functions for the AD7960 are shown in Figure 29 and Table 7. Figure 31. Analog Input CMRR vs. Frequency Table 7. Output Codes and Ideal Input Voltages Description FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR Analog Input (IN+ − IN−), REF = 5 V +4.999962 V +38.15 μV 0V −38.15 μV −4.999962 V −5 V Analog Input (IN+ − IN−), REF = 4.096 V +4.095969 V +31.25 μV 0V −31.25 μV −4.095969 V −4.096 V Rev. C | Page 15 of 24 Digital Output Code, Twos Complement (Hex) 0x1FFFF 0x00001 0x00000 0x3FFFF 0x20001 0x20000 AD7960 Data Sheet edge to the multiplexer inputs switching event results in no corruption. If the analog inputs are multiplexed during this quiet conversion time, the current conversion may be corrupted by up to 15 LSBs. TYPICAL APPLICATIONS Figure 32 shows an example of a typical connection diagram for driving the AD7960 using the two single-ended ADA4899-1 devices. The alternative ADC drivers are two single-ended ADA4897-1 op amps or a differential amplifier ADA4932-1 that can drive the inputs of the AD7960. If the analog inputs are multiplexed early enough, the inputs can slew fast enough to a full-scale signal and settle the input within the allowed time. The AD7960 is an ideal fit for high speed multiplexed applications such as digital X-ray, computed tomography, and infrared cameras that require superior performance in terms of noise, power, and throughput, which significantly reduces cost in these types of applications. The AD7960 has a quiet time requirement of 90 ns to 110 ns during the conversion, where the switching of multiplexer inputs (channels) must not occur to avoid the corruption of conversion. In other words, a delay of less than 90 ns and greater than 110 ns from the CNV± rising The AD7960 offers extremely low noise floor relative to its fullscale input. The combination of high throughput rate, low noise floor, and linearity also makes this part suitable for oversampling applications such as spectroscopy, MRI gradient control, and gas chromatography. The wide dynamic range of the AD7960 allows accurate measurements of both small and large signals from multiple channels. +VS +5V AD8031 ADR4550 +7V 0.1µF 10µF2 0.1µF 0.1µF +5V –VS 0.1µF +1.8V 0.1µF +1.8V 0.1µF +VS REFIN 56pF ADA4899-1 REF1 VDD1 VDD2 VIO CNV± 100Ω –VS IN+ D± 100Ω DCO± 100Ω AD7960 IN– +VS 33Ω VCM = 2.5V GND VCM 56pF 100Ω 2.5V 0V TO 5 V ADA4899-1 CLK± DIGITAL HOST LVDS TRANSMIT AND RECEIVE VCM = 2.5V DIGITAL INTERFACE SIGNALS 33Ω 0V TO 5 V 0.1µF –VS +VS VCM3 AD8031 0.1µF GROUND OF THE BOARD. THE REF AND REFIN PINS ARE DECOUPLED REGARDLESS OF EN1 AND EN0 SETTINGS. 3BUFFERED VCM PIN OUTPUT GIVES THE REQUIRED 2.5V COMMON-MODE SUPPLY FOR ANALOG INPUTS. Figure 32. Typical Application Diagram Rev. C | Page 16 of 24 09659-015 –VS 1 SEE THE VOLTAGE REFERENCE OPTIONS SECTION. CONNECTION TO EXTERNAL REFERENCE SIGNALS IS DEPENDENT ON THE EN1 AND EN0 SETTINGS. 2 A 10µF CAPACITOR WITH LOW ESL AND ESR IS USUALLY CONNECTED BETWEEN THE REF PIN AND REF_GND. CONNECT REF_GND TO THE COMMON Data Sheet AD7960 Table 8. Voltage Reference Options EN3 X1 X1 EN2 0 0 EN1 0 0 EN0 0 1 REFIN X1 0V X1 0 0 1 2.048 V X1 0 1 0 0V X1 0 1 1 0V 0 1 X1 1 1 1 0 0 0 0 0 1 X1 X1 0V X1 1 0 1 2.048 V X1 1 1 0 0V X1 1 1 1 0V 1 2 Reference Mode Description Power-down mode. Everything is powered down, including the LVDS interface. Interface powered up. Reference buffer disabled. An external 5 V reference is applied to the REF pin. Connect REFIN to 0 V in this mode. The bandwidth of the input sampling network is set to 28 MHz. Internal reference buffer enabled. An external 2.048 V reference applied to REFIN pin is required. A buffered 4.096 V reference is available on the REF pin. The bandwidth of the input sampling network is set to 28 MHz. Internal reference buffer disabled. Drive the REF pins with a 4.096 V external reference. Connect REFIN to 0 V in this mode. The bandwidth of the input sampling network is set to 28 MHz. Snooze mode. 2 LVDS powers down. The chip is unresponsive to CNV± start pulses. The wake-up time is fast (5 µs) when EN3 to EN0 are set to XX01 or XX10. Ensure that the CNV± start pulse is low when transitioning in and out of this mode. Test patterns output on LVDS. The ADC output is not available on the interface. Invalid mode. Reference buffer disabled. Drive the REF pins with a 5 V external reference. The bandwidth of the input sampling network is set to narrow (9 MHz). Internal reference buffer enabled and driving REF pin to 4.096 V. The bandwidth of the input sampling network is set to narrow (9 MHz). Reference buffer disabled. Drive the REF pins with a 4.096 V external reference. The bandwidth of the input sampling network is set to narrow (9 MHz). Snooze mode.2 LVDS powers down. The chip is unresponsive to CNV± start pulses. The wake-up time is fast (5 µs) when EN3 to EN0 are set to XX01 or XX10. X = don’t care. The snooze mode is not useful when the internal reference buffer is used because the fast wake-up is not possible due to the settling of the internal reference buffer. VOLTAGE REFERENCE OPTIONS Wake-Up Time from Power-Down and Snooze Modes The AD7960 allows buffering of the reference voltage. The AD7960 conversions are referred to a 5 V or 4.096 V reference voltage. There are three options for using an external reference. The AD7960 powers down when EN3 to EN0 = X000 and operates in snooze mode when EN3 to EN0 = XX11 using the correct reference choice as shown in Table 8. Typical wake-up times for the selected reference settings from power-down and snooze mode are shown in Table 9 and Table 10. Each wake-up time represents the duration from the EN3 to EN0 logic transition to when the ADC is ready for a CNV± rising edge. For example, the user must wait 1.4 ms from power-down before applying CNV± pulses to receive data conversion results when using REFIN = 0 V. • • • Externally buffered reference source of 5 V applied to the REF pin. Externally buffered reference source of 4.096 V applied to the REF pin. External reference of 2.048 V applied to the REFIN pin (high impedance input). The on-chip buffer gains this by 2 and drives the REF pin with 4.096 V. The recommended external references for the AD7960 are the ADR4520/ADR4540/ADR4550 and ADR440/ADR444/ADR445. The various options for creating this reference are controlled by the EN1 and EN0 pins (see Table 8). The −3 dB input bandwidth is controlled by EN2. EN2 = 0 sets a −3 dB input bandwidth of 28 MHz, and EN2 = 1 sets a −3 dB input bandwidth of 9 MHz. Use this lower bandwidth (9 MHz) only when the sample rate is 2 MSPS or lower. EN3 = 1 enables the VCM reference output, and EN3 = 0 disables the VCM reference output voltage. The best SNR and dynamic range performance is achieved by using the larger 5 V external voltage reference option. The improvement achieved is approximately 1.7 dB and is calculated using the following equation: Table 9. Wake-Up Time from Power-Down Mode, EN3 to EN0 = X000 To Active Mode EN3 to EN0 = XX01, REFIN = 0 V EN3 to EN0 = XX01, REFIN = 2.048 V EN3 to EN0 = XX10, REFIN = 0 V Wake-Up Time 1.4 ms 8 ms 1.4 ms Table 10. Wake-Up Time from Snooze Mode, EN3 to EN0 = XX11 To Active Mode EN3 to EN0 = XX01, REFIN = 0 V EN3 to EN0 = XX01, REFIN = 2.048 V EN3 to EN0 = XX10, REFIN = 0 V 5. 0 ∆SNR = 20 log 4.096 Rev. C | Page 17 of 24 Wake-Up Time 5 µs 8 ms 5 µs AD7960 Data Sheet POWER SUPPLY Power-Up The AD7960 uses both 5 V (VDD1) and 1.8 V (VDD2) power supplies, as well as a digital input/output interface supply (VIO). Drive the EN3 to EN0 pins with a 1.8 V logic level. VIO and VDD2 can be taken from the same 1.8 V source; however, it is best practice to isolate the VIO and VDD2 pins using separate traces as well as to decouple each pin separately. As is best practice for all ADCs, power on the core supplies prior to applying an external reference (where applicable). Apply the analog inputs last. 110 100 VDD2 = 1.8V VIO = 1.8V VDD1 = 5V 90 80 40 35 30 25 20 15 10 70 60 0 40 100 0 1 2 3 THROUGHPUT (MHz) 50 1k 10k 100k FREQUENCY (Hz) 1M 4 5 09659-128 5 09659-124 PSRR (dB) 45 POWER DISSIPATION (mW) The 5 V and 1.8 V supplies required for the AD7960 can be generated using Analog Devices, Inc., LDOs such as the ADP7104-5 and the ADP124-1.8. Figure 33 shows the PSRR vs. supply frequency of the AD7960. The AD7960 core power scales with throughput as shown in Figure 34, offering significant power budget savings at lower speed operation. When powering up the AD7960 device, first apply 1.8 V (VDD2, VIO) to the device, then ramp 5 V (VDD1). Set the reference configuration pins, EN0, EN1, and EN2, to the correct values. When an internal reference buffer is used (governed by the EN1 and EN0 values), apply the external reference of 2.048 V to the REFIN pin or 5 V/4.096 V to the REF pin. Figure 34. ADC Core Power Dissipation vs. Throughput, Self Clocked Mode, CNV± in CMOS Mode, Internal Reference Buffer Disabled Figure 33. PSRR vs. Supply Frequency Rev. C | Page 18 of 24 Data Sheet AD7960 DIGITAL INTERFACE The clock DCO± is a buffered copy of CLK± and is synchronous to the data, D±, which is updated on the falling edge of DCO± (tD). By maintaining good propagation delay matching between D± and DCO± through the board and the digital host, DCO± can be used to latch D± with good timing margin for the shift register. CONVERSION CONTROL All analog-to-digital conversions are controlled by the CNV± signal. This signal can be applied in the form of a CNV+/CNV− LVDS signal, or it can be applied in the form of a 1.8 V CMOS logic signal to the CNV+ pin when CNV− is grounded. The conversion is initiated by the rising edge of the CNV± signal. Conversions are initiated by a rising edge of the CNV± pulse. The CNV± pulse must be returned low (≤tCNVH maximum) for valid operation. After a conversion begins, it continues until completion. Additional CNV± pulses are ignored during the conversion phase. After tMSB elapses, the host begins to burst the CLK±. Note that tMSB is the maximum time for the MSB of the new conversion result. Use tMSB as the gating device for CLK±. The echoed clock, DCO±, and the data, D±, are driven in phase with D± being updated on the falling edge of DCO±; the host uses the rising edge of DCO± to capture D±. The only requirement is that the 18 CLK± pulses finish before tCLKL of the next conversion phase elapses, or the data is lost. After all 18 bits are read, up to tMSB, D± and DCO± are driven to 0. Set CLK± to idle low between CLK± bursts. After the AD7960 is powered up, the first conversion result generated is valid. The key beneficial feature of the AD7960 is that the user can return to the acquisition phase before the end of the conversion. The two methods for acquiring the digital data output of the AD7960 via the LVDS interface, are described in the Echoed Clock Interface Mode and Self Clocked Mode sections. Echoed Clock Interface Mode The digital operation of the AD7960 in echoed clock interface mode is shown in Figure 35. This interface mode, requiring only a shift register on the digital host, can be used with many digital hosts (such as FPGA, shift register, and microprocessor). It requires three LVDS pairs (D±, CLK±, and DCO±) between each AD7960 and the digital host. SAMPLE N SAMPLE N + 1 tCYC tCNVH CNV– CNV+ tACQ ACQUISITION ACQUISITION ACQUISITION tCLKL tCLK 17 CLK– 18 1 2 17 18 1 2 3 CLK+ tDCO 17 DCO– 18 1 2 17 1 18 2 3 DCO+ tMSB D– D1 N–1 D0 N–1 tD 0 D17 N D16 N D1 N D0 N Figure 35. Echoed Clock Interface Mode Timing Diagram Rev. C | Page 19 of 24 0 D17 N+1 D16 N+1 D15 N+1 09659-018 tCLKD D+ AD7960 Data Sheet Self Clocked Mode The self clocked mode data capture method allows the digital host to adapt its result capture timing to accommodate variations in propagation delay through any AD7960, for example, where data is captured from multiple AD7960 devices sharing a common input clock. The digital operation of the AD7960 in self clocked interface mode is shown in Figure 36. This interface mode reduces the number of traces between the ADC and the digital host to two LVDS pairs (CLK± and D±) or to a single pair if sharing a common CLK±. Multiple AD7960 devices can share a common CLK± signal. This can be useful in reducing the number of LVDS connections to the digital host. Conversions are initiated by a CNV± pulse. The CNV± pulse must be returned low (tCNVH maximum) for valid operation. After a conversion begins, it continues until completion. Additional CNV± pulses are ignored during the conversion phase. After the time, tMSB, elapses, the host begins to burst the CLK± signal to the AD7960. All 20 CLK± pulses must be applied in the window of time framed by tMSB and the subsequent tCLKL. The required 20 CLK± pulses must finish before tCLKL (referenced to the next conversion phase) elapses. Otherwise, the data is lost because it is overwritten by the next conversion result. When the self clocked interface mode is used, each ADC data-word is preceded by a 010 header sequence. After tMSB has elapsed, the first bit of the header, 0, automatically appears on D±, and the remaining two bits of the header, 10, are then clocked out by the first two CLK± falling edges at the beginning of the next sample. This header (010) is used to synchronize D± of each conversion in the digital host because, in this mode, there is no clock output synchronous to the data (D±) to allow the digital host to acquire the data output. Set CLK± to idle high between bursts of 20 CLK± pulses. The header bit and conversion data of the next ADC result are output on subsequent falling edges of CLK± during the next burst of the CLK± signal. Synchronization of the D± data to the acquisition clock of the digital host is accomplished by using one state machine per AD7960 device. For example, using a state machine that runs at the same speed as CLK± incorporates three phases of this clock frequency (120° apart). Each phase acquires the D± data as output by the ADC. When the self clocked interface mode is used, the AD7960 also allows the user to provide an extra (21st) clock pulse to see a guaranteed 0 state at the end of the frame, as shown in Figure 37. After tMSB has elapsed, the first bit of the header sequence, 0, automatically appears on D± and the remaining two bits of the header, 10, are then clocked out by the first two CLK± falling edges at the beginning of the next sample. This header (010) is used to synchronize D± of each conversion in the digital host because, in this mode, there is no clock output synchronous to the data (D±) to allow the digital host to acquire the data output. The AD7960 data captured on each phase of the state machine clock is then compared. The location of the 1 in the header in each set of acquired data allows the user to choose the state machine clock phase that occurs during the data valid window of D±. SAMPLE N SAMPLE N + 1 tCYC tCNVH CNV– CNV+ tACQ ACQUISITION ACQUISITION ACQUISITION tCLKL tCLK 19 CLK– 20 1 2 4 3 19 1 20 2 3 CLK+ D+ D– D1 N–1 D0 N–1 0 1 0 D17 N D16 N D1 N Figure 36. Self Clocked Interface Mode Timing Diagram Rev. C | Page 20 of 24 D0 N 0 1 0 D17 N+1 09659-019 tMSB tCLKD Data Sheet AD7960 SAMPLE N SAMPLE N + 1 tCYC tCNVH CNV– CNV+ tACQ ACQUISITION ACQUISITION ACQUISITION tCLKL tCLK CLK– 19 20 21 1 2 4 3 19 20 1 21 2 3 CLK+ D+ D– D1 N–1 D0 N–1 0 1 0 D17 N D16 N D1 N D0 N Figure 37. Self Clocked Interface Mode with Extra Clock Pulse Timing Diagram Rev. C | Page 21 of 24 0 1 0 D17 N+1 09659-020 tMSB tCLKD AD7960 Data Sheet APPLICATIONS INFORMATION LAYOUT Design the printed circuit board that houses the AD7960 so that the analog and digital sections are separated and confined to certain areas of the board. Avoid running digital lines under the device because these couple noise onto the device unless a ground plane under the AD7960 is used as a shield. Do not run fast switching signals, such as CNV± or CLK±, near analog signal paths. Avoid crossover of digital and analog signals. Use at least one ground plane. It can be common or split between the digital and analog sections. In the latter case, join the planes underneath the AD7960 devices. The AD7960 voltage reference input pin, REF, has dynamic input impedance. Decouple REF with minimal parasitic inductances by placing the reference decoupling ceramic capacitor close to and, ideally, right up against the REF and REF_GND pins and connecting them with wide, low impedance traces. Finally, decouple the VDD1, VDD2, and VIO power supplies of the AD7960 with ceramic capacitors, typically 100 nF, placed close to the AD7960 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. EVALUATING AD7960 PERFORMANCE Other recommended guidelines for the AD7960 schematic and layout are outlined in the user guide of the EVAL-AD7960FMCZ board (UG-490). The fully assembled and tested evaluation board, user guide, and software for controlling the EVALAD7960FMCZ board from a PC via the EVAL-SDP-CH1Z are available from the Analog Devices website at www.analog.com. Rev. C | Page 22 of 24 Data Sheet AD7960 OUTLINE DIMENSIONS 5.10 5.00 SQ 4.90 32 25 0.50 BSC TOP VIEW 0.80 0.75 0.70 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD 17 0.50 0.40 0.30 PIN 1 INDICATOR 1 24 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A PIN 1 INDICATOR 0.30 0.25 0.18 Figure 38. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-7) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD7960BCPZ AD7960BCPZ-RL7 EVAL-AD7960FMCZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board Z = RoHS Compliant Part. Rev. C | Page 23 of 24 Package Option CP-32-7 CP-32-7 AD7960 Data Sheet NOTES ©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09659-0-3/14(C) Rev. C | Page 24 of 24