8 7 6 5 4 3 2 1 REVISIONS ZONE SYM DESCRIPTION DATE Assy 20361640 - Revision 3 See Page 16 VSUB and Electronic Shutter D Imager Socket KAI-29050 CCDinB CCDinA CCDinA CCDinC CCDinC CCDinD CCDinD AD9928 AFE AD9928 AFE HCLK DRIVERS A&B Ra H2SLa H1Sa H1Ba H2Sa H2Ba H1Sb H1Bb_SD H2Sb H2Bb_SD H2SLb Rb C Ra H2SLa H1Sa H1Ba H2Sa H2Ba H1Sb H1Bb_SD H2Sb H2Bb_SD H2SLb Rb RGBa_AFE H2SLa_AFE H1ab_AFE H2ab_AFE H1Bb_SD_AFE H2Bb_SD_AFE H2SLb_AFE RGBb_AFE April 2016 D INTERCONNECT Analog Front End CCDinB APPROVAL RGBa_AFE H2SLa_AFE H1ab_AFE H2ab_AFE H1Bb_SD_AFE H2Bb_SD_AFE H2SLb_AFE RGBb_AFE TCLKP_AB TCLKP_AB TCLKN_AB TCLKN_AB DOUT0P_A_AB DOUT0P_A_AB DOUT0N_A_AB DOUT0N_A_AB DOUT1P_A_AB DOUT1P_A_AB DOUT1N_A_AB DOUT1N_A_AB DOUT0P_B_AB DOUT0P_B_AB DOUT0N_B_AB DOUT0N_B_AB DOUT1N_B_AB DOUT1N_B_AB DOUT1P_B_AB DOUT1P_B_AB TCLKP_CD TCLKP_CD TCLKN_CD TCLKN_CD DOUT0P_A_CD DOUT0P_A_CD DOUT0N_A_CD DOUT0N_A_CD DOUT1P_A_CD DOUT1P_A_CD DOUT1N_A_CD DOUT1N_A_CD DOUT0P_B_CD DOUT0P_B_CD DOUT0N_B_CD DOUT0N_B_CD DOUT1P_B_CD DOUT1P_B_CD DOUT1N_B_CD DOUT1N_B_CD TV57 HD_AB C HD_AB VD_AB VD_AB TV58 HCLK DRIVERS C&D Rc H2SLc H1Sc H1Bc H2Sc H2Bc H1Sd H1Bd_SD H2Sd H2Bd_SD H2SLd Rd Rc H2SLc H1Sc H1Bc H2Sc H2Bc H1Sd H1Bd_SD H2Sd H2Bd_SD H2SLd Rd RGBc_AFE H2SLc_AFE H1cd_AFE H2cd_AFE H1Bd_SD_AFE H2Bd_SD_AFE H2SLd_AFE RGBd_AFE GPO1_STROBE_AB RGBc_AFE H2SLc_AFE H1cd_AFE H2cd_AFE H1Bd_SD_AFE H2Bd_SD_AFE H2SLd_AFE RGBd_AFE SYNC_AB SYNC_AB RSTB_AB RSTB_AB SYNC_CD SYNC_CD RSTB_CD RSTB_CD GPO1_STROBE_AB SUBCK SUBCK TV49 GPO3_SCKA_AB GPO4_XSUBCK_SHPA_AB VCLK DRIVERS TOP V1T_3rd_AFE GPO6_XV21_SHPB_DVAL_AB V1T V2T V2T V2T_AFE V2T_AFE GPO2_CD V3T V3T V3T_AFE V3T_AFE GPO3_CD V4T V4T V4T_AFE V4T_AFE GPO4_CD FDG_CD_AFE GPO5_CD FDG_CD FDG_CD_AFE V1T_AFE GPO1_CD GPO6_CD GPO7_CD VCLK DRIVERS BOTTOM V1B_3rd_AFE B V1B V1B V1B_AFE V2B V2B_AFE V2B_AFE V3B V3B V3B_AFE V3B_AFE AFECS_CD V4B V4B V4B_AFE V4B_AFE FDG_AB_AFE SCLK SDATA V1B_AFE V2B FDG_AB TV6 TV8 TV4 TV1 TV3 TV7 TV5 SCLK V1B_3rd_AFE AFECS_AB FDG_AB TV51 TV50 TV48 V1T_3rd_AFE V1T FDG_CD V1T_AFE GPO5_SCKB_AB GPO6_XV21_SHPB_DVAL_AB OSC_EN FDG_AB_AFE AFECS_AB AFECS_CD OSC_EN DEV_ID DEV_ID Front End POWER B SDATA VAB_ADJ VAB_ADJ VAB_EN VAB_EN ESD_EN ESD_EN VCLK_EN VCLK_EN HCLK_EN HCLK_EN V15_EN V15_EN 20361636-Revision 2 Bare Board 20361640-Revision 3 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN Lens Mounting Holes N3 N4 N6 N5 + - FM1 FM2 Pic-n-Place Fids Top FM3 3 PL DEC TOL + - FM4 FM5 Pic-n-Place Fids Bot FM6 SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. NEXT ASSY USED ON APPLICATION 8 THREADS. IN ALL OTHER PLACES 2 PL DEC TOL ANGULAR TOL 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Top Level Drawing Gen2 Evaluation System 72 pin PGA Imager Board QA CHK Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361636 / 20361640 PROGRAM CADSTAR SHEET 1 1 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS MAIN SUPPLIES ZONE DESCRIPTION DATE APPROVAL +16V +12V J2 PJ-002A-SMT LT3479_16V LTM8022_6V V12 V16 U32 LT1761ES5-SD +16V +6V V6 1 3 1 VOUT 3 V15_EN ADJ GND 4 R72 200K 1% 2 1 V12 1 C143 10UF 25V 2 V12NEG 2 -12V D 1 4 SHDN\ LT3479_N12V CCD VDD +15V Amplifier LDO 40mA +15VA 5 VIN 2 D SYM C142 1uF 25V 10% VDD_ADJa 1 2 1 2 1 C127 10UF 25V C108 .1uF 25V 2 R73 17.4K 1% 2 V Clock Rails +3.3VD +3.3VA +16V Always On JMP2 1 OPTION to run 3.3 supplies off FPGA board or have local regulation for stand alone operating U9 LT1965EMS8E 2 JMP1 1 C VIN VOUT VIN VOUT 1 6 R16 200K 1% 3 SHDN ADJ 5 C174 .1uF 25V 2 2 1 C186 .01uF 2 SHDN\ 1 Sense C187 1uF 25V 10% GNDNC NC NC C172 1uF 25V 10% C46 4.7UF 25V VOUT 1 1 GND 1 1 VIN 4 3 6 2 7 2 2 4 5 1 C56 2.2uF 16V 2 20% 2 2 1 Main 3.3V Supply 8 1 TV23 1 2 2 VCLK_EN +16V 1 7 U43 LT1521CMS8-3.3 +6V +Vhigh V3rd level=+12 8 Sequenced 9 -VESD TV34 C57 .01uF VAB TV9 +15VA R15 C TV29 2 +6V VRD_B VRD_T TV56 23.2K 1% TV55 3 TV28 TV24 TV70 4 TV22 TV25 TV71 2 TV31 -VH -VOG_B -VOG_T TV26 -VRESET TV30 +Vhigh 1 1 U11 LT1175CS8 R37 31.6Kohm 1% 2 2 U23 LT1964ES5-SD C96 .1uF 25V 2 1 2 C95 1uF 25V 10% 1 1 R42 200K 1% 4 GND ADJ 2 IN 3 ESD_EN 5 SHDN C25 .1uF 25V 2 C99 .01uF 1 2 1 1 4.7UF 25V 3 GND VIN V-OUT VIN SENSE 8 1 TV10 TV11 5 +3.3VA -Vlow 2 TV69 4 2 ILIM2 7 1 ILIM4 6 -9V SHDN/ 2 OUT R19 162K 1% 5 C26 -12V ADJ_VN -12V 1 -12V 2 -9 R17 200K 1% -VESD 2 1 C62 2.2uF 16V 20% 2 C63 .01uF 1 -Vlow B B U27 LTM8022EV#PFB +12V 2 H1 G1 C110 .1uF 25V 2 2 C109 2.2uF 16V 20% H2 G3 H3 G2 C3 B3 A3 E1 D1 AUX E2 D2 G5 SHARE HCLK_EN G7 HCLK_EN_SS 2 1 BIAS E3 D3 H6 RT G6 PGOOD E4 D4 ADJ SYNC R55 15.0K 1% F5 Vout RUN/SS F7 C107 .01uF H7 E5 D5 C5 B5 A5 1 1 E7 D7 C7 B7 A7 1 U26 LT1964ES5-SD K R40 27K 1% .1uF 25V R49 200K 1% 4 GND ADJ 2 IN GND 5 SHDN VIN VOUT 2 -VH 1 R18 309K 1% 3 ADJ 2 1 GND 1 1 1 2 SHDN 2 OUT VOUT 6 Reset: Low level -3.5 R41 93.1K 2 2 C98 1uF 25V 10% +5VDC 1 VIN 7 2 1 1 3 C101 8 R48 309K 1% A 1 FDGH 1 F6 E6 D6 C6 B6 A6 1 U10 LT1965EMS8E +6V C4 B4 A4 Vin H5 C100 10UF 16V C2 B2 A2 2 CR26 1 MBRM120E 1 C1 B1 A1 C60 4.7UF 25V 4 5 9 2 1 C51 2.2uF 16V 2 20% C50 .01uF R20 110K 1% 2 -VRESET 2 2 HClock -5V -VH 20361636-Revision 2 Bare Board 20361640-Revision 3 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Power page 1 Gen2 Evaluation System 72 pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361636 / 20361640 PROGRAM CADSTAR SHEET 1 2 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE SYM DESCRIPTION DATE APPROVAL +12VP D V12 1 V12 +16V CR7 MBRM120E L3 10uH 2 BoostSW1 A D +16.5V K V16 1 2 BoostL 1 1 C150 10UF 16V C149 .01uF R80 200K 1% 2 2 5 4 3 Vin Vs 7 2 L C135 4.7UF_25V SW SW 2 10 LT3479 U34 SHDN 16V_FB FBN 8 1 Vref 12 1 1 9 SS R81 16.5K 1% FBP 1 2 C136 .01uF Rt 6 2 GND 13 GND PwrPad 14 Vc 15 11 1 C C 1 R93 15.0K 1% 2 R79 10K 1% 2 1 1.3MHz operating freq C134 2200PF 2 +12V U40 LTM8022EV#PFB H1 G1 1 B C1 B1 A1 H2 G3 E1 D1 F7 G5 BIAS E3 D3 G6 PGOOD E4 D4 ADJ SYNC H7 E5 D5 C5 B5 A5 .1uF 25V 1 F6 E6 D6 C6 B6 A6 2 2 H6 RT 1 C173 4.7UF_25V F5 AUX E2 D2 G7 Power for local 3.3 LDO if needed Power for Mechanical Shutter if needed 1 Vout SHARE 1 C175 C4 B4 A4 RUN/SS 2 B C3 B3 A3 Vin H5 V6 C2 B2 A2 H3 G2 R98 15.0K 1% +6V R95 24.9K 1% E7 D7 C7 B7 A7 R96 75.0K 1% GND 2 2 20361636-Revision 2 Bare Board 20361640-Revision 3 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Power page 2 LT3471 Gen2 Evaluation System 72 pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361636 / 20361640 PROGRAM CADSTAR SHEET 1 3 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE SYM DESCRIPTION DATE APPROVAL D D K C C112 1uF 25V 10% L2 10uH 1 V12 2 CR24 MBRM120E A C111 10UF 25V L1 10uH 1 V12N_SW 1 2 2 C C102 .1uF 25V 1 1 2 V12NEG 2 -12V 1 2 C105 2.2uF 16V 20% 5 4 3 Vin Vs 2 L 1 1 2 A C94 100PF SW SW 1 7 K R58 10K 1% 10 LT3479 U28 SHDN FBN R56 95.3K 1% CR25 MBRM120E 2 8 Vref 12 2 2 9 SS FBP 1 C104 .1uF 25V 1 Vout=-1.235(R300/R400) Rt 6 GND 13 GND PwrPad 14 Vc 15 11 1 1 R57 10K 1% R59 15.0K 1% 2 1 C103 2200PF 2 B B 2 20361636-Revision 2 Bare Board 20361640-Revision 3 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Power page 3 LT3479 Gen2 Evaluation System 72 pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361636 / 20361640 PROGRAM CADSTAR SHEET 1 4 of 17 __ 8 7 6 5 4 3 2 REVISIONS B-B Connector Spacing 4" B-B Mounting posts per Altera HSMC Spec N2 ZONE SYM DESCRIPTION DATE APPROVAL N1 2.8" D 1 N7 4" N8 J4-A J4-B ASP-122952-01 2 XCVR_RXp7 4 6 8 10 12 14 TCLKN_AB DOUT1P_B_AB DOUT1N_B_AB DOUT0P_B_AB DOUT0N_B_AB 22 24 XCVR_RXn6 XCVR_TXn6 XCVR_RXp5 XCVR_TXp5 XCVR_RXn5 XCVR_TXn5 XCVR_RXp4 XCVR_TXp4 XCVR_RXn4 XCVR_TXn4 XCVR_RXp3 XCVR_TXp3 XCVR_RXn3 XCVR_TXn3 XCVR_RXp2 XCVR_TXp2 XCVR_RXn2 26 28 30 32 34 XCVR_TXn2 XCVR_RXp1 XCVR_TXp1 XCVR_RXn1 XCVR_TXn1 XCVR_RXp0 XCVR_TXp0 XCVR_RXn0 XCVR_TXn0 SCL 36 38 40 SDA JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO CLKIN0 NC C CLKOUT0 1 42 HD_AB 3 44 VD_AB 5 46 7 48 RSTB_AB 9 SYNC_AB 11 13 15 50 AFECS_AB 52 54 TV60 56 17 58 19 60 SCLK 21 23 SDATA 25 27 29 DAC_CS DAC_CLR 31 33 35 37 39 ADC_CS TV61 TV62 62 64 66 TV63 TV64 68 70 72 TV65 TV66 TV67 TV68 74 76 CS5 78 CS6 80 82 84 86 174173164163162161 88 90 92 94 96 98 Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal* Signal* Signal* Signal* 100 3.3V 12V D +3.3VA J4-C ASP-122952-01 GND TCLKP_AB XCVR_TXp6 GND DOUT0N_A_AB 18 20 XCVR_RXp6 GND DOUT0P_A_AB 16 XCVR_TXn7 GND DOUT1N_A_AB XCVR_RXn7 NC DOUT1P_A_AB XCVR_TXp7 +12V +3.3VA +12V ASP-122952-01 41 GPO6_XV21_SHPB_DVAL_AB 102 43 104 45 106 47 110 SYNC_CD 51 53 112 TV2 114 AFECS_CD 55 116 57 118 59 120 61 122 63 124 65 126 67 128 69 130 71 132 73 134 75 136 77 138 79 140 81 142 83 144 85 146 87 148 89 150 91 152 93 154 95 156 97 158 99 Signal Signal Signal 12V 108 RSTB_CD 49 Signal 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal* Signal* Signal* Signal* 160 3.3V PSNTn 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 +3.3VD 135 137 +3.3VD 139 1 141 143 145 U38 147 16 LTC1665CGN 149 6 2 151 2 8 155 7 3 SCLK DAC_CS 157 DAC_CLR 159 VoutB 4 CS/LD VoutC CLR VoutD DIN VoutE Dout VoutF 11 5 9 V15_EN TV32 TV33 TV27 TV52 TV54 TV47 TV45 TV53 VoutA 153 12 13 14 VoutG 15 VoutH 168167166165 C Vcc GND GND GND GND GND GND GND C170 .1uF 25V Vref 10 GND 2 1 C171 10UF 16V 172171170169 ESD_EN HCLK_EN VCLK_EN OSC_EN VAB_EN VAB_ADJ DEV_ID_EN GND 1 1 +3.3VD R94 10K 1% U39 ADC081S021 1 2 Vdd 4 SCLK 5 DOUT0N_B_CD B DOUT1P_B_CD DOUT1N_B_CD TCLKP_CD TCLKN_CD 15 17 19 21 23 25 DOUT0P_A_CD DOUT0N_A_CD DOUT1P_A_CD DOUT1N_A_CD 27 29 31 33 35 37 39 XCVR_TXp7 XCVR_RXp7 XCVR_TXn7 XCVR_RXn7 XCVR_TXp6 XCVR_RXp6 XCVR_TXn6 XCVR_RXn6 XCVR_TXp5 XCVR_RXp5 XCVR_TXn5 XCVR_RXn5 XCVR_TXp4 XCVR_RXp4 XCVR_TXn4 XCVR_RXn4 XCVR_TXp3 XCVR_RXp3 XCVR_TXn3 XCVR_RXn3 XCVR_TXp2 XCVR_RXp2 XCVR_TXn2 XCVR_RXn2 XCVR_TXp1 XCVR_TXn1 XCVR_TXp0 XCVR_TXn0 XCVR_RXp1 XCVR_RXn1 XCVR_RXp0 XCVR_RXn0 SDA SCL JTAG_TCK JTAG_TMS JTAG_TDO JTAG_TDI CLKOUT0 CLKIN0 2 41 4 43 6 45 8 47 10 49 12 51 14 53 16 55 18 57 20 59 22 61 24 63 26 65 28 67 30 69 32 71 34 73 36 75 38 77 40 79 83 NC NC GND GND GND GND 81 85 161 162163164173174 87 89 91 93 95 97 Signal Signal Signal 3.3V 12V Signal Signal Signal Signal 3.3V 12V Signal Signal Signal Signal 3.3V 12V Signal Signal Signal Signal 3.3V 12V Signal Signal Signal Signal 3.3V 12V Signal Signal Signal Signal 3.3V 12V Signal Signal Signal Signal 3.3V 12V Signal Signal Signal Signal 3.3V 12V Signal Signal Signal Signal 3.3V 12V Signal* Signal* Signal* Signal* 3.3V GND 99 Signal 42 101 44 103 46 105 48 107 50 109 52 54 113 56 115 58 117 60 119 62 121 64 123 66 125 68 127 70 129 72 133 76 135 78 137 80 139 82 143 86 145 88 147 90 149 92 153 96 155 98 157 100 159 Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal 3.3V Signal Signal Signal 3.3V Signal Signal Signal 3.3V Signal Signal Signal 3.3V 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 12V Signal* Signal* Signal* Signal* B 120 12V Signal SDATA 118 12V Signal SDATA 116 12V Signal 106 114 12V Signal SCLK 112 12V Signal SCLK 110 12V Signal 104 108 12V Signal 2GND 102 12V 3.3V 156 158 160 3.3V 12V 165166167168 Signal 3.3V 151 94 Signal 3.3V 141 84 Signal 3.3V 131 74 Signal 3.3V 111 CS\ ADC_CS PSNTn GND 13 DOUT0P_B_CD ASP-122952-01 DEV_ID Vin 6 GND 11 ASP-122952-01 GND 9 ASP-122952-01 GND 7 J1-C GND 5 J1-B GND 3 J1-A GND 1 3 DIN 20361636-Revision 2 Bare Board 169170171 172 20361640-Revision 3 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Board to Board Interconnect Gen2 Evaluation System 72 pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361636 / 20361640 PROGRAM CADSTAR SHEET 1 5 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE AD Conversion Channel A,B D CCDinA CCDinA CCDinB CCDinB CCDinC CCDinD CCDinD TCLKP_AB TCLKN_AB TCLKN_AB DOUT0P_A_AB DOUT0P_A_AB DOUT0N_A_AB DOUT0N_A_AB DOUT1P_A_AB DOUT1P_A_AB DOUT1N_A_AB DOUT1N_A_AB DOUT0P_B_AB DOUT0P_B_AB DOUT0N_B_AB DOUT0N_B_AB DOUT1P_B_AB DOUT1P_B_AB DOUT1N_B_AB DOUT1N_B_AB AD Conversion Channel C,D CCDinC TCLKP_AB TCLKP_CD TCLKP_CD TCLKN_CD TCLKN_CD DOUT0P_A_CD DOUT0P_A_CD DOUT0N_A_CD DOUT0N_A_CD DOUT1P_A_CD DOUT1P_A_CD DOUT1N_A_CD DOUT1N_A_CD DOUT0P_B_CD DOUT0P_B_CD DOUT0N_B_CD DOUT0N_B_CD DOUT1P_B_CD DOUT1P_B_CD DOUT1N_B_CD DOUT1N_B_CD SYM DESCRIPTION DATE APPROVAL D BUFFERED USER ACCESS TO SIGNALS CONTROL OF THESE SIGNALS IS PROGRAMMED THROUGH THE AFE 74LVC2G04DBVR 104363-4 +3.3VD C 3 Timing Horizontal_Clocks GIO 1 OSC_VDD BD1 BLM18AG601SN1D SCLK 2 1 4 U25 40.0 MHZ C106 .1uF 25V OSC_EN OSC_EN 1 3 EN SDATA SDATA AFECS_AB AFECS_AB AFECS_CD AFECS_CD OUT U42-B HD_AB HD_AB VD_AB 1=S1 0=S2 GPO1_STROBE_AB 1 5 1 6 R101 15.0K 1% GPO1_STROBE_AB GPO3_SCKA_AB SYNC_CD GPO6_XV21_SHPB_DVAL_AB RSTB_AB RSTB_AB GPO7_XV23_VDR_EN_AB RSTB_CD RSTB_CD GND 2 AFE_CLOCK_AB U24-B 2 C 0=S1 1=S2 GPO3_SCKA_AB 1 GPO5_SCKB_AB U44 ZXMD63C03X 1=S1 0=S2 S 3 D 5 D 6 4 D 7 3 NFET D 8 G S 1 PFET 4 G 2 B R100 15.0K 1% GPO6_XV21_SHPB_DVAL_AB TV59 S2 Q2 3904 GPO4_XSUBCK_SHPA_AB GPO5_SCKB_AB SYNC_AB 4 2 U42-A GPO2_MSHUT_AB GPO1_CD 3 2 J3 74LVC2G04DBVR VD_AB E C97 .1uF 25V 2 J3 J3 GPO1_CD GPO2_CD GPO2_CD GPO3_CD GPO3_CD GPO4_CD GPO4_CD GPO5_CD GPO5_CD GPO6_CD GPO6_CD GPO7_CD GPO7_CD 2 S1 5 1 C J3 +6V +3.3VD GPO4_XSUBCK_SHPA_AB SYNC_CD VCC 1 SCLK SYNC_AB 2 4 J3 74LVC2G04DBVR 5 1 6 AFE_CLOCK_CD 2 U24-A 74LVC2G04DBVR RGBa_AFE RGBa_AFE H2SLa_AFE H2SLa_AFE H1ab_AFE H1ab_AFE H2ab_AFE B H2ab_AFE H1Bb_SD_AFE H1Bb_SD_AFE H2Bb_SD_AFE H2Bb_SD_AFE H2SLb_AFE B Change Phase to support Single or Dual clocking H2SLb_AFE RGBb_AFE Vertical Clocks RGBb_AFE Use Mode 3 Configuration H1A=H3A=/H2A=/H4A H1B=H3B=/H2B=/H4B GPO7_XV23_VDR_EN_AB V1B_3rd_AFE V1B_3rd_AFE V1B_AFE RGBc_AFE RGBc_AFE H2SLc_AFE H2cd_AFE H1Bd_SD_AFE V2B_AFE V3B_AFE V3B_AFE V4B_AFE V4B_AFE V1T_3rd_AFE V1T_AFE V1T_AFE H1cd_AFE V2T_AFE V2T_AFE H2cd_AFE V3T_AFE V3T_AFE V4T_AFE V4T_AFE H1Bd_SD_AFE H2Bd_SD_AFE V2B_AFE V1T_3rd_AFE H2SLc_AFE H1cd_AFE V1B_AFE H2Bd_SD_AFE H2SLd_AFE H2SLd_AFE RGBd_AFE RGBd_AFE Change Phase to support Single or Dual clocking SUBCK Use Mode 3 Configuration H1A=H3A=/H2A=/H4A H1B=H3B=/H2B=/H4B TV46 SUBCK FDG_AB_AFE FDG_AB_AFE FDG_CD_AFE FDG_CD_AFE 20361636-Revision 2 Bare Board 20361640-Revision 3 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Analog Front End page 1 Gen2 Evaluation System 72 pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361636 / 20361640 PROGRAM CADSTAR SHEET 1 6 of 17 __ 4 3 2 1 TW TS TW D TW DIFF Pair1 TS TW DIFF Pair2 TG D D GROUND +1.8V_A +1.8V_A +1.8V_A Keep TW, TS and D constant over trace length Keep TS <2TW Avoid Vias where possible Keep D>2TS Avoid 90 deg bends Design TW and TG for 50 ohms +1.8V_A +1.8V_A +1.8V_A 1 2 2 C159 .1uF 25V 2 A2 CCDIN_A 2 CCDinA_ B10 CDS L1 AVDD_B AVDD_A DC_RESTORE-> C160 .1uF 25V 1 2 Tw = .008 (8mil) Ts = .004 (4mil) D = .008 (0mil) Tg = .005 (5 mil) 1oz copper 4.2 Dielectric Constant between layer stack. 2 2 B3 CCDinA 2 C184 .1uF 25V L2 L4 L10 LVDD_B 2 C157 4.7UF_6.3V 1 LVDD_A C168 .1uF 25V 1 C177 C183 .1uF .1uF 25V 25V DVDD 1 C169 4.7UF_6.3V 1 C178 .1uF 25V 1 DVDD 1 1 CDS and Analog to Digital Converter 14-Bit ADC VGA C Reduced Range LVDS CLAMP C167 .1uF 25V A11 CCDinB 1 CCDIN_B CDS 2 CCDinB_ 14-Bit ADC VGA TCLKP M7 TCLKP_AB TCLKP_AB TCLKN L7 TCLKN_AB TCLKN_AB DOUT0P_A M6 DOUT0P_A_AB DOUT0P_A_AB DOUT0N_A L6 DOUT0N_A_AB DOUT0N_A_AB DOUT1P_A M5 DOUT1P_A_AB DOUT1P_A_AB DOUT1N_A L5 DOUT1N_A_AB DOUT1N_A_AB DOUT0P_B M9 DOUT0P_B_AB DOUT0P_B_AB DOUT0N_B L9 DOUT0N_B_AB DOUT0N_B_AB DOUT1P_B M8 DOUT1P_B_AB DOUT1P_B_AB DOUT1N_B L8 DOUT1N_B_AB DOUT1N_B_AB C +3.3VD C161 .1uF 25V CLAMP A4 1 REFT_A(1.4V) 2 C11 LDOIN_B C163 .1uF 25V 1 1 REFB_A(0.4V) 2 C2 LDOIN_A 1 C181 4.7UF_6.3V A5 C166 .1uF 25V +1.8V_A 2 C180 .1uF 25V 2 A9 1 REFT_B(1.4V) 2 LDOOUT_A C164 .1uF 25V B B1 LDO_A B A8 1 2 REFB_B(0.4V) LDOIN_B A3 B4 B5 A10 B9 B8 M2 M4 M10 B2 LDOOUT_B B12 LDOVSS_B LDOVSS_A LVSS_B LVSS_A DVSS AVSS_3B AVSS_2B AVSS1_B AVSS_3A AVSS1_A U41-A AD9928 AVSS_2A LDO_B B11 20361636-Revision 2 Bare Board 20361640-Revision 3 Completed Assy UNLESS OTHERWISE SPECIFIED MATERIAL DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN A 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 4 NEXT ASSY FINAL ASSY QUANITY REQD 3 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. DR FINISH NAME Analog Front End page 2 SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECO NO. Jim DiBella SIZE C DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. REL DATE 2 4/8/2016 A Gen2 Evaluation System 72 pin PGA Imager Board QA CHK SCALE DWG NO. 20361636 / 20361640 PROGRAM CADSTAR 1 SHEET 7 of 17 __ 4 3 2 1 TW TS TW D TW DIFF Pair1 TS TW DIFF Pair2 TG D D GROUND +1.8V_B +1.8V_B +1.8V_B Keep TW, TS and D constant over trace length Keep TS <2TW Avoid Vias where possible Keep D>2TS Avoid 90 deg bends Design TW and TG for 50 ohms +1.8V_B +1.8V_B +1.8V_B 1 2 2 C38 .1uF 25V 2 A2 CCDIN_A 2 CCDinC_ B10 CDS L1 AVDD_B AVDD_A DC_RESTORE-> C36 .1uF 25V 1 2 Tw = .008 (8mil) Ts = .004 (4mil) D = .008 (0mil) Tg = .005 (5 mil) 1oz copper 4.2 Dielectric Constant between layer stack. 2 2 B3 CCDinD 2 C5 .1uF 25V L2 L4 L10 LVDD_B 2 C39 4.7UF_6.3V 1 LVDD_A C28 .1uF 25V 1 C10 C2 .1uF .1uF 25V 25V DVDD 1 C27 4.7UF_6.3V 1 C9 .1uF 25V 1 DVDD 1 1 CDS and Analog to Digital Converter 14-Bit ADC VGA C Reduced Range LVDS CLAMP C29 .1uF 25V A11 CCDinC 1 CCDIN_B CDS 2 CCDinD_ 14-Bit ADC VGA TCLKP M7 TCLKP_CD TCLKP_CD TCLKN L7 TCLKN_CD TCLKN_CD DOUT0P_A M6 DOUT0P_A_CD DOUT0P_A_CD DOUT0N_A L6 DOUT0N_A_CD DOUT0N_A_CD DOUT1P_A M5 DOUT1P_A_CD DOUT1P_A_CD DOUT1N_A L5 DOUT1N_A_CD DOUT1N_A_CD DOUT0P_B M9 DOUT0P_B_CD DOUT0P_B_CD DOUT0N_B L9 DOUT0N_B_CD DOUT0N_B_CD DOUT1P_B M8 DOUT1P_B_CD DOUT1P_B_CD DOUT1N_B L8 DOUT1N_B_CD DOUT1N_B_CD C +3.3VD C35 .1uF 25V CLAMP A4 1 REFT_A(1.4V) 2 C11 LDOIN_B C33 .1uF 25V 1 1 REFB_A(0.4V) 2 C2 LDOIN_A 1 C6 4.7UF_6.3V A5 C30 .1uF 25V +1.8V_B 2 C7 .1uF 25V 2 A9 1 REFT_B(1.4V) 2 LDOOUT_A C32 .1uF 25V B B1 LDO_A B A8 1 2 REFB_B(0.4V) LDOIN_B A3 B4 B5 A10 B9 B8 M2 M4 M10 B2 LDOOUT_B B12 LDOVSS_B LDOVSS_A LVSS_B LVSS_A DVSS AVSS_3B AVSS_2B AVSS1_B AVSS_3A AVSS1_A U1-A AD9928 AVSS_2A LDO_B B11 20361636-Revision 2 Bare Board 20361640-Revision 3 Completed Assy UNLESS OTHERWISE SPECIFIED MATERIAL DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN A 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 4 NEXT ASSY FINAL ASSY QUANITY REQD 3 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. DR FINISH NAME Analog Front End page 3 SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECO NO. Jim DiBella SIZE C DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. REL DATE 2 4/8/2016 A Gen2 Evaluation System 72 pin PGA Imager Board QA CHK SCALE DWG NO. 20361636 / 20361640 PROGRAM CADSTAR 1 SHEET 8 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE SYM DESCRIPTION DATE APPROVAL D D +3.3VD E9 K8 HD_AB K7 VD_AB G10 SCK GPO6 H11 SDATA GPO7 SL H1A Horizontal Clock Driver SYNC H2A RSTB H3A J8 +3.3VD H4A A6 C1 RG_A GPO7_XV23_VDR_EN_AB K7 H2ab_AFE J6 SYNC_CD B7 H2B CLO C162 .1uF 25V H3B H4B F12 F11 HL_B 2 C8 J5 K5 H1 C5 F3 F10 D3 HD GIO VD Horizontal Clock Driver H1A SYNC H2A RSTB H3A F1 H1Bd_SD_AFE F2 H2Bd_SD_AFE E1 E2 D1 H2SLd_AFE HL_A C1 RGBa_AFE RGBd_AFE RG_A B6 CLI H1Bb_SD_AFE H1B B7 H2Bb_SD_AFE H2B CLO 1 C34 .1uF 25V H3B H4B F12 H1cd_AFE F11 H2cd_AFE E12 E11 D12 H2SLb_AFE H2SLc_AFE HL_B 2 C12 RGBb_AFE RGBc_AFE RG_B RGVSS_B RGVSS_A HVSS_B HVSS_A TEST0_C5 TEST1_H1 TEST1_J5 TCVSS IOVSS M11 TEST1_K5 RG_B Timing Generator Control Registers CLIVDD E11 C12 GPO7_CD GPO7 SL A6 E12 D12 RGVDD_B SDATA H4A AFE_CLOCK_CD H1B RGVDD_A H11 +3.3VD H2SLa_AFE GPO6_CD GPO6 J8 RSTB_CD CLI 1 G10 E9 H1ab_AFE B6 AFE_CLOCK_AB GPO5_CD GPO5 E2 HL_A GPO4_CD J10 SCK D10 M11 C8 J5 K5 B 1 1 R99 0 H1 C5 F3 F10 D3 D10 B SLAVE R97 0 MASTER C GPO3_CD GPO4 F9 2 GPO2_CD GPO2 GPO5_SCKB_AB GPO6_XV21_SHPB_DVAL_AB C8 4.7UF_6.3V GPO1_CD G9 GPO4_XSUBCK_SHPA_AB E1 D1 CLIVDD H9 GPO1 K11 J12 1 C11 .1uF 25V 2 H10 IOVSS RSTB_AB F2 2 GPO3 K8 VD 1 C1 4.7UF_6.3V D11 GPO3_SCKA_AB GIO J6 SYNC_AB GPO2_MSHUT_AB AFECS_CD F1 D2 U1-C AD9928 GPO1_STROBE_AB Timing Generator Control Registers HD E10 2 1 C4 .1uF 25V RGVSS_B GPO5 1 C37 .1uF 25V 2 RGVSS_A J10 E3 HVSS_B GPO2 GPO4 AFECS_AB L11 HVSS_A G9 K11 SDATA 2 2 TEST0_C5 RGVDD_A H9 GPO1 H10 F9 2 1 C3 .1uF 25V A7 GPO3 SCLK 1 C31 .1uF 25V D11 U41-C AD9928 J12 2 +3.3VD 1 C179 4.7UF_6.3V TCVDD D2 2 1 C176 .1uF 25V RGVDD_B E10 HVDD_B IOVDD TCVDD C E3 HVDD_A L11 2 1 C185 4.7UF_6.3V HVDD_B 2 2 1 C182 .1uF 25V HVDD_A 1 C158 .1uF 25V TEST1_H1 1 C165 .1uF 25V +3.3VD +3.3VD +1.8V_B 1 A7 +3.3VD TEST1_K5 +1.8V_A +3.3VD +3.3VD TEST1_J5 +3.3VD IOVDD +3.3VD TCVSS +3.3VD 2 2 20361636-Revision 2 Bare Board 20361640-Revision 3 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Analog Front End page 4 Gen2 Evaluation System 72 pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361636 / 20361640 PROGRAM CADSTAR SHEET 1 9 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE For 3V logic levels of V clock outputs Set: Vh to > 8VDC Vm to +3.3 Vl to 0VDC SYM DESCRIPTION DATE APPROVAL +3.3VD MASTER Use GIO for Sub Clock D D 3 Level Clocks K4 VDD1 (logic supply) J4 XV16(XSG1) VDD1 (logic supply) V1A D7 V1B D6 FDG_AB_AFE K2 VDD2 (logic supply) +Vhigh XV1 J2 VDD2 (logic supply) E4 +3.3VD XV17(XSG2) XVVDD XV18(XSG3) 1 1 K9 C154 .1uF 25V C155 4.7UF_25V C9 VH1 V2A C3 V2B D5 V3A D4 FDG_CD_AFE XV2 VH2 SLAVE XV19(XSG4) 2 2 XV20(XSG5) K10 C10 2 C153 4.7UF_25V K4 XV3 V3B VM2 2 VDD1 (logic supply) G12 J4 XV4 J9 1 D9 VDD2 (logic supply) G11 VDD2 (logic supply) E4 V5 H12 XV6 GPO7_XV23_VDR_EN_AB V6 J11 XV18(XSG3) K9 C9 V2B_AFE VH1 DNC_C4 DNC_J7 C XV7 U41-B AD9928 A1 V7 J1 K10 C10 NC_A1 XV8 V8 K12 VM1 V3B_AFE XV4 XV9 V9 L12 J9 V4B_AFE H4 D9 NC_H4 J3 XV10 NC_J3 V10 H3 V11 G4 XV5 VL2 V3B G12 V4 G11 V5 H12 V6 J11 V7 J1 V8 K12 V9 L12 V10 H3 V11 G4 V12 H2 V13 G3 V14 K3 V15 L3 SUBCK D8 C XV23(XSG8) V1T_AFE XV6 XV11 D4 XV22(XSG7) NC_K6 NC_M1 V3A VL1 K6 M1 D5 XV21(XSG6) NC_A12 NC_G1 V2B XV3 VM2 A12 G1 C3 XV19(XSG4) XV20(XSG5) J7 V2A XV2 VH2 VDR_EN C4 D6 XV17(XSG2) V1B_AFE XV24(XSG9) M3 V1B XVVDD XV23(XSG8) -Vlow D7 XV1 J2 V1B_3rd_AFE VL1 VL2 V1A K2 V4 XV22(XSG7) XV5 XV16(XSG1) VDD1 (logic supply) XV21(XSG6) C152 .1uF 25V 1 VM1 3 Level Clocks V1T_3rd_AFE V2T_AFE M3 V3T_AFE C4 XV24(XSG9) VDR_EN M12 NC_M12 XV12 V12 H2 DNC_C4 U1-B AD9928 J7 XV13 V13 DNC_J7 G3 A1 V4T_AFE XV7 NC_A1 XV8 A12 XV14 V14 NC_A12 K3 G1 NC_G1 XV9 H4 XV15 V15 NC_H4 L3 J3 XV10 NC_J3 K6 NC_K6 M1 C7 XSUBCK VMM SUBCK NC_M1 D8 XV11 M12 SUBCK NC_M12 XSUBCNT(GPO8) XV12 C6 VLL G2 VSS2 VSS1 -Vlow XVVSS XV13 K1 XV14 XV15 F4 C7 XSUBCK VMM XSUBCNT(GPO8) C6 G2 VSS2 VSS1 B XVVSS VLL K1 B F4 20361636-Revision 2 Bare Board 20361640-Revision 3 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Analog Front End page 5 Gen2 Evaluation System 72 pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361636 / 20361640 PROGRAM CADSTAR SHEET 1 10 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE SYM DESCRIPTION DATE APPROVAL C121 .1uF 25V H1Bb_SD_AFE H1Bb_SD_AFE TV41 1 U31 74LCX541BQX 2 1 20 R65 200K 1% D 2 K1 VCC 2 CR4-A HSMS-2805 18 3 4 16 A1 -VH 5 13 2 1 11 C124 .1uF 25V H2Bb_SD 12 9 1 H2SLb H2Bb_SD 8 H2Bb_SD_AFE TV42 H2SLb 14 7 C122 .1uF 25V H2Bb_SD_AFE 15 6 -VH D 17 H1Bb_SD RESET CLOCKS NEED TO BE LEVEL SHIFTED Rb H1Bb_SD 1 Rb 2 1 R66 200K 1% 2 19 K2 1 CR4-B HSMS-2805 GND K1 PPAD 10 2 21 R68 200K 1% C113 1 .1uF 25V A2 -VH -VH CR13-A HSMS-2805 A1 2 -VH -VH C123 .1uF 25V -VRESET H2SLb_AFE H2SLb_in TV43 H2SLb_AFE 1 2 U30 74LCX541BQX K1 1 CR5-A HSMS-2805 20 VCC 2 C R67 200K 1% 3 A1 5 7 9 TV44 RGBb_in 1 H2Sb H2Sb 14 H2Sa H2Sa 12 H1Sa H1Sa C 11 1 RGBb_AFE RGBb_AFE 16 13 8 C125 .1uF 25V H1Sb 15 6 -VH H1Sb 17 4 2 18 19 2 1 GND PPAD 10 K2 2 21 C86 1 .1uF 25V CR5-B HSMS-2805 R69 200K 1% -VH A2 2 -VH C114 .1uF 25V -VH RGBa_AFE RGBa_AFE TV35 Single H1_AFE = H1SL,H1BL,H1SR,H2BR* H2_AFE = H2SL,H2BL,H2SR,H1BR* RGBa_in 1 2 Dual H1_AFE = H1SL,H1BL,H1SR,H1BR* H2_AFE = H2SL,H2BL,H2SR,H2BR* 1 K1 R60 200K 1% 2 C116 .1uF 25V H2SLa_AFE H2SLa_AFE TV36 1 CR2-A HSMS-2805 A1 -VH H2SLa_in 2 1 B R62 200K 1% K2 CR2-B HSMS-2805 C115 .1uF 25V 20 A2 2 B U29 74LCX541BQX RESET CLOCKS NEED TO BE LEVEL SHIFTED VCC 2 18 3 H1Ba 17 Ra H1Ba 1 Ra 2 -VH 4 5 C117 .1uF 25V H2ab_AFE H2ab_AFE TV37 16 6 14 7 1 2 2 H1ab_AFE H1ab_AFE TV381 K2 H2SLa R61 200K 1% 11 2 CR14-B HSMS-2805 A2 1 CR3-A HSMS-2805 19 GND PPAD 10 C118 .1uF 25V 1 K1 A1 -VH H2Ba 12 9 R63 200K 1% H2SLa 13 8 1 H2Ba 15 2 C119 .1uF 25V 21 -VH -VRESET 1 -VH -VH 2 1 -VH TV40 2 CR3-B HSMS-2805 A2 TV39 K2 R64 200K 1% 20361636-Revision 2 Bare Board -VH 20361640-Revision 3 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH AB Hclock drivers Gen2 Evaluation System 72 pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361636 / 20361640 PROGRAM CADSTAR SHEET 1 11of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE SYM DESCRIPTION DATE APPROVAL C88 .1uF 25V H1Bd_SD_AFE 1 H1Bd_SD_AFE TV18 U22 74LCX541BQX 2 1 20 R50 200K 1% D 2 K2 VCC 2 CR17-B HSMS-2805 18 3 17 4 A2 5 -VH H2Bd_SD_AFE 1 TV19 H1Bd_SD H2Bd_SD H2Bd_SD H2SLd H2SLd D 14 7 C89 .1uF 25V H2Bd_SD_AFE 15 6 -VH H1Bd_SD 16 13 8 C91 .1uF 25V 12 9 11 Rd 1 2 1 RESET CLOCKS NEED TO BE LEVEL SHIFTED Rd 2 1 R51 200K 1% 2 K1 19 1 CR17-A HSMS-2805 GND PPAD 10 K2 2 21 C80 .1uF 25V 1 A1 -VH -VH CR13-B HSMS-2805 R53 200K 1% A2 2 -VH -VH C90 .1uF 25V -VRESET H2SLd_AFE H2SLd_AFE H2SLd_in 1 TV20 2 U20 74LCX541BQX K2 1 C R52 200K 1% 20 CR18-B HSMS-2805 VCC 2 18 3 A2 4 16 5 2 14 7 C H2Sc H2Sd H2Sd H1Sd H1Sd 11 1 RGBd_in 1 TV21 12 9 RGBd_AFE RGBd_AFE H2Sc 13 8 C92 .1uF 25V H1Sc 15 6 -VH H1Sc 17 19 2 1 GND K1 R54 200K 1% CR18-A HSMS-2805 2 21 C93 .1uF 25V 1 -VH A1 2 PPAD 10 -VH C81 .1uF 25V RGBc_AFE -VH RGBc_AFE 1 TV12 Single H1_AFE = H1SL,H1BL,H1SR,H2BR* H2_AFE = H2SL,H2BL,H2SR,H1BR* RGBc_in 2 Dual H1_AFE = H1SL,H1BL,H1SR,H1BR* H2_AFE = H2SL,H2BL,H2SR,H2BR* 1 K2 R43 200K 1% A2 2 C83 .1uF 25V 1 TV13 -VH H2SLc_in H2SLc_AFE H2SLc_AFE CR15-B HSMS-2805 2 1 B K1 R45 200K 1% CR15-A HSMS-2805 20 A1 2 B U19 74LCX541BQX VCC 2 18 3 17 -VH 4 C84 .1uF 25V H2cd_AFE TV14 5 15 7 13 6 H2cd_AFE 1 16 2 14 8 1 12 9 R46 200K 1% 2 C85 .1uF 25V H1cd_AFE TV15 H2Bc H1Bc 11 H2SLc C82 .1uF 25V H2Bc RESET CLOCKS NEED TO BE LEVEL SHIFTED Rc H1Bc 1 Rc 2 K2 1 CR16-B HSMS-2805 1 19 K1 A2 -VH H2SLc GND PPAD 10 21 C126 .1uF 25V 1 -VH CR14-A HSMS-2805 R44 200K 1% 2 A1 2 -VH -VH H1cd_AFE 1 2 1 K1 R47 200K 1% 2 A1 -VRESET CR16-A HSMS-2805 20361636-Revision 2 Bare Board A 20361640-Revision 3 Completed Assy TV17 -VH TV16 -VH UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH CD H Clock Drivers Gen2 Evaluation System 72 pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361636 / 20361640 PROGRAM CADSTAR SHEET 1 12 __ of 17 8 7 6 5 4 3 2 1 REVISIONS ZONE SYM DESCRIPTION DATE APPROVAL +Vhigh V3rd signal swings from Vmid to +9 1 2 2 S PFET V1T_3rd_AFE A TP7 TP10 1 K NFET K 1 S 1 2 5 D 7 NFET D 8 G S 1 C22 1000PF 2 G D TP12 D 6 1 2 R3 220 2 8 D C15 1000PF C24 1000PF 2 3 V4T_AFE 7 3 1 A D 6 S 4 G 5 D D 1 CR23 BAT54-04 V4T_AFE 2 3 V1T_3rd_AFE PFET 1 C13 1000PF 2 3 4 G CR19 BAT54-04 signal swings from Vhigh to Vmid (inverting drive control) 1 D U7 ZXMD63C03X V4T 2 .1uF 25V C47 2 1 1 2 PFET V1T_AFE CR22 BAT54-04 C16 1000PF 2 3 V1T_AFE 1 K C12 NOLOAD NFET C14 1000PF 2 1 D 5 D 6 D 7 D 8 V3T_AFE TP11 3 D 5 D 6 V1T V1T 3 V3T_AFE D 7 NFET D 8 G S 1 C21 1000PF 1 C20 1000PF 2 S 1 2 .1uF 25V C40 2 1 C 1 2 K G S 4 G A TP9 2 R2 100 1% 2 -Vlow 2 PFET 1 A 1 1 3 4 G CR20 BAT54-04 TP6 S -Vlow U6 ZXMD63C03X TP13 V3T V3T 2 R7 100 1% C signal swings from Vmid to Vlow (inverting drive control) R10 100 1% R4 100 1% -Vlow U3 ZXMD63C03X V4T 2 R11 100 1% D C41 .1uF 25V U2 ZXMD63C03X R12 100 1% R1 220 1 2 .1uF 25V C45 2 1 1 -Vlow -Vlow -Vlow R6 100 1% -Vlow 1 U4 ZXMD63C03X 2 TP8 CR21 BAT54-04 FDG_CD_AFE C43 1000PF 1 R9 220 1 3 7 NFET D 8 G S 1 V2T V2T 2 2 B C42 .1uF 25V 1 2 -Vlow D 5 D 6 D 7 NFET D 8 G S 1 C18 1000PF 2 1 D TP14 1 2 K S 6 4 G A 3 R5 100 1% R8 220 2 PFET CR28 BAT54-04 2 C49 .1uF 25V 2 D C17 1000PF 1 1 5 C19 1000PF 1 K B D 1 2 3 V2T_AFE U5 ZXMD63C03X 3 4 G A FDGH S PFET V2T_AFE -Vlow TP19 FDG_CD 2 2 -Vlow 20361636-Revision 2 Bare Board 20361640-Revision 3 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Top V Clock Drivers Gen2 Evaluation System 72 pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361636 / 20361640 PROGRAM CADSTAR SHEET 1 13 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE D SYM DESCRIPTION DATE APPROVAL D +Vhigh V3rd signal swings from Vmid to +9 1 2 2 S PFET 4 CR8 BAT54-04 V1B_3rd_AFE CR12 BAT54-04 V4B_AFE TP5 2 3 1 K NFET C70 1000PF 2 D 5 D 6 D 7 D 8 R27 220 4 D 5 D 6 D 7 NFET D 8 G S 1 C78 1000PF 2 3 V4B_AFE 1 K C79 1000PF 2 S 3 G 1 A 2 G S PFET G C72 1000PF TP2 1 2 3 1 A V1B_3rd_AFE 1 U18 ZXMD63C03X 1 1 2 TP16 V4B 2 .1uF 25V C61 2 1 C 1 2 PFET C71 1000PF 1 1 K C69 NOLOAD PFET NFET C73 1000PF 2 D 5 D 6 D 7 TP4 TP15 V1B V1B D 8 C76 1000PF S 1 2 -Vlow .1uF 25V C54 2 1 5 D 7 NFET D 8 G S 1 C77 1000PF 2 G D TP17 D 6 1 K 3 1 2 3 V3B_AFE S 4 G A 2 R30 100 1% 2 1 CR11 BAT54-04 V3B_AFE 2 3 signal swings from Vmid to Vlow (inverting drive control) 2 1 A V1B_AFE 1 3 4 G CR9 BAT54-04 TP1 S C -Vlow U17 ZXMD63C03X V3B V3B 2 R34 100 1% V1B_AFE R33 100 1% R28 100 1% -Vlow U15 ZXMD63C03X V4B 2 R36 100 1% signal swings from Vhigh to Vmid (inverting drive control) C55 .1uF 25V U14 ZXMD63C03X R35 100 1% R29 220 1 2 .1uF 25V C59 2 1 1 -Vlow -Vlow -Vlow R31 100 1% -Vlow 1 2 PFET V2B_AFE FDGH TP3 CR10 BAT54-04 R13 220 1 1 2 2 PFET CR27 BAT54-04 C48 1000PF NFET C23 1000PF 2 TP20 D 7 D 8 1 FDG_AB TP18 D 7 D 8 G S 1 V2B B V2B 2 2 C58 .1uF 25V 1 2 -Vlow -Vlow 2 R14 220 1 5 D 6 1 K 2 D 5 NFET C75 1000PF 1 2 3 K 3 D D 6 1 4 G A FDG_AB_AFE S C74 1000PF 2 3 V2B_AFE 3 1 A C44 .1uF 25V U8 ZXMD63C03X S 4 G R32 100 1% B U16 ZXMD63C03X G S 1 2 -Vlow 20361636-Revision 2 Bare Board 20361640-Revision 3 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Bottom V Clock Drivers Gen2 Evaluation System 72 pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361636 / 20361640 PROGRAM CADSTAR SHEET 1 14 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE VAB_ADJ VAB_ADJ VAB_EN VAB_EN SUBCK D VSUB SYM DESCRIPTION DATE APPROVAL VSUB VSUB SUBCK GPO1_STROBE_AB D GPO1_STROBE_AB Rc Video Outputs H2SLc H1Sc H1Bc H2Sc H2Bc CCDoutC CCDinC CCDoutD CCDinD CCDinC H1Sd H1Bd_SD CCDinD H2Sd H2Bd_SD H2SLd 1 Rd C87 2 .1uF 25V Rd VSUB H2SLd VRD_T H2Bd_SD H1Bd_SD +15VA H1Sd H2Sd 1 H2Sc H1Sc U21 KAI-29050 H1Bc H2Bc H2SLc Rc +15VA R39 27K 1% 1 VRD_T +15VA 2 1 -VOG_T -2 R24 49.9K 1%VRD_T C V3T 71 2 +12VDC 1 ESD 72 1 VDDc 67 V4T 70 GND 65 V2T 68 Rc 2 H2SLc 63 61 VOUTc RDc 66 64 H1Bc 59 OGc 60 H2Sc 57 H2Bc 62 R23 200K 1% C66 .1uF 25V 2 V1T 69 N/C 55 SUB 53 H1Sc 58 H2Sd 51 H1Bd H2SLd 49 47 H1Sd H2Bd 56 54 FDGcd 52 50 Rd 45 OGd 48 GND VDDd 43 41 RDd VOUTd 46 44 V1T 39 V2T 42 R38 39.2K 1% V3T 37 V4T 40 C -VH DevID 38 -5V FDGcd -VOG_T DEV_ID -VOG_T -VESD FDG_CD V1T C V2T D V3T V4T V1B A V2B V3B V4B A B FDG_AB VSUB VRD_B +15VA VRD_B +15VA FDGab FDGab 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 N/C V1B V2B VOUTA 5 7 VDDa RDa OGa 9 GND 11 Ra H2Ba H1Sa 13 15 H2SLa H1Ba H2Sa H1Sb H2Bb 17 SUB 19 N/C 21 H2Sb H2Sb H1Sb H1Sa H2Sa OGb 25 RDb 27 H1Bb H2SLb VOUTb V2B 29 Rb 31 V4B 33 GND VDDb ESD 35 V1B V3B B -VESD Rb Ra H2Ba H1Ba B H2SLa 23 H2SLb V3B 3 H1Bb_SD H2Bb_SD V4B 1 -VOG_B -VOG_B Ra H2SLa H1Sa H1Ba CCDoutB CCDinB CCDoutA CCDinA CCDinB H2Sa H2Ba CCDinA H1Sb H1Bb_SD H2Sb H2Bb_SD +15VA H2SLb Rb 1 1 C120 2 .1uF 25V R84 49.9K 1%VRD_B 2 1 +12VDC 1 C139 .1uF 25V 2 2 20361636-Revision 2 Bare Board 1 1 A R71 27K 1% 2 20361640-Revision 3 Completed Assy -VOG_B R85 200K 1% -2 UNLESS OTHERWISE SPECIFIED R70 39.2K 1% WHERE TOTAL TOLERANCE OS .001 + - -VH 3 PL DEC TOL + - -5V ANGULAR TOL USED ON 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL 2 PL DEC TOL APPLICATION 7 A DIMENSIONS APPLY AFTER FINISH DIM. ARE IN NEXT ASSY 8 MATERIAL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Imager Interface Gen2 Evaluation System 72 pin PGA Imager Board Imager PCB Interface QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361636 / 20361640 PROGRAM CADSTAR SHEET 1 15of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE SYM DESCRIPTION DATE Assy 20361640-Revision 2 to 3 Change R75 from 200K to 196K Change R89 from 71.5K to 63.4K C4 APPROVAL April 2016 D D VAB_ADJ U33 LT3050 +16V 6 OUT IN OUT 5 1 7 R75 196K 1% 4 VAB_EN VAB_EN VAB 8 IN SHDN 1 3 R90 100K 1% 2 2 C 9 FAULT 1 C145 1uF 25V 10% 2 1 ADJ 11 VAB_ADJ 2 1 1 Imon 1 1 1 C130 .1uF 25V C129 4.7UF_25V R88 9.09K 1% 12 Imax R89 63.4K 1% 2 2 C 2 C128 .01uF R74 2 15.0K 1% 2 1 Imin REF/BYP 1 C144 .01uF 2 GND GND 10 2 VAB LDO Current Limit programmed to 800umA Adjustable 5V to 15.5V +16V V16 +3.3VD 1 FAULT 1 Q1 BC847BVN 2 R92 4 B2 1 2 1 K2 E2 C148 .1uF 25V 100K 1% 2 2 5 Q2 C131 1uF 25V 10% 5 C2 3 4 2 GPO1_STROBE_AB 3 B 1 C1 C147 .1uF 25V U37 7SZ08 1 VSUB VSUB 2 VSUB 6 2 VSUBGND CR6-B HSMS-2805 R91 10K 1% 1 A2 C146 .1uF 25V B 1 B1 Q1 2 E1 R76 10K 1% 1 ES_LOW_CL 1 Scope GND 2 1 R78 10K 1% K1 R77 0 CR6-A HSMS-2805 2 2 2 A1 C133 .1uF 25V 1 SUBCK C132 1uF 25V 10% 1 -12V 2 Option to use TTL control for ES or To directily Drive CCD ES from AFE Populate the corrisponding coupling cap for the desired source of the ES 20361636-Revision 2 Bare Board 20361640-Revision 3 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH VSUB and Electronic Shutter Gen2 Evaluation System 72 pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361636 / 20361640 PROGRAM CADSTAR SHEET 1 16 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE SYM DESCRIPTION DATE APPROVAL D D +15VA 1 1 R22 49.9K 1% 1 C65 .1uF 25V C 4 2 5 ISF VCC C64 .1uF 25V 2 C68 .1uF 25V ISF 2 1 CCDinC OUT VEE U12 ADA4800 2 4 2 5 VCC C53 .1uF 25V C 2 3 IN CCDinD OUT EPAD VEE 7 2 IDRV 1 CCDoutD C67 .1uF 25V 1 2 3 IN 1 R25 200K 1% 6 2 1 C52 .1uF 25V IDRV 1 R26 49.9K 1% 1 2 CCDoutC 1 1 R21 200K 1% 6 2 +15VA U13 ADA4800 2 EPAD 7 B B +15VA +15VA 1 R82 49.9K 1% C137 .1uF 25V ISF 5 VCC 4 2 C138 .1uF 25V R86 49.9K 1% 2 C140 .1uF 25V C151 .1uF 25V IDRV 1 3 VEE U35 ADA4800 CCDinA OUT 2 ISF 5 VCC 4 2 C156 .1uF 25V 2 3 IN OUT VEE EPAD U36 ADA4800 7 2 IDRV 1 CCDoutB C141 .1uF 25V 1 2 2 IN 1 R87 200K 1% 6 2 1 1 2 CCDoutA 1 1 R83 200K 1% 6 2 1 1 1 2 CCDinB EPAD 7 20361636-Revision 2 Bare Board 20361640-Revision 3 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Video Output Buffers Gen2 Evaluation System 72 pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361636 / 20361640 PROGRAM CADSTAR SHEET 1 17of 17 __ 20361640 REV3 KAI 72 PIN PGA Imager Part Name BLM18AG601SN1D C4.7UF_0603_6V3_10 C10UF_0805_16V_80 C2200PF_0603_50V_10% C10UF_1210_25V_20 C4.7UF_0805_25V20 C1000PF_0603 Part Number BLM18AG601SN1D GRM188R60J475KE19D GRM21BF51C106ZE15L C0603C222K5RACTU ECJ‐4YB1E106M GRM21BR61E475MA12L C0603C102K5RACTU Description FERRITE CHIP 600 OHM 500MA 0603 CERCAP 4.7UF 6.3WVDC 10% CAP 10UF 16WVDC 80% CAP 2200PF X7R 50WVDC 10% CAP 10UF 25WVDC 20% X5R CERCAP 4.7UF 25WVDC 20% X5R CAP 1000PF X7R 50VDC 10% Qty 1 10 3 2 3 5 24 C.1UF_0603_25V C4.7UF_1210_25V20 C.01UF_0603 C2.2UF_0805_16V C100PF_0603 C1UF_0603_25V_10 HSMS2805 MBRM120E BAT54‐04 ASP‐122952‐01 104363‐4 JUMP_1206_SMT NRS5020T100MMGJ BC847BVN MMBT3904LT1 R220_0603 R2322_0603 C0603C104K3RACTU TMK325B7475KN‐T C0603C103K5RAC GRM21BF51C225ZA01 C0603C101J5GAC GRM188R61E105KA12D HSMS‐2805‐TR1G MBRM120ET3G BAT54‐04 ASP‐122952‐01 5‐104363‐4 NONE NRS5020T100MMGJ BC847BVN‐7 MMBT3904LT1G CRCW0603220RJNEA CRCW060323K2FKEA CAP .1UF 25WVDC +10% CAP 4.7UF 25WVDC 20% CAP .01UF 50WVDC 10% CAP 2.2UF 16WVDC 20% Y5V CAP 100PF 50WVDC 5% CAP 1UF 25V 10% DIODE DUAL SCHOTTKY BARRIER RECTIFIER 1A 20V SCHOTTKY DUAL SERIES CONNECTOR 5mm BOARD TO BOARD Mezzanine 5 POS SHROUDED MTE HDR ASS 1206 SMT JUMPER INDUCTOR 10uH 1.3A TRANSISTOR DUAL DIGITAL PNP/NPN TRANSISTOR G.P. NPN RESISTOR 220 1/16W 5% RESISTOR 23.2K 1/16W 1% 110 3 10 5 1 8 11 4 12 2 1 1 3 1 1 8 1 Comps BD1 C1 C6 C8 C27 C39 C157 C169 C179 C181 C185 C100 C150 C171 C103 C134 C111 C127 C143 C129 C135 C153 C155 C173 C13‐24 C43 C48 C70‐79 C2‐5 C7 C9‐11 C25 C28‐38 C40‐42 C44‐45 C47 C49 C52‐55 C58‐59 C61 C64‐68 C80‐93 C96‐97 C101‐102 C104 C106 C108 C110 C113‐ 126 C130 C133 C137‐141 C146‐148 C151‐152 C154 C156 C158‐168 C170 C174‐178 C180 C182‐184 C26 C46 C60 C50 C57 C63 C99 C107 C128 C136 C144 C149 C186 C51 C56 C62 C105 C109 C94 C95 C98 C112 C131 C142 C145 C172 C187 CR2‐6 CR13‐18 CR7 CR24‐26 CR8‐12 CR19‐23 CR27‐28 J1 J4 J3 JMP2 L1‐3 Q1 Q2 R1 R3 R8‐9 R13‐14 R27 R29 R15 R2003_0603 R3093_0603 R1623_0603 R1000_0603 R1103_0603 R4992_0603 R3162_0603 R3922_0603 R2702_0603 R9312_0603 R1502_0603 R9532_0603 R1002_0603 R1742_0603 R1963_0603 R0_0603 R1652_0603 R9091_0603 R6342_0603 R1003_0603 R2492_0603 CRCW0603200KFKEA CRCW0603309KFKEA CRCW0603162KFKEA CRCW0603100RFKEA CRCW0603110KFKEA CRCW060349K9FKEA CRCW060331K6FKEA CRCW060339K2FKEA ERJ‐3GEYJ273V CRCW060393K1FKEA ERJ‐3EKF1502V CRCW060395K3FKEA CRCW060310K0FKEA CRCW060317K4FKEA CRCW0603196KFKEA CRCW06030000Z0EA CRCW060316K5FKEA CRCW06039K09FKEA CRCW06036342FT CRCW0603100KFKEA CRCW060324K9FKEA RESISTOR 200K 1/16W 1% RESISTOR 309K 1/16W 1% RESISTOR 162K 1/16W 1% RESISTOR 100 1/16W 1% RESISTOR 110K 1/16W 1% RESISTOR 49.9K 1/16W 1% RESISTOR 31.6K ohm 1/16W 1% RESISTOR 39.2K 1/10W 1% RESISTOR 27K ohm 1/16W 1% RESISTOR 93.1K 1/16W 1% RESISTOR 15.0K 1/16W 1% RESISTOR 95.3K 1/16W 1% RESISTOR 10K 1/16W 1% RESISTOR 17.4K 1/16W 1% RESISTOR 196K 1/10W 1% RESISTOR 0 RESISTOR 16.5K 1/16W 1% RESISTOR 9.09K 1/16W 1% RESISTOR 63.4 K 1/16W 1% RESISTOR 100K 1/16W 1% RESISTOR 24.9K 1/16W 1% 32 2 1 16 1 6 1 2 3 1 7 1 7 1 1 3 1 1 1 2 1 R16‐17 R21 R23 R25 R42‐47 R49‐54 R60‐69 R72 R80 R83 R85 R87 R18 R48 R19 R2 R4‐7 R10‐12 R28 R30‐36 R20 R22 R24 R26 R82 R84 R86 R37 R38 R70 R39‐40 R71 R41 R55 R59 R74 R93 R98 R100‐101 R56 R57‐58 R76 R78‐79 R91 R94 R73 R75 R77 R97 R99 R81 R88 R89 R90 R92 R95 R7502_0603 AD9928 LT1175CS8 ADA4800 74LCX541BQX Socket KAI‐29050 LT1964ES5‐SD SN74LVC2G04 LTM8022 ZXMD63C03X LT3479EDE LT1761ES5‐SD LT3050 NC7SZ08 LTC1665C ADC081 LT1521‐3.3 LT1965EMS8E CRCW060375K0FKEA AD9928 LT1175CS8#PBF ADA4800ACPZ‐R7 74LCX541BQX IS230‐1371D‐75M‐R29‐L14‐A LT1964ES5‐SD#TRMPBF SN74LVC2G04DBVR LTM8022EV#PBF ZXMD63C03XTA LT3479EDE#PBF LT1761ES5‐SD#TRMPBF LT3050EDDB#TRMPBF NC7SZ08M5X LTC1665CGN#PBF ADC081S021 LT1521CMS8‐3.3#PBF LT1965EMS8E#PBF xxx xxx xxx xxx xxx xxx xxx REGULATOR LOW DROPOUT NEG with SHUTDOWN IC DUAL INVERTER GATE SOT‐23‐6 Step Down uModule Regulator IC N/P‐CHANNEL FAST SWITCH FET 3A DC/DC Converter ADJ REGULATOR LOW DROPOUT STDBY 100mA LDO with current limit and fault detect TINY AND GATE IC 8 BIT DAC 8CH IC 8 BIT ADC REG LDO 3.3V 300mA REGULATOR LOW DROPOUT NEG 1 2 1 4 6 1 2 2 2 13 2 1 1 1 1 1 1 2 R96 U1 U41 U11 U12‐13 U35‐36 U19‐20 U22 U29‐31 U21 U23 U26 U24 U42 U27 U40 U2‐8 U14‐18 U44 U28 U34 U32 U33 U37 U38 U39 U43 U9‐10 CAP 1UF 25V 10% DO NOT POPULATE 1206 SMT JUMPER DO NOT POPULATE CAP NOLOAD CAP NOLOAD JACK POWER 2.1mm DO NOT POPULATE FIDUCIAL BOARD LOCAL 40 DO NOT POPULATE Mounting Hole 150/95 DO NOT POPULATE 1 1 1 1 1 6 8 C132 JMP1 C12 C69 J2 FM1‐6 N1‐8 RESISTOR 75.0K 1/16W 1% CCD DUAL Signal Processor with HV Timing Generator ADJ REGULATOR LOW DROPOUT NEG CCD BUFFER AMPLIFIER OCTAL BUFFER DQFN package Socket for KAI-29050 NO LOADS