CT2542 / CT2543 Dual Redundant Remote Terminal for MIL-STD-1553B www.aeroflex.com/Avionics September 16, 2005 FEATURES ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ CT2542 Replaces DDC BUS-65142 and BUS-65144 CT2543 Replaces DDC BUS-65143 and BUS-65145 Functions as a Complete Remote Terminal Unit Supports 13 Mode Codes, Illegalization of Codes Allowed Transfers Data with DMA Type Handshaking Latched Outputs for Command Word and Word Count 14 Bit Built-ln-Test Word Register 4 Error Flag Outputs Advanced Low Power VLSI Technology Designed for commercial, industrial and aerospace applications MIL-PRF-38534 compliant devices available Aeroflex-Plainview is a Class H & K MIL-PRF-38534 manufacturer Packaging – Hermetic Metal - 68 Pin, 2.1" x 1.87" x .25" Plug-In Type Package - 82 Leads, 2.20" x 1.61" x .18" Flat Type Package DESC SMD# 5962–89798 ENCODER/ DECODER DATA BUS A DUAL DB0-DB15 PROTOCOL I/O AND BIT TRANSCEIVER DATA BUS B MIL-STD-1553B ENCODER/ DECODER A0-A11 ERROR FLAG INTERFACE PROCESSING LOGIC TIMING FLAGS STATUS BITS FIGURE 1 – FUNCTIONAL BLOCK DIAGRAM DESCRIPTION The Aeroflex-Plainview CT2542 contains 2 Transceivers, 2 Encoder/Decoders, Bit Processors and complete Remote Terminal (RT) logic. The device is constructed using Aeroflex advanced VLSI custom chip and hybrid technology. It functions as a complete dual redundant MIL-STD-1553B RT Unit supporting all 13 mode codes for dual redundant operation. The CT2542 is a pin-for-pin functional equivalent of the DDC BUS-65142/144 and performs parallel data transfers with a DMA type handshake. Multiple error flag outputs and host access to many of the RT Status Word bits are just some of the features that make this part ideal for many RT applications. The unit has an operating range of -55°C to +125°C. See "Ordering Information" (last sheet) for CT2543. SCDCT2542 Rev G ABSOLUTE MAXIMUM RATINGS Parameter Limits Units Power Supply Voltage (VEE) +0.3 to -18.0 Volts Power Supply Voltage (VCCL) -0.3 to +7.0 Volts ±20 (40Vp-p) Volts Receiver Input Voltage ±15 Volts Driver Output Current +200 mA Transmission Duty Cycle at TC = 125°C 100 % Operating Case Temperature Range (TC) -55 to +125 °C Receiver Differential Input POWER AND THERMAL DATA (SINGLE TRANSCEIVER AND LOGIC SECTION) Parameter/Conditions Symbol Min Typ Max Units Power Supply Voltage VEE VCCL -14.25 4.5 -15 5 -15.75 5.5 V V Thermal Resistance, most critical device ØJC - 60 - °C/W Power dissipation of most critical (hottest) device during continuous transmission (100% duty cycle) 1/ PC - 350 - mW IEE ICCL 2/ - 50 - 70 50 mA mA IEE @ 50% IEE @ 100% - - 175 270 mA mA Total supply current standby mode, or transmitting at less than 1% duty cycle (e.g. 20us of transmission every 2ms or longer interval) Total supply current transmitting at 1Mhz into a 35-ohm load at Point A in Figure 2 3/ Notes 1/ Decreases linearly to zero at zero duty cycle. 2/ Iccl limit does not change with mode of operation or duty cycle. 3/ Decreases linearly to applicable "standby" values at zero duty cycle. ELECTRICAL CHARACTERISTICS (RECEIVER SECTION) Parameter/Conditions Symbol Min Max Units ZIN 2K - Ω Differential voltage range VDIR ±20V - VPK Input common mode voltage range VICR ±10V - VPK CMMR 40 - dB VTH 0.86 1.2 VPK-PK Differential input impedance DC to 1MHz, Point B, Figure 2 Common mode rejection ratio (from Point A, Figure 1) Threshold characteristics (Sine wave at 1MHz) Note: Threshold voltages refer to Point A, Figure 2. SCDCT2542 Rev G 2 ELECTRICAL CHARACTERISTICS (TRANSMITTER SECTION) Parameter/Conditions Symbol Min Typ Max Units VO 24 - 35 VPK-PK tR & tF 100 - 300 nS Output offset at Point A in Figure 2 (35-ohm load) 2.5us after mid-bit crossing of parity bit of last word of a 660us message VOS - ±20 ±90 mVPK Differential output noise VNOI - - 10 mVPK-PK Differential output level at Point B, Figure 2 (145-ohm load) Rise and Fall times (10% to 90% of p-p output) LOGIC CHARACTERISTICS Symbol Parameter Min Max Units VIH Input "1" 2.4 - VDC VIL Input "0" - 0.7 VDC IIL Input l -80 -400 µA Note 1A IIH Input l -40 -200 µA Note 1B IIL Input l -20 +20 µA Note 2A IIH Input l -20 +20 µA Note 1B IIL Input l -20 -200 µA Note 5 IIH Input l -40 -400 µA VOH Output "1" 2.7 - VDC Note 3A/4A VOL Output "0" - 0.4 VDC Note 3B/4B Note 1: For INPUT pins 12,13,14,15, 53, 54, 55 (DDIP). VCC = 5.5V A. @ VIL = 0.4V B. @ VIH = 2.4V Note 2: All remaining INPUTS other than in Note 1. VCC = 5.5V A. @ VIL = 0.4V B. @ VIH = 2.4V Note 3: For OUTPUT pins 4 through 11 and 43 through 50 (DDIP). A. @ VCC = 4.5V and IOH = 2mA B. @ VCC = 2.4V and IOL = 4mA Note 4: All remaining OUTPUTS other than in Note 3. A. @ VCC = 4.5V and IOH = 1mA B. @ VCC = 5.5V and IOL = 2mA Note 5 For INPUT pins 4-11, 43-50 (DDIP). VCC= 5.5V A. @ VIL = 0.4V B. @ VIH = 2.4V SCDCT2542 Rev G 3 Conditions TERMINAL CONNECTIONS AND PIN FUNCTIONS Plug-In Pkg Flat Pkg Function 1 2 A9 Latched output of the most significant bit (MSB) in the subaddress field of the command word. 2 4 A7 Latched output of the third most significant bit in the subaddress field of the command word. 3 6 A5 Latched output of the least significant bit (LSB) in the subaddress field of the command word. 4 8 DB1 Bidirectional parallel data bus bit 1. 5 10 DB3 Bidirectional parallel data bus bit 3. 6 12 DB5 Bidirectional parallel data bus bit 5. 7 14 DB7 Bidirectional parallel data bus bit 7. 8 16 DB9 Bidirectional parallel data bus bit 9. 9 18 DB11 Bidirectional parallel data bus bit 11. 10 20 DB13 Bidirectional parallel data bus bit 13. 11 22 DB15 Bidirectional parallel data bus bit 15 (MSB). 12 24 BRO ENA 13 26 ADDRE Input of the MSB of the assigned terminal address. 14 28 ADDRC Input of the 3rd MSB of the assigned terminal address. 15 30 ADDRA Input of the 3rd MSB of the assigned terminal address. 16 32 RTADD ERR Output signal used to inform subsystem of an address parity error. If LOW, indicates parity error and the RT will not respond to any command address to a single terminal. It will still receive broadcast commands if BRO ENA is HIGH. 17 34 TXDATAOUT B LOW output to the primary side of the coupling transformer that connects to the B channel of the 1553 bus. 18 36 N/C 19 38 GND B 20 40 RXDATAIN B Input from the HIGH side of the primary side of the coupling transformer that connects to the B channel of the 1553 bus. 21 81 A3 Multiplexed address line output. When INCMD is LOW, or A5 through A9 are all zeroes or all ones (mode command), it represents the latched output of the 2nd MSB in the word count field of the command word. When INCMD is HIGH and A5 through A9 are not all zeroes or all ones, it represents the 2nd MSB of the current word counter. (See note 1). 22 79 A1 Multiplexed address line output. When INCMD is LOW, or A5 through A9 are all zeroes or all ones (mode command), it represents the latched output of the 2nd LSB in the word count field of the command word. When INCMD is HIGH and A5 through A9 are not all zeroes or all ones, it represents the 2nd LSB of the current word counter. (See note 1). 23 77 DTGRT Data transfer grant - Active LOW input signal from the subsystem that informs the RT, when DTREQ is asserted, to start the transfer. Once the transfer is started, DTGRT can be removed. 24 75 INCMD In command - HIGH level output signal used to inform the subsystem that the RT is presently servicing a command. When low, A0-A4 (see note 1) represent the word count of the present command. When high, A0-A4 represent the current word counter of non-mode commands. Description Broadcast enable - When HIGH, this input allows recognition of an RT address of all ones in the command word as a broadcast message. When LOW, it prevents response to RT address 31 unless it was the assigned terminal address. No connection. Power supply return connection for the B channel transceiver. SCDCT2542 Rev G 4 TERMINAL CONNECTIONS AND PIN FUNCTIONS (con’t) Plug-In Pkg Flat Pkg Function 25 73 HS FAIL Handshake fail - Output signal that goes LOW and stays LOW whenever the subsystem fails to supply DTGRT in time to do a successful transfer. Cleared by the next NBGT. 26 71 DTSTR DATA strobe - A LOW level output pulse (125 ns) present in the middle of every data word transfer over the parallel data bus. Used to latch or strobe the data into memory, FIFOs, registers, etc. Recommend using the rising edge to clock data in. (See note 2). 27 69 DAT/CMD Address line output that is LOW whenever the command word is being transferred to the subsystem over the parallel data bus, and is HIGH whenever data words are being transferred. 28 67 RT FAIL Remote terminal failure - Latched active LOW output signal to the subsystem to flag detection of a remote terminal continuous self-test failure. Also set if the watchdog timeout circuit is activated. Cleared by the start of the next message transmission (status word) and set if problem is again detected. 29 65 DTREQ Data transfer request - Active LOW output signal to the subsystem indicating that the RT has data for or needs data from the subsystem and requests a data transfer over the parallel data bus. Will stay LOW until transfer is completed or transfer until transfer is completed or transfer timeout has occurred. 30 63 ADBC Accept dynamic bus control - Active LOW input signal from subsystem used to set the dynamic bus control acceptance bit in the status register if the command word was a valid, legal mode command for dynamic bus control. 31 61 TEST 2 Factory test point - DO NOT USE. (See note 3). 32 59 A10 33 57 ILL CMD Illegal command - Active LOW input signal from the subsystem, strobed in on the rising edge of INCMD. Used to define the command word as illegal and to set the message error bit in the status register. 34 55 SS REQ Subsystem service request - Input from the subsystem used to control the service request bit in the status register. If LOW when the status word is updated, the service request bit will be set; if HIGH, it will be cleared. 35 53 BITEN Built-in-test word enable - LOW level output pulse (500 ns), present when the built-in-test word is enabled on the parallel data bus. (See note 4). 36 51 RXDATAIN A Input from the LOW side of the primary side of the coupling transformer that connects to the A channel of the 1553 bus. 37 49 VL A +5 Volt input power supply connection for the A channel transceiver. 38 47 VEEA -15 / -12 Volt input power supply connection for the A channel transceiver. (See note 7). 39 45 TXDATAOUT A HIGH output to the primary side of the coupling transformer that connects to the A channel of the 1553 bus. 40 43 NBGT New bus grant - LOW level output pulse (125 ns) used to indicate the start of a new protocol sequence in response to the command word just received. (See note 2). 41 3 A8 Latched output of the 2nd MSB in the subaddress field of the command word. 42 5 A6 Latched output of the 2nd LSB in the subaddress field of the command word. 43 7 DB0 Bidirectional parallel data bus bit 0 (LSB). 44 9 DB2 Bidirectional parallel data bus bit 2. 45 11 DB4 Bidirectional parallel data bus bit 4. 46 13 DB6 Bidirectional parallel data bus bit 6. 47 15 DB8 Bidirectional parallel data bus bit 8. Description Latched output of the T/R bit in the command word. SCDCT2542 Rev G 5 TERMINAL CONNECTIONS AND PIN FUNCTIONS (con’t) Plug-In Pkg Flat Pkg Function 48 17 DB10 Bidirectional parallel data bus bit 10. 49 19 DB12 Bidirectional parallel data bus bit 12. 50 21 DB14 Bidirectional parallel data bus bit 14. 51 23 VL 52 25 GND 53 27 ADDRD Input of the 2nd MSB of the assigned terminal address. 54 29 ADDRB Input of the 2nd LSB of the assigned terminal address. 55 31 ADDRP Input of address parity bit. The combination of assigned terminal address and ADDRP must be odd parity for the RT to work. 56 33 TXDATAOUT B HIGH, output to the primary side of the coupling transformer that connects to the B channel of the 1553 bus. 57 35 VEEB -15 / -12 Volt input power supply connection for the B channel transceiver. (See note 7). 58 37 VLB +5 Volt input power supply connection for the B channel transceiver. 59 39 RXDATAIN B Input from the LOW side of primary side of the coupling transformer that connects to the B channel of the 1553 bus. 60 80 A2 Multiplexed address line output. When INCMD is LOW, or A5 through A9 are all zeroes or all ones (mode command), it represents the latched output of the 3rd MSB in the word count field of the command word. When INCMD is HIGH and A5 through A9 are not all zeroes or all ones, it represents the 3rd MSB of the current word counter. (See note 1). 61 78 A0 Multiplexed address line output. When INCMD is LOW, or A5 through A9 are all zeroes or all ones (mode command), it represents the latched output of the LSB in the word count field of the command. When INCMD is HIGH and A5 through A9 are not all zeroes or all ones, it represents the LSB of the current word counter. (See note 1). 62 76 DTACK Data transfer acknowledge - Active LOW output signal during data transfers to or from the subsystem indicating the RTU has received the DTGRT in response to DTREQ and is presently doing the transfer. Can be connected directly pins 67 on Plug-In Pkg or pin 66 on Flat Pkg (BUF ENA) for control of 3-state data buffers; and to 3-state address buffer control lines, if they are used. 63 74 A4 Multiplexed address line output. When INCMD is LOW or A5 through A9 are all zeroes or all ones (mode command), it represents the latched output of the MSB in the word count field of the command word. When INCMD is HIGH and A5 through A9 are not all zeroes or all ones, it represents the MSB of the current word counter. (See note 1). 64 72 R/W Read/Write - Output signal that controls the direction of the internal data bus buffers. Normally, the signal is LOW and the buffers drive the data bus. When data is needed from the subsystem, it goes HIGH to turn the buffers around and the RT now appears as an input. The signal is HIGH only when DTREQ is active (LOW). 65 70 GBR Good block received - LOW level output pulse (500 ns) used to flag the subsystem that a valid, legal, non-mode receive command with the correct number of data words has been received without a message error and successfully transferred to the subsystem. (See note 4). 66 68 16 MHz 67 66 BUF ENA 68 64 RESET Description +5 Volt input power supply connection for RTU digital logic section. Power supply return for RTU digital logic section. 16 MHz clock input - Input for the master clock used to run RTU circuits. Buffer enable - Input used to enable or 3-state the internal data bus buffers when they are driving the bus. When LOW, the data bus buffers are enabled. Could be connected to DTACK, (pin 62, Plug-In Pkg), (pin 76, Flat Pkg) if RT is sharing the same data bus as the subsystem. (See note 5). Input resets entire RT when LOW. SCDCT2542 Rev G 6 TERMINAL CONNECTIONS AND PIN FUNCTIONS (con’t) Plug-In Pkg Flat Pkg Function 69 62 RT FLAG 70 60 TEST 1 Factory test point - DO NOT USE. (See note 6). 71 58 BUSY Subsystem busy - Input from the subsystem used to control the busy bit in the status register. If LOW when the status word is updated, the busy bit will be set; if HIGH, it will be cleared. If the busy bit is set in the status register, no data will be requested from the subsystem in response to a transmit command. On receive commands, data will still be transferred to subsystem. 72 56 SS FLAG Subsystem flag - Input from the subsystem used to control the subsystem flag bit in the status register. If LOW when the status word is updated, the subsystem flag will be set; if HIGH, it will be cleared. 73 54 MESS ERR Message error - Output signal that goes LOW and stays low whenever there is a format or word error with the received message over the 1553 data bus. Cleared by the next NBGT. 74 52 RXDATAIN A Input from the HIGH side of the primary side of the coupling transformer that contacts to the A channel of the 1553 bus. 75 50 GND A 76 48 N/C 77 46 TXDATAOUT A LOW output to the primary side of the coupling transformer that connects to the A channel of the 1553 bus. 78 44 STATEN Status word enable - LOW level active output signal present when the status word is enabled on the parallel data bus. Description Remote terminal flag - Input signal used to control the terminal flag bit in the status register. If LOW when the status word is updated, the terminal flag bit would be set; if HIGH, it would be cleared. Normally connected to RTFAIL; (pin 28, Plug-In Pkg); (pin 67, Flat Pkg). Power supply return connection for the A channel transceiver. No connection. (See note 7). NOTES: 1. When INCMD is LOW during the DTSTR immediately following NBGT, A0 through A4 are valid and equal to WC0 through WC4 of the received command word. The remaining time while INCMD is LOW and A5 through A9 are not all zeros or ones (i.e. MODE), A0 through A4 are equal to the last current word count plus one. When INCMD is HIGH and A5 through A9 are not MODE, A0 through A4 represent the current word counter. If A5 through A9 are equal to MODE, A0 through A4 are equal to WC0 through WC4 of the received command word, independent of the state of INCMD. 2. Pulse width is typically 125 ns. 3. Pin 31 for Plug-In Pkg, and pin 61 for Flat Pkg - (TEST 2) factory test point output: This pin provides the output of the device BIT comparison output. It indicates the loop test results for every word transmitted by the device. A test can be performed by actuating the RTU to transmit while the test fixture opens the receiver lines to force an error condition. A logic 1 (high) indicates the loop test passed. Normally this pin is left open. For Plug-In Pkg and Flat Pkg TEST 2 is not implemented and should be left open. 4. Pulse width is typically 375 ns. 5. Pin 67 for Plug-In Pkg, and pin 66 for Flat Pkg - BUF ENA: This pin is typically tied to DTACK, causing the device to drive the shared data bus only while DTACK is active. If desired BUF ENA can be gounded. The data will remain latched on the data bus pins for 19 µs from DTSRB and 4 µs for the last word of a message as the devices status word or BIT word is transferred to the BC (STATEN or BITEN low). Once the STATUS or BIT word transfer is complete, the data bus will automatically again contain the last data word. The device will automatically switch the direction of the internal buffers during a transmit operation. 6. Pin 70 for Plug-In Pkg, and pin 60 for Flat Pkg - (TEST 1) factory test point: This test allows the user to force the active channel to transmit indefinitely, in order to test the built-in watchdog timer feature of the device. When this pin is grounded and the active channel is stimulated with a valid transmit command, the device will respond with a status word and contiguous data (last data word loaded or STATUS WORD if none is loaded) until the built-in timeout occurs. Normally this pin is left open or an optional pull-up can be used. For Plug-In Pkg and Flat Pkg (TEST 1) is not implemented and should be left open. 7. For Flat Pkg, pins 1, 41, 42, and 82 are no connections. SCDCT2542 Rev G 7 Transformer Coupled Stubs DATA TX/RX STUB ISOLATION 2:1 1 : 1.41 CT2542 C 70Ω 55Ω A DATA TX/RX 55Ω Zoi VCMT = ±10 VPK DC to 2MHZ Direct Coupled Stubs STUB DATA TX/RX CT2542 55Ω 1.4 :1 B A DATA TX/RX 55Ω Zoi NOTES: 1. Point C, Vo = 18 Vpp Minimum 2. Transformer self Impedance ≥ 3KΩ at 1MHz 3. VCMT for transformer coupled stubs VCMD for direct coupled stubs 35Ω 35Ω + ±VCMD - FIGURE 2 – TYPICAL BUS COUPLED CONFIGURATIONS SCDCT2542 Rev G 8 SCDCT2542 Rev G 9 COMMAND SYNC 15 14 13 TRISTATE WORD COUNT 100ns MAX 2.1µs MAX 13 DATA WORD FROM SUBSYSTEM TRISTATE STATUS WORD 14 15.5µs max 15 1.1µs (STATUS BITS STROBED IN) (SRQ, BUSY, SSFLAG, RDBC, RTFLAG) ADDRESS = 00h SUB ADDRESS 4.5 ± 0.5µs STATUS SYNC 0 DATA SYNC 14 13 DON’T CARE 15 ADDRESS = 01h TRISTATE DATA WORD FROM SUBSYSTEM STROBED IN 100ns MAX P FIGURE 3 – TIMING DIAGRAM, TRANSMIT ONE WORD PREVIOUS STATE 4.5µs 1µs 125ns ILLCMD STROBED IN BUFFENA DB0 - DB4 A0 - A4 A6 - A10 R/W A11 (T/R) STATEN A5 (D/C) INCMD DTSTB DTACK DTGRT DTREQ P COMMAND WORD 0 NBGT 1 11µs ± .75µs 0 P 6.5µs ±0.5µs SCDCT2542 Rev G 10 COMMAND SYNC P A0 - A4 A6 - A10 R/W A11 (T/R) GBR STATEN A5 (D/C) INCMD DTSTB DTACK DTGRT DTREQ NBGT 0 BUFFENA DB0 - DB15 1 ILLCMD STROBED IN COMMAND WORD TRISTATE PREVIOUS STATE 1µs 125ns 4.5 ± 0.5µs DATA SYNC 15 13 12 DON’T CARE 4.5 ± 0.5µs 1.1µs (STATUS BITS STROBED IN) (SRQ,BUSY,SSFLAG,RDBC,RTFLAG) TRISTATE STATUS WORD P 100ns MAX 8 RECEIVE DATA WORD 4.5µs FOR HANDSHAKES < 3.5µs 15.5µs max STATUS SYNC FIGURE 4 – TIMING DIAGRAM, RECEIVE ONE WORD WORD COUNT 0 100ns MAX 2.1µs MAX 11 ADDRESS = 00h SUB ADDRESS 14 9.5µs ± 0.75µs 7 5 0 P 6.5µs ±0.5µs STATUS WORD ADDRESS = 01h TRISTATE 250ns FOR HANDSHAKES > 3.5µs 6 SCDCT2542 Rev G 11 BUFFENA DB0 - DB15 A0 - A4 A6 - A10 R/W A11 (T/R) GBR STATEN A5 (D/C) INCMD DTSTB DTACK DTGRT DTREQ NBGT 15 COMMAND WORD TRISTATE PREVIOUS STATE 1µs 125ns 4.5 ± 0.5µs RX COMMAND SYNC 13 1 100ns MAX 2.1µs MAX 0 P TRISTATE TX COMMAND SYNC 14 13 TRISTATE 250ns MAX DON’T CARE 4.0 ± 0.5µs 15 12 10 TX COMMAND WORD 11 0 P FIGURE 5A – TIMING DIAGRAM, RT TO RT RECEIVE ONE WORD (PART A) TRISTATE WORD COUNT ADDRESS = 00h SUB ADDRESS 14 TX STATUS SYNC TRANSMITTING RT RESPONSE TIME 15 14 13 SCDCT2542 Rev G 12 BUFFENA DB0 - DB15 A0 - A4 A6 - A10 R/W A11 (T/R) GBR STATEN A5 (D/C) INCMD DTSTB DTACK DTGRT DTREQ NBGT P 500ns TYP 4.5 ± 0.5µs 0 15 14 13 1 0 4.5 ± 0.5µs P 8 RECEIVE DATA WORD TRISTATE 4.5 µs FOR HANDSHAKES < 3.5µs 15.5µs MAX STATUS SYNC 6 5 1 STATUS WORD ADDRESS = 01h TRISTATE 6.5 ± 0.5µs P DON’T CARE 0 250ns FOR HANDSHAKES > 3.5µs 100ns MAX 7 FIGURE 5B – TIMING DIAGRAM, RT TO RT RECEIVE ONE WORD (PART B) TX RT STATUS RESPONSE DATA SYNC 9.5µs ±0.75µs NBGT 125ns 0ns MIN DTREQ 2.1µs MAX DTGRT 100ns MAX DTACK 635ns 375ns DTSTB 125ns INCMD 125ns 1µs A5 (D/C) WHEN T/R = 0 125ns A11 (T/R) VALID A6 - A10 SUB ADDRESS WORD COUNT A0 - A4 ADDRESS = 00h OR MODE 75ns MAX DB0 - DB15 TRISTATE 75ns MAX TRISTATE 75ns MAX TRISTATE 75ns MAX COMMAND WORD BUFFENA NOTE: 1. R/W = LOGIC 0 FIGURE 6 – TIMING DIAGRAM, COMMAND WORD TRANSFER SCDCT2542 Rev G 13 STATEN Receive Only GBR 375ns 125ns DTSTB 125ns 75ns TRISTATE DB0 - DB15 TRISTATE STATUS 75ns BUFFENA NOTE: 1. R/W = 0 FIGURE 7 – TIMING DIAGRAM, STATUS WORD TRANSFER BITEN 375ns 125ns DTSTB 125ns 75ns DB0 - DB15 TRISTATE TRISTATE BIT WORD 75ns BUFFENA NOTE: 1. R/W = 0 FIGURE 8 – TIMING DIAGRAM, BIT WORD TRANSFER SCDCT2542 Rev G 14 DTREQ DON’T CARE 0ns MIN DTGRT 100ns MAX 375ns TYP DTACK 125ns TYP DTSTB 125ns TYP 75ns MAX 75ns MAX TRISTATE VALID DB0 - DB15 RECEIVED DATA WORD BUFFENA 50ns MAX A0 - A4 NOTES: 1. R/W = Logic 0 2. (*) = Non-Mode Only 3. BUFFENA = DTACK ADDRESS or MODE *ADDRESS +1 FIGURE 9 – TIMING DIAGRAM, DATA TO SUBSYSTEM DTREQ DON’T CARE 0ns MIN DTGRT 100ns MAX 375ns TYP DTACK 125ns TYP DTSTB 125ns TYP R/W 50ns MIN DB0 - DB15 TRANSMIT DATA WORD VALID 50ns MAX 50ns MAX A0 - A4 NOTES: 1. (*) = Non-Mode Only 2. Word Count for Mode Code 3. BUFFENA = Don’t Care ADDRESS or MODE *ADDRESS +1 FIGURE 10 – TIMING DIAGRAM, DATA FROM SUBSYSTEM SCDCT2542 Rev G 15 SCDCT2542 Rev G 16 TRISTATE VALID RECEIVED DATA DON’T CARE 125ns MIN FIGURE 11 – TIMING DIAGRAM, DATA TRANSFERS TO SUBSYSTEM (NO HANDSHAKE) ADDRESS OR MODE FIELD DON’T CARE 125ns TYP 125ns MIN NOTES: 1. R/W = LOGIC 0 2. DTGRT = DTREQ = LOGIC 1 3. INCMD = DAT/CMD ARE LOGIC 1 A0 - A4 BUFFENA DB0 - DB15 DTSTB TRISTATE CT2542 PIN OUT DESCRIPTION (DDIP) 1 41 2 42 3 43 4 44 5 45 6 46 7 47 8 48 9 49 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 20 A10 A9 A8 A7 A6 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 +5V BRO ENA GND ADDRE ADDRD ADDRC ADDRB ADDRA ADDRP RTADERR TXDATA B TXDATA B -VEE B N/C +5V B GND B RXDATA B RXDATA B A3 A2 A1 A0 MIL-STD-1553B DTGRT REMOTE TERMINAL DTACK PROTOCOL UNIT INCMD A4 HSFAIL R/W DISTR GBR A5(DAT/CMD) 16MHz IN RTFAIL BUF ENA DTREQ RESET ADBC RTFLAG TP2 TP1 A11(T/R) BUSY ILLCMD SSFLAG SRQ ME BITEN RXDATA A RXDATA A GND A +5V A N/C -VEE A TXDATA A TXDATA A STATEN NBGT CT2542 21 60 22 61 23 62 24 63 25 64 26 65 27 66 28 67 29 68 30 69 31 70 32 71 33 72 34 73 35 74 36 75 37 76 38 77 39 78 40 Pin # Function Pin # Function 1 A10 40 NBGT 2 A8 41 A9 3 A6 42 A7 4 DB1 43 DB0 5 DB3 44 DB2 6 DB5 45 DB4 7 DB7 46 DB6 8 DB9 47 DB8 9 DB11 48 DB10 10 DB13 49 DB12 11 DB15 50 DB14 12 BRO ENA 51 +5V 13 ADDRE 52 GND 14 ADDRC 53 ADDRD 15 ADDRA 54 ADDRB 16 RTADERR 55 ADDRP 17 TXDATA B 56 TXDATA B 18 N/C 57 -VEE B 19 GND B 58 +5V B 20 RXDATA B 59 RXDATA B 21 A3 60 A2 22 A1 61 A0 23 DTGRT 62 DTACK 24 INCMD 63 A4 25 HSFAIL 64 R/W 26 DTSTR 65 GBR 27 A5 (DAnT/CMD) 66 16MHz IN 28 RTFAIL 67 BUF ENA 29 DTREQ 68 RESET 30 ADBC 69 RTFLAG 31 TP2 (NC) 70 TP1 (NC) 32 A11 (T/R) 71 BUSY 33 ILLCMD 72 SSFLAG 34 SRQ 73 ME 35 BITEN 74 RXDATA A 36 RXDATA A 75 GND A 37 +5V A 76 N/C 38 -VEE A 77 TXDATA A 39 TXDATA A 78 STATEN FIGURE 12 – DDIP PIN CONNECTION DIAGRAM, CT2542 AND PINOUT TABLE SCDCT2542 Rev G 17 CT2512 PIN OUT DESCRIPTION (FP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 N/C A10 A9 A8 A7 A6 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 +5V BR0 ENA GND ADDRE ADDRD ADDRC ADDRB ADDRA ADDRP RTADERR TXDATA B TXDATA B -VEE B N/C +5V B GND B RXDATA B RXDATA B N/C N/C A3 A2 A1 MIL-STD-1553B A0 REMOTE TERMINAL DTGRT DTACK PROTOCOL UNIT INCMD A4 HSFAIL R/W DISTR GBR A5(DAT/CMD) 16MHz IN RTFAIL BUF ENA DTREQ RESET ADBC RTFLAG TP2 TP1 A11(T/R) BUSY ILLCMD SSFLAG SRQ ME BITEN RXDATA A RXDATA A GND A +5V A N/C -VEE A TXDATA A TXDATA A STATEN NBGT N/C CT2542-FP 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 Pin # Function Pin # Function 1 NC 42 NC 2 A10 43 NBGT 3 A9 44 STATEN 4 A8 45 TXDATA A 5 A7 46 TXDATA A 6 A6 47 VEE A 7 DB0 48 N/C 8 DB1 49 +5V A 9 DB2 50 GND A 10 DB3 51 RXDATA A 11 DB4 52 RXDATA A 12 DB5 53 BITEN 13 DB6 54 ME 14 DB7 55 SRQ 15 DB8 56 SSFLAG 16 DB9 57 ILLCMD 17 DB10 58 BUSY 18 DB11 59 A11 (T/R) 19 DB12 60 TP1 20 DB13 61 TP2 21 DB14 62 RTFLAG 22 DB15 63 ADBC 23 +5V 64 RESET 24 BRO ENA 65 DTREQ 25 GND 66 BUF ENA 26 ADDRE 67 RTFAIL 27 ADDRD 68 16MHz IN 28 ADDRC 69 A5 (DAT/CMD) 29 ADDRB 70 GBR 30 ADDRA 71 DTSTR 31 ADDRP 72 R/W 32 RTADERR 73 HSFAIL 33 TXDATA B 74 A4 34 TXDATA B 75 INCMD 35 -VEE B 76 DTACK 36 N/C 77 DTGRT 37 +5V B 78 A0 38 GND B 79 A1 39 RXDATA B 80 A2 40 RXDATA B 81 A3 41 NC 82 NC FIGURE 13 – FLAT PACKAGE PIN CONNECTION DIAGRAM, CT2542 AND PINOUT TABLE SCDCT2542 Rev G 18 PLUG IN PACKAGE OUTLINE 2.100 1.870 Lead 1 & ESD Designator 1.900 .100 .110 Pin 2 Pin 1 .050 Pin 19 TYP Pin 20 .250 MAX Pin 59 Pin 41 .018 DIA TYP 1.650 1.500 Pin 60 Pin 78 .100 Pin 21 Pin 22 TYP Pin 40 Pin 39 .250 1.800 FLAT PACKAGE OUTLINE .050 2.200 MAX .015 Pin 82 .010 ±.002 Pin 42 .181 MAX 1.610 MAX Lead 1 & ESD Designator .500 TYP .095 (4 Places) Pin 41 2.000 .050 Lead Centers 41 Leads/Side SCDCT2542 Rev G 19 .105 ORDERING INFORMATION Model Number CT2542 CT2542-FP Screening Military Temperature, -55°C to +125°C, Screened to the individual test methods of MIL-STD-883 CT2542-701 Power Supplies DESC SMD # Package +5V & -15V - Plug in Flat Package Industrial Temperature, -40°C to +85°C, No Burn-in CT2542-FP-701 CT2542-001-2 Plug in Flat Package - 5962–8979803XA CT2542-001-1 5962–8979803XC CT2542-201-2 5962–8979803YA CT2542-201-1 5962–8979803YC CT2543 CT2543-FP Military Temperature, -55°C to +125°C, Screened to the individual test methods of MIL-STD-883 CT2543-701 CT2543-FP-701 +5V & -12V - Plug in Plug in Flat Package - 5962–8979804XA CT2543-001-1 5962–8979804XC CT2543-201-2 5962–8979804YA CT2543-201-1 5962–8979804YC PLAINVIEW, NEW YORK Toll Free: 800-THE-1553 Fax: 516-694-6715 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com Flat Package Flat Package Industrial Temperature, -40°C to +85°C, No Burn-in CT2543-001-2 Plug in Plug in Flat Package [email protected] Aeroflex Microelectronic Solutions reserves the right to change at any time without notice the specifications, design, function, or form of its products described herein. All parameters must be validated for each customer's application by engineering. No liability is assumed as a result of use of this product. No patent licenses are implied. Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused SCDCT2542 Rev G 20