DATA SHEET Document Number: MC88LV926 Rev. 7, 4/2006 Freescale Semiconductor Technical Data MC88LV926 Low Skew CMOS PLL 68060 Clock Low Skew CMOS PLL 68060 Driver MC88LV926 Clock Driver The MC88LV926 Clock Driver utilizes phase-locked loop technology to lock its low skew outputs' frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The RST_IN/RST_OUT(LOCK) pins provide a processor reset function designed specifically for the MC68/EC/LC030/040/060 microprocessor family. To support the 68060 processor, the 88LV926 operates from a 3.3 V supply. The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it to multiple locations on a board. The PLL also allows the MC88LV926 to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency. LOW SKEW CMOS PLL 68080 CLOCK DRIVER Features • • • • • • • • • • 2X_Q Output Meets All Requirements of the 50 and 66 MHz 68060 Microprocessor PCLK Input Specifications Low Voltage 3.3 V VCC Three Outputs (Q0–Q2) with Output–Output Skew <500 ps CLKEN Output for Half Speed Bus Applications The Phase Variation from Part-to-Part Between SYNC and the ‘Q' Outputs Is Less than 600 ps (Derived from the TPD Specification, Which Defines the Part-to-Part Skew) SYNC Input Frequency Range from 5.0 MHz to 2X_Q FMax/4 All Outputs Have ± 36 mA Drive (Equal High and Low) CMOS Levels Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL-Level Compatible with VCC = 3.3 V Test Mode Pin (PLL_EN) Provided for Low Frequency Testing 20-Lead SOIC Pb-Free Package Available DW SUFFIX 20-LEAD PLASTIC SOIC PACKAGE CASE 751D-06 EG SUFFIX 20-LEAD PLASTIC SOIC PACKAGE Pb-FREE PACKAGE CASE 751D-06 Three ‘Q' outputs (Q0-Q2) are provided with less than 500 ps skew between their rising edges. A 2X_Q output runs at twice the ‘Q' output frequency. The 2X_Q output is ideal for 68060 systems which require a 2X processor clock input, and it meets the tight duty cycle spec of the 50 and 66 MHz 68060. The QCLKEN output is designed to drive the CLKEN input of the 68060 when the bus logic runs at half of the microprocessor clock rate. The QCLKEN output is skewed relative to the 2X_Q output to ensure that CLKEN setup and hold times of the 68060 are satisfied. A Q/2 frequency is fed back internally, providing a fixed 2X multiplication from the ‘Q' outputs to the SYNC input. Since the feedback is done internally (no external feedback pin is provided) the input/output frequency relationships are fixed. The Q3 output provides an inverted clock output to allow flexibility in the clock tree design. In normal phase-locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88LV926 in a static ‘test mode'. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board test environment. The RST_OUT(LOCK) pin doubles as a phase-lock indicator. When the RST_IN pin is held high, the open drain RST_OUT pin will be pulled actively low until phase-lock is achieved. When phase-lock occurs, the RST_OUT(LOCK) is released and a pullup resistor will pull the signal high. To give a processor reset signal, the RST_IN pin is toggled low, and the RST_OUT(LOCK) pin will stay low for 1024 cycles of the ‘Q' output frequency after the RST_IN pin is brought back high. Description of the RST_IN/RST_OUT(LOCK) Functionality The RST_IN and RST_OUT(LOCK) pins provide a 68030/040/060 processor reset function, with the RST_OUT pin also acting as a lock indicator. If the RST_IN pin is held high during system power-up, the RST_OUT pin will be in the low state until steady state phase/frequency lock to the input reference is achieved. 1024 ‘Q' output cycles after phase-lock is achieved the RST_OUT(LOCK) pin will go into a high impedance state, allowing it to be pulled high by an external pull-up resistor (see the AC/ DC specs for the characteristics of the RST_OUT(LOCK) pin). If the RST_IN pin is held low during power-up, the RST_OUT(LOCK) pin will remain low. IDT™ Low Skew CMOS PLL 68060 Clock Driver MC88LV926 © Freescale Semiconductor, Inc., has 2005. All rights reserved. Freescale Timing Solutions Organization been acquired by Integrated Device Technology, Inc 1 MC88LV926 Low Skew CMOS PLL 68060 Clock Driver NETCOM Q3 1 20 GND VCC 2 19 2X_Q MR 3 18 QCLKEN RST_IN 4 17 VCC VCC(AN) 5 16 Q2 RC1 6 15 GND GND(AN) 7 14 RST_OUT(LOCK) SYNC 8 13 PLL_EN GND 9 12 Q1 11 VCC Q0 10 Figure 1. Pinout: 20-Lead Wide SOIC Package (Top View) Description of the RST_IN/RST_OUT(LOCK) Functionality (continued) After the system start-up is complete and the 88LV926 is phase-locked to the SYNC input signal (RST_OUT high), the processor reset functionality can be utilized. When the RST_IN pin is toggled low (min. pulse width=10 nS), RST_OUT(LOCK) will go to the low state and remain there for 1024 cycles of the ‘Q' output frequency (512 SYNC cycles). During the time in which the RST_OUT(LOCK) is actively pulled low, all the 88LV926 clock outputs will continue operating correctly and in a locked condition to the SYNC input (clock signals to the 68030/040/060 family of processors must continue while the processor is in reset). A propagation delay after the 1024th cycle RST_OUT(LOCK) goes back to the high impedance state to be pulled high by the resistor. Power Supply Ramp Rate Restriction for Correct 030/040 Processor Reset Operation During System Start-up Because the RST_OUT(LOCK) pin is an indicator of phase-lock to the reference source, some constraints must be placed on the power supply ramp rate to make sure the RST_OUT(LOCK) signal holds the processor in reset during system start-up (power-up). With the recommended loop filter values (see Figure 7) the lock time is approximately 10ms. The phase-lock loop will begin attempting to lock to a reference source (if it is present) when VCC reaches 2 V. If the VCC ramp rate is significantly slower than 10 ms, then the PLL could lock to the reference source, causing RST_OUT(LOCK) to go high before the 88LV926 and 030/ 040 processor is fully powered up, violating the processor reset specification. Therefore, if it is necessary for the RST_IN pin to be held high during power-up, the VCC ramp rate must be less than 10 mS for proper 68030/040/060 reset operation. This ramp rate restriction can be ignored if the RST_IN pin can be held low during system start-up (which holds RST_OUT low). The RST_OUT(LOCK) pin will then be pulled back high 1024 cycles after the RST_IN pin goes high. Table 1. Capacitance and Power Specifications Symbol Parameter Value Type Unit Test Conditions CIN Input Capacitance 4.5(1) pF VCC = 3.3 V CPD Power Dissipation Capacitance 40(1) pF VCC = 3.3 V PD1 Power Dissipation at 33MHz With 50Ω Thevenin Termination 15mW/Output(1) 90mW/Device mW VCC = 3.3 V T = 25°C PD2 Power Dissipation at 33MHz With 50Ω Parallel Termination to GND 37.5mW/Output(1) 225mW/Device mW VCC = 3.3 V T = 25°C 1. Value at VCC = 3.3 V TBD MC88LV926 IDT™ Low Skew CMOS PLL 68060 Clock Driver MC88LV926 Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Advanced Clock Drivers Device Data 2 Freescale Semiconductor 2 MC88LV926 Low Skew CMOS PLL 68060 Clock Driver NETCOM Table 2. Maximum Ratings(1) Symbol Parameter Limits Unit VCC, AVCC DC Supply Voltage Referenced to GND –0.5 to 7.0 V Vin DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V Vout DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V Iin DC Input Current, Per Pin ±20 mA Iout DC Output Sink/Source Current, Per Pin ±50 mA ICC DC VCC or GND Current Per Output Pin ±50 mA Tstg Storage Temperature –65 to +150 °C 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Table 3. Recommended Operating Conditions Symbol Limits Unit VCC Supply Voltage 3.3 ±0.3 V Vin DC Input Voltage 0 to VCC V Vout DC Output Voltage 0 to VCC V TA Ambient Operating Temperature 0 to 70 °C Static Discharge Voltage > 1500 V ESD Parameter Table 4. DC Characteristics (TA = 0°C to 70°C; VCC = 3.3 V ± 0.3 V)(1) Symbol VCC Parameter Guaranteed Limits Unit Condition 3.0 3.3 2.0 2.0 V VOUT = 0.1V or VCC – 0.1V Minimum Low Level Input Voltage 3.0 3.3 0.8 0.8 V VOUT = 0.1V or VCC – 0.1V VOH Minimum High Level Output Voltage 3.0 3.3 2.2 2.5 V VIN = VIH or VIL = –24mA IOH = –24mA VOL Minimum Low Level Output Voltage 3.0 3.3 0.55 0.55 V VIN = VIH or IIN Maximum Input Leakage Current 3.3 ±1.0 μA VI = VCC, GND ICCT Maximum ICC/Input 3.3 2.0 (3) mA VI = VCC – 2.1V IOLD Minimum Dynamic(4) Output Current 3.3 50 mA VOLD = 1.25V Max 3.3 –50 mA VOHD = 2.35 Min 3.3 750 μA VI = VCC, GND VIH Minimum High Level Input VIL Voltage(1) IOHD ICC Maximum Quiescent Supply Current VIL = +24mA(2) IOH = +24mA 1. The MC88LV926 can also be operated from a 3.3V supply. VOH output levels will vary 1:1 with VCC, input levels and current specs will be unchanged, except VIH; when VCC > 4.0 volts, VIH minimum level is 2.7 volts. 2. IOL is +12mA for the RST_OUT output. 3. Maximum test duration 2.0ms, one output loaded at a time. 4. The PLL_EN input pin is not guaranteed to meet this specification. IDT™ Low Skew CMOS PLL 68060 Clock Driver Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor 3 MC88LV926 MC88LV926 3 MC88LV926 Low Skew CMOS PLL 68060 Clock Driver NETCOM RST_OUT RST_IN Lock Indicator RESET_OUT 2X_Q Q ÷2 R SYNC1 CH PUMP PFD VCO Q Q0 ÷4 R PLL_EN 0 Q 1 Q1 ÷4 R ÷8 Q Q2 ÷4 R Q3 Q ÷4 R Power–On Reset CLKEN Delay ÷4 R MR Figure 2. MC88LV926 Logic Block Diagram Table 5. Sync Input Timing Requirements Symbol Parameter tRISE/FALL SYNC Input Rise/Fall Time, SYNC Input From 0.8V to 2.0V tCYCLE, SYNC Input Input Clock Period Duty Cycle Duty Cycle, SYNC Input SYNC Input(1) Minimum Maximum Unit – 5.0 ns 1 f2X_Q/4 200(1) ns 50% ± 25% 1. When VCC > 4.0 volts, Maximum SYNC Input Period is 125 ns. MC88LV926 IDT™ Low Skew CMOS PLL 68060 Clock Driver MC88LV926 Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Advanced Clock Drivers Device Data 4 Freescale Semiconductor 4 MC88LV926 Low Skew CMOS PLL 68060 Clock Driver NETCOM Table 6. Frequency Specifications (TA = 0°C to 70°C; VCC = 3.3 V ± 0.3 V Symbol Parameter Guaranteed Minimum Unit Fmax (2X_Q) Maximum Operating Frequency, 2X_Q Output 66 MHz Fmax (‘Q') Maximum Operating Frequency, Q0–Q3 Outputs 33 MHz NOTE: Maximum Operating Frequency is guaranteed with the 88LV926 in a phase-locked condition. Table 7. AC Characteristics (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V Symbol Parameter Minimum Maximum Unit Condition tRISE/FALL All Outputs Rise/Fall Time, into 50Ω Load 0.3 1.6 ns tRISE – 0.8 V to 2.0 V tFALL – 2.0 V to 0.8 V tRISE/FALL 2X_Q Output Rise/Fall Time into a 50Ω Load 0.5 1.6 ns tRISE – 0.8 V to 2.0 V tFALL – 2.0 V to 0.8 V tpulse width(a)(1) (Q0, Q1, Q2, Q3) Output Pulse Width Q0, Q1, Q2, Q3 at 1.65V 0.5tcycle – 0.5 0.5tcycle + 0.5 ns 50 Ω Load Terminated to VCC/ 2 (See Application Note 3) tpulse width(b)(1) (2X_Q Output) Output Pulse Width 2X_Q at 1.65V 0.5tcycle – 0.5 0.5tcycle + 0.5 ns 50 Ω Load Terminated to VCC/ 2 (See Application Note 3) tSKEWr(2) (Rising) Output–to–Output Skew Between Outputs Q0–Q2 (Rising Edge Only) – 500 ps Into a 50Ω Load Terminated to VCC/2 (See Timing Diagram in Figure 6) tSKEWf(2) (Falling) Output–to–Output Skew Between Outputs Q0–Q2 (Falling Edge Only) – 1.0 ns Into a 50 Ω Load Terminated to VCC/2 (See Timing Diagram in Figure 6) tSKEWall(2) Output–to–Output Skew 2X_Q, Q0–Q2, Q3 – 750 ps Into a 50 Ω Load Terminated to VCC/2 (See Timing Diagram in Figure 6) tSKEW QCLKEN(1) Output–to–Output Skew QCLKEN to 2X_Q 2X_Q = 50 MHz 2X_Q = 66 MHz ns 9.7(3) – Into a 50 Ω Load Terminated to VCC/2 (See Timing Diagram in Figure 6) (2) 7.0(3) tLOCK(4) Phase–Lock Acquisition Time, All Outputs to SYNC Input 1 10 ms tPHL MR – Q(1) Propagation Delay, MR to Any Output (High–Low) 1.5 13.5 ns 9 – ns Into a 50 Ω Load Terminated to VCC/2 tREC, MR to Reset Recovery Time rising MR edge to SYNC(1)(5) falling SYNC edge(6) tW, MR LOW(1) (5) Minimum Pulse Width, MR input Low 5 – ns tW, RST_IN Minimum Pulse Width, RST_IN Low 10 – ns When in Phase–Lock tPZL(1) Output Enable Time RST_IN Low to RST_OUT Low 1.5 16.5 ns See Application Notes, Note 5 tPLZ(1) Output Enable Time RST_IN High to RST_OUT High Z 1016 ‘Q' Cycles (508 Q/2 Cycles) 1024 ‘Q' Cycles (512 Q/2 Cycles) ns See Application Notes, Note 5 LOW(1) 1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this methodology. 2. Under equally loaded conditions and at a fixed temperature and voltage. 3. Guaranteed that QCLKEN will meet the setup and hold time requirement of the 68060. 4. With VCC fully powered–on: tCLOCK Max is with C1 = 0.1 μF; tLOCK Min is with C1 = 0.01 μF. 5. Specification is valid only when the PLL_EN pin is low. 6. See Application Notes, Note 4 for the distribution in time of each output referenced to SYNC. IDT™ Low Skew CMOS PLL 68060 Clock Driver Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor 5 MC88LV926 MC88LV926 5 MC88LV926 Low Skew CMOS PLL 68060 Clock Driver NETCOM APPLICATION NOTES 1. 2. Statistical characterization techniques were used to guarantee those specifications which cannot be measured on the ATE. MC88LV926 units were fabricated with key transistor properties intentionally varied to create a 14 cell designed experimental matrix. IC performance was characterized over a range of transistor properties (represented by the 14 cells) in excess of the expected process variation of the wafer fabrication area. IC performance to each specification and fab variation were used to set performance limits of ATE testable specifications within those which are to be guaranteed by statistical characterization. In this way, all units passing the ATE test will meet or exceed the nontested specifications limits. A 470 KΩ or 1 MΩ resistor tied to either Analog VCC or Analog GND, as shown in Figure 3, is required to 3. ensure no jitter is present on the MC88LV926 outputs. This technique causes a phase offset between the SYNC input and the Q0 output, measured at the pins. The tPD spec describes how this offset varies with process, temperature, and voltage. The specs were arrived at by measuring the phase relationship for the 14 lots described in note 1 while the part was in phaselocked operation. The actual measurements were made with a 10 MHz SYNC input (1.0 ns edge rate from 0.8 V to 2.0 V). The phase measurements were made at 1.5 V. See Figure 3 for a graphical description. Two specs (tRISE/FALL and tPULSE Width 2X_Q output, see AC Specifications) guarantee that the MC88LV926 meets the 33 MHz and 66 MHz 68060 P-Clock input specification. RC1 External Loop Filter 330 Ω 0.1 μF Analog VCC 1 MΩ or 470 KΩ Reference Resistor R2 C1 1 MΩ or 470 K Ω Reference Resistor RC1 330 Ω 0.1 μF Analog GND C1 Analog GND With the 470 KΩ resistor tied in this fashion, the TPD specification measured at the input pins is: With the 470 KΩ resistor tied in this fashion, the TPD specification measured at the input pin is: tPD = 2.25 ns ± 1.0 ns (Typical Values) tPD = –0.80 ns ± 0.30 ns 3V SYNC InputT R2 3V SYNC Input 2.25 ns Offset –0.8 ns Offset 5V 5V Q0 OutputT Q0 Output Figure 3. Depiction of the Fixed SYNC to Q0 Offset (tPD) Which Is Present When a 470 KΩ Resistor Is Tied to VCC or Ground RST_OUT Pin VCC 1K Internal Logic CL Analog GND Figure 4. RST_OUT Test Circuit MC88LV926 IDT™ Low Skew CMOS PLL 68060 Clock Driver MC88LV926 Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Advanced Clock Drivers Device Data 6 Freescale Semiconductor 6 MC88LV926 Low Skew CMOS PLL 68060 Clock Driver NETCOM 2X_Q 12.5 MHz Crystal Oscillator Q0 Q1 Q2 SYNC MR PLL_EN RST_IN 66 MHz P–Clock Output 33 MHz B–Clock and System Outputs Q3 QCLKEN RST_OUT Delay 33 MHz CLKEN Output Figure 5. Logical Representation of the MC88LV926 With Input/Output Frequency Relationships SYNC Input tCYCLE SYNC Input tSKEWall tSKEWf tSKEWr tSKEWf tSKEWr Q0–Q3 Outputs tCYCLE ‘Q' Outputs 2X_Q Output QCLKEN tSKEWQCLKEN tSKEWQCLKEN NOTES: 1. The MC88LV926 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50% duty cycle. 2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as “windows”, not as a ± deviation around a center point. Figure 6. Output/Input Switching Waveforms and Timing Relationships 4. The tPD spec includes the full temperature range from 0°C to 70°C and the full VCC range from 3.0 V to 3.3 V. If the ΔT and ΔVCC is a given system are less than the specification limits, the tPD spec window will be reduced. 5. The RST_OUT pin is an open drain N–Channel output. Therefore an external pull–up resistor must be provide to pull up the RST_OUT pin when it goes into the high impedance state (after the MC88LV926 is phase-locked to the reference input with RST_IN held high or 1024 ‘Q' cycles after the RST_IN pin goes high when the part is locked). In the tPLZ and tPZL specifications, a 1 KΩ resistor is used as a pull-up as shown in Figure 3. IDT™ Low Skew CMOS PLL 68060 Clock Driver Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor 7 MC88LV926 MC88LV926 7 MC88LV926 Low Skew CMOS PLL 68060 Clock Driver NETCOM NOTES CONCERNING LOOP FILTER AND BOARD LAYOUT ISSUES 1. Figure 7 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter-free operation: 1a. All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable voltage transients at the RC1 pin. 1b. The 47 Ω resistors, the 10 μF low frequency bypass capacitor, and the 0.1 μF high frequency bypass capacitor form a wide bandwidth filter that will make the 88LV926 PLL insensitive to voltage transients from the system digital VCC supply and ground planes. This filter will typically ensure that a 100mV step deviation on the digital VCC supply will cause no more than a 100 ps phase deviation on the 88LV926 outputs. A 250 mV step deviation on VCC using the recommended filter values will cause no more than a 250 ps phase deviation; if a 25 μF bypass capacitor is used (instead of 10 μF) a 250 mV VCC step will cause no more than a 100 ps phase deviation. If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, the above described VCC step deviations should not occur at the 88LV926's digital VCC supply. The purpose of the bypass filtering scheme shown in Figure 6 is to give the 88LV926 additional protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system. 1c. There are no special requirements set forth for the loop filter resistors (470 K and 33 0Ω). The loop filter capacitor (0.1uF) can be a ceramic chip capacitor, the same as a standard bypass capacitor. 1d. The 470 K reference resistor injects current into the internal charge pump of the PLL, causing a fixed offset between the outputs and the SYNC input. This also prevents excessive jitter caused by inherent PLL dead– band. If the VCO (2X_Q output) is running above 40 MHz, the 470 K resistor provides the correct amount of current injection into the charge pump (2–3 μA). If the VCO is running below 40 MHz, a 1 MΩ reference resistor should be used (instead of 470 K). 2. In addition to the bypass capacitors used in the analog filter of Figure 7, there should be a 0.1 μF bypass capacitor between each of the other (digital) four VCC pins and the board ground plane. This will reduce output switching noise caused by the 88LV926 outputs, in addition to reducing potential for noise in the ‘analog' section of the chip. These bypass capacitors should also be tied as close to the 88LV926 package as possible. Board VCC NOTE: Further loop optimization may occur. 47 Ω 5 10 μF Low Freq Bias 0.1 μF High Freq Bias 470 KΩ or Analog VCC 330 Ω 1 MΩ 6 RC1 7 Analog GND 0.1 μF (Loop Filter Cap) Analog Loop Filter/VCO Section of the MC88LV926 20-Pin SOIC Package (not drawn to scale) 47 Ω Board GND A separate Analog power suppy is not necessary and should not be used. Following these prescribed guidelines is all that is necessary to use the MC88LV926 in a normal digital environment. Figure 7. Recommended Loop Filter and Analog Isolation Scheme for the MC88LV926 MC88LV926 IDT™ Low Skew CMOS PLL 68060 Clock Driver MC88LV926 Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Advanced Clock Drivers Device Data 8 Freescale Semiconductor 8 MC88LV926 Low Skew CMOS PLL 68060 Clock Driver NETCOM MC68060 16.67 MHz X–TAL Oscillator SYNC System Reset RST_IN 2X_Q QCLKEN Q0 Q1 Q2 Q3 66MHz ASIC PCLK CLKEN Reset ASIC 33MHz RST_OUT Memory Module Figure 8. Typical MC88LV926/MC68060 System Configuration IDT™ Low Skew CMOS PLL 68060 Clock Driver Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor 9 MC88LV926 MC88LV926 9 MC88LV926 Low Skew CMOS PLL 68060 Clock Driver NETCOM PACKAGE DIMENSIONS 10X PIN NUMBER 10.55 10.05 0.25 M B 2.65 2.35 0.25 0.10 A 20X 1 20 PIN 1 INDEX 0.49 0.35 0.25 6 M T A B 18X 1.27 A 10 4 12.95 12.65 A 11 T SEATING PLANE 20X 7.6 7.4 0.1 T B 5 0.75 X45˚ 0.25 0.32 0.23 1.0 0.4 7˚ 0˚ NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS A AND B TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. INTER-LEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE WIDTH TO EXCEED 0.62 MM. SECTION A-A CASE 751D-06 ISSUE H 20-LEAD SOIC PACKAGE MC88LV926 IDT™ Low Skew CMOS PLL 68060 Clock Driver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 10 10 MC88LV926 Advanced Clock Drivers Devices Freescale Semiconductor MC88LV926 MPC92459 PART NUMBERS 900 Low MHz Skew Low CMOS Voltage PLL LVDS 68060 Clock Clock Synthesizer Driver TITLE INSERT PRODUCT NAME AND DOCUMENT NETCOM NETCOM Innovate with IDT and accelerate your future networks. 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