AD9122-DSCC: Military Data Sheet

REVISIONS
LTR
DESCRIPTION
DATE
Prepared in accordance with ASME Y14.24
APPROVED
Vendor item drawing
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PMIC N/A
PREPARED BY
Phu H. Nguyen
Original date of drawing
YY MM DD
CHECKED BY
13-01-11
Phu H. Nguyen
APPROVED BY
Thomas M. Hess
SIZE
A
REV
AMSC N/A
4
CODE IDENT. NO.
5
6
7
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9
10
11
12
13
14
15
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil/
TITLE
MICROCIRCUIT, DIGITAL-LINEAR, DUAL,
16-BIT, 1130 MSPS, TxDAC+ DIGITAL TO
ANALOG CONVERTER, MONOLITHIC SILICON
DWG NO.
V62/12654
16236
PAGE
1
OF
15
5962-V036-13
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance dual, 16-bit, 1130 MSPS, TxDAC+ digital to
analog converter microcircuit, with an operating temperature range of -55°C to +105°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/12654
-
Drawing
number
01
X
E
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s).
Device type
Generic
01
AD9122-EP
Circuit function
Dual, 16-bit, 1130 MSPS, TxDAC+ digital to analog converter
1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter
Number of pins
X
72
JEDEC PUB 95
Package style
JEDEC MO-220-VNND-4
Lead Frame Chip Scale Package
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
Z
DLA LAND AND MARITIME
COLUMBUS, OHIO
Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12654
PAGE
2
1.3 Absolute maximum ratings.
1/
AVDD33 to AVSS, EPAD, CVSS, DVSS ...............................................................
IOVDD to AVSS, EPAD, CVSS, DVSS ..................................................................
DVDD18, CVDD18 to AVSS, EPAD, CVSS, DVSS ...............................................
AVSS to EPAD, CVSS, DVSS ...............................................................................
EPAD to AVSS, CVSS, DVSS ...............................................................................
CVSS to AVSS, EPAD, DVSS ...............................................................................
DVSS to AVSS, EPAD, CVSS ...............................................................................
FSADJ, REFIO, IOUT1P, IOUT1N, IOUT2P, IOUT2N to AVSS ............................
D[15:0]P, D[15:0]N, FRAMEP, FRAMEN, DCIP, DCIN to EPAD, DVSS ................
DACCLKP, DACCLKN, REFCLKP, REFCLKN to CVSS .......................................
���������
RESET, �����
IRQ, ���
CS, SCLK, SDIO, SDO to EPAD, DVSS .............................................
Junction temperature .............................................................................................
Storage temperature range ....................................................................................
-0.3 V to +3.6 V
-0.3 V to +3.6 V
-0.3 V to +2.1 V
-0.3 V to +0.3 V
-0.3 V to +0.3 V
-0.3 V to +0.3 V
-0.3 V to +0.3 V
-0.3 V to AVDD33 + 0.3 V
-0.3 V to DVDD18 + 0.3 V
-0.3 V to CVDD18 + 0.3 V
-0.3 V to IOVDD + 0.3 V
125°C
-65°C to +150°C
1.4 Thermal characteristics.
Thermal resistance
Case outline
Case X
θJA
θJB
θJC
Unit
20.7
10.9
1.1
°C/W
Conditions
EPAD soldered to
ground plane
2. APPLICABLE DOCUMENTS
JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)
JEP95
–
Registered and Standard Outlines for Semiconductor Devices
(Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103
North 10th Street, Suite 240–S, Arlington, VA 22201-2107)
THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE)
IEEE Standard 1596
-
IEEE Standard for low-voltage differential signals (LVDS) for scalable coherent.
(Copies of these documents are available online at http://www.ieee.org or from the IEEE Service Center, 445 Hoes Lane, P.O. Box
1331, Piscataway, NJ 08855–1331.
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
1/
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12654
PAGE
3
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as
specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1
Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2
Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3
Terminal function. The terminal function shall be as shown in figure 3.
3.5.4
Functional block diagram. The functional block diagram shall be as shown in figure 4.
3.5.5
Timing diagram for input data port. The timing diagram for input data port shall be as shown in figure 5.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12654
PAGE
4
TABLE I. Electrical performance characteristics. 1/
Test
Symbol
Limits
Test conditions
2/
Min
Typ
Unit
Max
DC SPECIFICATIONS
Resolution
Accuracy
Differential Nonlinearity
Integral Nonlinearity
Main DAC outputs
Offset error
Gain error (with internal reference)
Full scale output current 3/
Output compliance range
Power Supply Rejection Ratio, AVD33
output resistance
Gain ADC monotonicity
Settling time to within ±0.5 LSB
Main DAC temperature drift
Offset
Gain
Reference voltage
Reference
Internal reference voltage
Output resistance
Analog supply voltages
AVD33
CVD18
Digital supply voltages
DVDD18
IOVDD
Power consumption
2 x Mode
2 x Mode
8 x Mode
AVDD33
CVDD18
DVDD18
Power down mode
(Register 0x01 = 0xF0)
Power up time
Operating range
DNL
INL
-0.001
-4.6
8.66
-1.0
-0.3
16
Bits
±2.1
±3.7
LSB
LSB
0
±2
19.6
+0.001
+4.6
31.66
+1.0
+0.3
10
4/
20
%FSR
mA
V
%FSR/V
MΩ
ns
0.04
100
30
ppm/°C
1.2
5
V
kΩ
3.13
1.71
3.3
1.8
3.47
1.89
V
1.71
1.71
1.8
1.8/3.3
1.89
3.47
V
fDAC = 491.22 MSPS, IF = 10 MHz, PLL Off
fDAC = 491.22 MSPS, IF = 10 MHz, PLL On
fDAC = 800 MSPS, IF = 10 MHz, PLL Off
-55
834
913
1135
55
85
444
6.5
mW
1259
57
90
505
18.8
260
+25
+105
mA
mW
ms
°C
See footnote at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12654
PAGE
5
TABLE I. Electrical performance characteristics - Continued. 1/
Test
Symbol
Limits
Test conditions
5/
Min
Typ
Unit
Max
DIGITAL SPECIFICATIONS
CMOS input logic level
Input VIN logic high
Input VIN logic low
IOVDD = 1.8 V
IOVDD = 2.5 V
IOVDD = 3.3 V
IOVDD = 1.8 V
IOVDD = 2.5 V, 3.3 V
1.2
1.6
2.0
V
0.6
0.8
CMOS output logic level
IOVDD = 1.8 V
IOVDD = 2.5 V
IOVDD = 3.3 V
Input VIN logic low
IOVDD = 1.8 V, 2.5 V, 3.3 V
LVDS receiver inputs 6/ (Applies to data, DCI, and FRAME inputs)
Input voltage range,
VIA or VIB
Input differential threshold
VIDTH
Input differential hysteresis,
VIDTHH to
VIDTHL
Receiver differential input impedance
RIN
LVDS input rate
7/
DAC clock input (DACCLKP, DACCLKN)
Differential peak-to-peak voltage
Common mode voltage
Self-biased input, ac-coupled
Maximum clock rate
REFCLK input (REFCLKP, REFCLKN)
Differential peak-to-peak voltage
Common mode voltage
REFCLK frequency (PLL mode)
1 GHz ≤ fVCO ≤ 2.1 GHz
REFCLK frequency (SYNC mode)
See Multichip synchronization section of
the manufacturer data for more conditions
Serial port interface
Maximum clock rate
SCLK
Maximum pulse width high
tPWH
Minimum pulse width low
tPWL
Setup time, SDIO to SCLK
tDS
Hold time, SDIO to SCLK
tDH
Data valid, SDO to SCLK
tDV
���
tDCSB
Setup time, CS to SCLK
Input VIN logic high
1.4
1.8
2.4
V
0.4
825
-100
1675
+100
mV
120
Ω
500
1.25
2000
mV
V
MHz
500
1.25
2000
mV
V
MHz
20
80
100
1230
100
15.625
0
600
600
40
12.5
12.5
MHz
ns
2.1
0.75
2.85
1.4
See footnote at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12654
PAGE
6
TABLE I. Electrical performance characteristics - Continued. 1/
Test
Symbol
Limits
Test conditions
5/
Min
Unit
Typ
Max
DIGITAL INPUT DATA TIMING SPECIFICATIONS
Latency (DACCLK cycles)
1 x Interpolation (With or without modulation)
1 x Interpolation (With or without modulation)
1 x Interpolation (With or without modulation)
1 x Interpolation (With or without modulation)
Inverse Sinc
Fire modulation
Test
Spurious-Free Dynamic Range (SFDR)
Two tone Intermodulation Distortion (IMD)
Noise Spectral Density (NSD),
Eight-tone, 500 kHz tone spacing
W-CDMA Adjacent Channel Leakage Ratio
(ACLR), Single carrier
W-CDMA second ACLR, single carrier
64
135
292
608
20
8
Symbol
Test conditions
2/
Cycles
Limits
Min
AC SPECIFICATIONS
fDAC = 100 MSPS, fOUT = 20 MHz
fDAC = 200 MSPS, fOUT = 50 MHz
fDAC = 400 MSPS, fOUT = 70 MHz
fDAC = 800 MSPS, fOUT = 70 MHz
fDAC = 200 MSPS, fOUT = 50 MHz
fDAC = 400 MSPS, fOUT = 60 MHz
fDAC = 400 MSPS, fOUT = 80 MHz
fDAC = 800 MSPS, fOUT = 100 MHz
fDAC = 200 MSPS, fOUT = 80 MHz
fDAC = 400 MSPS, fOUT = 80 MHz
fDAC = 800 MSPS, fOUT = 80 MHz
fDAC = 491.52 MSPS, fOUT = 10 MHz
fDAC = 491.52 MSPS, fOUT = 122.88 MHz
fDAC = 983.04 MSPS, fOUT = 122.88 MHz
fDAC = 491.52 MSPS, fOUT = 10 MHz
fDAC = 491.52 MSPS, fOUT = 122.88 MHz
fDAC = 983.04 MSPS, fOUT = 122.88 MHz
Typ
Unit
Max
78
80
69
72
84
86
84
81
-162
-163
-164
84
82
83
88
86
88
dBc
dBc
dBm/Hz
dBc
dBc
See footnote at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12654
PAGE
7
TABLE I. Electrical performance characteristics - Continued. 1/
1/
2/
3/
4/
5/
6/
7/
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not
necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise
noted.
Based on a 10 kΩ external resistor between FSADJ and AVSS.
Guaranteed.
TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate,
unless otherwise noted.
LVDS receiver is compliant with the IEEE 1596 reduced range link, unless otherwise noted.
Maximum rate (MSPS) with DVDD and CVDD supply regulation
Bus Width
Nibble (4 Bits)
Byte (8 Bits)
Word (16 Bits)
Interpolation
factor
1x
2x
4x
8x
1x
2x
4x
8x
1x
2 x (HB1)
2 x (HB2)
4x
8x
fINTERFACE (MSPS)
DVDD18, CVDD18 =
1.8 V ± 5% 1.8 V ± 2% 1.9 V ± 2%
1000
1100
1130
1000
1100
1130
1000
1100
1130
1000
1100
1130
1000
1100
1130
1000
1100
1130
1000
1100
1130
500
550
565
1000
1100
1130
800
900
900
1000
1100
1130
500
550
565
250
275
282.5
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
fDAC (MSPS)
DVDD18, CVDD18 =
1.8 V ± 5%
1.8 V ± 2%
1.9 V ± 2%
125
137.5
141.25
250
275
282.5
500
550
565
1000
1100
1130
250
275
282.5
500
550
565
1000
1100
1130
1000
1100
1130
500
550
565
800
900
900
1000
1100
1130
1000
1100
1130
1000
1100
1130
CODE IDENT NO.
16236
REV
DWG NO.
V62/12654
PAGE
8
Case X
D/E
D1/E1
PIN 1
IDENTIFIER
TOP VIEW
12° MAX
SEATING
PLANE
A1
A
L1
19
18
A3
A2
e
b
48 PLS
36
37
L1
EXPOSED
PAD
D2/E2
PIN 1
IDENTIFIER
L
1
54
55
72
e1
BOTTOM VIEW
FIGURE 1. Case outline.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12654
PAGE
9
Dimensions
Millimeters
Symbol
Min
Max
Symbol
A
A1
A2
A3
b
D/E
0.80
1.00
0.80
0.20 REF
0.05
0.18
0.30
10.00 BSC
D1/E1
D2/E2
e
e1
L
L1
Millimeters
Min
Max
9.75 BSC
5.85
6.15
0.50 BSC
8.50 REF
0.30
0.50
0.24
0.60
NOTES:
1. All linear dimensions are in millimeters.
2. Falls within JEDEC MO-220-VNND-4.
FIGURE 1. Case outline - Continued.
Case outline X
Terminal
Terminal
symbol
number
Terminal
number
Terminal
symbol
Terminal
number
1
2
3
CVDD18
DACCLKP
DACCLKN
19
20
21
4
5
CVSS
FRAMEP
22
23
D10N
6
7
8
9
10
11
12
13
14
15
16
17
18
FRAMEN
�����
IRQ
D15P
D15N
NC
IOVDD
DVDD18
D14P
D14N
D13P
D13N
D12P
D12N
24
25
26
27
28
29
30
31
32
33
34
35
36
D11P
D11N
Terminal
symbol
Terminal
number
Terminal
symbol
D4P
D4N
55
56
57
NC
AVSS
AVDD33
58
59
IOUT2P
IOUT2N
60
61
62
63
64
65
66
67
68
69
70
71
72
AVDD33
AVSS
REFIO
FSADJ
AVSS
AVDD33
IOUT1N
IOUT1P
AVDD33
REFCLKN
REFCLKP
CVDD18
CVDD18
37
38
39
D3P
D9P
40
41
D2P
D9N
D8P
D8N
DCIP
DCIN
DVDD18
DVSS
D7P
D7N
D6P
D6N
D5P
D5N
42
43
44
45
46
47
48
49
50
51
52
53
54
D10P
D3N
D2N
DVDD18
DVSS
D1P
D1N
D0P
D0N
DVDD18
SDO
SDIO
SCLK
���
CS
���������
RESET
NOTES:
1. Exposed PAD (EPAD) must be soldered to the ground plane (AVSS). The EPAD provides an electrical, thermal,
and mechanical connection to the board.
2. NC = No Connect. Do not connect to this pin.
FIGURE 2. Terminal connections.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12654
PAGE
10
Case outline X
Terminal
number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Mnemonic
Description
CVDD18
DACCLKP
DACCLKN
CVSS
FRAMEP
FRAMEN
�����
IRQ
1.8 V clock supply. Supplies clock receivers, clock distribution, and PLL circuitry
DAC clock input, positive.
DAC clock input, negative.
Clock supply common.
Frame input, Positive. This pin must be tied to DVSS if not used.
Frame input, Negative. This pin must be tied to DVDD18 if not used.
Interrupt request. Open rain, active low output. Connect an external pull-up to IOVDD through a 10
kΩ resistor.
Data bit 15 (MSB), Positive.
Data bit 15 (MSB), Negative.
No connect. Do not connect to this pin.
�����������, and IRQ
�����. 1.8 V to 3.3 V can be supplied to this pin.
Supply pin for Serial port I/O pins, RESERT
1.8 V digital supply. Supplies power to digital core and digital data ports.
Data bit 14, Positive.
Data bit 14, Negative.
Data bit 13, Positive.
Data bit 13, Negative.
Data bit 12, Positive.
Data bit 12, Negative.
Data bit 11, Positive.
Data bit 11, Negative.
Data bit 10, Positive.
D15P
D15N
NC
IOVDD
DVDD18
D14P
D14N
D13P
D13N
D12P
D12N
D11P
D11N
D10P
22
23
D10N
24
25
26
27
28
29
30
31
32
33
34
35
36
D9N
D8P
D8N
DCIP
DCIN
DVDD18
DVSS
D7P
D7N
D6P
D6N
D5P
D5N
D9P
Data bit 10, Negative.
Data bit 9, Positive.
Data bit 9, Negative.
Data bit 8, Positive.
Data bit 8, Negative.
Data clock input, Positive.
Data clock input, Negative.
1.8 V Digital supply. Supplies power to digital core and digital data ports.
Digital common.
Data bit 7, Positive.
Data bit 7, Negative.
Data bit 6, Positive.
Data bit 6, Negative.
Data bit 5, Positive.
Data bit 5, Negative.
FIGURE 3. Terminal function.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
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REV
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PAGE
11
Case outline X - Continued
Terminal
number
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Mnemonic
D4P
D4N
D3P
D3N
D2P
D2N
DVDD18
DVSS
D1P
D1N
D0P
D0N
DVDD18
SDO
SDIO
SCLK
���
CS
���������
RESET
NC
AVSS
AVDD33
IOUT2P
IOUT2N
AVDD33
AVSS
REFIO
FSADJ
AVSS
AVDD33
IOUT1N
IOUT1P
AVDD33
REFCLKN
REFCLKP
CVDD18
CVDD18
EPAD
Description
Data bit 4, Positive.
Data bit 4, Negative.
Data bit 3, Positive.
Data bit 3, Negative.
Data bit 2, Positive.
Data bit 2, Negative.
1.8 V Digital supply. Supplies power to digital core and digital data ports.
Digital common.
Data bit 1, Positive.
Data bit 1, Negative.
Data bit 0, Positive.
Data bit 0, Negative.
1.8 V Digital supply. Supplies power to digital core and digital data ports.
Serial port data Output (CMOS levels with respect to IOVDD)
Serial port data Input/Output (CMOS levels with respect to IOVDD)
Serial port clock Input (CMOS levels with respect to IOVDD)
Serial port chip select, Active low (CMOS levels with respect to IOVDD)
Reset, Active low (CMOS levels with respect to IOVDD)
No Connect. Do not connect to this pin.
Analog supply common.
3.3 V Analog supply.
Q DAC Positive current output.
Q DAC Negative current output.
3.3 V Analog supply.
Analog supply common.
Voltage reference. Nominally 1.2 V output. Should be decoupled to AVSS.
Full Scale current output adjust. Place a 10 kΩ resistor from this pin to AVSS.
Analog supply common.
3.3 V Analog supply.
I DAC Negative current output.
I DAC Positive current output.
3.3 V Analog supply.
PLL reference clock input, Negative. This pin has s secondary function as a synchronization input.
PLL reference clock input, Positive. This pin has s secondary function as a synchronization input.
1.8 V Clock supply. Supplies clock receivers, clock distribution, and PLL circuitry
1.8 V Clock supply. Supplies clock receivers, clock distribution, and PLL circuitry
The exposed pad (EPAD) must be soldered to the ground plane (AVSS). The EPAD provides an electrical
thermal, and mechanical connection to the board.
FIGURE 3. Terminal function - Continued.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
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REV
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12
16
f
/2
NCO
AND
MOD
HB1
PRE
MOD
HB2
10
HB3
I OFFSET
INV
SINC
IOUT1N
DAC_CLK
Q OFFSET
DAT
REC
A
EIVE
R
FIFO
DATA
IOUT1P
AUX
DAC 1
16-BIT
16
D15P/D15N
D0P/D0N
1.2 G
16
DCIP/DCIN
FRAMEP/FRAMEN
16
1.2 G
IOUT2N
GAIN 2
GAIN 1
INVSINC_CLK
PHASE
CORRECTION
INTP
FACTOR
HB3_CLK
HB2_CLK
MODE
HB1_CLK
10
IOUT2P
AUX
DAC 2
16-BIT
REF
AND
BIAS
10
INTERNAL CLOCK TIMING AND CONTROL LOGIC
REFIO
FSADJ
DAC CLK_SEL
PROGRAMMING
REGISTERS
PLL
CONTROL
SERIAL
INPUT/OUTPUT
PORT
POWER-ON
RESET
MULTICHIP
SYNCHRONIZATION
SYNC
0
DAC_CLK
1
CLOCK
MULTIPLIER
(2x TO 16x)
CLK
RCVR
DACCLKP
CLK
RCVR
REFCLKP
DACCLKN
REFCLKN
RESET
CS
IRQ
SCLK
SDO
SDIO
PLL_LOCK
FIGURE 4. Functional block diagram.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12654
PAGE
13
tDATA
tDATA
DCI
SAMPLING
INTERVAL
SAMPLING
INTERVAL
DATA
tS
tH
tH
tS
Data to DCI setup and hold times
DCI delay register Minimum setup time,
0x16, Bits[1:0]
ts (ns)
00
-0.01
01
-0.19
10
-0.38
11
-0.44
Minimum hold time,
tH (ns)
0.65
0.95
1.22
1.38
Sampling interval
(ns)
0.64
0.76
0.84
0.94
The data interface timing can be verified by using sample error detection (SED) circuitry.
For more information, see the interface timing validation section in the manufacturer data
sheet.
FIGURE 5. Timing diagram for input data port.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12654
PAGE
14
4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of
present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current
sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Vendor item drawing
administrative control
number 1/
Device
manufacturer
CAGE code
Vendor part number
V62/12654-01XE
24355
AD9122SCPZ-EP
1/ The vendor item drawing establishes an administrative control number for
identifying the item on the engineering documentation.
CAGE code
24355
DLA LAND AND MARITIME
COLUMBUS, OHIO
Source of supply
Analog Devices
1 Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12654
PAGE
15
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