PDF Data Sheet Rev. A

Dual, Low Power, 8-/10-/12-/14-Bit
TxDAC Digital-to-Analog Converters
AD9714/AD9715/AD9716/AD9717
FEATURES
GENERAL DESCRIPTION
Power dissipation @ 3.3 V, 2 mA output
37 mW @ 10 MSPS
86 mW @ 125 MSPS
Sleep mode: <3 mW @ 3.3 V
Supply voltage: 1.8 V to 3.3 V
SFDR to Nyquist
84 dBc @ 1 MHz output
75 dBc @ 10 MHz output
AD9717 NSD @ 1 MHz output, 125 MSPS, 2 mA: −151 dBc/Hz
Differential current outputs: 1 mA to 4 mA
2 on-chip auxiliary DACs
CMOS inputs with single-port operation
Output common mode: adjustable 0 V to 1.2 V
Small footprint 40-lead LFCSP RoHS-compliant package
The AD9714/AD9715/AD9716/AD9717 are pin-compatible,
dual, 8-/10-/12-/14-bit, low power digital-to-analog converters
(DACs) that provide a sample rate of 125 MSPS. These TxDAC®
converters are optimized for the transmit signal path of communication systems. All the devices share the same interface, package,
and pinout, providing an upward or downward component
selection path based on performance, resolution, and cost.
APPLICATIONS
1.
Wireless infrastructures
Picocell, femtocell base stations
Medical instrumentation
Ultrasound transducer excitation
Portable instrumentation
Signal generators, arbitrary waveform generators
The AD9714/AD9715/AD9716/AD9717 offer exceptional ac and
dc performance and support update rates up to 125 MSPS.
The flexible power supply operating range of 1.8 V to 3.3 V and
low power dissipation of the AD9714/AD9715/AD9716/AD9717
make them well-suited for portable and low power applications.
PRODUCT HIGHLIGHTS
2.
3.
Low Power.
DACs operate on a single 1.8 V to 3.3 V supply; total power
consumption reduces to 35 mW at 125 MSPS with a 1.8 V
supply. Sleep and power-down modes are provided for low
power idle periods.
CMOS Clock Input.
High speed, single-ended CMOS clock input supports a
125 MSPS conversion rate.
Easy Interfacing to Other Components.
Adjustable output common mode from 0 V to 1.2 V allows
easy interfacing to other components that accept commonmode levels greater than 0 V.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved.
AD9714/AD9715/AD9716/AD9717
TABLE OF CONTENTS
Features .............................................................................................. 1 Estimating the Overall DAC Pipeline Delay........................... 42 Applications ....................................................................................... 1 Reference Operation .................................................................. 43 General Description ......................................................................... 1 Reference Control Amplifier .................................................... 43 Product Highlights ........................................................................... 1 DAC Transfer Function ............................................................. 44 Revision History ............................................................................... 3 Analog Output ............................................................................ 44 Functional Block Diagram .............................................................. 4 Self-Calibration........................................................................... 45 Specifications..................................................................................... 5 Coarse Gain Adjustment ........................................................... 46 DC Specifications ......................................................................... 5 Using the Internal Termination Resistors ............................... 47 Digital Specifications ................................................................... 7 Applications Information .............................................................. 48 AC Specifications.......................................................................... 8 Output Configurations .............................................................. 48 Absolute Maximum Ratings............................................................ 9 Differential Coupling Using a Transformer ............................... 48 Thermal Resistance ...................................................................... 9 Single-Ended Buffered Output Using an Op Amp ................ 48 ESD Caution .................................................................................. 9 Differential Buffered Output Using an Op Amp ................... 49 Pin Configurations and Function Descriptions ......................... 10 Auxiliary DACs........................................................................... 49 Typical Performance Characteristics ........................................... 18 DAC-to-Modulator Interfacing ................................................ 50 Terminology .................................................................................... 31 Theory of Operation ...................................................................... 32 Correcting for Nonideal Performance of Quadrature
Modulators on the IF-to-RF Conversion ................................ 50 Serial Peripheral Interface (SPI) ................................................... 33 I/Q-Channel Gain Matching .................................................... 50 General Operation of the Serial Interface ............................... 33 LO Feedthrough Compensation .............................................. 51 Instruction Byte .......................................................................... 33 Results of Gain and Offset Correction .................................... 51 Serial Interface Port Pin Descriptions ..................................... 33 Modifying the Evaluation Board to Use the ADL5370
On-Board Quadrature Modulator ........................................... 52 MSB/LSB Transfers..................................................................... 34 Serial Port Operation ................................................................. 34 Pin Mode ..................................................................................... 34 SPI Register Map............................................................................. 35 SPI Register Descriptions .............................................................. 36 Digital Interface Operation ........................................................... 40 Digital Data Latching and Retimer Block ............................... 41 Evaluation Board Shematics and Artwork .................................. 53 Schematics ................................................................................... 53 Silkscreens ................................................................................... 61 Bill of Materials ............................................................................... 76 Outline Dimensions ....................................................................... 79 Ordering Guide .......................................................................... 79 Rev. A | Page 2 of 80
AD9714/AD9715/AD9716/AD9717
REVISION HISTORY
3/09—Rev. 0 to Rev. A
Changes to Figure 1........................................................................... 4
Changed DVDD = 3.3 V to DVDD = 1.8 V,
Table 1 Conditions ............................................................................ 5
Changes to Table 1 ............................................................................ 5
Changed DVDD = 3.3 V to DVDD = 1.8 V,
Table 2 Conditions ............................................................................ 7
Changed DVDD = 3.3 V to DVDD = 1.8 V, and DVDDIO = 1.8 V
to DVDDIO = 3.3 V, Table 3 Conditions ....................................... 8
Changed DVDD = 3.3 V to DVDD = 1.8 V, CVDD = 3.3 V to
CVDD = 1.8 V, Table 4 Conditions................................................. 8
Changes to Table 5 and Table 6 ....................................................... 9
Changes to Figure 2 and Table 7 ...................................................10
Changes to Figure 3 and Table 8 ...................................................12
Changes to Figure 4 and Table 9 ...................................................14
Changes to Table 10 ........................................................................16
Changes to Typical Performance Characteristics Section .........18
Changes to Figure 84 and Theory of Operation Section ...........32
Added Figure 85 to Figure 88; Renumbered Sequentially .........34
Changes to Pin Mode Section........................................................35
Changes to Table 13 ........................................................................36
Changes to Table 14 ........................................................................37
Changes to Digital Interface Operation Section and Figure 89 to
Figure 93 ........................................................................................... 40
Changes to Digital Data Latching and Retimer Block Section,
Figure 94, and Retimer Section ..................................................... 41
Changes to Estimating the Overall DAC Pipeline Delay
Section .............................................................................................. 42
Added Reference Operation Section, Figure 96,
Recommendations When Using an External Reference Section,
and Reference Control Amplifier Section.................................... 43
Added Table 17; Renumbered Sequentially ................................. 43
Added DAC Transfer Function Section and Analog Output
Section .............................................................................................. 44
Changes to Figure 99 and Figure 100 ........................................... 46
Changes to Auxiliary DACs Section and Figure 107.................. 49
Changes to DAC-to-Modulator Interfacing Section and
Figure 108 ......................................................................................... 49
Changes to Figure 108 and Figure 109 ......................................... 50
Added Evaluation Board Schematics and Artwork Section, and
Figure 112 to Figure 134................................................................. 53
Added Bill of Materials Section and Table 18 ............................. 76
8/08—Revision 0: Initial Version
Rev. A | Page 3 of 80
AD9714/AD9715/AD9716/AD9717
AD9717
1V
SPI
INTERFACE
DB11
QRSET
16kΩ
DB10
CMLI
FSADJI/AUXI
FSADJQ/AUXQ
REFIO
RESET/PINMD
SCLK/CLKMD
SDIO/FORMAT
CS/PWRDN
DB13 (MSB)
DB12
FUNCTIONAL BLOCK DIAGRAM
IRSET
16kΩ
10kΩ
DB9
IREF
100µA
DB8
IOUTN
IOUTP
500Ω
RLIP
AUX1DAC
AVDD
1 INTO 2
INTERLEAVED
DATA
INTERFACE
DVSS
RLIN
500Ω
I DAC
BAND
GAP
DVDDIO
IRCML
1kΩ TO
250Ω
AVSS
AUX2DAC
I DATA
RLQP
500Ω
1.8V
LDO
Q DATA
QOUTP
Q DAC
QOUTN
DB7
500Ω
CVSS
CVDD
CLKIN
DCLKIO
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
Figure 1.
Rev. A | Page 4 of 80
RLQN
QRCML
1kΩ TO
250Ω
CMLQ
CLOCK
DIST
DB6
07265-001
DVDD
AD9714/AD9715/AD9716/AD9717
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 2 mA, maximum sample rate, unless
otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY, AVDD = DVDDIO =
CVDD = 3.3 V
Differential Nonlinearity (DNL)
Precalibration
Postcalibration
Integral Nonlinearity (INL)
Precalibration
Postcalibration
ACCURACY, AVDD = DVDDIO =
CVDD = 1.8 V
Differential Nonlinearity (DNL)
Precalibration
Postcalibration
Integral Nonlinearity (INL)
Precalibration
Postcalibration
MAIN DAC OUTPUTS
Offset Error
Gain Error
Internal Reference
Full-Scale Output Current1
AVDD = 3.3 V
AVDD = 1.8 V
Output Compliance Range
Output Resistance
Crosstalk, Q DAC to I DAC
fOUT = 30 MHz
fOUT = 60 MHz
MAIN DAC TEMPERATURE DRIFT
Offset
Gain
Reference Voltage
AUXDAC OUTPUTS
Resolution
Full-Scale Output Current
(Current Sourcing Mode)
Voltage Output Mode
Output Compliance Range
(Sourcing 1 mA)
Output Compliance Range
(Sinking 1 mA)
Output Resistance in Current
Output Mode, AVSS to 1 V
AUX DAC Monotonicity
Guaranteed
REFERENCE OUTPUT
Internal Reference Voltage
Output Resistance
Min
−1
AD9714
Typ
Max
8
Min
AD9716
Typ
Max
12
Min
AD9717
Typ
Max
14
Unit
Bits
±0.08
±0.01
±0.4
±0.2
±1.7
±1.0
LSB
LSB
±0.025
±0.01
±0.13
±0.05
±0.4
±0.3
±1.8
±1.3
LSB
LSB
±0.02
±0.005
±0.08
±0.01
±0.4
±0.2
±1.2
±1.0
LSB
LSB
±0.025
±0.02
±0.12
±0.05
±0.4
±0.25
±1.5
±1.1
LSB
LSB
0
2
2
0
200
+1
−1
+2
−2
4
2.5
+1.2
1
1
−0.5
0
2
2
0
200
+1
−1
+2
−2
4
2.5
+1.2
1
1
−0.5
0
2
2
0
200
+1
−1
+2
−2
4
2.5
+1.2
1
1
−0.5
0
2
2
0
200
+1
mV
+2
% of FSR
4
2.5
+1.2
mA
mA
V
MΩ
97
78
97
78
97
78
97
78
dB
dB
0
±40
±25
0
±40
±25
0
±40
±25
0
±40
±25
ppm/°C
ppm/°C
ppm/°C
10
125
10
125
10
125
10
125
Bits
μA
VSS
VSS
VDD
VDD −
0.25
VDD
VSS +
0.25
0.98
AD9715
Typ
Max
10
±0.02
±0.003
−2
1
1
−0.5
Min
VSS
VSS
VDD
VDD −
0.25
VDD
VSS +
0.25
VSS
VSS
VDD
VDD −
0.25
VDD
VSS +
0.25
VSS
VSS
VDD
VDD −
0.25
VDD
VSS +
0.25
V
V
V
1
1
1
1
MΩ
10
10
10
10
Bits
1.025
10
1.08
0.98
1.025
10
1.08
Rev. A | Page 5 of 80
0.98
1.025
10
1.08
0.98
1.025
10
1.08
V
kΩ
AD9714/AD9715/AD9716/AD9717
Parameter
REFERENCE INPUT
Voltage Compliance
AVDD = 3.3 V
AVDD = 1.8 V
Input Resistance External
Reference Mode
DAC MATCHING
Gain Matching
ANALOG SUPPLY VOLTAGES
AVDD
CVDD
DIGITAL SUPPLY VOLTAGES
DVDD
DVDDIO
POWER CONSUMPTION, AVDD =
DVDDIO = CVDD = 3.3 V
fDAC = 125 MSPS, IF = 12.5 MHz
IAVDD
IDVDD + IDVDDIO
ICVDD
Power-Down Mode with Clock
Power-Down Mode, No Clock
Power Supply Rejection Ratio
POWER CONSUMPTION, AVDD =
DVDDIO = CVDD = 1.8 V.
fDAC = 125 MSPS, IF = 12.5 MHz
IAVDD
IDVDD + IDVDDIO
ICVDD
Power-Down Mode with Clock
Power-Down Mode, No Clock
Power Supply Rejection Ratio
OPERATING RANGE
1
Min
AD9714
Typ
Max
0.1
0.1
1.25
1.0
Min
AD9715
Typ
Max
0.1
0.1
1
1.25
1.0
Min
AD9716
Typ
Max
0.1
0.1
1
1.25
1.0
Min
AD9717
Typ
Max
0.1
0.1
1
Unit
1.25
1.0
V
V
MΩ
1
−1
+1
−1
+1
−1
+1
−1
+1
% FSR
1.7
1.7
3.5
3.5
1.7
1.7
3.5
3.5
1.7
1.7
3.5
3.5
1.7
1.7
3.5
3.5
V
V
1.7
1.7
1.9
3.5
1.7
1.7
1.9
3.5
1.7
1.7
1.9
3.5
1.7
1.7
1.9
3.5
V
V
–40
86
10
11
3
50
1.5
−0.04
86
10
11
3
50
1.5
−0.04
86
10
11
3
50
1.5
−0.04
86
10
11
3
50
1.5
−0.04
mW
mA
mA
mA
mW
mW
% FSR/V
35
10
8
1.5
12
850
−0.001
+25
35
10
8
1.5
12
850
−0.001
+25
35
10
8
1.5
12
850
−0.001
+25
35
10
8
1.5
12
850
−0.001
+25
mW
mA
mA
mA
mW
μW
% FSR/V
°C
+85
–40
+85
Based on a 10 kΩ external resistor.
Rev. A | Page 6 of 80
–40
+85
–40
+85
AD9714/AD9715/AD9716/AD9717
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 2 mA, maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
DAC CLOCK INPUT (CLKIN)
VIH
VIL
Maximum Clock Rate
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
INPUT DATA
1.8 V Q Channel or DCLKIO Falling Edge
Setup
Hold
1.8 V I Channel or DCLKIO Rising Edge
Setup
Hold
3.3 V Q Channel or DCLKIO Falling Edge
Setup
Hold
3.3 V I Channel or DCLKIO Rising Edge
Setup
Hold
VIH
VIL
Min
Typ
2.1
3
0
2.1
Rev. A | Page 7 of 80
Max
Unit
0.9
125
V
V
MSPS
25
20
20
MHz
ns
ns
0.25
1.2
ns
ns
0.13
1.1
ns
ns
−0.2
1.5
ns
ns
−0.2
1.6
3
0
ns
ns
V
V
0.9
AD9714/AD9715/AD9716/AD9717
AC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 2 mA, maximum sample rate, unless
otherwise noted.
Table 3.
Parameter
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 125 MSPS, fOUT = 10 MHz
fDAC = 125 MSPS, fOUT = 50 MHz
TWO TONE INTERMODULATION
DISTORTION (IMD)
fDAC = 125 MSPS, fOUT = 10 MHz
fDAC = 125 MSPS, fOUT = 50 MHz
NOISE SPECTRAL DENSITY (NSD)
EIGHT-TONE, 500 kHz TONE SPACING
fDAC = 125 MSPS, fOUT = 10 MHz
fDAC = 125 MSPS, fOUT = 50 MHz
W-CDMA ADJACENT CHANNEL LEAKAGE
RATIO (ACLR), SINGLE CARRIER
fDAC = 61.44 MSPS, fOUT = 20 MHz
fDAC = 122.88 MSPS, fOUT = 30 MHz
Min
AD9714
Typ
Max
Min
AD9715
Typ
Max
Min
AD9716
Typ
Max
Min
AD9717
Typ
Max
Unit
75
60
82
61
83
62
84
63
dBc
dBc
86
71
87
71
88
71
89
71
dBc
dBc
−129
−123
−141
−135
−149
−137
−152
−141
dBc/Hz
dBc/Hz
−71
−72
−71
−72
−71
−72
−71
−72
dBc
dBc
TMIN to TMAX, AVDD = 1.8 V, DVDD = 1.8 V, DVDDIO = 1.8 V, CVDD = 1.8 V, IxOUTFS = 2 mA, maximum sample rate, unless
otherwise noted.
Table 4.
Parameter
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 125 MSPS, fOUT = 10 MHz
fDAC = 125 MSPS, fOUT = 50 MHz
TWO TONE INTERMODULATION
DISTORTION (IMD)
fDAC = 125 MSPS, fOUT = 10 MHz
fDAC = 125 MSPS, fOUT = 50 MHz
NOISE SPECTRAL DENSITY (NSD)
EIGHT-TONE, 500 kHz TONE SPACING
fDAC = 125 MSPS, fOUT = 10 MHz
fDAC = 125 MSPS, fOUT = 50 MHz
W-CDMA ADJACENT CHANNEL LEAKAGE
RATIO (ACLR), SINGLE CARRIER
fDAC = 61.44 MSPS, fOUT = 20 MHz
fDAC = 122.88 MSPS, fOUT = 30 MHz
Min
AD9714
Typ
Max
Min
AD9715
Typ
Max
Min
AD9716
Typ
Max
Min
AD9717
Typ
Max
Unit
75
55
78
56
79
57
80
58
dBc
dBc
79
53
80
53
84
53
85
53
dBc
dBc
−132
−126
−141
−131
−146
−131
−148
−132
dBc/Hz
dBc/Hz
−68
−68
−68
−68
−68
−68
−68
−68
dBc
dBc
Rev. A | Page 8 of 80
AD9714/AD9715/AD9716/AD9717
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
AVDD, DVDDIO, CVDD to AVSS, DVSS, CVSS
DVDD to DVSS
AVSS to DVSS, CVSS
DVSS to AVSS, CVSS
CVSS to AVSS, DVSS
REFIO, FSADJQ, FSADJI, CMLQ, CMLI to AVSS
QOUTP, QOUTN, IOUTP, IOUTN, RLQP, RLQN,
RLIP, RLIN to AVSS
DBn1 (MSB) to DB0 (LSB), CS, SCLK, SDIO,
RESET to DVSS
CLKIN to CVSS
Junction Temperature
Storage Temperature Range
1
Rating
−0.3 V to +3.9 V
−0.3 V to +2.1 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to AVDD + 0.3 V
−1.0 V to AVDD + 0.3 V
−0.3 V to DVDDIO + 0.3 V
−0.3 V to CVDD + 0.3 V
125°C
−65°C to +150°C
n stands for 7 for the AD9714, 9 for the AD9715, 11 for the AD9716, and 13
for the AD9717.
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 6.
Package Type
40-Lead LFCSP (with No Airflow
Movement)
1
θJA
29.8
θJB1
19.0
θJC1
3.4
Unit
°C/W
These calculations are intended to represent the thermal performance of the
indicated packages using a JEDEC multilayer test board. Do not assume the
same level of thermal performance in actual applications without a careful
inspection of the conditions in the application to determine that they are
similar to those assumed in these calculations.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
Rev. A | Page 9 of 80
AD9714/AD9715/AD9716/AD9717
40
39
38
37
36
35
34
33
32
31
DB6
DB7 (MSB)
CS/PWRDN
SDIO/FORMAT
SCLK/CLKMD
RESET/PINMD
REFIO
FSADJI/AUXI
FSADJQ/AUXQ
CMLI
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
AD9714
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
RLIN
IOUTN
IOUTP
RLIP
AVDD
AVSS
RLQP
QOUTP
QOUTN
RLQN
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PAD IS CONNECTED TO AVSS AND
SHOULD BE SOLDERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CORNERS IS
CONNECTED TO THIS PAD.
07265-066
NC
NC
NC
NC
NC
DCLKIO
CVDD
CLKIN
CVSS
CMLQ
11
12
13
14
15
16
17
18
19
20
DB5 1
DB4 2
DB3 3
DB2 4
DVDDIO 5
DVSS 6
DVDD 7
DB1 8
DB0 (LSB) 9
NC 10
Figure 2. AD9714 Pin Configuration
Table 7. AD9714 Pin Function Descriptions
Pin No.
1 to 4
5
6
7
Mnemonic
DB[5:2]
DVDDIO
DVSS
DVDD
8
9
10 to 15
16
17
18
19
20
DB1
DB0 (LSB)
NC
DCLKIO
CVDD
CLKIN
CVSS
CMLQ
21
RLQN
22
23
24
QOUTN
QOUTP
RLQP
25
26
27
AVSS
AVDD
RLIP
28
29
30
IOUTP
IOUTN
RLIN
Description
Digital Inputs.
Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal).
Digital Common.
Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a
1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
Digital Inputs.
Digital Input (LSB).
No Connect. These pins are not connected to the chip.
Data Input/Output Clock. Clock used to qualify input data.
Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
LVCMOS Sampling Clock Input.
Sampling Clock Supply Voltage Common.
Q DAC Output Common-Mode Level. When the internal on chip (QRCML) is enabled, this pin is connected to
the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip
(QRCML) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a
resistor (see the Using the Internal Termination Resistors section). The recommended value for this external
resistor is 0 Ω.
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
Analog Common.
Analog Supply Voltage (1.8 V to 3.3 V).
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
Rev. A | Page 10 of 80
AD9714/AD9715/AD9716/AD9717
Pin No.
31
Mnemonic
CMLI
32
FSADJQ/AUXQ
33
FSADJI/AUXI
34
REFIO
35
RESET/PINMD
36
SCLK/CLKMD
37
SDIO/FORMAT
38
CS/PWRDN
39
40
41 (EPAD)
DB7 (MSB)
DB6
Exposed Pad
(EPAD)
Description
I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the
on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (IRCML) is
disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor
(see the Using the Internal Termination Resistors section). The recommended value for this external resistor
is 0 Ω.
Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the fullscale current output adjust for Q DAC and must be connected to AVSS through a resistor (see the Theory of
Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on chip (QRSET) is enabled, this pin is the auxiliary Q DAC
output.
Full-Scale Current Output Adjust (FSADJI). When the internal on chip (IRSET) is disabled, this pin is full-scale
current output adjust for I DAC and must be connected to AVSS through a resistor (see the Theory of
Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC
output.
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
Pulse RESET high to reset the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the
Retimer section).
Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for serial port.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pulldown to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the two
complement input data format.
Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. In pin mode, a logic
high (pull-up to DVDDIO) powers down the device, except for the SPI port.
Power-Down (PWRDN). In pin mode, PWRDN powers down the device except for the SPI port.
Digital Input (MSB).
Digital Input.
The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the
package corners is connected to this pad.
Rev. A | Page 11 of 80
40
39
38
37
36
35
34
33
32
31
DB8
DB9 (MSB)
CS/PWRDN
SDIO/FORMAT
SCLK/CLKMD
RESET/PINMD
REFIO
FSADJI/AUXI
FSADJQ/AUXQ
CMLI
AD9714/AD9715/AD9716/AD9717
PIN 1
INDICATOR
AD9715
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
RLIN
IOUTN
IOUTP
RLIP
AVDD
AVSS
RLQP
QOUTP
QOUTN
RLQN
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PAD IS CONNECTED TO AVSS AND
SHOULD BE SOLDERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CORNERS IS
CONNECTED TO THIS PAD.
07265-067
DB0 (LSB)
NC
NC
NC
NC
DCLKIO
CVDD
CLKIN
CVSS
CMLQ
11
12
13
14
15
16
17
18
19
20
DB7 1
DB6 2
DB5 3
DB4 4
DVDDIO 5
DVSS 6
DVDD 7
DB3 8
DB2 9
DB1 10
Figure 3. AD9715 Pin Configuration
Table 8. AD9715 Pin Function Descriptions
Pin No.
1 to 4
5
6
7
Mnemonic
DB[7:4]
DVDDIO
DVSS
DVDD
8 to 10
11
12 to 15
16
17
18
19
20
DB[3:1]
DB0 (LSB)
NC
DCLKIO
CVDD
CLKIN
CVSS
CMLQ
21
RLQN
22
23
24
QOUTN
QOUTP
RLQP
25
26
27
AVSS
AVDD
RLIP
28
29
30
IOUTP
IOUTN
RLIN
Description
Digital Inputs.
Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal).
Digital Common.
Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a
1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
Digital Inputs.
Digital Input (LSB).
No Connect. These pins are not connected to the chip.
Data Input/Output Clock. Clock used to qualify input data.
Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
LVCMOS Sampling Clock Input.
Sampling Clock Supply Voltage Common.
Q DAC Output Common-Mode Level. When the internal on chip (QRCML) is enabled, this pin is connected to
the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip
(QRCML) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a
resistor (see the Using the Internal Termination Resistors section). The recommended value for this external
resistor is 0 Ω.
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
Analog Common.
Analog Supply Voltage (1.8 V to 3.3 V).
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
Rev. A | Page 12 of 80
AD9714/AD9715/AD9716/AD9717
Pin No.
31
Mnemonic
CMLI
32
FSADJQ/AUXQ
33
FSADJI/AUXI
34
REFIO
35
RESET/PINMD
36
SCLK/CLKMD
37
SDIO/FORMAT
38
CS/PWRDN
39
40
41 (EPAD)
DB9 (MSB)
DB8
Exposed Pad
(EPAD)
Description
I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the
on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (IRCML) is
disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor
(see the Using the Internal Termination Resistors section). The recommended value for this external resistor
is 0 Ω.
Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the fullscale current output adjust for Q DAC and must be connected to AVSS through a resistor (see the Theory of
Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on chip (QRSET) is enabled, this pin is the auxiliary Q DAC
output.
Full-Scale Current Output Adjust (FSADJI). When the internal on chip (IRSET) is disabled, this pin is the fullscale current output adjust for I DAC and must be connected to AVSS through a resistor (see the Theory of
Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC
output.
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
Pulse RESET high to reset the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the
Retimer section).
Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low
(pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the
twos complement input data format.
Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for
the SPI port.
Digital Input (MSB).
Digital Input.
The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the
package corners is connected to this pad.
Rev. A | Page 13 of 80
40
39
38
37
36
35
34
33
32
31
DB10
DB11 (MSB)
CS/PWRDN
SDIO/FORMAT
SCLK/CLKMD
RESET/PINMD
REFIO
FSADJI/AUXI
FSADJQ/AUXQ
CMLI
AD9714/AD9715/AD9716/AD9717
PIN 1
INDICATOR
AD9716
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
RLIN
IOUTN
IOUTP
RLIP
AVDD
AVSS
RLQP
QOUTP
QOUTN
RLQN
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PAD IS CONNECTED TO AVSS AND
SHOULD BE SOLDERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CORNERS IS
CONNECTED TO THIS PAD.
07265-003
DB2
DB1
DB0 (LSB)
NC
NC
DCLKIO
CVDD
CLKIN
CVSS
CMLQ
11
12
13
14
15
16
17
18
19
20
DB9 1
DB8 2
DB7 3
DB6 4
DVDDIO 5
DVSS 6
DVDD 7
DB5 8
DB4 9
DB3 10
Figure 4. AD9716 Pin Configuration
Table 9. AD9716 Pin Function Descriptions
Pin No.
1 to 4
5
6
7
Mnemonic
DB[9:6]
DVDDIO
DVSS
DVDD
8 to 12
13
14, 15
16
17
18
19
20
DB[5:1]
DB0 (LSB)
NC
DCLKIO
CVDD
CLKIN
CVSS
CMLQ
21
RLQN
22
23
24
QOUTN
QOUTP
RLQP
25
26
27
AVSS
AVDD
RLIP
28
29
30
IOUTP
IOUTN
RLIN
Description
Digital Inputs.
Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal).
Digital Common.
Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a
1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
Digital Inputs.
Digital Input (LSB).
No Connect. These pins are not connected to the chip.
Data Input/Output Clock. Clock used to qualify input data.
Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
LVCMOS Sampling Clock Input.
Sampling Clock Supply Voltage Common.
Q DAC Output Common-Mode Level. When the internal on chip (QRCML) is enabled, this pin is connected to
the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip
(QRCML) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a
resistor (see the Using the Internal Termination Resistors section). The recommended value for this external
resistor is 0 Ω.
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
Analog Common.
Analog Supply Voltage (1.8 V to 3.3 V).
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
Rev. A | Page 14 of 80
AD9714/AD9715/AD9716/AD9717
Pin No.
31
Mnemonic
CMLI
32
FSADJQ/AUXQ
33
FSADJI/AUXI
34
REFIO
35
RESET/PINMD
36
SCLK/CLKMD
37
SDIO/FORMAT
38
CS/PWRDN
39
40
41 (EPAD)
DB11 (MSB)
DB10
Exposed Pad
(EPAD)
Description
I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the
on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (IRCML) is
disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor
(see the Using the Internal Termination Resistors section). The recommended value for this external resistor
is 0 Ω.
Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the fullscale current output adjust for Q DAC and must be connected to AVSS through a resistor (see the Theory of
Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on chip (QRSET) is enabled, this pin is the auxiliary Q DAC
output.
Full-Scale Current Output Adjust (FSADJI). When the internal on chip (IRSET) is disabled, this pin is the fullscale current output adjust for I DAC and must be connected to AVSS through a resistor (see the Theory of
Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC
output.
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
Pulse RESET high to reset the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the
Retimer section).
Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low
(pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the
twos complement input data format.
Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for
the SPI port.
Digital Input (MSB).
Digital Input.
The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the
package corners is connected to this pad.
Rev. A | Page 15 of 80
40
39
38
37
36
35
34
33
32
31
DB12
DB13 (MSB)
CS/PWRDN
SDIO/FORMAT
SCLK/CLKMD
RESET/PINMD
REFIO
FSADJI/AUXI
FSADJQ/AUXQ
CMLI
AD9714/AD9715/AD9716/AD9717
PIN 1
INDICATOR
AD9717
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
RLIN
IOUTN
IOUTP
RLIP
AVDD
AVSS
RLQP
QOUTP
QOUTN
RLQN
NOTES
1. THE EXPOSED PAD IS CONNECTED TO AVSS AND
SHOULD BE SOLDERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CORNERS IS
CONNECTED TO THIS PAD.
07265-002
DB4
DB3
DB2
DB1
DB0 (LSB)
DCLKIO
CVDD
CLKIN
CVSS
CMLQ
11
12
13
14
15
16
17
18
19
20
DB11 1
DB10 2
DB9 3
DB8 4
DVDDIO 5
DVSS 6
DVDD 7
DB7 8
DB6 9
DB5 10
Figure 5. AD9717 Pin Configuration
Table 10. AD9717 Pin Function Descriptions
Pin No.
1 to 4
5
6
7
Mnemonic
DB[11:8]
DVDDIO
DVSS
DVDD
8 to 14
15
16
17
18
19
20
DB[7:1]
DB0 (LSB)
DCLKIO
CVDD
CLKIN
CVSS
CMLQ
21
RLQN
22
23
24
QOUTN
QOUTP
RLQP
25
26
27
AVSS
AVDD
RLIP
28
29
30
IOUTP
IOUTN
RLIN
Description
Digital Inputs.
Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal).
Digital Common.
Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a
1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
Digital Inputs.
Digital Input (LSB).
Data Input/Output Clock. Clock used to qualify input data.
Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
LVCMOS Sampling Clock Input.
Sampling Clock Supply Voltage Common.
Q DAC Output Common-Mode Level. When the internal on chip (QRCML) is enabled, this pin is connected to
the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip
(QRCML) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a
resistor (see the Using the Internal Termination Resistors section). The recommended value for this external
resistor is 0 Ω.
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
Analog Common.
Analog Supply Voltage (1.8 V to 3.3 V).
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
Rev. A | Page 16 of 80
AD9714/AD9715/AD9716/AD9717
Pin No.
31
Mnemonic
CMLI
32
FSADJQ/AUXQ
33
FSADJI/AUXI
34
REFIO
35
RESET/PINMD
36
SCLK/CLKMD
37
SDIO/FORMAT
38
CS/PWRDN
39
40
41 (EPAD)
DB13 (MSB)
DB12
Exposed Pad
(EPAD)
Description
I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the
on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (IRCML) is
disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor
(see the Using the Internal Termination Resistors section). The recommended value for this external resistor
is 0 Ω.
Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the fullscale current output adjust for Q DAC and must be connected to AVSS through a resistor (see the Theory of
Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on chip (QRSET) is enabled, this pin is the auxiliary Q DAC
output.
Full-Scale Current Output Adjust (FSADJI). When the internal on chip (IRSET) is disabled, this pin is the fullscale current output adjust for I DAC and must be connected to AVSS through a resistor (see the Theory of
Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC
output.
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
Pulse RESET high to reset the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the
Retimer section).
Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low
(pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the
twos complement input data format.
Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for
the SPI port.
Digital Input (MSB).
Digital Input.
The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the
package corners is connected to this pad.
Rev. A | Page 17 of 80
AD9714/AD9715/AD9716/AD9717
TYPICAL PERFORMANCE CHARACTERISTICS
1.5
1.5
1.0
1.0
POSTCALIBRATION INL (LSB)
0.5
0
–0.5
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
–1.5
1.0
1.0
POSTCALIBRATION DNL (LSB)
PRECALIBRATION DNL (LSB)
1.5
0.5
0
–0.5
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
Figure 7. AD9717 Precalibration DNL at 1.8 V (DVDD = 1.8 V)
6144
8192 10,240 12,288 14,336 16,384
CODE
0
–0.5
–1.0
0
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
Figure 10. AD9717 Postcalibration DNL at 1.8 V (DVDD = 1.8 V)
1.75
1.25
1.25
POSTCALIBRATION INL (LSB)
1.75
0.75
0.25
–0.25
–0.75
0.75
0.25
–0.25
–0.75
–1.25
0
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
07265-006
–1.25
–1.75
4096
0.5
–1.5
07265-005
–1.0
0
2048
Figure 9. AD9717 Postcalibration INL at 1.8 V (DVDD = 1.8 V)
1.5
–1.5
0
07265-008
0
Figure 6. AD9717 Precalibration INL at 1.8 V (DVDD = 1.8 V)
PRECALIBRATION INL (LSB)
–0.5
–1.0
07265-004
–1.5
0
07265-007
–1.0
0.5
Figure 8. AD9717 Precalibration INL at 3.3 V (DVDD = 1.8 V)
–1.75
0
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
Figure 11. AD9717 Postcalibration INL at 3.3 V (DVDD = 1.8 V)
Rev. A | Page 18 of 80
07265-009
PRECALIBRATION INL (LSB)
IxOUTFS = 2 mA, maximum sample rate, unless otherwise noted. DVDD is always at 1.8 V.
1.75
1.75
1.25
1.25
POSTCALIBRATION DNL (LSB)
0.75
0.25
–0.25
–0.75
–0.25
–0.75
–1.25
0
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
–1.75
07265-010
0
0.4
0.4
0.3
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
0
512
1024
1536
2048
CODE
2560
3072
3584
4096
0.1
0
–0.1
–0.2
–0.4
0
512
1024
1536
2048
CODE
2560
3072
3584
4096
Figure 16. AD9716 Postcalibration INL at 1.8 V
0.4
0.3
0.3
POSTCALIBRATION DNL (LSB)
0.4
0.2
0.1
0
–0.1
–0.2
–0.3
0.2
0.1
0
–0.1
–0.2
–0.3
0
512
1024
1536
2048
CODE
2560
3072
3584
4096
07265-012
PRECALIBRATION DNL (LSB)
8192 10,240 12,288 14,336 16,384
CODE
0.2
Figure 13. AD9716 Precalibration INL at 1.8 V
–0.4
6144
–0.3
07265-011
–0.4
4096
Figure 15. AD9717 Postcalibration DNL at 3.3 V
POSTCALIBRATION INL (LSB)
PRECALIBRATION INL (LSB)
Figure 12. AD9717 Precalibration DNL at 3.3 V
2048
07265-014
–1.75
0.25
07265-013
–1.25
0.75
Figure 14. AD9716 Precalibration DNL at 1.8 V
–0.4
0
512
1024
1536
2048
CODE
2560
3072
3584
Figure 17. AD9716 Postcalibration DNL at 1.8 V
Rev. A | Page 19 of 80
4096
07265-015
PRECALIBRATION DNL (LSB)
AD9714/AD9715/AD9716/AD9717
0.4
0.4
0.3
0.3
POSTCALIBRATION INL (LSB)
0.2
0.1
0
–0.1
–0.2
0
–0.1
–0.2
–0.3
0
512
1024
1536
2048
CODE
2560
3072
3584
4096
–0.4
07265-016
0
0.4
0.4
0.3
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
2048
CODE
2560
3072
3584
4096
0.2
0.1
0
–0.1
–0.2
0
512
1024
1536
2048
CODE
2560
3072
3584
4096
–0.4
0
Figure 19. AD9716 Precalibration DNL at 3.3 V
1024
1536
2048
CODE
2560
3072
3584
4096
0.13
0.08
POSTCALIBRATION INL (LSB)
0.08
0.03
–0.02
0
128
256
384
512
CODE
640
768
896
1024
07265-018
–0.07
–0.12
512
Figure 22. AD9716 Postcalibration DNL at 3.3 V
0.13
PRECALIBRATION INL (LSB)
1536
–0.3
07265-017
–0.4
1024
Figure 21. AD9716 Postcalibration INL at 3.3 V
POSTCALIBRATION DNL (LSB)
PRECALIBRATION DNL (LSB)
Figure 18. AD9716 Precalibration INL at 3.3 V
512
07265-020
–0.4
0.1
07265-019
–0.3
0.2
Figure 20. AD9715 Precalibration INL at 1.8 V
0.03
–0.02
–0.07
–0.12
0
128
256
384
512
CODE
640
768
896
Figure 23. AD9715 Postcalibration INL at 1.8 V
Rev. A | Page 20 of 80
1024
07265-021
PRECALIBRATION INL (LSB)
AD9714/AD9715/AD9716/AD9717
0.13
0.08
0.08
0.03
–0.02
–0.07
128
256
384
512
CODE
640
768
896
1024
–0.07
–0.12
0
0.13
0.08
0.08
POSTCALIBRATION INL (LSB)
0.13
0.03
–0.02
–0.07
–0.12
0
128
256
384
512
CODE
640
768
896
1024
–0.12
POSTCALIBRATION DNL (LSB)
0.03
–0.02
–0.07
512
CODE
640
768
896
1024
07265-024
PRECALIBRATION DNL (LSB)
0.08
384
768
896
1024
0
128
256
384
512
CODE
640
768
896
1024
Figure 28. AD9715 Postcalibration INL at 3.3 V
0.08
256
640
–0.07
0.13
128
512
CODE
–0.02
0.13
0
384
0.03
Figure 25. AD9715 Precalibration INL at 3.3 V
–0.12
256
Figure 27. AD9715 Postcalibration DNL at 1.8 V
07265-023
PRECALIBRATION INL (LSB)
Figure 24. AD9715 Precalibration DNL at 1.8 V
128
07265-026
0
–0.02
Figure 26. AD9715 Precalibration DNL at 3.3 V
0.03
–0.02
–0.07
–0.12
0
128
256
384
512
CODE
640
768
896
Figure 29. AD9715 Postcalibration DNL at 3.3 V
Rev. A | Page 21 of 80
1024
07265-027
–0.12
0.03
07265-025
POSTCALIBRATION DNL (LSB)
0.13
07265-022
PRECALIBRATION DNL (LSB)
AD9714/AD9715/AD9716/AD9717
0.025
0.025
0.020
0.020
0.015
0.015
POSTCALIBRATION INL (LSB)
0.010
0.005
0
–0.005
–0.010
–0.015
0
–0.005
–0.010
–0.015
–0.020
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
CODE
–0.025
07265-028
0
Figure 33. AD9714 Postcalibration INL at 1.8 V
0.025
0.025
0.020
0.020
0.015
0.015
POSTCALIBRATION DNL (LSB)
PRECALIBRATION DNL (LSB)
Figure 30. AD9714 Precalibration INL at 1.8 V
0.010
0.005
0
–0.005
–0.010
–0.015
–0.020
0.010
0.005
0
–0.005
–0.010
–0.015
–0.020
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
CODE
–0.025
07265-029
–0.025
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
CODE
Figure 34. AD9714 Postcalibration DNL at 1.8 V
0.025
0.020
0.020
0.015
0.015
POSTCALIBRATION INL (LSB)
0.025
0.010
0.005
0
–0.005
–0.010
–0.015
–0.020
0.010
0.005
0
–0.005
–0.010
–0.015
–0.020
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
CODE
07265-030
PRECALIBRATION INL (LSB)
Figure 31. AD9714 Precalibration DNL at 1.8 V
–0.025
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
CODE
07265-032
–0.025
0.005
07265-031
–0.020
0.010
Figure 32. AD9714 Precalibration INL at 3.3 V
–0.025
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
CODE
Figure 35. AD9714 Postcalibration INL at 3.3 V
Rev. A | Page 22 of 80
07265-033
PRECALIBRATION INL (LSB)
AD9714/AD9715/AD9716/AD9717
0.025
0.025
0.020
0.020
0.015
0.015
POSTCALIBRATION DNL (LSB)
0.010
0.005
0
–0.005
–0.010
–0.015
–0.020
0.005
0
–0.005
–0.010
–0.015
–0.020
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
CODE
–0.025
07265-034
–0.025
0.010
0
Figure 36. AD9714 Precalibration DNL at 3.3 V
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
CODE
07265-037
PRECALIBRATION DNL (LSB)
AD9714/AD9715/AD9716/AD9717
Figure 39. AD9714 Postcalibration DNL at 3.3 V
–126
–126
AD9714
AD9714
–129
–132
–132
–138
NSD (dBc)
NSD (dBc)
–135
AD9715
–144
–138
AD9715
–141
–144
AD9716
–147
AD9716
–150
–153
0
5
10
15
20
25
30
35
40
45
50
55
fOUT (MHz)
–156
07265-038
–156
Figure 37. AD9714/AD9715/AD9716/AD9717 Noise Spectral Density at 1.8 V
AD9717
0
5
10
15
20
25
30
35
40
45
50
fOUT (MHz)
55
07265-035
AD9717
–150
Figure 40. AD9714/AD9715/AD9716/AD9717 Noise Spectral Density at 3.3 V
–133
–133
–136
–136
–40°C
+85°C
–139
–139
–142
–40°C
–145
–148
–148
–151
–151
–154
5
10
15
20
25
30
35
40
45
50
+85°C
07265-141
NSD (dBc)
+25°C
–145
07265-138
NSD (dBc)
+25°C
–142
–154
55
5
fOUT (MHz)
10
15
20
25
30
35
40
45
50
55
fOUT (MHz)
Figure 38. AD9717 Noise Spectral Density at Three Temperatures, 1.8 V
Figure 41. AD9717 Noise Spectral Density at Three Temperatures, 3.3 V
Rev. A | Page 23 of 80
AD9714/AD9715/AD9716/AD9717
–130
–130
–133
–133
–136
–136
–139
–139
NSD (dBc)
1.8V, 2mA
–145
–145
–148
–151
–151
–154
–154
07265-142
–148
–157
0
5
10
15
20
25
30
35
40
45
50
3.3V, 1mA
–142
–157
55
0
5
10
15
25
30
35
40
45
50
55
Figure 45. AD9717 Noise Spectral Density at Three Output Currents, 3.3 V
–10
–10
–20
–20
–30
–30
–40
–40
–50
–50
(dBm)
(dBm)
Figure 42. AD9717 Noise Spectral Density at Two Output Currents, 1.8 V
–60
–60
–70
–80
–80
–90
–90
–100
–100
1.5MHz/DIV
STOP 16MHz
07265-085
–70
START 1MHz
20
fOUT (MHz)
fOUT (MHz)
–110
3.3V, 2mA
3.3V, 4mA
07265-145
–142
–110
Figure 43. AD9717 Two Tone Spectrum, 1.8 V
START 1MHz
1.4MHz/DIV
STOP 15MHz
07265-088
NSD (dBc)
1.8V, 1mA
Figure 46. AD9717 Two Tone Spectrum, 3.3 V
88
100
AD9717
82
94
AD9716
AD9714
AD9715
AD9716
AD9717
64
AD9715
82
AD9714
76
58
52
88
5
10
15
20
25
30
35
40
45
50
fOUT (MHz)
70
5
10
15
20
25
30
35
40
45
50
fOUT (MHz)
Figure 44. AD9714/AD9715/AD9716/AD9717 IMD at 1.8 V
Figure 47. AD9714/AD9715/AD9716/AD9717 IMD at 3.3 V
Rev. A | Page 24 of 80
07265-040
IMD (dBc)
70
07265-098
IMD (dBc)
76
AD9714/AD9715/AD9716/AD9717
90
90
+85°C
84
84
+25°C
+25°C
78
IMD (dBc)
72
–40°C
72
66
66
60
60
54
5
10
15
20
25
30
35
40
45
07265-151
+85°C
–40°C
07265-148
54
5
50
10
15
20
Figure 48. AD9717 IMD at Three Temperatures, 1.8 V
35
40
45
50
91
82
88
76
0dB
–3dB
–3dB
IMD (dBc)
IMD (dBc)
30
Figure 51. AD9717 IMD at Three Temperatures, 3.3 V
88
–6dB
70
64
85
82
–6dB
0dB
79
58
5
10
15
20
25
30
fIN (MHz)
35
40
45
76
07265-089
52
25
fOUT (MHz)
fOUT (MHz)
50
5
10
15
20
25
30
35
40
45
07265-090
IMD (dBc)
78
50
fIN (MHz)
Figure 49. AD9717 IMD at Three Digital Input Levels, 1.8 V
Figure 52. AD9717 IMD at Three Digital Input Levels, 3.3 V
90
90
84
84
78
78
IMD (dBc)
1mA
72
4mA
1mA
72
2mA
66
66
60
54
5
10
15
20
25
30
35
40
45
07265-153
60
07265-150
IMD (dBc)
2mA
54
50
5
fOUT (MHz)
10
15
20
25
30
35
40
45
fOUT (MHz)
Figure 50. AD9717 IMD at Two Output Currents, 1.8 V
Figure 53. AD9717 IMD at Three Output Currents, 3.3 V
Rev. A | Page 25 of 80
50
–10
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–80
–80
–90
–90
–100
–100
–110
START 1MHz
1.5MHz/DIV
STOP 16MHz
07265-084
–70
–110
START 1MHz
Figure 54. AD9717 Single-Tone Spectrum, 1.8 V
STOP 15MHz
Figure 57. AD9717 Single-Tone Spectrum, 3.3 V
86
93
AD9717
AD9716
AD9715
AD9714
80
AD9717
AD9716
AD9715
AD9714
90
87
74
84
SFDR (dBc)
SFDR (dBc)
1.4MHz/DIV
07265-087
(dBm)
(dBm)
AD9714/AD9715/AD9716/AD9717
68
62
81
78
75
72
56
5
10
15
20
25
30
35
40
45
50
55
66
60
07265-158
07265-155
50
69
5
10
15
20
25
fOUT (MHz)
35
40
45
50
55
Figure 55. AD9714/AD9715/AD9716/AD9717 SFDR at 1.8 V
Figure 58. AD9714/AD9715/AD9716/AD9717 SFDR at 3.3 V
90
90
84
84
+85°C
78
SFDR (dBc)
+25°C
72
66
72
3.3V, –40°C
66
–40°C
60
3.3V, +25°C
07265-156
5
10
15
20
25
30
35
40
45
50
55
07265-159
60
54
48
60
3.3V, +85°C
78
SFDR (dBc)
30
fOUT (MHz)
54
5
60
10
15
20
25
30
35
40
45
50
55
fOUT (MHz)
fOUT (MHz)
Figure 59. AD9717 SFDR at Three Temperatures, 3.3 V
Figure 56. AD9717 SFDR at Three Temperatures, 1.8 V
Rev. A | Page 26 of 80
60
AD9714/AD9715/AD9716/AD9717
90
90
85
85
–6dB
80
80
–6dB
0dB
–3dB
65
70
60
60
55
55
0
10
20
30
fIN (MHz)
40
50
50
07265-092
50
60
–3dB
65
0dB
0
10
20
30
40
50
07265-091
70
75
SFDR (dBc)
SFDR (dBc)
75
60
fIN (MHz)
Figure 60. SFDR at Three Digital Input Levels vs. fIN, 1.8 V
Figure 63. SFDR at Three Digital Input Levels vs. fIN, 3.3 V
90
90
84
84
4m A
78
SFDR (dBc)
SFDR (dBc)
78
72
1mA
66
2m A
66
2mA
60
72
1m A
07265-160
48
5
10
15
20
25
30
35
40
45
50
55
07265-162
60
54
54
60
5
10
15
fOUT (MHz)
20
25
30
35
40
45
50
55
60
fOUT (MHz)
Figure 61. SFDR at Two Output Currents, 1.8 V
Figure 64. SFDR at Three Output Currents, 3.3 V
10dB/DIV
AC-COUPLED: UNSPECIFIED
BELOW 20MHz
10dB/DIV
AC-COUPLED: UNSPECIFIED
BELOW 20MHz
VBW 300kHz
CENTER 22.90MHz
SPAN 38.84MHz
SWEEP 126ms (601pts)
RES BW 30kHz
TOTAL CARRIER POWER –19.81dBm/7.87420MHz
REF CARRIER POWER –19.81dBm/4.03420MHz
RCC FILTER: OFF FILTER ALPHA 0.22
SPAN 38.84MHz
SWEEP 126ms (601pts)
TOTAL CARRIER POWER –25.42dBm/7.68000MHz
REF CARRIER POWER –25.42dBm/3.84000MHz
RCC FILTER: OFF FILTER ALPHA 0.22
OFFSET INTEG
LOWER
UPPER
dBc
dBm
dBc
dBm
FREQ
BW
1. –25.42dBm 5.000MHz 3.840MHz –72.52 –97.94 –72.44 –97.86
2. –88.16dBm 10.00MHz 3.840MHz –72.82 –98.24 –73.02 –98.44
15.00MHz 3.840MHz –72.18 –97.60 –71.88 –97.30
07265-161
OFFSET INTEG
LOWER
UPPER
dBc
dBm
dBc
dBm
FREQ
BW
1. –19.81dBm 5.000MHz 3.840MHz –70.32 –90.13 –72.61 –92.42
2. –85.75dBm 10.00MHz 3.840MHz –71.81 –91.61 –71.60 –91.41
15.00MHz 3.840MHz –72.59 –92.40 –65.50 –85.31
VBW 300kHz
Figure 62. AD9717 One-Carrier ACLR, 1.8 V
Figure 65. AD9717 One-Carrier ACLR, 3.3 V
Rev. A | Page 27 of 80
07265-163
CENTER 22.90MHz
RES BW 30kHz
AD9714/AD9715/AD9716/AD9717
–60
–60
1mA PRECAL
1mA PRECAL
–65
1mA POSTCAL
2mA POSTCAL
ACLR (dBc)
ACLR (dBc)
–65
2mA POSTCAL
1mA POSTCAL
–70
2mA PRECAL
–70
4mA POSTCAL
–75
2mA PRECAL
35
45
fOUT (MHz)
07265-068
25
–80
15
25
35
45
fOUT (MHz)
Figure 66. AD9717 One-Carrier W-CDMA First ACLR, 1.8 V
07265-070
4mA PRECAL
–75
15
Figure 69. AD9717 One-Carrier W-CDMA First ACLR, 3.3 V
–60
–60
1mA PRECAL
1mA PRECAL
–65
2mA PRECAL
ACLR (dBc)
ACLR (dBc)
–65
1mA POSTCAL
2mA PRECAL
1mA POSTCAL
–70
–70
–75
2mA POSTCAL
4mA PRECAL
2mA POSTCAL
35
45
fOUT (MHz)
07265-071
25
–80
15
25
35
45
fOUT (MHz)
Figure 67. AD9717 One-Carrier W-CDMA Second ACLR, 1.8 V
Figure 70. AD9717 One-Carrier W-CDMA Second ACLR, 3.3 V
–60
–60
07265-074
4mA POSTCAL
–75
15
1mA PRECAL
1mA PRECAL
–65
2mA POSTCAL
ACLR (dBc)
ACLR (dBc)
–65
1mA POSTCAL
1mA POSTCAL
2mA PRECAL
–70
4mA PRECAL
–70
2mA POSTCAL
–75
2mA PRECAL
40
fOUT (MHz)
–80
20
07265-072
30
30
40
fOUT (MHz)
Figure 68. AD9717 One-Carrier W-CDMA Third ACLR, 1.8 V
Figure 71. AD9717 One-Carrier W-CDMA Third ACLR, 3.3 V
Rev. A | Page 28 of 80
07265-075
4mA POSTCAL
–75
20
AD9714/AD9715/AD9716/AD9717
AC-COUPLED:UNSPECIFIED
BELOW 20MHz
10dB/DIV
10dB/DIV
AC-COUPLED: UNSPECIFIED
BELOW 20MHz
SPAN 38.84MHz
VBW 300kHz
CENTER 22.90MHz
SWEEP 126ms (601pts)
TOTAL CARRIER POWER –23.08dBm/7.87420MHz
REF CARRIER POWER –25.84dBm/4.03420MHz
RCC FILTER: OFF FILTER ALPHA 0.22
SWEEP 126ms (601pts)
TOTAL CARRIER POWER –33.14dBm/7.87420MHz
REF CARRIER POWER –25.86dBm/4.03420MHz
RCC FILTER: OFF FILTER ALPHA 0.22
OFFSET INTEG
LOWER
UPPER
dBc
dBm
dBc
dBm
FREQ
BW
1. –25.86dBm 5.000MHz 3.840MHz –66.28 –92.13 –66.68 –92.53
2. –26.47dBm 10.00MHz 3.840MHz –68.17 –94.02 –66.93 –92.78
15.00MHz 3.840MHz –64.89 –90.73 –65.84 –91.69
07265-164
OFFSET INTEG
LOWER
UPPER
dBc
dBm
dBc
dBm
FREQ
BW
1. –25.84dBm 5.000MHz 3.840MHz –65.45 –91.30 –65.63 –91.47
2. –26.35dBm 10.00MHz 3.840MHz –67.01 –92.85 –67.05 –92.89
15.00MHz 3.840MHz –65.22 –91.06 –65.33 –91.18
Figure 72. AD9717 Two-Carrier ACLR, 1.8 V
–55
SPAN 38.84MHz
VBW 300kHz
RES BW 30kHz
07265-165
CENTER 22.90MHz
RES BW 30kHz
Figure 75. AD9717 Two-Carrier ACLR, 3.3 V
–55
1mA PRECAL
1mA POSTCAL
1mA PRECAL
1mA POSTCAL
–60
2mA PRECAL
2mA PRECAL
ACLR (dBc)
ACLR (dBc)
–60
2mA POSTCAL
–65
–65
2mA POSTCAL
4mA PRECAL
–70
25
30
fOUT (MHz)
35
40
–75
15
4mA POSTCAL
20
25
30
35
40
fOUT (MHz)
Figure 73. AD9717 Two-Carrier W-CDMA First ACLR, 1.8 V
07265-076
20
07265-073
–70
15
Figure 76. AD9717 Two-Carrier W-CDMA First ACLR, 3.3 V
–55
–55
1mA PRECAL
1mA PRECAL
–60
1mA POSTCAL
ACLR (dBc)
ACLR (dBc)
–60
1mA POSTCAL
2mA PRECAL
2mA PRECAL
–65
–65
2mA POSTCAL
–70
2mA POSTCAL
25
30
35
40
fOUT (MHz)
07265-077
20
–75
15
20
25
30
35
40
fOUT (MHz)
Figure 74. AD9717 Two-Carrier W-CDMA Second ACLR, 1.8 V
Figure 77. AD9717 Two-Carrier W-CDMA Second ACLR, 3.3 V
Rev. A | Page 29 of 80
07265-080
4mA POSTCAL
4mA PRECAL
–70
15
AD9714/AD9715/AD9716/AD9717
–55
–55
1mA PRECAL
1mA PRECAL
–60
1mA POSTCAL
ACLR (dBc)
ACLR (dBc)
–60
2mA PRECAL
1mA POSTCAL
2mA PRECAL
–65
–65
2mA POSTCAL
–70
2mA POSTCAL
30
35
40
fOUT (MHz)
07265-078
25
–75
20
35
40
Figure 81. AD9717 Two-Carrier W-CDMA Third ACLR, 3.3 V
0.4
1.0
0.3
0.8
0.2
0.6
0.1
0.4
AUXDAC INL (LSB)
0
–0.1
–0.2
–0.3
0.2
0
–0.2
–0.4
–0.6
–0.4
0
128
256
384
512
CODE
640
768
896
07265-147
–0.8
1024
–1.0
0
128
256
384
512
CODE
640
768
896
07265-144
AUXDAC DNL (LSB)
30
fOUT (MHz)
Figure 78. AD9717 Two-Carrier W-CDMA Third ACLR, 1.8 V
–0.5
25
07265-081
4mA POSTCAL
4mA PRECAL
–70
20
1024
Figure 82. AUXDAC INL
Figure 79. AUXDAC DNL
25
TOTAL CURRENT @ 1mA OUT
30
TOTAL CURRENT @ 2mA OUT
20
TOTAL CURRENT @ 4mA OUT
CURRENT (mA)
15
TOTAL CURRENT @ 1mA OUT
10
AVDD @ 2mA OUT
20
AVDD @ 4mA OUT
AVDD @ 2mA OUT
10
AVDD @ 1mA OUT
AVDD @ 1mA OUT
5
DVDD
DVDD
0
0
20
40
60
80
100
120
fCLK (MHz)
140
0
0
20
40
60
80
100
120
fCLK (MHz)
Figure 80. Supply Current vs. Clock Frequency at 1.8 V
Figure 83. Supply Current vs. Clock Frequency at 3.3 V
Rev. A | Page 30 of 80
140
07265-044
CVDD
CVDD
07265-041
CURRENT (mA)
TOTAL CURRENT @ 2mA OUT
AD9714/AD9715/AD9716/AD9717
TERMINOLOGY
Linearity Error or Integral Nonlinearity (INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by
a straight line drawn from zero scale to full scale.
Power Supply Rejection
Power supply rejection is the maximum change in the full-scale
output as the supplies are varied from minimum to maximum
specified voltages.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Settling Time
Settling time is the time required for the output to reach and
remain within a specified error band around its final value,
measured from the start of the output transition.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
Offset error is the deviation of the output current from the
ideal of zero. For IOUTP, 0 mA output is expected when the
inputs are all 0. For IOUTN, 0 mA output is expected when all
inputs are set to 1.
Gain Error
Gain error is the difference between the actual and the ideal
output span. The actual span is determined by the difference
between the output when all inputs are set to 1 and the output
when all inputs are set to 0.
Output Compliance Range
Output compliance range is the range of allowable voltage at
the output of a current-output DAC. Operation beyond the
maximum compliance limits can cause either output stage
saturation or breakdown, resulting in nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from
the ambient value (25°C) to the value at either TMIN or TMAX.
For offset and gain drift, the drift is reported in ppm of fullscale range per degree Celsius (ppm FSR/°C). For reference
drift, the drift is reported in parts per million per degree
Celsius (ppm/°C).
Spurious Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the peak
amplitude of the output signal and the peak spurious signal
between dc and the frequency equal to half the input data rate.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured fundamental.
It is expressed as a percentage or in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels (dB).
Adjacent Channel Leakage Ratio (ACLR)
ACLR is the ratio in decibels relative to the carrier (dBc)
between the measured power within a channel relative to its
adjacent channel.
Complex Image Rejection
In a traditional two-part upconversion, two images are created
around the second IF frequency. These images have the effect of
wasting transmitter power and system bandwidth. By placing
the real part of a second complex modulator in series with the
first complex modulator, either the upper or lower frequency
image near the second IF can be rejected.
Rev. A | Page 31 of 80
AD9714/AD9715/AD9716/AD9717
CMLI
FSADJI/AUXI
FSADJQ/AUXQ
REFIO
RESET/PINMD
SCLK/CLKMD
SDIO/FORMAT
CS/PWRDN
DB13 (MSB)
DB12
THEORY OF OPERATION
1V
SPI
INTERFACE
DB11
AD9717
QRSET
16kΩ
DB10
IRSET
16kΩ
10kΩ
DB9
IREF
100µA
DB8
IOUTN
IOUTP
500Ω
RLIP
AUX1DAC
AVDD
1 INTO 2
INTERLEAVED
DATA
INTERFACE
DVSS
RLIN
500Ω
I DAC
BAND
GAP
DVDDIO
IRCML
1kΩ TO
250Ω
AVSS
AUX2DAC
I DATA
RLQP
500Ω
1.8V
LDO
Q DATA
QOUTP
Q DAC
QOUTN
DB7
500Ω
CVSS
CVDD
CLKIN
DCLKIO
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
RLQN
QRCML
1kΩ TO
250Ω
CMLQ
CLOCK
DIST
DB6
07265-046
DVDD
Figure 84. Simplified Block Diagram
Figure 84 shows a simplified block diagram of the AD9714/
AD9715/AD9716/AD9717 that consists of two DACs, digital
control logic, and a full-scale output current control. Each DAC
contains a PMOS current source array capable of providing a
nominal full-scale current (IxOUTFS) of 2 mA and a maximum of
4 mA. The arrays are divided into 31 equal currents that make
up the five most significant bits (MSBs). The next four bits, or
middle bits, consist of 15 equal current sources whose value is
1/16 of an MSB current source. The remaining LSBs are binary
weighted fractions of the current sources of the middle bits.
Implementing the middle and lower bits with current sources,
instead of an R-2R ladder, enhances its dynamic performance
for multitone or low amplitude signals and helps maintain the
high output impedance of the DACs (that is, >200 MΩ).
All of these current sources are switched to one or the other
of the two output nodes (IOUTP or IOUTN) via PMOS differential
current switches. The switches are based on the architecture that
was pioneered in the AD976x family, with further refinements
to reduce distortion contributed by the switching transient. This
switch architecture also reduces various timing errors and
provides matching complementary drive signals to the inputs
of the differential current switches.
The analog and digital I/O sections of the AD9714/AD9715/
AD9716/AD9717 have separate power supply inputs (AVDD and
DVDDIO) that can operate independently over a 1.8 V to 3.3 V
range. The core digital section requires 1.8 V. An optional on-chip
LDO is provided for DVDDIO supplies greater than 1.8 V, or the
1.8 V can be supplied directly through DVDD. A 1.0 μF bypass
capacitor at DVDD (Pin 7) is required when using the LDO.
The core is capable of operating at a rate of up to 125 MSPS. It
consists of edge-triggered latches and the segment decoding logic
circuitry. The analog section includes PMOS current sources,
associated differential switches, a 1.0 V band gap voltage
reference, and a reference control amplifier.
Each DAC full-scale output current is regulated by the reference
control amplifier and can be set from 1 mA to 4 mA via an external
resistor, xRSET, connected to its full-scale adjust pin (FSADJx).
The external resistor, in combination with both the reference
control amplifier and voltage reference, VREFIO, sets the reference
current, IxREF, which is replicated to the segmented current sources
with the proper scaling factor. The full-scale current, IxOUTFS, is
32 × IxREF.
Optional on-chip xRSET resistors are provided that can be programmed between a nominal value of 8 kΩ to 32 kΩ (4 mA to
1 mA IxOUTFS, respectively).
The AD9714/AD9715/AD9716/AD9717 provide the option of
setting the output common mode to a value other than AVSS
via the output common-mode pins (CMLI and CMLQ). This
facilitates directly interfacing the output of the AD9714/AD9715/
AD9716/AD9717 to components that require common-mode
levels greater than 0 V.
Rev. A | Page 32 of 80
AD9714/AD9715/AD9716/AD9717
SERIAL PERIPHERAL INTERFACE (SPI)
The serial port of the AD9714/AD9715/AD9716/AD9717 is a
flexible, synchronous serial communications port that allows easy
interfacing to many industry-standard microcontrollers and
microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel®
SSR protocols. The interface allows read/write access to all registers
that configure the AD9714/AD9715/AD9716/AD9717. Single or
multiple byte transfers are supported, as well as MSB first or
LSB first transfer formats. The serial interface port of the AD9714/
AD9715/AD9716/AD9717 is configured as a single I/O pin on
the SDIO pin.
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communications cycle on the AD9714/
AD9715/AD9716/AD9717. Phase 1 is the instruction cycle, which
is the writing of an instruction byte into the AD9714/AD9715/
AD9716/AD9717, coinciding with the first eight SCLK rising
edges. In Phase 2, the instruction byte provides the serial port
controller of the AD9714/AD9715/AD9716/AD9717 with information regarding the data transfer cycle. The Phase 1 instruction
byte defines whether the upcoming data transfer is a read or write,
the number of bytes in the data transfer, and the starting register
address for the first byte of the data transfer. The first eight SCLK
rising edges of each communication cycle are used to write the
instruction byte into the AD9714/AD9715/AD9716/AD9717.
A Logic 1 on Pin 35 (RESET/PINMD), followed by a Logic 0,
resets the SPI port timing to the initial state of the instruction
cycle. This is true regardless of the present state of the internal
registers or the other signal levels present at the inputs to the
SPI port. If the SPI port is in the midst of an instruction cycle
or a data transfer cycle, none of the present data is written.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9714/
AD9715/AD9716/AD9717 and the system controller. Phase 2 of
the communication cycle is a transfer of one, two, three, or four
data bytes, as determined by the instruction byte. Using one multibyte transfer is the preferred method. Single-byte data transfers
are useful to reduce CPU overhead when register access requires
one byte only. Registers change immediately upon writing to the
last bit of each transfer byte.
INSTRUCTION BYTE
The instruction byte contains the information shown in Table 11.
Table 11.
MSB
DB7
R/W
DB6
N1
DB5
N0
DB4
A4
DB3
A3
DB2
A2
DB1
A1
LSB
DB0
A0
R/W (Bit 7 of the instruction byte) determines whether a read or a
write data transfer occurs after the instruction byte write. Logic 1
indicates a read operation. Logic 0 indicates a write operation.
N1 and N0 (Bit 6 and Bit 5 of the instruction byte) determine the
number of bytes to be transferred during the data transfer cycle.
The bit decodes are shown in Table 12.
Table 12. Byte Transfer Count
N1
0
0
1
1
N0
0
1
0
1
Description
Transfer 1 byte
Transfer 2 bytes
Transfer 3 bytes
Transfer 4 bytes
A4, A3, A2, A1, and A0 (Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the
instruction byte) determine which register is accessed during the
data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The
following register addresses are generated internally by the
AD9714/AD9715/AD9716/AD9717, based on the LSBFIRST bit
(Register 0x00, Bit 6).
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK—Serial Clock
The serial clock pin is used to synchronize data to and from the
AD9714/AD9715/AD9716/AD9717 and to run the internal state
machines. The SCLK maximum frequency is 20 MHz. All data
input to the AD9714/AD9715/AD9716/AD9717 is registered on
the rising edge of SCLK. All data is driven out of the AD9714/
AD9715/AD9716/AD9717 on the falling edge of SCLK.
CS—Chip Select
An active low input starts and gates a communications cycle.
It allows more than one device to be used on the same serial
communications lines. The SDIO/FORMAT pin reaches a
high impedance state when this input is high. Chip select
should stay low during the entire communications cycle.
SDIO—Serial Data I/O
The SDIO pin is used as a bidirectional data line to transmit
and receive data.
Rev. A | Page 33 of 80
AD9714/AD9715/AD9716/AD9717
MSB/LSB TRANSFERS
INSTRUCTION CYCLE
When LSBFIRST = 1 (LSB first), the instruction and data bytes
must be written from the least significant bit to the most significant bit. Multibyte data transfers in LSB first format start with
an instruction byte that includes the register address of the least
significant data byte followed by multiple data bytes. The serial
port internal byte address generator increments for each byte
of the multibyte communication cycle.
The serial port controller data address of the AD9714/AD9715/
AD9716/AD9717 decrements from the data address written
toward 0x00 for multibyte I/O operations if the MSB first mode
is active. The serial port controller address increments from the
data address written toward 0x1F for multibyte I/O operations
if the LSB first mode is active.
SERIAL PORT OPERATION
The serial port configuration of the AD9714/AD9715/AD9716/
AD9717 is controlled by Register 0x00. It is important to note
that the configuration changes immediately upon writing to the
last bit of the register. For multibyte transfers, writing to this
register can occur during the middle of the communications
cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communications cycle.
The same considerations apply to setting the software reset bit
(Register 0x00, Bit 5). All registers are set to their default values
except Register 0x00, which remains unchanged.
Use of single-byte transfers or initiating a software reset is
recommended when changing serial port configurations to
prevent unexpected device behavior.
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
A2
A1 A0 D7N D6N D5 N
D30 D20 D10 D00
A3
A2 A1 A0
D6 N D5N
D30 D20 D1 0 D00
SDO
Figure 86. Serial Register Interface Timing, MSB First Read
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
SDIO
A0
A1 A2 A3
A4 N0
N1 R/W D00 D10 D20
D4N D5N D6N D7N
Figure 87. Serial Register Interface Timing, LSB First Write
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
SDIO
A0
A1 A2
A3
A4
N0
N1 R/W
D10 D20
D4N D5N D6N D7N
D0
SDO
Figure 88. Serial Register Interface Timing, LSB First Read
PIN MODE
The AD9714/AD9715/AD9716/AD9717 can also be operated
without ever writing to the serial port. With the RESET/PINMD
pin tied high, the SCLK pin becomes CLKMD to provide for
clock mode control (see the Retimer section), the SDIO pin
becomes FORMAT and selects the input data format, and the
CS/PWRDN pin serves to power down the device.
Operation is otherwise exactly as defined by the default register
values in Table 13; therefore, external resistors at FSADJI and
FSADJQ are needed to set the DAC currents, and both DACs
are active. This is also a convenient quick checkout mode.
DAC currents can be externally adjusted in pin mode by sourcing
or sinking currents at the FSADJI/AUXI and FSADJQ/AUXQ
pins as desired with the fixed resistors installed. An op amp
output with appropriate series resistance is one of many possibilities. This has the same effect as changing the resistor value.
Place at least 10 kΩ resistors in series right at the DAC to guard
against accidental short circuits and noise modulation. The
REFIO pin can be adjusted ±25% in a similar manner, if desired.
07265-291
R/W N1 N0 A4 A3
A4
D7
SCLK
SDIO
R/W N1 N0
07265-290
SDIO
07265-289
When LSBFIRST = 0 (MSB first), the instruction and data bytes
must be written from the most significant bit to the least significant
bit. Multibyte data transfers in MSB first format start with an
instruction byte that includes the register address of the most
significant data byte. Subsequent data bytes should follow in
order from a high address to a low address. In MSB first mode,
the serial port internal byte address generator decrements for
each data byte of the multibyte communications cycle.
SCLK
07265-288
The serial port of the AD9714/AD9715/AD9716/AD9717 can
support both most significant bit (MSB) first or least significant
bit (LSB) first data formats. This functionality is controlled by
the LSBFIRST bit (Register 0x00, Bit 6). The default is MSB first
(LSBFIRST = 0).
DATA TRANSFER CYCLE
CS
Figure 85. Serial Register Interface Timing, MSB First Write
Rev. A | Page 34 of 80
AD9714/AD9715/AD9716/AD9717
SPI REGISTER MAP
Table 13.
Name
SPI Control
Power-Down
Data Control
I DAC Gain
IRSET
IRCML
Q DAC Gain
QRSET
QRCML
AUXDAC Q
AUX CTLQ
AUXDAC I
AUX CTLI
Reference Resistor
Cal Control
Cal Memory
Memory Address
Memory Data
Memory R/W
CLKMODE
Version
Addr
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x14
0x1F
Default
0x00
0x40
0x34
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x34
0x00
0x00
0x03
Bit 7
Bit 6
Reserved
LSBFIRST
LDOOFF
LDOSTAT
TWOS
Reserved
Reserved
IRSETEN
Reserved
IRCMLEN
Reserved
Reserved
QRSETEN
Reserved
QRCMLEN Reserved
QAUXEN
Bit 5
Reset
PWRDN
IFIRST
QAUXRNG[1:0]
IAUXEN
IAUXRNG[1:0]
Reserved
PRELDQ
PRELDI
CALSELQ
CALSTATQ CALSTATI
Reserved
Reserved
CALRSTQ
CALRSTI
CLKMODEQ[1:0]
Bit 4
LNGINS
Q DACOFF
IRISING
Bit 3
Bit 2
I DACOFF
QCLKOFF
SIMULBIT
DCI_EN
I DACGAIN[5:0]
IRSET[5:0]
IRCML[5:0]
Q DACGAIN[5:0]
QRSET[5:0]
QRCML[5:0]
QAUXDAC[7:0]
QAUXOFS[2:0]
IAUXDAC[7:0]
IAUXOFS[2:0]
RREF[5:0]
CALSELI
CALCLK
DIVSEL[2:0]
CALMEMQ[1:0]
MEMADDR[5:0]
MEMDATA[5:0]
CALEN
SMEMWR
SMEMRD
Searching Reacquire
CLKMODEN
Version[7:0]
Rev. A | Page 35 of 80
Bit 1
Bit 0
ICLKOFF
DCOSGL
EXTREF
DCODBL
QAUXDAC[9:8]
IAUXDAC[9:8]
CALMEMI[1:0]
UNCALQ UNCALI
CLKMODEI[1:0]
AD9714/AD9715/AD9716/AD9717
SPI REGISTER DESCRIPTIONS
Reading these registers returns previously written values for all defined register bits, unless otherwise noted.
Table 14.
Register
SPI Control
Power-Down
Data Control
I DAC Gain
Address
0x00
0x01
0x02
0x03
Bit
6
Name
LSBFIRST
5
Reset
4
LNGINS
7
LDOOFF
6
LDOSTAT
5
PWRDN
4
Q DACOFF
3
I DACOFF
2
QCLKOFF
1
ICLKOFF
0
EXTREF
7
TWOS
5
IFIRST
4
IRISING
3
SIMULBIT
2
DCI_EN
1
DCOSGL
0
DCODBL
5:0
I DACGAIN[5:0]
Description
0 (default): MSB first, per SPI standard.
1: LSB first, per SPI standard.
Note that the user must always change the LSB/MSB order in single-byte
instructions to avoid erratic behavior due to bit order errors.
Execute software reset of SPI and controllers, reload default register values except
Register 0x00.
1: sets software reset; write 0 on the next (or any following) cycle to release reset.
0 (default): the SPI instruction word uses a 5-bit address.
1: the SPI instruction word uses a 13-bit address.
0 (default): LDO voltage regulator on.
1: turns core LDO voltage regulator off.
0: indicates that the core LDO voltage regulator is off.
1 (default) : indicates that the core LDO voltage regulator is on.
0 (default): all analog and digital circuitry and SPI logic are powered on.
1: powers down all analog and digital circuitry except for SPI logic.
0 (default): turns on Q DAC output current.
1: turns off Q DAC output current.
0 (default): turns on I DAC output current.
1: turns off I DAC output current.
0 (default): turns on Q DAC clock.
1: turns off Q DAC clock.
0 (default): turns on I DAC clock.
1: turns off I DAC clock.
0 (default): turns on internal voltage reference.
1: powers down internal voltage reference (external reference required).
0 (default): unsigned binary input data format.
1: twos complement input data format.
0: pairing of data—Q first of pair on data input pads.
1 (default): pairing of data—I first of pair on data input pads.
0: Q data latched on DCLKIO rising edge.
1 (default): I data latched on DCLKIO rising edge.
0 (default): allows simultaneous input and output enable on DCLKIO.
1: disallows simultaneous input and output enable on DCLKIO.
Controls the use of the DCLKIO pad for data clock input.
0: data clock input disabled.
1 (default): data clock input enabled.
Controls the use of the DCLKIO pad for data clock output.
0 (default): data clock output disabled.
1: data clock output enabled; regular strength driver.
Controls the use of the DCLKIO pad for data clock output.
0 (default): DCODBL data clock output disabled.
1: DCODBL data clock output enabled; paralleled with DCOSGL for 2× drive
current.
DAC I fine gain adjustment; alters the full-scale current as shown in Figure 100.
Default IDACGAIN = 0x00.
Rev. A | Page 36 of 80
AD9714/AD9715/AD9716/AD9717
Register
IRSET
IRCML
Address
0x04
0x05
Bit
7
Name
IRSETEN
5:0
IRSET[5:0]
7
IRCMLEN
5:0
IRCML[5:0]
Q DAC Gain
0x06
5:0
Q DACGAIN[5:0]
QRSET
0x07
7
QRSETEN
5:0
QRSET[5:0]
7
QRCMLEN
5:0
QRCML[5:0]
QRCML
0x08
AUXDAC Q
0x09
7:0
QAUXDAC[7:0]
AUX CTLQ
0x0A
7
QAUXEN
6:5
QAUXRNG[1:0]
4:2
QAUXOFS[2:0]
1:0
QAUXDAC[9:8]
Description
0 (default): IRSET resistor value for I channel is set by an external resistor connected
to the FADJI/AUXI pin. Nominal value for this external resistor is 16 kΩ.
1: enables the on-chip IRSET value to be changed for I channel.
Changes the value of the on-chip IRSET resistor for I channel; this scales the full-scale
current of the DAC in ~0.25 dB steps twos complement (nonlinear); see Figure 99.
000000 (default): IRSET = 16 kΩ.
011111: IRSET = 32 kΩ.
100000: IRSET = 8 kΩ.
111111: IRSET = 16 kΩ.
0 (default): IRCML resistor value for the I channel is set by an external resistor
connected to the CMLI pin. Recommended value for this external resistor is 0 Ω.
1: enables on-chip IRCML adjustment for I channel.
Changes the value of the on-chip IRCML resistor for I channel; this adjusts the
common-mode level of the DAC output stage.
000000 (default): IRCML = 250 Ω.
100000: IRCML= 625 Ω.
111111: IRCML = 1 kΩ.
DAC Q fine gain adjustment; alters the full-scale current as shown in Figure 100.
Default QDACGAIN = 0x00.
0 (default): QRSET resistor value for Q channel is set by an external resistor connected
to the FADJQ/AUXQ pin. Recommended value for this external resistor is 16 kΩ.
1: enables on-chip QRSET adjustment for Q channel.
Changes the value of the on-chip QRSET resistor for Q channel; this scales the fullscale current of the DAC in ~0.25 dB steps twos complement (nonlinear); see
Figure 99.
000000 (default): QRSET = 16 kΩ.
011111: QRSET = 32 kΩ.
100000: QRSET = 8 kΩ.
111111: QRSET = 16 kΩ.
0 (default): QRCML resistor value for the Q channel is set by an external resistor
connected to CMLQ pin. Recommended value for this external resistor is 0 Ω.
1: enables on-chip QRCML adjustment for Q channel.
Changes the value of the on-chip QRCML resistor for Q channel; this adjusts the
common-mode level of the DAC output stage.
000000 (default): QRCML = 250 Ω.
100000: QRCML = 625 Ω.
111111: QRCML = 1 kΩ.
AUXDAC Q output voltage adjustment word LSBs.
0x3FF: sets AUXDAC Q output to full scale.
0x200: sets AUXDAC Q output to midscale.
0x000 (default): sets AUXDAC Q output to bottom of scale.
0 (default): AUXDAC Q output disabled.
1: enables AUXDAC Q output.
00 (default): sets AUXDAC Q output voltage range to 2 V.
01: sets AUXDAC Q output voltage range to 1.5 V.
10: sets AUXDAC Q output voltage range to 1.0 V.
11: sets AUXDAC Q output voltage range to 0.5 V.
000 (default): sets AUXDAC Q top of range to 1.0 V.
001: sets AUXDAC Q top of range to 1.5 V.
010: sets AUXDAC Q top of range to 2.0 V.
011: sets AUXDAC Q top of range to 2.5 V.
100: sets AUXDAC Q top of range to 2.9 V.
AUXDAC Q output voltage adjustment word MSBs (default = 00).
Rev. A | Page 37 of 80
AD9714/AD9715/AD9716/AD9717
Register
AUXDAC I
Address
0x0B
Bit
7:0
Name
IAUXDAC[7:0]
AUX CTLI
0x0C
7
IAUXEN
6:5
IAUXRNG[1:0]
4:2
IAUXOFS[2:0]
Reference
Resistor
0x0D
1:0
5:0
IAUXDAC[9:8]
RREF[5:0]
Cal Control
0x0E
7
PRELDQ
6
PRELDI
5
CALSELQ
4
CALSELI
3
CALCLK
2:0
DIVSEL[2:0]
7
CALSTATQ
6
CALSTATI
3:2
CALMEMQ[1:0]
1:0
CALMEMI[1:0]
5:0
5:0
MEMADDR[5:0]
MEMDATA[5:0]
Cal Memory
Memory Address
Memory Data
0x0F
0x10
0x11
Description
AUXDAC I output voltage adjustment word LSBs.
0x3FF: sets AUXDAC I output to full scale.
0x200: sets AUXDAC I output to midscale.
0x000 (default): sets AUXDAC I output to bottom of scale.
0 (default): AUXDAC I output disabled.
1: enables AUXDAC I output.
00 (default): sets AUXDAC I output voltage range to 2 V.
01: sets AUXDAC I output voltage range to 1.5 V.
10: sets AUXDAC I output voltage range to 1.0 V.
11: sets AUXDAC I output voltage range to 0.5 V.
000 (default): sets AUXDAC I top of range to 1.0 V.
001: sets AUXDAC I top of range to 1.5 V.
010: sets AUXDAC I top of range to 2.0 V.
011: sets AUXDAC I top of range to 2.5 V.
100: sets AUXDAC I top of range to 2.9 V.
AUXDAC I output voltage adjustment word MSBs (default = 00).
Permits an adjustment of the on-chip reference voltage and output at REFIO (see
Figure 98) twos complement.
000000 (default): sets the value of RREF to 10 kΩ, VREF = 1.0 V.
011111: sets the value of RREF to 12 kΩ, VREF = 1.2 V.
100000: sets the value of RREF to 8 kΩ, VREF = 0.8 V.
111111: sets the value of RREF to 10 kΩ, VREF = 1.0 V.
0 (default): preload Q DAC calibration reference set to 32.
1: preload Q DAC calibration reference set by user (Cal Address 1).
0 (default): preload I DAC calibration reference set to 32.
1: preload I DAC calibration reference set by user (Cal Address 1).
0 (default): Q DAC self-calibration done.
1: select Q DAC self-calibration.
0 (default): I DAC self-calibration done.
1: select I DAC self-calibration.
0 (default): calibration clock disabled.
1: calibration clock enabled.
Calibration clock divide ratio from DAC clock rate.
000 (default): divide by 256.
001: divide by 128.
…
110: divide by 4.
111: divide by 2.
0 (default): Q DAC calibration in progress.
1: calibration of Q DAC complete.
0 (default): I DAC calibration in progress.
1: calibration of I DAC complete.
Status of Q DAC calibration memory.
00 (default): uncalibrated.
01: self-calibrated.
10: user calibrated.
Status of I DAC calibration memory.
00 (default): uncalibrated.
01: self-calibrated.
10: user calibrated.
Address of static memory to be accessed.
Data for static memory access.
Rev. A | Page 38 of 80
AD9714/AD9715/AD9716/AD9717
Register
Memory R/W
CLKMODE
Version
Address
0x12
0x14
0x1F
Bit
7
Name
CALRSTQ
6
CALRSTI
4
CALEN
3
SMEMWR
2
SMEMRD
1
UNCALQ
0
UNCALI
7:6
CLKMODEQ[1:0]
4
Searching
3
2
Reacquire
CLKMODEN
1:0
CLKMODEI[1:0]
7:0
Version[7:0]
Description
0 (default): no action.
1: clear CALSTATQ.
0 (default): no action.
1: clear CALSTATI.
0 (default): no action.
1: initiate device self-calibration.
0 (default): no action.
1: write to static memory (calibration coefficients).
0 (default): no action.
1: read from static memory (calibration coefficients).
0 (default): no action.
1: reset Q DAC calibration coefficients to default (uncalibrated).
0 (default): no action.
1: reset I DAC calibration coefficients to default (uncalibrated).
Depending on the CLKMODEN bit setting, these two bits reflect the phase
relationship between DCLKIO and CLKIN, as described in Table 16.
If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer.
If CLKMODEN = 1, read/write; value in this register sets Q clock phases; force if
needed to better synchronize the DACs (see the Retimer section).
Data path retimer status bit.
0 (default): clock relationship established.
1: indicates that the internal data path retimer is searching for clock relationship
(device output is not usable while this bit is high).
Edge triggered, 0 to 1 causes the retimer to reacquire the clock relationship.
0 (default): CLKMODEI/CLKMODEQ values computed by the two retimers and
read back in CLKMODEI[1:0] and CLKMODEQ[1:0].
1: CLKMODE values set in CLKMODEI[1:0] override both I and Q retimers.
Depending on CLKMODEN bit setting, these two bits reflect the phase
relationship between DCLKIO and CLKIN as described in Table 16.
If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer.
If CLKMODEN = 1, read/write; value in this register sets I clock phases; force if
needed to better synchronize the DACs (see the Retimer section).
Hardware version of the device. This register is set to 0x03 for the latest version of
the device.
Rev. A | Page 39 of 80
AD9714/AD9715/AD9716/AD9717
DIGITAL INTERFACE OPERATION
Digital data for the I and Q DACs is supplied over a single
parallel bus (DB[n:0), where n is 7 for the AD9714, 9 for
the AD9715, 11 for the AD9716, and 13 for the AD9717)
accompanied by a qualifying clock (DCLKIO). The I and Q
data are provided to the chip in an interleaved double data
rate (DDR) format. The maximum guaranteed data rate is
250 MSPS with a 125 MHz clock. The order of data pairing
and the sampling edge selection is user programmable using
the IFIRST and IRISING data control bits, resulting in four
possible timing diagrams. These are shown in Figure 89,
'JHVSF90, Figure 91, and Figure 92.
DCLKIO
Z
A
B
C
D
E
I DATA
Z
B
Q DATA
A
C
F
G
H
D
F
E
G
07265-049
DB[n:0]
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE
AD9716, AND 13 FOR THE AD9717.
Figure 91. Timing Diagram with IFIRST = 1, IRISING = 0
DCLKIO
DCLKIO
Z
A
B
C
D
E
F
G
H
DB[n:0]
Z
B
Q DATA
Y
A
D
Z
A
B
C
D
E
F
G
H
F
C
E
07265-047
I DATA
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE
AD9716, AND 13 FOR THE AD9717.
I DATA
Y
A
Q DATA
Z
B
C
E
D
F
07265-050
DB[n:0]
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE
AD9716, AND 13 FOR THE AD9717.
Figure 89. Timing Diagram with IFIRST = 0, IRISING = 0
Figure 92. Timing Diagram with IFIRST = 1, IRISING = 1
DCLKIO
DB[n:0]
I DATA
Z
A
B
Y
C
D
A
E
F
G
C
Ideally, the rising and falling edges of the clock fall in the center
of the keep-in-window formed by the setup and hold times, tS
and tH. Refer to Table 2 for setup and hold times. A detailed
timing diagram is shown in Figure 93.
H
E
X
Z
B
D
tS tH
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE
AD9716, AND 13 FOR THE AD9717.
tS tH
DB[n:0]
Figure 90. Timing Diagram with IFIRST = 0, IRISING = 1
07265-051
Q DATA
07265-048
DCLKIO
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE
AD9715, 11 FOR THE AD9716, AND 13 FOR THE AD9717.
Figure 93. Setup and Hold Times for All Input Modes
In addition to the different timing modes listed in Table 2, the
input data can also be presented to the device in either unsigned
binary or twos complement format. The format type is chosen
via the TWOS data control bit.
Rev. A | Page 40 of 80
AD9714/AD9715/AD9716/AD9717
OR
DB[n:0]
(INPUT)
RETIMER-CLK
D-FF
D-FF
D-FF
D-FF
0
1
2
3
D-FF
TO DAC CORE
IOUT
CLKIN-INT
IOUT
NOTES
D-FFs:
0: RISING OR FALLING EDGE
TRIGGERED FOR I OR Q DATA.
1, 2, 3, 4: RISING EDGE TRIGGERED.
DELAY1
DELAY1
RETIMER-CLK
DCLKIO-INT
4
IE
IE
OE
DCLKIO
(INPUT/OUTPUT)
07265-052
DELAY2
CLKIN
(INPUT)
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE AD9716, AND 13 FOR THE AD9717.
Figure 94. Simplified Diagram of AD9714/AD9715/AD9716/AD9717 Timing
The AD9714/AD9715/AD9716/AD9717 have two clock inputs,
DCLKIO and CLKIN. The CLKIN is the analog clock whose
jitter affects DAC performance, and the DCLKIO is a digital
clock from an FPGA that needs to have a fixed relationship with
the input data to ensure that the data is picked
up correctly by the flip-flops on the pads.
Figure 94 is a simplified diagram of the entire data capture
system in the AD9714/AD9715/AD9716/AD9717. The double
data rate input data (DB[n:0), where n is 7 for the AD9714, 9
for the AD9715, 11 for the AD9716, and 13 for the AD9717) is
latched at the pads/pins either on the rising edge or the falling edge
of the DCLKIO-INT clock, as determined by IRISING, Bit 4 of
SPI Address 0x02. Bit 5 of SPI Address 0x02, IFIRST, determines
which channel data is latched first (that is, I or Q). The captured
data is then retimed to the internal clock (CLKIN-INT) in the
retimer block before being sent to the final analog DAC core
(D-FF 4), which controls the current steering output switches. All
delay blocks depicted in Figure 94 are noninverting, and any wires
without an explicit delay block can be assumed to have no delay.
Setting Bit 1 or Bit 0 of SPI Address 0x02, DCOSGL or DCODBL,
respectively, to logic high allows the user to obtain a DCLKIO
output from the CLKIN input for use in the user’s PCB system.
It is strongly recommended that DCI_EN = DCOSGL = high or
DCI_EN = DCODBL = high not be used even though the
device may appear to function correctly. Similarly, do not set
DCOSGL and DCODBL to logic high simultaneously.
Retimer
The AD9714/AD9715/AD9716/AD9717 have an internal data
retimer circuit that compares the CLKIN-INT and DCLKIO-INT
clocks and, depending on their phase relationship, selects a
retimer clock (RETIMER-CLK) to safely transfer data from
the DCLKIO used at the chip’s input interface to the CLKIN
used to clock the analog DAC cores (D-FF 4).
The retimer selects one of the three phases shown in Figure 95.
The retimer is controlled by the CLKMODE SPI bits, as shown
in Table 15.
1/2 PERIOD
180°
90°
Only one channel is shown in Figure 94 with the data pads
(DB[n:0), where n is 7 for the AD9714, 9 for the AD9715, 11 for
the AD9716, and 13 for the AD9717) serving as double data
rate pads for both channels.
The default PINMD and SPI settings are IE = high (closed)
and OE = low (open). These settings are enabled when RESET/
PINMD (Pin 35) is held high. In this mode, the user has to supply
both DCLKIO and CLKIN. In PINMD, it is also recommended
that the DCLKIO and the CLKIN be in phase for proper functioning of the DAC, which can easily be ensured by tying the
pins together on the PCB. If the user can access the SPI, setting
Bit 2 of SPI Address 0x02, DCI_EN, to logic low causes the
CLKIN to be used as the DCLKIO also.
RETIMER-CLKs
DATA
CLOCK
270°
1/4 PERIOD
1/2 PERIOD
07265-042
DIGITAL DATA LATCHING AND RETIMER BLOCK
Figure 95. RETIMER-CLK Phases
Note that, in most cases, more than one retimer phase works
and ,in such cases, the retimer arbitrarily picks one phase that
works. The retimer cannot pick the best or safest phase. If the
user has a working knowledge of the exact phase relationship
between DCLKIO and CLKIN (and thus DCLKIO-INT and
CLKIN-INT because the delay is approximately the same for
both clocks and equal to DELAY1), then the retimer can be
forced to this phase with CLKMODEN = 1, as described in
Table 15 and the following paragraphs.
Rev. A | Page 41 of 80
AD9714/AD9715/AD9716/AD9717
Table 15. Timer Register List
Bit Name
CLKMODEQ[1:0]
Searching
Reacquire
CLKMODEN
CLKMODEI[1:0]
Description
Q data path retimer clock selected output. Valid after the searching bit goes low.
High indicates that the internal data path retimer is searching for the clock relationship (DAC is not usable until it is low again).
Changing this bit from 0 to 1 causes the data path retimer circuit to reacquire the clock relationship.
0: uses CLKMODEI/CLKMODEQ values (as computed by the two internal retimers) for I and Q clocking.
1: uses the CLKMODE value set in CLKMODEI[1:0] to override the bits for both I and Q retimers (that is, force the retimer).
I data path retimer clock selected output. Valid after searching goes low.
If CLKMODEN = 1, a value written to this register overrides both the I and Q automatic retimer values.
Table 16. CLKMODEI/CLKMODEQ Details
CLKMODEI[1:0]/CLKMODEQ[1:0]
00
01
10
11
DCLKIO-to-CLKIN Phase Relationship
0° to 90°
90° to 180°
180° to 270°
270° to 360°
When RESET is pulsed high and then returns low (the part is in
SPI mode), the retimer runs and automatically selects a suitable
clock phase for the RETIMER-CLK within 128 clock cycles. The
SPI searching bit, Bit 4 of SPI Address 0x14, returns to low,
indicating that the retimer has locked and the part is ready for
use. The reacquire bit, Bit 3 of SPI Address 0x14, can be used to
reinitiate phase detection in the I and Q retimers at any time.
CLKMODEQ[1:0] and CLKMODEI[1:0] of SPI Address 0x14
provide readback for the values picked by the internal phase
detectors in the retimer (see Table 16).
To force the two retimers (I and Q) to pick a particular phase
for the retimer clock (they must both be forced to the same
value), CLKMODEN, Bit 2 of SPI Address 0x14, should be set
high and the required phase value is written into CLKMODEI[1:0]
and CLKMODEQ[1:0]. For example, if the DCLKIO and the
CLKIN are in phase to the first order, the user can safely force the
retimers to pick Phase 2 for the RETIMER-CLK. This forcing
function may be useful for synchronizing multiple devices.
RETIMER-CLK Selected
Phase 2
Phase 3
Phase 3
Phase 1
ESTIMATING THE OVERALL DAC PIPELINE DELAY
DAC pipeline latency is affected by the phase of the RETIMERCLK that is selected. If latency is critical to the system and must
be constant, the retimer should be forced to a particular phase and
not be allowed to automatically select a phase each time.
Consider the case in which DCLKIO = CLKIN (that is, in
phase), and the RETIMER-CLK is forced to Phase 2. Assume
that IRISING is 1 (that is, Q data is latched on the rising edge
and I data is latched on the falling edge). Then the latency to the
output for the I channel is three clock cycles (D-FF 1, D-FF 3,
and D-FF 4, but not D-FF 2 because it is latched on the half
clock cycle or 180°). The latency to the output for the Q channel
from the time the falling edge latches it at the pads in D-FF 0
is 2.5 clock cycles (½ clock cycle to D-FF 1, 1 clock cycle to
D-FF 3, and 1 clock cycle to D-FF 4). This latency for the AD9714/
AD9715/AD9716/AD9717 is case specific and needs to be calculated based on the RETIMER-CLK phase that is automatically
selected or manually forced.
In pin mode, it is expected that the user tie CLKIN and DCLKIO
together. The device has a small amount of programmable
functionality using the unused SPI pins (SCLK, SDIO, and CS).
If the two chip clocks are tied together, the SCLK pin can be
tied to ground, and the chip uses a clock for the retimer that is
180° out of phase with the two input clocks (that is, Phase 2,
which is the safest and best option). The chip has an additional
option in pin mode when the redefined SCLK pin is high. Use
this mode if using pin mode, but CLKIN and DCLKIO are not
tied together (that is, not in phase). Holding SCLK high causes
the internal clock detector to use the phase detector output to
determine which clock to use in the retimer (that is, select a
suitable RETIMER-CLK phase). The action of taking SCLK
high causes the internal phase detector to reexamine the two
clocks and determine the relative phase. Whenever the user
wants to reevaluate the relative phase of the two clocks, the
SCLK pin can be taken low and then high again.
Rev. A | Page 42 of 80
AD9714/AD9715/AD9716/AD9717
REFERENCE OPERATION
REFERENCE CONTROL AMPLIFIER
The AD9714/AD9715/AD9716/AD9717 contain an internal
1.0 V band gap reference. The internal reference can be disabled
by setting Bit 0 (EXTREF) of the power-down register (Address
0x01) through the SPI interface. To use the internal reference,
decouple the REFIO pin to AVSS with a 0.1 μF capacitor, enable
the internal reference, and clear Bit 0 of the power-down register
(Address 0x01) through the SPI interface. Note that this is the
default configuration. The internal reference voltage is present
at REFIO. If the voltage at REFIO is to be used anywhere else in
the circuit, an external buffer amplifier with an input bias current
of less than 100 nA must be used to avoid loading the reference.
An example of the use of the internal reference is shown in
Figure 96.
The AD9714/AD9715/AD9716/AD9717 contain a control
amplifier that regulates the full-scale output current, IxOUTFS.
The control amplifier is configured as a V-I converter, as shown
in Figure 96. The output current, IxREF, is determined by the
ratio of the VREFIO and an external resistor, xRSET, as stated in
Equation 4 (see the DAC Transfer Function section). IxREF, is
mirrored to the segmented current sources with the proper scale
factor to set IxOUTFS, as stated in Equation 3.
AD9714/AD9715/
AD9716/AD9717
REFIO
I DAC
OR
Q DAC
–
+
0.1µF
xRSET
CURRENT
SCALING
×32
IxOUTFS
07265-218
FSADJx
IxREF
AVSS
Figure 96. Internal Reference Configuration
REFIO serves as either an input or an output, depending on
whether the internal or an external reference is used. Table 17
summarizes the reference operation.
When an external resistor greater than 16 kΩ is used on the
FSADJx pins, care must be taken to maintain the high frequency
equivalent circuit to an impedance lower than 16 kΩ by
splitting the resistor into two resistors in series with a 10 nF
capacitor in parallel with the resistor to AVSS (see Figure 97).
AD9714/AD9715/
AD9716/AD9717
Table 17. Reference Operation
Reference Mode
Internal
External
REFIO Pin
Connect 0.1 μF
capacitor
Apply external
capacitor
REFIO
Register Setting
Register 0x01, Bit 0 = 0
(default)
Register 0x01, Bit 0 = 1
(for power saving)
An external reference can be used in applications requiring
tighter gain tolerances or lower temperature drift. Also, a
variable external voltage reference can be used to implement a
method for gain control of the DAC output.
Recommendations When Using an External Reference
Apply the external reference to the REFIO pin. The internal
reference can be directly overdriven by the external reference,
or the internal reference can be powered down to save power
consumption
The external 0.1 μF compensation capacitor on REFIO is not
required unless specified by the external voltage reference
manufacturer. The input impedance of REFIO is 10 kΩ when
the internal reference is powered up and 1 MΩ when it is
powered down.
Rev. A | Page 43 of 80
FSADJx
0.1µF
R < 16kΩ
xRSET
10nF
AVSS
Figure 97. xRSET Configuration for Values > 16 kΩ
07265-219
VBG
1.0V
The control amplifier allows a 2.5:1 adjustment span of IxOUTFS
from 1 mA to 4 mA by setting IxREF between 125 μA and 31.25 μA
(set xRSET between 8 kΩ and 32 kΩ). The wide adjustment span
of IxOUTFS provides several benefits. The first relates directly to
the power dissipation of the AD9714/AD9715/AD9716/AD9717,
which is proportional to IxOUTFS (see the DAC Transfer Function
section). The second benefit relates to the ability to adjust the
output over a 8 dB range with 0.25 dB steps, which is useful for
controlling the transmitted power. The small signal bandwidth
of the reference control amplifier is approximately 500 kHz.
This allows the device to be used for low frequency, small signal
multiplying applications.
AD9714/AD9715/AD9716/AD9717
DAC TRANSFER FUNCTION
The AD9714/AD9715/AD9716/AD9717 provide two differential current outputs, IOUTP/IOUTN and QOUTP/QOUTN.
IOUTP and QOUTP provide a near full-scale current output,
IxOUTFS, when all bits are high (that is, DAC CODE = 2N − 1,
where N = 8, 10, 12, or 14 for the AD9714, AD9715, AD9716,
and AD9717, respectively), while IOUTN and QOUTN, the
complementary outputs, provide no current. The current
outputs appearing at the positive DAC outputs, IOUTP and
QOUTP, and at the negative DAC outputs, IOUTN and QOUTN,
are a function of both the input code and IxOUTFS and can be
expressed as follows:
IOUTP = (IDAC CODE/2N) × IIOUTFS
(1)
N
QOUTP = (QDAC CODE/2 ) × IQOUTFS
IOUTN = ((2N − 1) − IDAC CODE)/2N × IIOUTFS
N
(2)
N
QOUTN = ((2 − 1) − QDAC CODE)/2 × IQOUTFS
where:
IDAC CODE and QDAC CODE = 0 to 2N − 1 (that is, decimal
representation).
IIOUTFS and IQOUTFS are functions of the reference currents, IIREF
and IQREF, respectively, which are nominally set by a reference
voltage, VREFIO, and external resistors, IRSET and QRSET, respectively. IIOUTFS and IQOUTFS can be expressed as follows:
IIOUTFS = 32 × IIREF
(3)
IQOUTFS = 32 × IQREF
where:
IIREF = VREFIO/IRSET
(4)
IQREF = VREFIO/QRSET
or
IIOUTFS = 32 × VREFIO/IRSET
(5)
IQOUTFS = 32 × VREFIO/QRSET
A differential pair (IOUTP/IOUTN or QOUTP/QOUTN)
typically drives a resistive load directly or via a transformer. If
dc coupling is required, the differential pair (IOUTP/IOUTN or
QOUTP/QOUTN) should be connected to matching resistive
loads, xRLOAD, that are tied to analog common, AVSS. The
single-ended voltage output appearing at the positive and
negative nodes is
VIOUTP = IOUTP × IRLOAD
(6)
VQOUTP = QOUTP × QRLOAD
VIOUTN = IOUTN × IRLOAD
VQOUTN = QOUTN × QRLOAD
To achieve the maximum output compliance of 1 V at the
nominal 4 mA output current, IRLOAD = QRLOAD must be set
to 250 Ω.
(7)
Substituting the values of IOUTP, IOUTN, and IxREF, VIDIFF can
be expressed as
VIDIFF = {(2 × IDAC CODE – (2N − 1))/2N} ×
(8)
(32 × VREFIO/IRSET) × IRLOAD
Equation 8 highlights some of the advantages of operating the
AD9714/AD9715/AD9716/AD9717 differentially. First, the
differential operation helps cancel common-mode error sources
associated with IOUTP and IOUTN, such as noise, distortion,
and dc offsets. Second, the differential code-dependent current and
subsequent voltage, VIDIFF, is twice the value of the single-ended
voltage output (that is, VIOUTP or VIOUTN), thus providing twice
the signal power to the load. Note that the gain drift temperature
performance for a single-ended output (VIOUTP and VIOUTN) or
differential output (VIDIFF) of the AD9714/AD9715/AD9716/
AD9717 can be enhanced by selecting temperature-tracking
resistors for xRLOAD and xRSET because of their ratiometric
relationship, as shown in Equation 8.
ANALOG OUTPUT
The complementary current outputs in each DAC, IOUTP/
IOUTN and QOUTP/QOUTN, can be configured for singleended or differential operation. IOUTP/IOUTN and QOUTP/
QOUTN can be converted into complementary single-ended
voltage outputs, VIOUTP and VIOUTN, as well as VQOUTP and VQOUTN
via a load resistor, xRLOAD, as described in the DAC Transfer
Function section by Equation 6 through Equation 8. The differential voltages, VIDIFF and VQDIFF, existing between VIOUTP and VIOUTN,
and VQOUTP and VQOUTN, can also be converted to a single-ended
voltage via a transformer or a differential amplifier configuration.
The ac performance of the AD9714/AD9715/AD9716/AD9717
is optimum and is specified using a differential transformercoupled output in which the voltage swing at IOUTP and IOUTN
is limited to ±0.5 V. The distortion and noise performance of
the AD9714/AD9715/AD9716/AD9717 can be enhanced when
it is configured for differential operation. The common-mode
error sources of both IOUTP/IOUTN and QOUTP/QOUTN
can be significantly reduced by the common-mode rejection
of a transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed waveform increases and/or its amplitude increases. This is due to
the first-order cancellation of various dynamic common-mode
distortion mechanisms, digital feedthrough, and noise. Performing
a differential-to-single-ended conversion via a transformer also
provides the ability to deliver twice the reconstructed signal
power to the load (assuming no source termination). Because
the output currents of IOUTP/IOUTN and QOUTP/QOUTN
are complementary, they become additive when processed
differentially.
Rev. A | Page 44 of 80
AD9714/AD9715/AD9716/AD9717
SELF-CALIBRATION
The AD9714/AD9715/AD9716/AD9717 have a self-calibration
feature that improves the DNL of the device. Performing a selfcalibration on the device improves device performance in low
frequency applications. The device performance in applications
where the analog output frequencies are above 5 MHz are generally
influenced more by dynamic device behavior than by DNL and,
in these cases, self-calibration is unlikely to provide much benefit.
The calibration clock frequency is equal to the DAC clock
divided by the division factor chosen by the DIVSEL value. Each
calibration clock cycle is between 32 and 2048 DAC input clock
cycles, depending on the value of DIVSEL[2:0] (Register 0x0E,
Bits[2:0]). The frequency of the calibration clock should be
between 0.5 MHz and 4 MHz for reliable calibrations. Best
results are obtained by setting DIVSEL[2:0] (Register 0x0E,
Bits[2:0]) to produce a calibration clock frequency between
these values. Separate self-calibration hardware is included
for each DAC. The DACs can be self-calibrated individually or
simultaneously.
The AD9714/AD9715/AD9716/AD9717 allow reading and
writing of the calibration coefficients. There are 32 coefficients
in total. The read/write feature of the coefficients can be useful
for improving the results of the self-calibration routine by
averaging the results of several self-calibration cycles and
loading the averaged results back into the device.
To read the calibration coefficients, use the following steps:
1.
2.
3.
4.
5.
6.
To perform a device self-calibration, the following procedure
can be used:
1.
2.
3.
4.
5.
6.
7.
Write 0x00 to Register 0x12. This ensures that the
UNCALI and UNCALQ bits are reset.
Set up a calibration clock between 0.5 MHz and 4 MHz
using DIVSEL[2:0], and then enable the calibration clock
by setting the CALCLK bit (Register 0x0E, Bit 3).
Select the DAC(s) to self-calibrate by setting either Bit 4
(CALSELI) for the I DAC and/or Bit 5 (CALSELQ) for the
Q DAC in Register 0x0E. Note that each DAC contains
independent calibration hardware so that they can be
calibrated simultaneously.
Start self-calibration by setting the CALEN bit (Register 0x12,
Bit 4). Wait approximately 300 calibration clock cycles.
Check if the self-calibration has completed by reading
the CALSTATI bit (Bit 6) and CALSTATQ bit (Bit 7) in
Register 0x0F. Logic 1 indicates that the calibration has
completed.
When the self-calibration has completed, write 0x00 to
Register 0x12.
Disable the calibration clock by clearing the CALCLK bit
(Register 0x0E, Bit 3).
Select which DAC core to read by setting either Bit 4
(CALSELI) for the I DAC or Bit 5 (CALSELQ) for the
Q DAC in Register 0x0E. Write the address of the first
coefficient (0x01) to Register 0x10.
Set the SMEMRD bit (Register 0x12, Bit 2) by writing 0x04
to Register 0x12.
Read the 6-bit value of the first coefficient by reading the
contents of Register 0x11.
Clear the SMEMRD bit by writing 0x00 to Register 0x12.
Repeat Step 2 through Step 4 for each of the remaining 31
coefficients by incrementing the address by 1 for each read.
Deselect the DAC core by clearing either Bit 4 (CALSELI)
for the I DAC or Bit 5 (CALSELQ) for the Q DAC in
Register 0x0E.
To write the calibration coefficients to the device, use the
following steps:
1.
2.
3.
4.
5.
6.
7.
Rev. A | Page 45 of 80
Select which DAC core to write to by setting either Bit 4
(CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q
DAC in Register 0x0E.
Set the SMEMWR bit (Register 0x12, Bit 3) by writing 0x08
to Register 0x12.
Write the address of the first coefficient (0x01) to
Register 0x10.
Write the value of the first coefficient to Register 0x11.
Repeat Step 2 through Step 4 for each of the remaining 31
coefficients by incrementing the address by one for each
write.
Clear the SMEMWR bit by writing 0x00 to Register 0x12.
Deselect the DAC core by clearing either Bit 4 (CALSELI)
for the I DAC or Bit 5 (CALSELQ) for the Q DAC in
Register 0x0E.
AD9714/AD9715/AD9716/AD9717
COARSE GAIN ADJUSTMENT
Option 3
Option 1
Even when the device is in pin mode, full-scale values can be
adjusted by sourcing or sinking current from the FSADJx pins.
Any noise injected here appears as amplitude modulation of the
output. Thus, a portion of the required series resistance (at least
20 kΩ) must be installed right at the pin. A range of ±10% is
quite practical using this method.
A coarse full-scale output current adjustment can be achieved
using the lower six bits in Register 0x0D. This adds or subtracts
up to 20% from the band gap voltage on Pin 34 (REFIO), and
the voltage on the FSADJx resistors tracks this change. As a
result, the DAC full-scale current varies by the same amount.
A secondary effect to changing the REFIO voltage is that the
full-scale voltage in the AUXDAC also changes by the same
magnitude. The register uses twos complement format, in
which 011111 maximizes the voltage on the REFIO node
and 100000 minimizes the voltage.
1.30
1.25
As in Option 3, when the device is in pin mode, both full-scale
values can be adjusted by sourcing or sinking current from the
REFIO pin. Noise injected here appears as amplitude modulation
of the output; therefore, a portion of the required series resistance (at least 10 kΩ) must be installed at the pin. A range of
±25% is quite practical when using this method.
1.20
Fine Gain
1.15
Each main DAC has independent fine gain control using the
lower six bits in Register 0x03 (I DAC gain) and Register 0x06
(Q DAC gain). Unlike Coarse Gain Option 1, this impacts only
the main DAC full-scale output current. These registers use straight
binary format. One application in which straight binary format
is critical is for side-band suppression while using a quadrature
modulator. This is described in more detail in the Applications
Information section.
1.10
1.05
1.00
0.95
0.90
0.85
0
8
16
24
32
CODE
40
48
2.22
07265-054
0.80
56
Option 2
IOUTFS (mA)
2.18
While using the internal FSADJx resistors, each main DAC can
achieve independently controlled coarse gain using the lower
six bits of Register 0x04 (IRSET[5:0]) and Register 0x07
(QRSET[5:0]). Unlike Coarse Gain Option 1, this impacts only
the main DAC full-scale output current. The register uses twos
complement format and allows the output current to be changed
in approximately 0.25 dB steps.
2.16
2.14
2.12
2.10
4.0
3.5
0
8
16
24
32
40
GAIN DAC CODE
48
Figure 100. Typical DAC Gain Characteristics
3.0
VOUT_Q OR VOUT_I
2.5
2.0
1.5
1.0
0.5
0
0
10
20
30
40
xRSET CODE
50
60
07265-055
OUTPUT OF I/V CONVERTER (V)
3.3V DAC1
3.3V DAC2
1.8V DAC1
1.8V DAC2
2.20
Figure 98. Typical VREF Voltage vs. Code
Figure 99. Effect of xRSET Code
Rev. A | Page 46 of 80
56
64
07265-056
VREF
Option 4
AD9714/AD9715/AD9716/AD9717
1200
USING THE INTERNAL TERMINATION RESISTORS
CML
RCML
RLIN
500Ω
IOUTN
I DAC
OR
Q DAC
RLIP
07265-057
IOUTP
500Ω
Figure 101. Simplified Internal Load Options
1100
1000
900
RESISTANCE (Ω)
800
700
600
500
400
300
200
0
8
16
24
32
CODE
40
48
56
07265-058
The AD9717/AD9716/AD9715/AD9714 have four 500 Ω
termination internal resistors (two for each DAC output).
To use these resistors to convert the DAC output current to a
voltage, connect each DAC output pin to the adjacent load pin.
For example, on the I DAC, IOUTP must be shorted to RLIP
and IOUTN must be shorted to RLIN. In addition, the CMLI
or CMLQ pin must be connected to ground directly or through
a resistor. If the output current is at the nominal 2 mA and the
CMLI or CMLQ pin is tied directly to ground, this produces a
dc common-mode bias voltage on the DAC output equal to 0.5 V.
If the DAC dc bias must be higher than 0.5 V, an external
resistor can be connected between the CMLI or CMLQ pin and
ground. This part also has an internal common-mode resistor
that can be enabled. This is explained in the Using the Internal
Common-Mode Resistor section.
Figure 102. Typical CML Resistor Value vs. Register Code
Using the CMLx Pins for Optimal Performance
The CMLx pins also serve to change the DAC bias voltages
in the parts allowing them to run at higher dc output bias
voltages. When running the bias voltage below 0.9 V and an
AVDD of 3.3 V, the parts perform optimally when the CMLx
pins are tied to ground. When the dc bias increases above 0.9 V,
set the CMLx pins at 0.5 V for optimal performance. The maximum dc bias on the DAC output should be kept at or below 1.2 V
when the supply is 3.3 V. When the supply is 1.8 V, keep the dc
bias close to 0 V and connect the CMLx pins directly to ground.
Using the Internal Common-Mode Resistor
These devices contain an adjustable internal common-mode
resistor that can be used to increase the dc bias of the DAC
outputs. By default, the common-mode resistor is not connected. When enabled, it can be adjusted from ~250 Ω to
~1 kΩ. Each main DAC has an independent adjustment
using the lower six bits in Register 0x05 (IRCML[5:0]) and
Register 0x08 (QRCML[5:0]).
Rev. A | Page 47 of 80
AD9714/AD9715/AD9716/AD9717
APPLICATIONS INFORMATION
OUTPUT CONFIGURATIONS
The following sections illustrate some typical output configurations for the AD9714/AD9715/AD9716/AD9717. Unless
otherwise noted, it is assumed that IxOUTFS is set to a nominal
2 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A
differential output configuration can consist of either an
RF transformer or a differential op amp configuration. The
transformer configuration provides the optimum high frequency performance and is recommended for any application
that allows ac coupling. The differential op amp configuration
is suitable for applications requiring dc coupling, signal gain,
and/or a low output impedance.
A single-ended output is suitable for applications in which low
cost and low power consumption are primary concerns.
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-tosingle-ended signal conversion, as shown in Figure 103. The
distortion performance of a transformer typically exceeds
that available from standard op amps, particularly at higher
frequencies. Transformer coupling provides excellent rejection
of common-mode distortion (that is, even-order harmonics)
over a wide frequency range. It also provides electrical isolation
and can deliver voltage gain without adding noise. Transformers
with different impedance ratios can also be used for impedance
matching purposes. The main disadvantages of transformer
coupling are low frequency roll-off, lack-of-power gain, and
high output impedance.
A differential resistor, RDIFF, can be inserted in applications
where the output of the transformer is connected to the load,
RLOAD, via a passive reconstruction filter or cable. RDIFF, as
reflected by the transformer, is chosen to provide a source
termination that results in a low voltage standing wave ratio
(VSWR). Note that approximately half the signal power is
dissipated across RDIFF.
SINGLE-ENDED BUFFERED OUTPUT USING
AN OP AMP
An op amp such as the ADA4899-1 can be used to perform
a single-ended current-to-voltage conversion, as shown in
Figure 104. The AD9714/AD9715/AD9716/AD9717 are configured with a pair of series resistors, RS, off each output. For best
distortion performance, RS should be set to 0 Ω. The feedback
resistor, RFB, determines the peak-to-peak signal swing by the
formula
VOUT = RFB × IFS
The common-mode voltage of the output is determined by the
formula

R
VCM  VREF  1  FB
RB

 RFB  I FS


2

The maximum and minimum voltages out of the amplifier are,
respectively,
 R
VMAX  VREF  1  FB
RB




VMIN = VMAX – IFS × RFB
CF
IOUTN 29
RFB
RB
AD9714/AD9715/
AD9716/AD9717
RLOAD
+5V
AD9714/AD9715/
AD9716/AD9717
RS
Figure 103. Differential Output Using a Transformer
REFIO 34
IOUTN 29
The center tap on the primary side of the transformer must be
connected to a voltage that keeps the voltages on IOUTP and
IOUTN within the output common-mode voltage range of the
device. Note that the dc component of the DAC output current
is equal to IxOUTFS and flows out of both IOUTP and IOUTN.
The center tap of the transformer should provide a path for
this dc current. In most applications, AGND provides the most
convenient voltage for the transformer center tap. The complementary voltages appearing at IOUTP and IOUTN (that is, VIOUTP
and VIOUTN) swing symmetrically around AGND and should be
maintained with the specified output compliance range of the
AD9714/AD9715/AD9716/AD9717.
Rev. A | Page 48 of 80
–
ADA4899-1
VOUT
+
RS
C
–5V
AVSS 25
07265-060
OPTIONAL RDIFF
07265-059
IOUTP 28
IOUTP 28
Figure 104. Single-Supply Single-Ended Buffer
AD9714/AD9715/AD9716/AD9717
DIFFERENTIAL BUFFERED OUTPUT
USING AN OP AMP
A dual op amp (see the circuit shown in Figure 105) can be used
in a differential version of the single-ended buffer shown in
Figure 104. The same RC network is used to form a one-pole
differential, low-pass filter to isolate the op amp inputs from
the high frequency images produced by the DAC outputs. The
feedback resistors, RFB, determine the differential peak-to-peak
signal swing by the formula
To keep the pin count reasonable, these auxiliary DACs each
share a pin with the corresponding FSADJx resistor. They are,
therefore, usable only when enabled and when that DAC is
operated on its internal full-scale resistors. A simple I-to-V
converter is implemented on chip with selectable shunt resistors
(3.2 kΩ to 16 kΩ) such that if REFIO is set to exactly 1 V, REFIO/2
equals 0.5 V and the following equation describes the no load
output voltage:

1. 5 
 16 k 
VOUT  0.5 V   I DAC 
R S 

VOUT = 2 × RFB × IFS
The maximum and minimum single-ended voltages out of the
amplifier are, respectively,



VCM = VMAX − RFB × IFS
16kΩ
RFB
4kΩ
8kΩ 16kΩ 16kΩ
–
–
+
REFIO
2
ADA4841-2
+
REFIO 34
VOUT
C
Figure 106. AUXDAC Simplified Circuit Diagram
+
RS
The SPI speed limits the update rate of the auxiliary DACs. The
data is inverted such that IAUXDAC is full scale at 0x000 and zero
at 0x1FF, as shown in Figure 107.
ADA4841-2
–
CF
3.0
RFB
OP AMP OUTPUT VOLTAGE vs. CHANGES
IN ROFFSET AND DAC CURRENT IN µA
2.8
07265-061
RB
2.6
ROFFSET = 3.3kΩ
ROFFSET = 4kΩ
ROFFSET = 5.3kΩ
ROFFSET = 8kΩ
ROFFSET = 16kΩ
2.4
Figure 105. Single-Supply Differential Buffer
2.2
2.0
OUTPUT (V)
AUXILIARY DACs
The DACs of the AD9714/AD9715/AD9716/AD9717 feature
two versatile and independent 10-bit auxiliary DACs suitable
for dc offset correction and similar tasks.
1.8
1.6
1.4
1.2
1.0
0.8
Because the AUXDACs are driven through the SPI port, they
should never be used in timing-critical applications, such
as inside analog feedback loops.
0.6
0.4
0.2
0
0
10
20
30
40
50 60 70 80
IAUXDAC (µA)
90
100 110 120 130
07265-045
AVSS 25
IOUTN 29
AUX
PIN
OP AMP
RS
IOUTP 28
(OFS > 4 = 4)
OFS2
OFS1
OFS0
CF
RB
RNG: 00 = > 125µA fS
01 = > 62µA fS
10 = > 31µA fS
11 = > 16µA fS
AUXDAC
[9:0]
The common-mode voltage of the differential output is
determined by the formula
AD9714/AD9715/
AD9716/AD9717
AVDD
RNG0
RNG1
VMIN = VMAX − RFB × IFS
07265-043
 R
VMAX  VREF  1  FB
RB

Figure 106 illustrates the function of all the SPI bits controlling
these DACs with the exception of the QAUXEN (Register 0x0A,
Bit 7) and IAUXEN (Register 0x0C, Bit 7) bits and gating to
prohibit RS < 3.2 kΩ.
Figure 107. AUXDAC Op Amp Output vs. Current, AVDD = 3.3 V, No Load,
AUXDAC 0x1FF to 0x000
Rev. A | Page 49 of 80
AD9714/AD9715/AD9716/AD9717
AD9714/AD9715/
AD9716/AD9717
I OR Q DAC
500Ω
AD9714/AD9715/
AD9716/AD9717
AUX DAC
The auxiliary DACs can be used for local oscillator (LO) cancellation when the DAC output is followed by a quadrature modulator.
This LO feedthrough is caused by the input referred dc offset
voltage of the quadrature modulator (and the DAC output offset
voltage mismatch) and can degrade system performance. Typical
DAC-to-quadrature modulator interfaces are shown in Figure 108
and Figure 109, with the series resistor value chosen to give an
appropriate adjustment range. Figure 108 also shows external
load resistors in use. Often, the input common-mode voltage for
the modulator is much higher than the output compliance range
of the DAC, so that ac coupling or a dc level shift is necessary. If
the required common-mode input voltage on the quadrature
modulator matches that of the DAC, the dc blocking capacitors in
Figure 108 can be removed and the on-chip resistors can be
connected.
MODULATOR
V+
0.1µF
0.1µF
ADL537x
FAMILY
I OR Q
INPUTS
500Ω
50kΩ
CORRECTING FOR NONIDEAL PERFORMANCE OF
QUADRATURE MODULATORS ON THE IF-TO-RF
CONVERSION
DAC-TO-MODULATOR INTERFACING
OPTIONAL
PASSIVE
FILTERING
1kΩ
Figure 109. Simplified DC Coupling to Quadrature Modulator ADL537x
Family or Equivalent Is Enabled By Using Internal Components
When not enabled (QAUXEN or IAUXEN = 0), the respective
DAC output is in open circuit.
AD9714/AD9715/
AD9716/AD9717
I OR Q DAC
OPTIONAL
LOW-PASS
FILTERING
07265-167
Two registers are assigned to each DAC with 10 bits for the actual
DAC current to be generated, a 3-bit offset (and gain) adjustment, a 2-bit current range adjustment, and an enable/disable
bit. Setting the QAUXOFS (Register 0x0A, Bits[4:2]) and
IAUXOFS (Register 0x0C, Bits[4:2]) bits to all 1s disables the
respective op amp and routes the DAC current directly to the
respective FSADJI/AUXI or FSADJQ/AUXQ pins. This is
especially useful when the loads to be driven are beyond the
limited capability of the on-chip amplifier.
QUADRATURE
MODULATOR
I OR Q
INPUTS
Analog quadrature modulators make it very easy to realize
single sideband radios. However, there are several nonideal
aspects of quadrature modulator performance. Among these
analog degradations are gain mismatch and LO feedthrough.
Gain Mismatch
The gain in the real and imaginary signal paths of the quadrature modulator may not be matched perfectly. This leads
to less than optimal image rejection because the cancellation of
the negative frequency image is less than perfect.
LO Feedthrough
The quadrature modulator has a finite dc referred offset, as well
as coupling from its LO port to the signal inputs. These can lead
to a significant spectral spur at the frequency of the quadrature
modulator LO.
The AD9714/AD9715/AD9716/AD9717 have the capability
to correct for both of these analog degradations. However,
understand that these degradations drift over temperature;
therefore, if close to optimal single sideband performance
is desired, a scheme for sensing these degradations over
temperature and correcting them may be necessary.
I/Q-CHANNEL GAIN MATCHING
499Ω
499Ω
5kΩ
TO
100kΩ
07265-166
AD9714/AD9715/
AD9716/AD9717
AUX DAC
Figure 108. Typical Use of Auxiliary DACs and External Components for
Coupling to Quadrature Modulators
Figure 109 shows a greatly simplified circuit that takes full
advantage of the internal components supplied in the DAC. A
low-pass or band-pass passive filter is recommended when
spurious signals from the DAC (distortion and DAC images)
at the quadrature modulator inputs can affect the system
performance. In the example shown in Figure 109, the filter
must be able to pass dc to properly bias the modulator. Placing
the filter at the location shown in Figure 108 and Figure 109
allows easy design of the filter because the source and load impedances can easily be designed close to 500 Ω for a 2 mA full-scale
output. Once the resistance at the modulator inputs is known,
the user can easily look up the range of input offsets that may be
encountered and compute a value for the series resistor on the
AUXDAC output.
Fine gain matching is achieved by adjusting the values in the
DAC fine gain adjustment registers. For the I DAC, these values
are in the I DAC gain register (Register 0x03). For the Q DAC,
these values are in the Q DAC gain register (Register 0x06). These
are 6-bit values that cover ±2% of full scale. To perform gain
compensation starting from the default values of zero, raise the
value of one of these registers a few steps until it can be determined if the amplitude of the unwanted image is increased or
decreased. If the unwanted image increases in amplitude, remove
the step and try the same adjustment on the other DAC control
register. Iterate register changes until the rejection cannot be
improved further. If the fine gain adjustment range is not sufficient
to find a null (that is, the register goes full scale with no null
apparent), adjust the course gain settings of the two DACs
accordingly and try again. Variations on this simple method
are possible.
Rev. A | Page 50 of 80
To achieve LO feedthrough compensation, the user should start
with the default conditions of the AUXDAC registers, and then
increment the magnitude of one or the other AUXDAC output
voltages. While this is being done, the amplitude of the LO
feedthrough at the quadrature modulator output should be
sensed. If the LO feedthrough amplitude increases, try either
decreasing the output voltage of the AUXDAC being adjusted,
or try adjusting the output voltage of the other AUXDAC. It
may take practice before an effective algorithm is achieved. The
AD9714/AD9715/AD9716/AD9717 evaluation board can be
used to adjust the LO feedthrough down to the noise floor,
although this is not stable over temperature.
449.0
450.0
452.5
Figure 110. AD9714/AD9715/AD9716/AD9717 and ADL5370 with a SingleTone Signal at 450 MHz, No Gain or LO Compensation
5
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
447.5
449.0
450.0
FREQUENCY (MHz)
RESULTS OF GAIN AND OFFSET CORRECTION
The results of gain and offset correction can be seen in Figure 110
and Figure 111. Figure 110 shows the output spectrum of the
quadrature demodulator before gain and offset correction.
Figure 111 shows the output spectrum after correction. The
LO feedthrough spur at 450 MHz has been suppressed to the
noise level. This result can be achieved by applying the correction, but the correction must be repeated after a large change in
temperature.
451.0
FREQUENCY (MHz)
(dB)
To achieve LO feedthrough compensation in a circuit, each
output of the two AUXDACs must be connected through a
100 kΩ resistor to one side of the differential DAC output. See
the Auxiliary DACS section for details of how to use AUXDACs.
The purpose of these connections is to drive a very small amount
of current into the nodes at the quadrature modulator inputs,
thereby adding a slight dc bias to one or the other of the
quadrature modulator signal inputs.
07265-064
LO FEEDTHROUGH COMPENSATION
5
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
447.5
451.0
452.5
07265-065
Note that LO feedthrough compensation is independent of
phase compensation. However, gain compensation can affect
the LO compensation because the gain compensation may
change the common-mode level of the signal. The dc offset of
some modulators is common-mode level dependent. Therefore,
it is recommended that the gain adjustment be performed prior
to LO compensation.
(dB)
AD9714/AD9715/AD9716/AD9717
Figure 111. AD9714/AD9715/AD9716/AD9717 and ADL5370 with a SingleTone Signal at 450 MHz, Gain and LO Compensation Optimized
Note that gain matching improves the negative frequency image
rejection, but it is also related to the phase mismatch in the
quadrature modulator. It can be improved by adjusting the
relative phase between the two quadrature signals at the digital
side or properly designing the low-pass filter between the DACs
and quadrature modulators. Phase mismatch is frequency dependent; therefore, routines must be developed to adjust it if
wideband signals are desired.
Rev. A | Page 51 of 80
AD9714/AD9715/AD9716/AD9717
MODIFYING THE EVALUATION BOARD TO
USE THE ADL5370 ON-BOARD QUADRATURE
MODULATOR
To evaluate the ADL5370 on this board, the population of these
same components should be reversed so that they are in the
following positions:
The evaluation board contains an Analog Devices, Inc.,
ADL5370 quadrature modulator. The AD9714/AD9715/
AD9716/AD9717 and the ADL5370 provide an easy-tointerface DAC/modulator combination that can be easily
characterized on the evaluation board. Solderable jumpers
can be configured to evaluate the single-ended or differential
outputs of the AD9714/AD9715/AD9716/AD9717. This setup
is the default configuration from the factory and consists of
the following population of the components:






JP55, JP56, JP76, JP82—soldered
R13, R14, R52, R53—populated
R50, R57, T1, T2—unpopulated
The AUXDAC outputs can be connected to Test Point TP44 and
Test Point TP45 if LO feedthrough compensation is necessary.
JP55, JP56, JP76, JP82—unsoldered
R13, R14, R52, R53—unpopulated
R50, R57, T1, T2—populated
Rev. A | Page 52 of 80
5V
J3
5V
2
1
SMAEDGE
1
2
3
4
U2
U4
U6
U7
5V
RC0603
78.7K
5VIN
R3
NC
FB
OUT6
SD
OUT5
IN4
R29
8
7
6
5
OUT5 5
OUT6 6
FB 7
NC 8
R10
FB 7
NC 8
IN3
5V
RC0603
78.7K
GND
ADP3334
SD
IN4
5V
78.7K
RC0603
R5
NC
FB
OUT5 5
OUT6 6
RC0603
GND
ADP3334
SD
IN4
5V
78.7K
GND
ADP3334
SD
IN3
IN3
1
2
3
OUT6
GND
1
ADP3334
2
3
4
1
2
3
4
5V
5V
5V
5VGND;3,4,5
5VINT
5V
1UF
CC0603
C37
5V
1UF
CC0603
C21
5V
1UF
CC0603
C18
5V
1UF
CC0603
C12
OUT5
IN3
8
7
6
5
CC0603
100PF
100PF
100PF
100PF
JP28
2
1 A B 3
JP88
3.3
1.8
C38
2
1 A B 3
JP29
3.3
1.8
C30
2
A B 3
JP26
3.3
1.8
1
C19
2
1 A B 3
JP22
3.3
1.8
C13
CC0603
CC0603
CC0603
IN4
R32
R36
76.8K
R30
R31
76.8K
R12
C14
C20
RC0603
64.9K
5V
1UF
CC0603
C31
RC0603
64.9K
5V
1UF
1
1
1
JP15
1
C88
5V
1UF
5V
DVDDX_IN
B A
2
1
5V
2
SMAEDGE
J4
2
5V
SMAEDGE
1
J5
5V
1
2
3
4
2
J8
78.7K
5V
RC0603
R4
NC
FB
OUT6
OUT5
CVDDX_IN
SD U11
GND
ADP3334
IN3
IN4
SMAEDGE
1
AVDD_IN
DVDD_IN
CVDD_IN
DVDDX_IN
5VGND;3,4,5
AVDD_IN
B A
2
JP54
5V
2
J2
5VGND;3,4,5
1
SMAEDGE
5VGND;3,4,5
5VGND;3,4,5
DVDD_IN
B A
2
JP10
CVDD_IN
B A
2
CC0603
3
3
3
5VUSB
64.9K
5V
1UF
CC0603
C17
RC0603
64.9K
5V
1UF
CC0603
CC0603
R8
R2
76.8K
R23
76.8K
JP3
RC0603
RC0603
4
RC0603
RC0603
JP6
0.1UF
0.1UF
0.1UF
0.1UF
8
7
6
5
5V
LC1812
100PF
LC1812
L19
EXC-CL4532U1
LC1812
EXC-CL4532U1
L16
LC1812
L12
EXC-CL4532U1
LC1812
EXC-CL4532U1
L4
LC1812
L7
EXC-CL4532U1
LC1812
EXC-CL4532U1
L3
LC1812
L6
EXC-CL4532U1
EXC-CL4532U1
L2
LC1812
EXC-CL4532U1
L5
EXC-CL4532U1
L1
LC1812
2
1 A B 3
JP89
3.3
1.8
C89
C61
CC0603
5V
C15
CC0603
5V
C9
CC0603
5V
C7
CC0603
5V
C3
CC0603
0.1UF
CC0603
Rev. A | Page 53 of 80
RC0603
Figure 112. Power Supplies and Filters
R92
R25
76.8K
ACASE
ACASE
ACASE
ACASE
ACASE
CVDDX_IN
C60
CC0603
0.1UF
C16
CC0603
0.1UF
C8
CC0603
0.1UF
C6
CC0603
0.1UF
C10
CC0603
0.1UF
RC0603
64.9K
1UF
CVDDX
DVDDX
AVDD
DVDD
CVDD
5V
SMAEDGE
J11
5VGND;3,4,5
C
TP23
BLK
TP24
RED
TP9
BLK
TP8
RED
TP6
BLK
TP5
RED
TP4
BLK
TP13
RED
C
TP14
BLK
TP12
RED
2
1
3 B A 1
C86
JP78
2
CC0603
C57
10UF
6.3V
C1
10UF
6.3V
C5
10UF
6.3V
C4
10UF
6.3V
C2
10UF
6.3V
07265-184
3
AD9714/AD9715/AD9716/AD9717
EVALUATION BOARD SHEMATICS AND ARTWORK
SCHEMATICS
6
5
34
36
38
40
33
35
37
39
1IN
DB10X
DB11X
DB7X
DB8X
DB1X
DB0X
DB0X
DB2X
DB1X
DB4X
DB3X
DB3X
DB5X
DB4X
DB2X
DB6X
DB5X
DB6X
DB7X
DB8X
DB9X
DB9X
DB11X
DB12X
DB10X
DB12X
DB13X
DB13X
DIGITAL INPUTS
J1 AND RP3, THE MSB IS DB13, DB11, DB9, OR DB7, DEPENDING ON THE PART.
J11
SSW-120-02-SM-D-R-A
32
30
28
26
24
22
20
18
16
14
12
10
31
29
27
25
23
21
19
17
15
13
11
9
8
4
3
7
2
1
9
10
11
12
13
14
15
8
7
6
5
4
3
2
1
22
16
9
10
11
12
13
14
15
RNETCTS743-8
RP4
RNETCTS743-8
8
7
6
5
4
3
2
RP31
22
1
16
MSB
RP5
DNP
1
16
PCB Bottom Side
HEADER RIGHT ANGLE FEMALE
2
3
2
Rev. A | Page 54 of 80
15
Figure 113. Digital Inputs
TP22
WHT
0
4
8
14
RNETCTS743-8
5
7
9
13
6
10
6
5
11
12
4
12
7
3
13
11
2
14
8
15
9
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
Match length
to path from
S5 to Pin 18
of U1.
No stub
R6
RC0402
RP1
10
16 DNP 1
RNETCTS743-8
TP10
BLK
AD9714/AD9715/AD9716/AD9717
07265-185
Figure 114. Clock Input and DUT
Rev. A | Page 55 of 80
RC0402
C
2
1
C24
CC0603
0.1UF
C26
CC0603
0.1UF
AVDD
C27
CC0603
0.1UF
C
C77
00.1UF
CVDD
R107
DNP
R108
10K
U12
OUT
C 23
CC0603
0.01UF
DVDD
C25
CC0603
0.01UF
C 28
CC0603
0.01UF
OSC-S1703
GND
OVCC
4
TP30
WHT
C39
CC0603
1UF
00.01UF
C78
3
C
C
EN
CC0402
CC0402
QOTC
CLKIN
CVDD
DCLKIO
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DVDDIO
DB8
DB9
DB10
DB11
C
RC0402
RLIN
IOUTN
IOUTP
DB3
DB2
CMLI
DB5
DB4
FSADJI/AUXI
FSADJQ/AUXQ
DB6
REFIO
DVDD
DB7
SCLK/CLKMD
RESET/PINMD
DVSS
DB8
DVDDIO
CS/PWRDN
SDIO/FORMAT
DB9
DB13 (MSB)
C
DB10
0
R68
DNP
DB12
RC0402
THE AD9714/AD9715/AD9716
CAN BE USED IN U1.
DB1
RC0402
21
22
23
JP32
24 JP33
25
S5
RC0402
IOTC
FSADJ2
R71
10K
IOUTA
IOUTB
QOUTB
QOUTA
ACASE
R80
U8
CC0603
TP3
WHT
C11
0.1UF
QOTC
IOTC
DNP
0
DNP
R19
RC0402
R26
RC0402
R21
RC0402
R20
RC0402
1
0
2
3
DGND;5
R18
49.9
DVDD
4
10K
C55
C56
1NF
QOT_CML
IOT_CML
DGND;3,4,5
S11
CC0402
00.1UF
R17
DNP
CC0402
R72
JP11
RC0402
SW1
0
C59
4.7UF
6.3V
REFIO
SN74LVC1G34DCK
DGND;3
DVDDX;5
2
4
RC0402
DNP
AVDD
DVDDX
DVDDX
R70
10K
RMODE-SCLK
MODE-SDIO
SLEEP-CSB
DB13
DB12
0
FSADJ1
DNP
26 JP34
27
28
29
R67
C
RC0402
R69
30 JP35
31
32
33
34
35
36
37
38
39
40
RC0402
CGND;3,4,5
OUT0R
R65
R66
DNP TP26
WHT
DNP R110
0
DB11
0
0
RC0402
40-LEAD LFCSP
RLIP
AD9717
15
AVDD
DB0 (LSB)
16
AVSS
DCLKIO
17
RLQP
CVDD
18
QOUTP
CLKIN
AGND;41
19
QOUTN
CVSS
20
RLQN
CMLQ
U1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RC0402
R47
RC0402
R46
R48
00.1UF
Keep parallel
C
C101
C34
R34
0
RC0402
0 R64
TP25
WHT
00.1UF
DNP R122
DCLKIO
RC0402
R33
CC0402
CC0402
CVDDX
OUT2R
0
RC0402
CLKIN
RC0603
R7
RC0402
RC0402
= SHARE COMPONENT PAD.
AD9714/AD9715/AD9716/AD9717
07265-186
FSADJ1
32K
0.1%
R1
TP1
WHT
IOT_CML
RC0805
RC0805
8K
0.1%
R51
R22
DNP
R99
100K
TP34
WHT
JP90
R97
DNP
S9
REFIO
IOUT NETWORK AND FSADJ1
RC0603
100K
OPAMPIN
R35
RC0402
R117 0
R94
T2
C107
3
2
RC0603
6
4
CC0603
0.1UF
RC0402
RC0402
0
S
ADTL1-12
P
R115 499
R116 0
WHT
TP44
1
3
R93
RC0603
0
RC0603
1
N5V
4
C108
5 DNP
AGND;9
0.1UF
0.1UF
RC0402
C106
FB
ADA4899-1
OUT
U13
-V2
6
-V1
+IN
7 8
+V
-IN DIS
P5V
N5V
R123
0-DNP
R79
0
R37
DNP
1UF 1
P5V
S12
TP41
BLK
2 AGND;3,4,5
DNP
C104
10UF
10V
S4
AGND;3,4,5
S3
AGND;3,4,5
R9
DNP
TP39
RED
ACASE
RC0603
CERAMIC
C105
0
RC0603
10V
10UF
C103
TP40
ORG
ACASE
RC0603
RC0402
R114 15
RC0603
3
4
R119
2
5
ADT9-1T
DNP
R118
T8
P 1
6 S
0.2NF
R113 499
C102
R15
0-DNP
TP31
WHT
RC0603
DNP
R11
RC0603
RC0603
OPAMPIN
R111
10-DNP
R57
453
RC0603
AGND;3,4,5
DNP
RC0603
WHEN C95 IS NOT
DNP, 10pF TO 1nF IS RECOMMENDED
C95
CC0603
DNP
R98
DNP
WHEN R13 AND R14 ARE NOT
DNP, 499 IS RECOMMENDED
FSADJ resistors must have low TC
16K
0.1%
R49
CC0603
C22
0.1UF
R13
DNP
R14
DNP
RC0603
IOUTB
TP33
DNP
D1N
JP56
RC0603
IOUTA
JP7
ERA6YEB323V, ERA6Y
JP8
ERA6YEB323V, ERA6Y
RC0603
JP9
ERA6YEB323V, ERA6Y
TP32
DNP
D1P
JP12
RC0603
Rev. A | Page 56 of 80
CC0402
Figure 115. IOUT Network and FSADJ1
CC0603
RC0603
RC0805
CC0603
RC0603
CC0805
JP55
AD9714/AD9715/AD9716/AD9717
07265-187
FSADJ2
QOT_CML
QOUTB
TP17
WHT
CC0603
RC0603
32K
0.1%
R58
C48
0.1UF
R52
DNP
R54
DNP
JP82
RC0603
8K
0.1%
R60
RC0805
RC0805
RC0805
R102
100K
TP35
WHT
DNP
R101
DNP
TP37
DNP
C96
CC0603
RC0603
FSADJ resistors must have low TC
16K
0.1%
R59
JP91
WHEN R52 AND R53 ARE NOT
DNP, 499 IS RECOMMENDED
R53
DNP
JP20
QOUTA
RC0603
JP21
ERA6YEB323V, ERA6Y
RC0603
JP16
ERA6YEB323V, ERA6Y
Rev. A | Page 57 of 80
ERA6YEB323V, ERA6Y
Figure 116. QOUT Network and FSADJ2
RC0603
D2N
D2P
JP77
TP36
DNP
RC0603
JP76
2
R55
S10
AGND;3,4,5
DNP
RC0603
RC0603
100k
3
1
RC0603
QOUT NETWORK AND FSADJ2
WHT
TP45
R106 0
4
6
RC0603
S
0
ADTL1-12
P
T1
R105
WHEN R112 IS NOT DNP,
10 IS RECOMMENDED
WHEN C96 IS NOT DNP,
10pF TO 1nF IS RECOMMENDED
R100
DNP
RC0603
1
R50
453
R112
DNP
R16
0
TP38
WHT
R121
RC0603
DNP
2
P 1
5
6 S
3
4
T5
ADT9-1T
RC0603
R120 DNP
0
R124
R83
R38
0
RC0603
RC0603
0
RC0603
RC0603
OPAMPIN
R56
DNP
S8
AGND;3,4,5
R42
DNP
S6
AGND;3,4,5
AD9714/AD9715/AD9716/AD9717
07265-188
RC0603
RC0603
MLX-0532610571
Figure 117. SPI Port
Rev. A | Page 58 of 80
0
0
R82
5V
RC0402
R62
RC0402
SLEEP-CSB
RMODE-SCLK
MODE-SDIO
MODE-SDO
P3
pcb bottom side
MP2
5
4
3
2
1
MP1
R39
R40
22
22
22RC0402 R41
R28
22
DVDDX
C114
CC0603
0.1UF
5VUSB
0.1UF
8
10
9
11
12
13
14
C109
CC0603
0.1UF
22 RA3-AN3-VREF+
20 RA1-AN1
21 RA2-AN2-VREF-
18 MCLR-VPP-RE3
19 RA0-AN0
16 RB6-KBI2-PGC
17 RB7-KBI3-PGD
14 RB4-AN11-KBI0
15 RB5-KBI1-PGM
13
MOSI
MISO
EN1
SSEL1
SCK
U3
N31C
5VGND;45
5VUSB
11 RB2-AN8-INT2-VMO
12 RB3-AN9-VPO
9 RB0-AN12-INT0
10 RB1-AN10-INT1
7 AVDD1
8 VDD1
5 RD7
6 VSS1
3 RD5
4 RD6
1 RC7-RX-DT
2 RD4
1 VCCA
VCCY
2
Y1
A1
3
U5
Y2
A2
4
A3 ADG3304 Y3
5
Y4
A4
6
NCY
NCA
7
GND
EN
C100
CC0603
RA0
SSEL2
SSEL1
SCK
MISO
5VUSB
EN2
EN1
MOSI
RC2-CCP1
VUSB
RD0
RD1
RD2
RD3
RC4-D--VM
RC5-D+-VP
CSB
SCLK
SDIO
TP20
WHT
TP19
WHT
TP18
WHT
DVDD
RA4-T0CKI-RCV
RA5-AN4-HLVDIN
RE0-AN5
RE1-AN6
RE2-AN7
AVDD2
VDD2
AVSS
VSS2
OSC1-CLK1
OSC2-CLKO-RA6
22
22
22
RC0402
RC0402 R45
R44
R103
0
RC0402
RC1206
R87
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
470NF
A2
A1
VCCA
3
U14
C112
Y2 12
Y3 11
VCCY 14
Y1 13
5V
5
5V
EN2
SSEL2
SCK
MOSI
MISO
MISO
C33
R43
RC0402
0
5VUSB
10PF-1%
CC0603
0.1UF
CC0603
TP7
BLK
5V
C49
CC0603
5VGND;2
10PF-1%
CC0603
R27
Y1
20.000MHZ
1M
D1
1 LNJ312G8TRA
2
2
pcb Top side
VBUS
D-
D+
ID-X
GND-4
RC0403
R63
P1
S3
A3 ADG3304
Y4 10
A4
6
9
NCA
7
GND
EN 8
4
3
2
1
C111
CC0603
0.1UF
TP2
DNP
C110
CC0603
S1
499
1
41
4
5
2
5VUSB
5V
EXC-CL3225U1
L15
3
C84
5VUSB
0.1UF
CC0603
42
43
44
C97
RC6-TX-CK
C98
0.1UF
CC0603
RC0-TIOSO-T1CKI
C99
0.1UF
CC0603
RC1-T1OSI-UOE
0.1UF
CC0603
PIC18F4450
C32
10UF
6.3V
GRN
5VUSB
MOSI
AD9714/AD9715/AD9716/AD9717
07265-189
L14
Rev. A | Page 59 of 80
Figure 118. Modulated Output
L18
7.5PF
DNP
C93
CC0805
DNP
C94
3
1
RC0603
R78
4
6
RC0603
R75
RC0603
ADTL1-12
0
4
R74
P NC=2,5 S
T3
0
0
ADTL1-12
P NC=2,5 S
6
10UF
10V
100PF
C50
CC0402
J6
ETC1-1-13
VDDM_IN
2
1
SMAEDGE
AGND;3,4,5
CC0402
0.1UF
C47
CC0402
CC0402
RED
TP16
BLK
TP21
4
MODULATED OUTPUT
MOD_QP
ACASE
VDDM
C43
MOD_QN
MOD_IN
MOD_IP
P
4.7PF
LC1008
LC1008
DNP
R73
RC0603
T4
C64
CC0805
1.8UH
C75
L20
CC0805
DNP
C91
3
1
T6
S
C65
CC0805
LC1008
LC1008
1.8UH
CC0805
7.5PF
DNP
CC0805
DNP
DNP
C92
CC0805
1
L9
C74
L8
CC0805
4.7PF
C79
LC1008
7.5PF
CC0805
1.8UH
4.7PF
LC1008
LC1008
C80
CC0805
L11
LC1008
1.8UH
C82
L17
CC0805
3
D2P
D2N
D1P
D1N
C81
L10
CC0805
R24
R61
0
C53
DNP
100PF
7.5PF
100PF
RC0603
1k
RC0603
1k
QBBN
COM4B
COM4A
IBBN
IBBP
VPS5
VPS1A
VPS1B
VPS1C
VPS1D
COM2A
VOUT
AGND;25
COM3B
C35
22UF
16V
VPS2A
COM3A
LC1812
L13
2
1
13
14
15
16
17
18
19
20
21
22
23
24
CC0402
C36
CC0402
0.1UF EXC-CL4532U1
J7
SMAEDGE
AGND;3,4,5
VPS2B
COM2B
LOIP ADL5370 VPS4
LOIN
VPS3
U9
QBBP
COM1B
DNP
MOD_QP
MOD_QN
COM1A
ACASE
12
11
10
9
8
7
6
5
4
3
2
1
MOD_IP
MOD_IN
C73
C54
2
100PF
4.7PF
C29
CC0402
0.1UF
BLK
TP43
VDDM
RED
TP42
100PF
CC0402
C51
C90
VDDM
VDDM
10UF
10V
C41
ACASE
10UF
10V
C44
ACASE
0.1UF
CC0402
100PF
CC0402
C63
100PF
C87
100PF
CC0402
0.1UF
0.1UF
C83
CC0402
C72
CC0402
C52
CC0402
VDDM
AD9714/AD9715/AD9716/AD9717
5
07265-190
J10
C
RC0805
CGND;3,4,5
C
C
C
CVDDX
R91
49.9
4
S 6
5
1
R77
CGND;5
3
4
RC0402
SW2
1.8K
JTX-4-10T+
1:4
2
3
1 P
2
T9
1.8K
HSMS-281C
C62
C
CC0402
D3
RA0
1NF
RC0402
R76
1
3
2
C46
C45
0
0.1UF
RC0402
R86
0.1UF
CC0402
CC0402
C
CLOCK DRIVER CHIP
CVDDX
CVDDX
CVDDX
SLEEP-CSB
MODE-SDO
MODE-SDIO
RMODE-SCLK
CVDDX
CVDDX
CVDDX
CVDDX
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
GND3
VS13
FUNC
STATUS
VS7
GND2
Figure 119. Clock Driver Chip
Rev. A | Page 60 of 80
CC0402
CC0402
CC0402
C113
0.1UF
C69
0.1UF
C42
0.1UF
CC0402
CC0402
CC0402
VS8
OUT1B
OUT1
VS9
VS6
VS10
C
OUT4
OUT4B
OUT2
U10
CGND;49
VS11
VS12
OUT3B
OUT2B
GND1
VS5
CSB
SDO
SDIO
AD9512BCPZ
GND4
CLK1B
OUT3
VS14
SCLK
VS15
CLK1
CLK2B
VS4
OUT0
OUT0B
CLK2
VS16
GND5
NC1
VS3
RSET
VS2
GND6
VS17
DSYNCB
VS1
VS18
DSYNC
C85
0.1UF
C70
0.1UF
C66
0.1UF
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
C
CC0402
CC0402
CC0402
C58
0.1UF
C71
0.1UF
C67
0.1UF
CVDDX
CVDDX
CVDDX
CVDDX
CVDDX
CVDDX
CVDDX
CVDDX
CVDDX
CVDDX
CVDDX
CC0402
CC0402
CC0402
0
0
R81
C
RC0402
C40
0.1UF
C76
0.1UF
C68
0.1UF
CVDDX
C
C
RC0402
DNP R109
OUT2R
RC0402
OUT0R
DNP R90
WHEN R90 AND R109
ARE NOT DNP, 49.9
IS RECOMMENDED
RC0402
R89
RC0402
R88
4.12K
07265-191
1
AD9714/AD9715/AD9716/AD9717
AD9714/AD9715/AD9716/AD9717
07265-203
SILKSCREENS
Figure 120. Layer 2, Ground Plane
Rev. A | Page 61 of 80
07265-204
AD9714/AD9715/AD9716/AD9717
Figure 121. Layer 3, Power Plane
Rev. A | Page 62 of 80
07265-205
AD9714/AD9715/AD9716/AD9717
Figure 122. Assembly—Primary Side
Rev. A | Page 63 of 80
07265-206
AD9714/AD9715/AD9716/AD9717
Figure 123. Assembly—Secondary Side
Rev. A | Page 64 of 80
07265-217
AD9714/AD9715/AD9716/AD9717
Figure 124. Solder Mask—Primary Side with Socket
Rev. A | Page 65 of 80
07265-207
AD9714/AD9715/AD9716/AD9717
Figure 125. Solder Mask—Secondary Side
Rev. A | Page 66 of 80
07265-208
AD9714/AD9715/AD9716/AD9717
Figure 126. Hard Gold Plated with Bumps and Socket
Rev. A | Page 67 of 80
07265-209
AD9714/AD9715/AD9716/AD9717
Figure 127. Primary Side Paste
Rev. A | Page 68 of 80
07265-210
AD9714/AD9715/AD9716/AD9717
Figure 128. Secondary Side Paste
Rev. A | Page 69 of 80
07265-211
AD9714/AD9715/AD9716/AD9717
Figure 129. Silkscreen—Primary Side
Rev. A | Page 70 of 80
07265-212
AD9714/AD9715/AD9716/AD9717
Figure 130. Silkscreen—Secondary Side
Rev. A | Page 71 of 80
07265-213
AD9714/AD9715/AD9716/AD9717
Figure 131. Layer 1—Primary Side
Rev. A | Page 72 of 80
07265-214
AD9714/AD9715/AD9716/AD9717
Figure 132. Layer 4—Secondary Side
Rev. A | Page 73 of 80
07265-215
AD9714/AD9715/AD9716/AD9717
Figure 133. Immersion Gold, No Socket, No Bumps
Rev. A | Page 74 of 80
07265-216
AD9714/AD9715/AD9716/AD9717
Figure 134. Solder Mask—Primary Side, No Socket
Rev. A | Page 75 of 80
AD9714/AD9715/AD9716/AD9717
BILL OF MATERIALS
Table 18.
Qty
6
17
4
2
1
2
1
1
1
1
1
Reference Designator
C1, C2, C4, C5, C32, C57
C3, C6, C7, C8, C9, C10, C11,
C15, C16, C22, C24, C26,
C27, C48, C60, C61, C107
C12, C14, C17, C18, C20,
C21, C31, C37, C39, C86, C88
C13, C19, C30, C38, C89
C23, C25, C28
C29, C36, C47, C52, C72, C90
C33, C49
C34, C40, C42, C45, C46,
C55, C58, C66, C67, C68,
C69, C70, C71, C76, C77,
C85, C101, C113
C35
C41, C43, C44
C50, C51, C53, C54, C63,
C73, C83, C87
C56, C62
C59
C64, C75, C79, C82
C65, C74, C80, C81
C78
C84, C97, C98, C99, C100,
C106, C108, C109, C111,
C112, C114
C91, C92, C93, C94
C95, C96
C102
C103, C104
C105
C110
D1
D3
J1
6
J2, J3, J4, J5, J8, J11
CC0805
CC0603
CC0402
CAPSMDA
CC0805
CC0603
Panasonic LNJ312G8TRA
HSMS-281C
Samtec
SSW-120-02-SM-D-RA
SMAEDGE
2
J6, J7
SMAEDGE
SMAEDGE
5
J10, S3, S5, S6, S11
SMAUPA04
SMA200UP
5
11
S4, S8, S9, S10, S12
JP3, JP7, JP8, JP9, JP11, JP12,
JP16, JP20, JP21, JP28, JP77
JP6, JP10, JP15, JP22, JP26,
JP29, JP54, JP78, JP88, JP89
JP32, JP33, JP34, JP35, JP55,
JP56, JP76, JP82, JP90, JP91
SMAUPA04
JPRBLK02
SMA200UP
JPRBLK02
DNP
DNP
0.2 nF capacitor
10 μF, 10 V capacitor
1 μF ceramic capacitor
470 nF capacitor
LED-SMD-TSS-GRN
HSMS-281C
40-pin right angle
header female
DNP SMA connector
edge right angle
SMA connector
edge right angle
SMA connector RF
5-pin upright
DNP
2-pin jumper header
JPRBLK03
JPRBLK03
3-pin jumper header
JPRSLD02
JPRSLD02
Solder jumper
11
5
3
6
2
18
1
3
8
2
1
4
4
1
11
10
10
Device
CAPSMDA
CC0603
Package
ACASE
CC0603
Description
10 μF, 6.3 V capacitor
0.1 μF capacitor
CC0603
CC0603
1 μF capacitor
CC0603
CC0603
CC0402
CC0603
CC0402
CC0603
CC0603
CC0402
CC0603
CC0402
100 pF capacitor
0.01 μF capacitor
0.1 μF capacitor
10 pF, 1% capacitor
0.1 μF capacitor
CAPSMDA
CAPSMDB
CC0402
ACASE
ACASE
CC0402
22 μF,16 V capacitor
10 μF, 10 V capacitor
100 pF capacitor
CC0402
CAPSMDA
CC0805
CC0805
CC0402
CC0603
CC0402
ACASE
CC0805
CC0805
CC0402
CC0603
1 nF capacitor
4.7 μF, 6.3 V capacitor
7.5 pF, 1% capacitor
4.7 pF, 1% capacitor
0.01 μF capacitor
0.1 μF capacitor
CC0805
CC0603
CC0402
ACASE
CC0805
CC0603
1.6 mm x 0.8 mm
SOT323-3
40-pin through
hole
SMAEDGE
Rev. A | Page 76 of 80
Part No./
Manufacturer
LNJ312G8TRA
HSMS-281C
SSW-120-02-SM-D-RA/
Samtec
AD9714/AD9715/AD9716/AD9717
Qty
11
Device
IND1812
Package
LC1812
Description
EXC-CL4532U1
4
4
1
1
1
Reference Designator
L1, L2, L3, L4, L5, L6, L7,
L12, L13, L16, L19
L8, L9, L10, L11
L14, L17, L18, L20
L15
P1
P3
IND1008
IND1008
IND1210
USB-MINIB
Molex 0532610571
LC1008
LC1008
LC1210
USB-MINIB
Molex 0532610571
2
R1, R58
RC0805
RC0805
1.8 μH, 10%
DNP
EXC-CL3225U1
USB mini 5-pin
1.25 mm, 5-pin wireto-board connector
32 kΩ, 0.1% resistor
5
5
6
7
RC0603
RC0603
RC0402
RC0402
RC0603
RC0603
RC0402
RC0402
76.8 kΩ resistor
78.7 kΩ resistor
0 Ω resistor
DNP
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
10 kΩ resistor
64.9 kΩ resistor
DNP
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
0 Ω resistor
DNP
0 Ω resistor
RC0603
RC0603
DNP
RC0402
RC0402
RC0402
RC0603
RC0603
RC0402
RC0402
RC0402
RC0402
RC0603
RC0603
RC0402
49.9 Ω resistor
0 Ω resistor
DNP
1 kΩ resistor
1 MΩ resistor
22 Ω resistor
RC0603
RC0402
RC0402
RC0603
RC0402
RC0402
100 kΩ resistor
0 Ω resistor
0 Ω resistor
2
R2, R23, R25, R31, R36
R3, R4, R5, R10, R29
R6, R33, R34, R64, R65, R67
R17, R66, R68, R69, R107,
R110, R122
R7
R8, R12, R30, R32, R92
R9, R37, R42, R56, R97, R98,
R100, R101
R11, R38, R79, R83
R13, R14, R52, R53
R15, R16, R123, R124,
R73 to R75, R78, R93, R94,
R105, R106
R22, R54, R118, R119,
R120, R121
R18
R19, R21
R20 , R26, R80
R24, R61
R27
R28, R39, R40, R41, R44,
R45, R103
R35, R55, R99, R102
R43
R46, R47, R48, R62, R82,
R86, R116, R117
R49, R59
RC0805
RC0805
16 kΩ, 0.1% resistor
2
2
R50, R57
R51, R60
RC0603
RC0805
RC0603
RC0805
453 Ω resistor
8 kΩ, 0.1% resistor
3
3
1
2
1
1
2
2
1
2
1
2
R63, R113, R115
R70, R71, R108
R72
R76, R77
R81
R87
R88, R89
R90, R109
R91
R111, R112
R114
RP1, RP5
RC0402
RC0402
RC0402
RC0402
RC0402
RC1206
RC0402
RC0402
RC0805
RC0603
RC0402
RNETCTS743-8
RC0402
RC0402
RC0402
RC0402
RC0402
RC1206
RC0402
RC0402
RC0805
RC0603
RC0402
RNETCTS743-8
499 Ω resistor
10 kΩ resistor
25 Ω resistor
1.8 kΩ resistor
4.12 kΩ resistor
0 Ω resistor
0 Ω resistor
DNP
49.9 Ω resistor
DNP
15 Ω resistor
DNP
1
5
8
4
4
10
6
1
2
3
2
1
7
4
1
8
Rev. A | Page 77 of 80
Part No./
Manufacturer
EXC-CL4532U1
EXC-CL3225U1
0532610571/
Molex
ERA6YEB323V,
ERA6Y
ERA6YEB323V,
ERA6Y
ERA6YEB323V,
ERA6Y
AD9714/AD9715/AD9716/AD9717
Qty
2
2
4
1
Reference Designator
RP3, RP4
SW1, SW2
T1, T2, T3, T6
T4
Device
RNETCTS743-8
KEYBDSWG
ADTL1-12
ETC1-1-13
Package
RNETCTS743-8
OMRONB3SG
MINI_CD542
SM-22
Description
22 Ω resistor
B3S-1100 push-button
DNP
M/A COM ETC1-1-13
2
T5, T8
ADT9-1T
MINI_CD542
ADT9-1T
1
T9
JTX-4-10T
MINI_BH292
JTX-4-10T+
16
LOOPMINI
LOOPMINI
White test point
LOOPMINI
LOOPMINI
LOOPMINI
LOOPMINI
DNP
Red test point
LOOPMINI
LOOPMINI
LOOPMINI
LOOPMINI
DNP
Black test point
1
1
TP1, TP3, TP17, TP18,
TP19, TP20, TP22, TP25,
TP26, TP30, TP31, TP34,
TP35, TP38, TP44, TP45
TP32, TP33, TP36, TP37
TP5, TP8, TP12, TP13,
TP16, TP24, TP39, TP42
TP2
TP4, TP6, TP7, TP9, TP10,
TP11, TP14, TP15, TP21,
TP23, TP41, TP43
TP40
U1
LOOPMINI
40-lead LFCSP, AD9717
LOOPMINI
LFCSP040-CP1
5
U2, U4, U6, U7, U11
ADP3334
8-lead SOIC
1
U3
USB-PIC18F4550-I/ML-ND
QFN044P65MM-EP1
2
U5, U14
ADG3304BRUZ
14-lead TSSOP
1
U8
74LVC1G34
SC70-05
1
U9
ADL5370
LFCSP024P5MM-EP1
Orange test point
40-lead LFCSP,
AD9717
ADP3334 voltage
regulator
PIC18F4550,
microchip USB
port chip
QFN44 8X8MM
ADG3304,
14-lead TSSOP
SN74LVC1G34DCK,
TI buffer
ADL5370ACPZ
1
U10
AD9512
LFCSP048-CP1
AD9512BCPZ
1
1
U12
U13
OSC-S1703
8-lead SOIC, ADA4899-1
OSC-S1703
SOIC8-N-EP
DNP
Op amp, ADA4899-1
1
Y1
ABM3B-20.000MHZ-10-1-U-T
SMD 3.2 mm × 5.0 mm
20 MHz
4
8
1
12
Rev. A | Page 78 of 80
Part No./
Manufacturer
ETC1-1-13/
M/A-COM
ADT9-1T/
Mini-Circuits
JTX-4-10T/
Mini-Circuits
AD9717/
Analog Devices
ADP3334/
Analog Devices
PIC18F4550
ADG3304BRUZ/
Analog Devices
TI-DCK =
SC70_05 PKG
ADL5370ACPZ/
Analog Devices
AD9512BCPZ/
Analog Devices
ADA4899-1/
Analog Devices
300-8214-1-ND/
Digi-Key
AD9714/AD9715/AD9716/AD9717
OUTLINE DIMENSIONS
6.00
BSC SQ
0.60 MAX
0.60 MAX
TOP
VIEW
0.50
BSC
5.75
BSC SQ
0.50
0.40
0.30
12° MAX
0.80 MAX
0.65 TYP
0.30
0.23
0.18
1
4.25
4.10 SQ
3.95
EXPOSED
PAD
(BOT TOM VIEW)
21
20
11
10
0.25 MIN
4.50
REF
0.05 MAX
0.02 NOM
SEATING
PLANE
40
0.20 REF
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
072108-A
PIN 1
INDICATOR
1.00
0.85
0.80
PIN 1
INDICATOR
31
30
Figure 135. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9714BCPZ1
AD9714BCPZRL71
AD9715BCPZ1
AD9715BCPZRL71
AD9716BCPZ1
AD9716BCPZRL71
AD9717BCPZ1
AD9717BCPZRL71
AD9714-EBZ1
AD9715-EBZ1
AD9716-EBZ1
AD9717-EBZ1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
Rev. A | Page 79 of 80
Package Option
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
AD9714/AD9715/AD9716/AD9717
NOTES
©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07265-0-3/09(A)
Rev. A | Page 80 of 80