Version 2.0, 8 May 2006 CoolSET™-F3 ICE3 B03 6 5 L ICE3 A10 6 5 L ICE3 A15 6 5 L Off-Line SMPS Current Mode Controller with integrated 650V Startup Cell/Depletion CoolMOS™ and Latched off Mode Power Management & Supply N e v e r s t o p t h i n k i n g . CoolSET™-F3 ICE3xxx65L Revision History: 2006-05-08 Datasheet Previous Version: 1.0 ( ICE3A1065L/ICE3A1565L ), 1.2 ( ICE3B0365L ) Page Subjects (major changes since last revision) Group ICE3B0365L, ICE3A1065L and ICE3A1565L together 11, 12, 13 Revise typo to trigger level at FB ( C5 ) 15 Revise pulse drain current 20 Add temperature derating curve 3, 23 Add marking 25 Add PCB layout recommendation For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http:// www.infineon.com CoolMOS™, CoolSET™ are trademarks of Infineon Technologies AG. Edition 2006-05-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München © Infineon Technologies AG 1999. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. CoolSET™-F3 ICE3xxx65L Off-Line SMPS Current Mode Controller with integrated 650V Startup Cell/Depletion CoolMOS™ and Latched off Mode Product Highlights • Active Burst Mode to reach the lowest Standby Power Requirements < 100mW • Latched Off Mode and Auto Restart Mode to increase robustness and safety of the system • Adjustable Blanking Window for high load jumps to increase system reliability • Pb-free lead plating DIP package; RoHS compilant PG-DIP-8-6 test Features Description • The new generation CoolSET™-F3 Controller provides Active Burst Mode to reach the lowest Standby Power Requirements <100mW at no load. As the controller is always active during Active Burst Mode, there is an immediate response on load jumps without any black out in the SMPS. In Active Burst Mode the ripple of the output voltage can be reduced <1%. Furthermore, to increase the robustness and safety of the system, the device enters into Latched Off Mode in the cases of Overtemperature, Overvoltage or Short Winding. The Latched Off Mode can only be reset by disconnecting the main line. Auto Restart Mode is entered for cases like open loop or overload. By means of an internal precise peak current limitation, the dimension of the transformer and the secondary diode can be lowered which leads to more cost efficiency. An adjustable blanking window prevents the IC from entering Auto Restart Mode or Active Burst Mode unintentionally in case of high load jumps. • • • • • • • • • • • • • • • 650V avalanche rugged CoolMOS™ with built in switchable Startup Cell Active Burst Mode for lowest Standby Power @ light load controlled by Feedback Signal Fast load jump response in Active Burst Mode 67/100kHz internally fixed switching frequency Latched Off Mode for Overtemperature Detection Latched Off Mode for Overvoltage Detection Latched Off Mode for Short Winding Detection Auto Restart Mode for Overload and Open Loop Auto Restart Mode for VCC Undervoltage Blanking Window for short duration high current User defined Soft Start Minimum of external components required Max Duty Cycle 72% Overall tolerance of Current Limiting < ±5% Internal PWM Leading Edge Blanking Soft driving for low EMI Typical Application + CBulk 85 ... 270 VAC Converter DC Output Snubber - CVCC VCC Drain Startup Cell Power Management PWM Controller Current Mode CoolMOS™ Precise Low Tolerance Peak Current Limitation GND Control Unit CS RSense FB Active Burst Mode Latched Off Mode SoftS Auto Restart Mode CoolSET™-F3 with Latch off Mode Type Package Marking VDS FOSC ICE3B0365L ICE3A1065L ICE3A1565L PG-DIP-8-6 PG-DIP-8-6 PG-DIP-8-6 ICE3B0365L ICE3A1065L ICE3A1565L 650V 650V 650V 67KHz 100kHz 100KHz CSoftS RDSon1) 6.45 2.95 1.70 1) typ @ T=25°C 2) Calculated maximum input power rating at Ta=75°C, Tj=125°C and without copper area as heat sink. Version 2.0 3 230VAC ±15%2) 85-265 VAC2) 22W 32W 42W 10W 16W 20W 8 May 2006 CoolSET™-F3 ICE3xxx65L Table of Contents Page 1 1.1 1.2 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Configuration with PG-DIP-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.6.2.1 3.6.2.2 3.6.2.3 3.6.3 3.6.3.1 3.6.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Adjustable Blanking Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Latched Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Auto Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 CoolMOS™ Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5 Temperature derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 6 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 7 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 8 Schematic for recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . .25 Version 2.0 4 8 May 2006 CoolSET™-F3 ICE3xxx65L Pin Configuration and Functionality 1 Pin Configuration and Functionality 1.1 Pin Configuration with PG-DIP-8-6 Pin Symbol Function 1 SoftS Soft-Start 2 FB Feedback 3 CS Current Sense/ 650V1) Depl. CoolMOS™ Source 4 Drain 650V1) Depl. CoolMOS™ Drain 5 Drain 650V1) Depl. CoolMOS™ Drain 6 n.c. Not Connected 7 VCC Controller Supply Voltage 8 GND Controller Ground 1) 1.2 SoftS (Soft Start & Auto Restart Control) The SoftS pin combines the functions of Soft Start during Start Up and error detection for Auto Restart Mode. These functions are implemented and can be adjusted by means of an external capacitor at SoftS to ground. This capacitor also provides an adjustable blanking window for high load jumps, before the IC enters into Auto Restart Mode. FB (Feedback) The information about the regulation is provided by the FB Pin to the internal Protection Unit and to the internal PWM-Comparator to control the duty cycle. The FBSignal controls in case of light load the Active Burst Mode of the controller. at Tj = 110°C CS (Current Sense) The Current Sense pin senses the voltage developed on the series resistor inserted in the source of the integrated Depl. CoolMOS™. If CS reaches the internal threshold of the Current Limit Comparator, the Driver output is immediately switched off. Furthermore the current information is provided for the PWMComparator to realize the Current Mode. Package PG-DIP-8-6 SoftS 1 8 GND FB 2 7 VCC CS 3 6 n.c. Drain Figure 1 Note: 4 5 Pin Functionality Drain (Drain of integrated Depl. CoolMOS™) Pin Drain is the connection to the Drain of the internal Depl. CoolMOSTM. VCC (Power supply) The VCC pin is the positive supply of the IC. The operating range is between 8.5V and 21V. GND (Ground) The GND pin is the ground of the controller. Drain Pin Configuration PG-DIP-8-6(top view) Pin 4 and 5 are shorted within the DIP 8 package. Version 2.0 5 8 May 2006 Figure 2 Version 2.0 FB CSoftS SoftS 85 ... 270 VAC 6 3.4V 4.0V 1.30V 4.8V 5.4V 4.0V 21V VCC C6b C6a C5 C4 C3 C2 C1 T1 T2 3.25kΩ 1 G2 & G1 T3 1 G3 G5 & Tj >140°C & G6 & G11 Active Burst Mode Auto Restart Mode Latched Off Mode Power-Down Reset Latched Off Mode Reset VVCC < 6V Thermal Shutdown Spike Blanking 8.0us 1V Internal Bias Power Management ICE3xxxxxL / CoolSET™-F3 with Latched off Mode Control Unit 10pF 5kΩ RFB 6.5V S1 4.4V 5kΩ RSoftS 6.5V CBulk 15V 6.5V & G7 Current Mode x3.7 C8 PWM Comparator PWM OP 0.85V C7 Soft Start Soft-Start Comparator 8.5V Undervoltage Lockout Voltage Reference C11 1 G8 0.72 & G10 C12 C10 1pF & G9 Gate Driver D1 10kΩ CoolMOS™ Current Limiting Vcsth Leading Edge Blanking 220ns 1.66V FF1 S R Q Drain Startup Cell PWM Section CVCC 0.257V Propagation-Delay Compensation Spike Blanking 190ns Clock Duty Cycle max Oscillator VCC Snubber CS RSense GND + 2 Converter DC Outpu VOUT - CoolSET™-F3 ICE3xxx65L Representative Blockdiagram Representative Blockdiagram Representative Blockdiagram 8 May 2006 CoolSET™-F3 ICE3xxx65L Functional Description 3 Functional Description All values which are used in the functional description are typical values. For calculating the worst cases the min/max values which can be found in section 4 Electrical Characteristics have to be considered. power limitation can be avoided together with the integrated Propagation Delay Compensation. Therefore the maximum power is nearly independent on the input voltage which is required for wide range SMPS. There is no need for an extra over-sizing of the SMPS, e.g. the transformer or the secondary diode. 3.1 3.2 Introduction Drain CoolSET™-F3 is the further development of the CoolSET™-F2 to meet the requirements for the lowest Standby Power at minimum load and no load conditions. A new fully integrated Standby Power concept is implemented into the IC in order to keep the application design easy. Compared to CoolSET™-F2 no further external parts are needed to achieve the lowest Standby Power. An intelligent Active Burst Mode is used for this Standby Mode. After entering this mode there is still a full control of the power conversion by the secondary side via the same optocoupler that is used for the normal PWM control. The response on load jumps is optimized. The voltage ripple on Vout is minimized. Vout is further on well controlled in this mode. The usually external connected RC-filter in the feedback line after the optocoupler is integrated in the IC to reduce the external part count. Furthermore a high voltage Startup Cell is integrated into the IC which is switched off once the Undervoltage Lockout on-threshold of 15V is exceeded. This Startup Cell is part of the integrated Depl. CoolMOS™. The external startup resistor is no longer necessary as this Startup Cell is connected to the Drain. Power losses are therefore reduced. This increases the efficiency under light load conditions drastically. The Soft-Start capacitor is also used for providing an adjustable blanking window for high load jumps. During this time window the overload detection is disabled. With this concept no further external components are necessary to adjust the blanking window. In order to increase the robustness and safety of the system, the IC provides 2 levels of protection modes: Latched Off Mode and Auto Restart Mode. The Latched Off Mode is only entered under dangerous conditions which can damage the SMPS if not switched off immediately. A restart of the system can only be done by disconnecting the AC line. The Auto Restart Mode reduces the average power conversion to a minimum under unsafe operating conditions. This is necessary for a prolonged fault condition which could otherwise lead to a destruction of the SMPS over time. Once the malfunction is removed, normal operation is automatically initiated after the next Start Up Phase. The internal precise peak current limitation reduces the costs for the transformer and the secondary diode. The influence of the change in the input voltage on the Version 2.0 Power Management VCC Startup Cell Depl. CoolMOS™ Power Management Undervoltage Lockout 15V Internal Bias 8.5V Latched Off Mode Reset VVCC < 6V Voltage Reference Power-Down Reset 6.5V Auto Restart Mode Active Burst Mode T1 Latched Off Mode SoftS Figure 3 Power Management The Undervoltage Lockout monitors the external supply voltage VVCC. When the SMPS is plugged to the main line the internal Startup Cell is biased and starts to charge the external capacitor CVCC which is connected to the VCC pin. This VCC charge current which is provided by the Startup Cell from the Drain pin is 1.05mA. When VVCC exceeds the on-threshold VCCon=15V the internal voltage reference and bias circuit are switched on. Then the Startup Cell is switched off by the Undervoltage Lockout and therefore no power losses present due to the connection of the Startup Cell to the Drain voltage. To avoid uncontrolled ringing at switch-on a hysteresis is implemented. The switch-off of the controller can only take place after Active Mode was entered and VVCC falls below 8.5V. 7 8 May 2006 CoolSET™-F3 ICE3xxx65L Functional Description signal VSoftS which is generated by the external capacitor CSofts in combination with the internal pull up resistor RSoftS, determines the duty cycle until VSoftS exceeds 4V. When the Soft Start begins, CSoftS is immediately charged up to approx. 1V by T2. Therefore the Soft Start Phase takes place between 1V and 4V. Above VSoftsS = 4V there is no longer duty cycle limitation DCmax which is controlled by comparator C7 since comparator C2 blocks the gate G7 (see Figure 4). This maximum charge current in the very first stage when VSoftS is below 1V, is limited to 1.30mA. The maximum current consumption before the controller is activated is about 160µA. When VVCC falls below the off-threshold VCCoff=8.5V the internal reference is switched off and the Power Down reset let T1 discharging the soft-start capacitor CSoftS at pin SoftS. Thus it is ensured that at every startup cycle the voltage ramp at pin SoftS starts at zero. The internal Voltage Reference is switched off if Latched Off Mode or Auto Restart Mode is entered. The current consumption is then reduced to 300µA. Once the malfunction condition is removed, this block will then turn back on. The recovery from Auto Restart Mode does not require disconnecting the SMPS from the AC line. In case Latched Off Mode is entered, VCC needs to be lowered below 6V to reset the Latched Off Mode. This is done usually by disconnecting the SMPS from the AC line. When Active Burst Mode is entered the internal Bias is switched off in order to reduce the current consumption below 1.05mA while keeping the Voltage Reference still active as this is necessary in this mode. VSoftS max. Startup Phase 5.4V 4V 1V max. Soft Start Phase 3.3 Startup Phase DCmax 6.5V 3.25k t DC1 DC2 RSoftS T2 T3 SoftS 1V t1 CSoftS Soft Start Soft-Start Comparator C7 & Figure 5 C2 4V 0.85V CS PWM OP Figure 4 Startup Phase By means of this extra charge stage, there is no delay in the beginning of the Startup Phase when there is still no switching. Furthermore Soft Start is finished at 4V to have faster the maximum power capability. The duty cycles DC1 and DC2 are depending on the mains and the primary inductance of the transformer. The limitation of the primary current by DC2 is related to VSoftS = 4V. But DC1 is related to a maximum primary current which is limited by the internal Current Limiting with CS = 1V. Therefore the maximum Startup Phase is divided into a Soft Start Phase until t1 and a phase from t1 until t2 where maximum power is provided if demanded by the FB signal. Gate Driver G7 x3.7 t2 t Soft Start At the beginning of the Startup Phase, the IC provides a Soft Start duration whereby it controls the maximum primary current by means of a duty cycle limitation. A Version 2.0 8 8 May 2006 CoolSET™-F3 ICE3xxx65L Functional Description 3.4 PWM Section 3.4.3 0.72 Gate Driver PWM Section Oscillator VCC Duty Cycle max PWM-Latch 1 Clock Gate Soft Start Comparator PWM Comparator FF1 1 G8 R CoolMOS™ Gate Driver S Q & G9 Gate Driver Current Limiting Figure 7 Internal CoolMOS™ Gate Figure 6 The driver-stage is optimized to minimize EMI and to provide high circuit efficiency. This is done by reducing the switch on slope when exceeding the internal CoolMOS™ threshold. This is achieved by a slope control of the rising edge at the driver’s output (see Figure 8). PWM Section Block 3.4.1 Oscillator The oscillator generates a fixed frequency. The switching frequency for ICE3Axx65L is fOSC = 100kHz and ICE3Bxx65L is fOSC = 67kHz. A resistor, a capacitor and a current source and current sink which determine the frequency are integrated. The charging and discharging current of the implemented oscillator capacitor are internally trimmed, in order to achieve a very accurate switching frequency. The ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of Dmax=0.72. (internal) VGate ca. t = 130ns 5V t Figure 8 3.4.2 PWM-Latch FF1 The oscillator clock output provides a set pulse to the PWM-Latch when initiating the internal CoolMOS™ conduction. After setting the PWM-Latch can be reset by the PWM comparator, the Soft Start comparator or the Current-Limit comparator. In case of resetting, the driver is shut down immediately. Version 2.0 Gate Driver Gate Rising Slope Thus the leading switch on spike is minimized. When the integrated CoolMOS™ is switched off, the falling shape of the driver is slowed down when reaching 2V to prevent an overshoot below ground. Furthermore the driver circuit is designed to eliminate cross conduction of the output stage. During powerup when VCC is below the undervoltage lockout threshold VVCCoff, the output of the Gate Driver is low to disable power transfer to the secondary side. 9 8 May 2006 CoolSET™-F3 ICE3xxx65L Functional Description 3.5 Current Limiting PWM Latch FF1 short winding in the transformer or the secondary diode is shorten. To ensure that there is no accidentally entering of the Latched Mode by the comparator C11 a spike blanking with 190ns is integrated in the output path of comparator C11. Latched Off Mode Current Limiting Spike Blanking 190ns 3.5.1 1.66V C11 Leading Edge Blanking VSense Propagation-Delay Compensation Vcsth Vcsth C10 PWM-OP tLEB = 220ns Leading Edge Blanking 220ns t & G10 C12 Figure 10 0.257V Each time when the internal CoolMOS™ is switched on, a leading edge spike is generated due to the primary-side capacitances and secondary-side rectifier reverse recovery time. This spike can cause the gate drive to switch off unintentionally. To avoid a premature termination of the switching pulse, this spike is blanked out with a time constant of tLEB = 220ns. During this time, the gate drive will not be switched off. 1pF 10k Active Burst Mode D1 CS Figure 9 3.5.2 Current Limiting Block Propagation Delay Compensation In case of overcurrent detection, the switch-off of the internal CoolMOS™ is delayed due to the propagation delay of the circuit. This delay causes an overshoot of the peak current Ipeak which depends on the ratio of dI/ dt of the peak current (see Figure 11). There is a cycle by cycle Current Limiting realized by the Current-Limit comparator C10 to provide an overcurrent detection. The source current of the internal CoolMOS™ is sensed via an external sense resistor RSense . By means of RSense the source current is transformed to a sense voltage VSense which is fed into the pin CS. If the voltage VSense exceeds the internal threshold voltage Vcsth the comparator C10 immediately turns off the gate drive by resetting the PWM Latch FF1. A Propagation Delay Compensation is added to support the immediate shut down without delay of the internal CoolMOS™ in case of Current Limiting. The influence of the AC input voltage on the maximum output power can thereby be avoided. To prevent the Current Limiting from distortions caused by leading edge spikes a Leading Edge Blanking is integrated in the current sense path for the comparators C10, C12 and the PWM-OP. The output of comparator C12 is activated by the Gate G10 if Active Burst Mode is entered. Once activated the current limiting is thereby reduced to 0.257V. This voltage level determines the power level when the Active Burst Mode is left if there is a higher power demand. A further comparator C11 is implemented to detect dangerous current levels which could occur if there is a Version 2.0 Leading Edge Blanking Signal2 ISense Ipeak2 Ipeak1 ILimit IOvershoot2 Signal1 tPropagation Delay IOvershoot1 t Figure 11 Current Limiting The overshoot of Signal2 is bigger than of Signal1 due to the steeper rising waveform. This change in the slope is depending on the AC input voltage. Propagation Delay Compensation is integrated to limit the overshoot dependency on dI/dt of the rising primary 10 8 May 2006 CoolSET™-F3 ICE3xxx65L Functional Description 3.6 current. That means the propagation delay time between exceeding the current sense threshold Vcsth and the switch off of the internal CoolMOS™ is compensated over temperature within a wide range. Current Limiting is now possible in a very accurate way. E.g. Ipeak = 0.5A with RSense = 2. Without Propagation Delay Compensation the current sense threshold is set to a static voltage level Vcsth=1V. A current ramp of dI/dt = 0.4A/µs, that means dVSense/dt = 0.8V/µs, and a propagation delay time of i.e. tPropagation Delay =180ns leads then to an Ipeak overshoot of 14.4%. By means of propagation delay compensation the overshoot is only about 2% (see Figure 12). with compensation Control Unit The Control Unit contains the functions for Active Burst Mode, Auto Restart Mode and Latched Off Mode. The Active Burst Mode and the Auto Restart Mode are combined with an Adjustable Blanking Window which is depending on the external Soft Start capacitor. By means of this Adjustable Blanking Window, the IC avoids entering into these two modes accidentally. Furthermore it also provides a certain time whereby the overload detection is delayed. This delay is useful for applications which normally works with a low current and occasionally require a short duration of high current. without compensation 3.6.1 V Adjustable Blanking Window 1,3 SoftS 1,25 VSense 1,2 6.5V 1,15 1,1 5kΩ R SoftS 1,05 1 4.4V 0,95 1 0,9 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 V µs 2 dVSense dt Figure 12 S1 Overcurrent Shutdown G4 C3 The Propagation Delay Compensation is realized by means of a dynamic threshold voltage Vcsth (see Figure 13). In case of a steeper slope the switch off of the driver is earlier to compensate the delay. VOSC G2 & 5.4V Auto Restart Mode & 4.8V C4 G5 max. Duty Cycle Active Burst Mode off time VSense Propagation Delay t 1.30V Control Unit Figure 14 Signal1 Version 2.0 G6 C6 Vcsth Figure 13 & FB Signal2 Adjustable Blanking Window VSoftS is clamped at 4.4V by the closed switch S1 after the SMPS is settled. If overload occurs VFB is exceeding 4.8V. Auto Restart Mode can’t be entered as the gate G5 is still blocked by the comparator C3. But after VFB has exceeded 4.8V the switch S1 is opened via the gate G2. The external Soft Start capacitor can now be charged further by the integrated pull up resistor RSoftS. The comparator C3 releases the gates G5 and G6 once VSofts has exceeded 5.4V. Therefore there is no entering of Auto Restart Mode possible during this charging time of the external capacitor t Dynamic Voltage Threshold Vcsth 11 8 May 2006 CoolSET™-F3 ICE3xxx65L Functional Description 3.6.2.1 Entering Active Burst Mode The FB signal is always observed by the comparator C5 if the voltage level falls below 1.30V. In that case the switch S1 is released which allows the capacitor CSoftS to be charged starting from the clamped voltage level at 4.4V in normal operating mode. If VSoftS exceeds 5.4V the comparator C3 releases the gate G6 to enter the Active Burst Mode. The time window that is generated by combining the FB and SoftS signals with gate G6 avoids a sudden entering of the Active Burst Mode due to large load jumps. This time window can be adjusted by the external capacitor CSoftS. After entering Active Burst Mode a burst flag is set and the internal bias is switched off in order to reduce the current consumption of the IC down to approx. 1.05mA. In this Off State Phase the IC is no longer self supplied so that therefore CVCC has to provide the VCC current (see Figure 16). Furthermore gate G11 is then released to start the next burst cycle once VFB has 3.4V exceeded. It has to be ensured by the application that the VCC remains above the Undervoltage Lockout Level of 8.5V to avoid that the Startup Cell is accidentally switched on. Otherwise power losses are significantly increased. The minimum VCC level during Active Burst Mode is depending on the load conditions and the application. The lowest VCC level is reached at no load conditions at VOUT. CSoftS. The same procedure happens to the external Soft Start capacitor if a low load condition is detected by comparator C5 when VFB is falling below 1.30V. Only after VSoftS has exceeded 5.4V and VFB is still below 1.30V Active Burst Mode is entered. 3.6.2 Active Burst Mode The controller provides Active Burst Mode for low load conditions at VOUT. Active Burst Mode increases significantly the efficiency at light load conditions while supporting a low ripple on VOUT and fast response on load jumps. During Active Burst Mode which is controlled only by the FB signal the IC is always active and can therefore immediately response on fast changes at the FB signal. The Startup Cell is kept switched off to avoid increased power losses for the self supply. SoftS 6.5V 5kΩ RSoftS Internal Bias 4.4V S1 Current Limiting 3.6.2.2 Working in Active Burst Mode After entering the Active Burst Mode the FB voltage rises as VOUT starts to decrease due to the inactive PWM section. Comparator C6a observes the FB signal if the voltage level 4V is exceeded. In that case the internal circuit is again activated by the internal Bias to start with switching. As now in Active Burst Mode the gate G10 is released the current limit is only 0.257V to reduce the conduction losses and to avoid audible noise. If the load at VOUT is still below the starting level for the Active Burst Mode the FB signal decreases down to 3.4V. At this level C6b deactivates again the internal circuit by switching off the internal Bias. The gate G11 is released as after entering Active Burst Mode the burst flag is set. If working in Active Burst Mode the FB voltage is changing like a saw tooth between 3.4V and 4V (see Figure 16). & C3 G10 5.4V 4.8V C4 FB C5 Active Burst Mode & G6 1.30V C6a 4.0V & G11 C6b 3.4V Figure 15 3.6.2.3 Leaving Active Burst Mode The FB voltage immediately increases if there is a high load jump. This is observed by comparator C4. As the current limit is ca. 26% during Active Burst Mode a certain load jump is needed that FB can exceed 4.8V. At this time C4 resets the Active Burst Mode which also Control Unit Active Burst Mode The Active Burst Mode is located in the Control Unit. Figure 15 shows the related components. Version 2.0 12 8 May 2006 CoolSET™-F3 ICE3xxx65L Functional Description blocks C12 by the gate G10. Maximum current can now be provided to stabilize VOUT. VFB Entering Active Burst Mode 4.80V 4.00V 3.40V 3.6.3 Protection Modes The IC provides several protection features which are separated into two categories. Some enter Latched Off Mode, the others enter Auto Restart Mode. The Latched Off Mode can only be reset if VCC is falling below 6V. Both modes prevent the SMPS from destructive states. The following table shows the relationship between possible system failures and the chosen protection modes. Leaving Active Burst Mode 1.30V VSoftS t Blanking Window Latched Off Mode Overtemperature Latched Off Mode Short Winding/Short Diode Latched Off Mode 5.40V 4.40V VCS VCC Overvoltage t Overload Auto Restart Mode Open Loop Auto Restart Mode VCC Undervoltage Auto Restart Mode Short Optocoupler Auto Restart Mode 3.6.3.1 Current limit level during 1.00V Active Burst Mode Latched Off Mode CS 0.257V VVCC Latched Off Mode Reset VVCC < 6V t C11 1.70V Spike Blanking 190ns 1 Latched Off Mode G3 8.5V IVCC VCC t Spike Blanking 8.0us C1 28V 7.2mA 1.05mA Thermal Shutdown VOUT t Voltage Reference Tj >140°C Max. Ripple < 1% Control Unit Figure 17 t Figure 16 Version 2.0 Latched Off Mode The VCC voltage is observed by comparator C1 if 21V is exceeded. The output of C1 is combined with the output of C4 which observes FB signal if 4.8V is Signals in Active Burst Mode 13 8 May 2006 CoolSET™-F3 ICE3xxx65L Functional Description operating mode comparator C10 keeps the maximum level of the CS signal at 1V. If there is a failure such as short winding or short diode, C10 is no longer able to limit the CS signal at 1V. C11 detects then the over current and enters immediately the Latched Off Mode to keep the SMPS in a safe stage. exceeded. Therefore the overvoltage detection is only activated if the FB signal is outside the operating range > 4.8V, e.g. when Open Loop happens. This means any small voltage overshoots of VVCC during normal operating can not start the Latched Off Mode. The internal Voltage Reference is switched off once Latched Off Mode is entered in order to reduce the current consumption of the IC as much as possible. Latched Off Mode can only be reset by decreasing VVCC < 6V. In this stage, only the UVLO is working which controls the Startup Cell by switching on/off at VVCCon/VVCCoff. During this phase, the average current consumption is only 300µA. As there is no longer a selfsupply by the auxiliary winding, VCC drops. The Undervoltage Lockout switches on the integrated Startup Cell when VCC falls below 8.5V. The Startup Cell is switched off again when VCC has exceeded 15V. Once the Latched Off Mode was entered, there is no Start Up Phase after VCC has exceeded the switchon level of the Undervoltage Lockout. Therefore VCC changes between the switch-on and switch-off levels of the Undervoltage Lockout with a saw tooth shape (see Figure 18). 3.6.3.2 Auto Restart Mode SoftS 6.5V 5kΩ 4.4V 1 S1 G2 Voltage Reference C3 VVCC 5.4V t.b.d 4.8V & C4 IVCCStart t Figure 19 VOUT Auto Restart Mode Control Unit Auto Restart Mode In case of Overload or Open Loop, FB exceeds 4.8V which will be observed by C4. At this time S1 is released that VSoftS can increase. If VSoftS exceeds 5.4V which is observed by C3, Auto Restart Mode is entered as both inputs of the gate G5 are high. In combining the FB and SoftS signals, there is a blanking window generated which prevents the system to enter Auto Restart Mode due to large load jumps. This time window is the same as for the Active Burst Mode and can therefore be adjusted by the external CSoftS. In case of VCC undervoltage, the IC enters into the Auto Restart Mode and starts a new startup cycle. Short Optocoupler also leads to VCC undervoltage as there is no self supply after activating the internal reference and bias. In contrast to the Latched Off Mode, there is always a Startup Phase with switching cycles in Auto Restart Mode. After this Start Up Phase, the conditions are again checked whether the failure mode is still present. Normal operation is resumed once the failure mode is removed that had caused the Auto Restart Mode. 1.05mA t Signals in Latched Off Mode The Thermal Shutdown block monitors the junction temperature of the IC. After detecting a junction temperature higher than 140°C, Latched Off Mode is entered. The signals coming from the temperature detection and VCC overvoltage detection are fed into a spike blanking with a time constant of 8.0µs to ensure system reliability. Furthermore, a short winding or short diode on the secondary side can be detected by the comparator C11 which is in parallel to the propagation delay compensated current limit comparator C10. In normal Version 2.0 G5 FB 8.5V Figure 18 RSoftS 14 8 May 2006 CoolSET™-F3 ICE3xxx65L Electrical Characteristics 4 Electrical Characteristics Note: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are not violated. 4.1 Note: Absolute Maximum Ratings Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7 (VCC) is discharged before assembling the application circuit. Parameter Symbol Limit Values Unit Remarks Tj=110°C min. max. - 650 V ICE3B0365L ID_Puls1 - 1.6 A ICE3A1065L ID_Puls2 - 3.4 A ICE3A1565L ID_Puls3 - 6.1 A Avalanche energy, repetitive tAR limited by max. Tj=150°C1) ICE3B0365L EAR1 - 0.005 mJ ICE3A1065L EAR2 - 0.07 mJ ICE3A1565L EAR3 - 0.15 mJ Avalanche current, repetitive tAR limited by max. Tj=150°C ICE3B0365L IAR1 - 0.3 A ICE3A1065L IAR2 - 1.0 A ICE3A1565L IAR3 - 1.5 A Drain Source Voltage Pulse drain current, tp limited by Tjmax VDS VCC Supply Voltage VVCC -0.3 22 V FB Voltage VFB -0.3 6.5 V SoftS Voltage VSoftS -0.3 6.5 V CS Voltage VCS -0.3 6.5 V Junction Temperature Tj -40 150 °C Storage Temperature TS -55 150 °C Thermal Resistance Junction -Ambient RthJA - 90 K/W PG-DIP-8-6 ESD Capability(incl. Drain Pin) VESD - 3 kV Human body model2) 1) Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f 2) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor) Version 2.0 15 8 May 2006 CoolSET™-F3 ICE3xxx65L Electrical Characteristics 4.2 Note: Operating Range Within the operating range the IC operates as described in the functional description. Parameter Symbol Limit Values min. max. Unit VCC Supply Voltage VVCC VVCCoff 20 V Junction Temperature of Controller TjCon -25 130 °C Junction Temperature of CoolMOS™ TjCoolMOS -25 150 °C 4.3 4.3.1 Note: Remarks Max value limited due to thermal shut down of controller Characteristics Supply Section The electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range TJ from – 25 °C to 130 °C. Typical values represent the median values, which are related to 25°C. If not otherwise stated, a supply voltage of VCC = 15 V is assumed. Parameter Symbol Limit Values min. typ. max. Unit Test Condition Start Up Current IVCCstart - 160 220 µA VVCC =14V VCC Charge Current IVCCcharge1 0.55 1.05 1.60 mA VVCC = 0V IVCCcharge2 - 0.88 - mA VVCC =14V Leakage Current of Start Up Cell and CoolMOS™ IStartLeak - 0.2 50 µA VVCC=16V, VDrain = 450V at Tj=100°C Supply Current with Inactive Gate IVCCsup_ng - 5.5 7.0 mA ICE3B0365L IVCCsup_g1 - 5.5 7.0 mA ICE3A1065L IVCCsup_g2 - 5.9 7.5 mA ICE3A1565L IVCCsup_g3 - 6.3 8.0 mA Supply Current with Active Gate VSoftS = 4.4V IFB = 0, Supply Current in Latched Off Mode IVCClatch - 300 - µA IFB = 0 ISofts = 0 Supply Current in Auto Restart Mode with Inactive Gate IVCCrestart - 300 - µA IFB = 0 ISofts = 0 Supply Current in Active Burst Mode with Inactive Gate IVCCburst1 - 1.05 1.25 mA VVCC =15V VFB = 3.7V, VSoftS = 4.4V IVCCburst2 - 0.95 1.15 mA VVCC = 9.5V VFB = 3.7V, VSoftS = 4.4V VVCCon VVCCoff VVCChys 14.2 8.0 - 15.0 8.5 6.5 15.8 9.0 - V V V VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hysteresis Version 2.0 16 8 May 2006 CoolSET™-F3 ICE3xxx65L Electrical Characteristics 4.3.2 Internal Voltage Reference Parameter Symbol Trimmed Reference Voltage 4.3.3 VREF Limit Values min. typ. max. 6.37 6.50 6.63 Unit Test Condition V measured at pin FB IFB = 0 PWM Section Parameter Symbol Limit Values Unit min. typ. max. fOSC_A1 92 100 108 kHz fOSC_A2 94 100 106 kHz fOSC_B1 61 67 73 kHz fOSC_B2 63 67 71 kHz Max. Duty Cycle Dmax 0.67 0.72 0.77 Min. Duty Cycle Dmin 0 - - PWM-OP Gain AV 3.5 3.7 3.9 Voltage Ramp Max Level VMax-Ramp - 0.85 - V VFB Operating Range Min Level VFBmin 0.3 0.7 - V VFB Operating Range Max level VFBmax - - 4.75 V FB Pull-Up Resistor RFB 16 20 27 kΩ SoftS Pull-Up Resistor RSoftS 39 50 62 kΩ Fixed Oscillator Frequency Fixed Oscillator Frequency 1) ICE3Axx65L ICE3Bxx65L Test Condition Tj = 25°C Tj = 25°C VFB < 0.3V CS=1V, limited by Comparator C41) The parameter is not subjected to production test - verified by design/characterization Version 2.0 17 8 May 2006 CoolSET™-F3 ICE3xxx65L Electrical Characteristics 4.3.4 Control Unit Parameter Symbol Limit Values min. typ. max. Unit Test Condition Deactivation Level for SoftS Comparator C7 by C2 VSoftSC2 3.85 4.00 4.15 V VFB > 5V Clamped VSoftS Voltage during Normal Operating Mode VSoftSclmp 4.23 4.40 4.57 V VFB = 4V Activation Limit of Comparator C3 VSoftSC3 5.20 5.40 5.60 V VFB > 5V SoftS Startup Current ISoftSstart - 1.3 - mA VSoftS = 0V Over Load & Open Loop Detection Limit for Comparator C4 VFBC4 4.62 4.80 4.98 V VSoftS > 5.6V Active Burst Mode Level for Comparator C5 VFBC5 1.23 1.30 1.37 V VSoftS > 5.6V Active Burst Mode Level for Comparator C6a VFBC6a 3.85 4.00 4.15 V After Active Burst Mode is entered Active Burst Mode Level for Comparator C6b VFBC6b 3.25 3.40 3.55 V After Active Burst Mode is entered Overvoltage Detection Limit VVCCOVP 20 21 22 V VFB > 5V Latched Thermal Shutdown1) TjSD 130 140 150 °C Spike Blanking tSpike - 8.0 - µs Power Down Reset for Latched Mode VVCCPD 4.0 6.0 7.5 V 1) After Latched Off Mode is entered The parameter is not subjected to production test - verified by design/characterization Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP and VVCCPD Version 2.0 18 8 May 2006 CoolSET™-F3 ICE3xxx65L Electrical Characteristics 4.3.5 Current Limiting Parameter Symbol Limit Values min. typ. max. Unit Test Condition dVsense / dt = 0.6V/µs (see Figure 12) Peak Current Limitation (incl. Propagation Delay) Vcsth 0.97 1.02 1.07 V Peak Current Limitation during Active Burst Mode VCS2 0.232 0.257 0.282 V Leading Edge Blanking tLEB - 220 - ns VSoftS = 4.4V CS Input Bias Current ICSbias -1.0 -0.2 0 µA VCS =0V Over Current Detection for Latched Off Mode VCS1 1.570 1.66 1.764 V CS Spike Blanking for Comparator C11 tCSspike - 190 - ns 4.3.6 CoolMOS™ Section Parameter Symbol Limit Values min. typ. max. Unit Test Condition Drain Source Breakdown Voltage V(BR)DSS 600 650 - - V V Tj = 25°C Tj = 110°C Drain Source On-Resistance ICE3B0365L RDSon1 - 6.45 13.7 7.50 17.0 Ω Ω Tj = 25°C Tj=125°C1) at ID = 0.3A ICE3A1065L RDSon2 - 2.95 6.60 3.42 7.56 Ω Ω Tj = 25°C Tj=125°C1) at ID = 1.0A ICE3A1565L RDSon3 - 1.70 3.57 1.96 4.12 Ω Ω Tj = 25°C Tj=125°C1) at ID = 1.5A ICE3B0365L Co(er)1 - 3.65 - pF VDS = 0V to 480V ICE3A1065L Co(er)2 - 7.0 - pF ICE3A1565L Co(er)3 - 11.63 - pF Rise Time trise - 302) - ns Fall Time tfall - 302) - ns Effective output capacitance, energy related 1) The parameter is not subjected to production test - verified by design/characterization 2) Measured in a Typical Flyback Converter Application Version 2.0 19 8 May 2006 CoolSET™-F3 ICE3xxx65L Temperature derating curve 5 Temperature derating curve Safe Operating Area for ICE3A(B)0365(L) ID = f ( VDS ) parameter : D = 0, TC = 25deg.C 10 ID [A] 1 0.1 tp = tp = tp = tp = tp = DC 0.01 0.01ms 0.1ms 1ms 10ms 100ms 0.001 1 10 100 1000 V DS [V] Figure 20 Safe Operating area ( SOA ) curve for ICE3B03065L Safe Operating Area for ICE3A(B)1065(L) ID = f ( VDS ) parameter : D = 0, TC = 25deg.C 10 ID [A] 1 0.1 tp = tp = tp = tp = tp = DC 0.01 0.1ms 1ms 10ms 100ms 1000ms 0.001 1 10 100 1000 V DS [V] Figure 21 Safe Operating area ( SOA ) curve for ICE3A1065L Version 2.0 20 8 May 2006 CoolSET™-F3 ICE3xxx65L Temperature derating curve Safe Operating Area for ICE3A(B)1565(L) ID = f ( VDS ) parameter : D = 0, TC = 25deg.C 10 ID [A] 1 0.1 tp = tp = tp = tp = tp = DC 0.01 0.1ms 1ms 10ms 100ms 1000ms 0.001 1 10 100 1000 V DS [V] Figure 22 Safe Operating area ( SOA ) curve for ICE3A1565L SOA temperature derating coefficient curve for F3 & F2 CoolSET SOA temperature derating coefficient [%] 120 100 80 60 40 20 0 0 20 40 60 80 100 120 140 Junction temperature Tc [deg.C] Figure 23 SOA temperature derating coefficient curve Version 2.0 21 8 May 2006 CoolSET™-F3 ICE3xxx65L Outline Dimension 6 Outline Dimension PG-DIP-8-6 (Plastic Dual In-Line Outline) Figure 24 PG-DIP-8-6 ( Pb-free lead plating Platic Dual-in-Line Outline ) Dimensions in mm Version 2.0 22 8 May 2006 CoolSET™-F3 ICE3xxx65L Marking 7 Marking Marking Figure 25 Marking for ICE3B0365L Marking Figure 26 Marking for ICE3A1065L Version 2.0 23 8 May 2006 CoolSET™-F3 ICE3xxx65L Marking Marking Figure 27 Marking for ICE3A1565L Version 2.0 24 8 May 2006 CoolSET™-F3 ICE3xxx65L Schematic for recommended PCB layout 8 Schematic for recommended PCB layout TR1 BR1 Spark Gap 3 FUSE1 L D21 Vo L1 C1 Spark Gap 1 C12 R11 C11 bulk cap X-CAP D11 C21 GND Spark Gap 2 D11 Spark Gap 4 Z11 N C2 Y-CAP R12 C3 Y-CAP C16 CS DRAIN C4 Y-CAP GND IC11 SOFTS/BL F3 CoolSET VCC R21 R13 R14 D13 R23 GND FB C22 C15 C13 * R22 NC C23 C14 IC12 F3 CoolSET schematic for recommended PCB layout R24 IC21 R25 Figure 28 Schematic for recommended PCB layout General guideline for PCB layout design using F3 CoolSET (refer to Figure 28): 1. “Star Ground “at bulk capacitor ground, C11: “Star Ground “means all primary DC grounds should be connected to the ground of bulk capacitor C11 separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET device effectively. The primary DC grounds include the followings. a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11. b. DC ground of the current sense resistor, R12 c. DC ground of the CoolSET device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector of IC12 should be connected to the GND pin of IC11 and then “star “connect to the bulk capacitor ground. d. DC ground from bridge rectifier, BR1 e. DC ground from the bridging Y-capacitor, C4 2. High voltage traces clearance: High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur. a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm b. 600V traces (drain voltage of CoolSET IC11) to nearby trace: > 2.5mm 3. Filter capacitor close to the controller ground: Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pin as possible so as to reduce the switching noise coupled into the controller. Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 28): 1. Add spark gap Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated charge during surge test through the sharp point of the saw-tooth plate. a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1: Gap separation is around 1.5mm (no safety concern) Version 2.0 25 8 May 2006 CoolSET™-F3 ICE3xxx65L Schematic for recommended PCB layout b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND: These 2 Spark Gaps can be used when the lightning surge requirement is >6KV. 230Vac input voltage application, the gap separation is around 5.5mm 115Vac input voltage application, the gap separation is around 3mm 2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input 3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12: The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET and reduce the abnormal behavior of the CoolSET. The diode can be a fast speed diode such as IN4148. The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through the sensitive components such as the primary controller, IC11. Version 2.0 26 8 May 2006 CoolSET™-F3 ICE3xxx65L Schematic for recommended PCB layout Version 2.0 27 8 May 2006 Total Quality Management Qualität hat für uns eine umfassende Bedeutung. Wir wollen allen Ihren Ansprüchen in der bestmöglichen Weise gerecht werden. Es geht uns also nicht nur um die Produktqualität – unsere Anstrengungen gelten gleichermaßen der Lieferqualität und Logistik, dem Service und Support sowie allen sonstigen Beratungs- und Betreuungsleistungen. Quality takes on an allencompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way. So we are not only concerned with product quality. We direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. Dazu gehört eine bestimmte Geisteshaltung unserer Mitarbeiter. Total Quality im Denken und Handeln gegenüber Kollegen, Lieferanten und Ihnen, unserem Kunden. Unsere Leitlinie ist jede Aufgabe mit „Null Fehlern“ zu lösen – in offener Sichtweise auch über den eigenen Arbeitsplatz hinaus – und uns ständig zu verbessern. Part of this is the very special attitude of our staff. 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