Dual, 3 V, CMOS, LVDS Differential Line Receiver ADN4664 ±15 kV ESD protection on output pins 400 Mbps (200 MHz) switching rates Flow-through pinout simplifies PCB layout 100 ps channel-to-channel skew (typical) 2.5 ns maximum propagation delay 3.3 V power supply High impedance outputs on power-down Low power design: typically 3 mW (quiescent) Interoperable with existing 5 V LVDS drivers Accepts small swing (310 mV typical) differential signal levels Supports open, short, and terminated input fail-safe 0 V to −100 mV threshold region Conforms to TIA/EIA-644 LVDS standard Industrial operating temperature range: −40°C to +85°C Available in surface-mount (SOIC) package FUNCTIONAL BLOCK DIAGRAM VCC ADN4664 RIN1+ ROUT1 RIN1– RIN2+ ROUT2 RIN2– GND 07961-001 FEATURES Figure 1. APPLICATIONS Point-to-point data transmission Multidrop buses Clock distribution networks Backplane receivers GENERAL DESCRIPTION The ADN4664 is a dual, CMOS, low voltage differential signaling (LVDS) line receiver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flow-through pinout for easy PCB layout and separation of input and output signals. The ADN4664 and its companion driver, the ADN4663, offer a new solution to high speed, point-to-point data transmission, and a low power alternative to emitter-coupled logic (ECL) or positive emitter-coupled logic (PECL). The device accepts low voltage (310 mV typical) differential input signals and converts them to a single-ended 3 V TTL/ CMOS logic level. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADN4664 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................7 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................8 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 11 Specifications..................................................................................... 3 Applications Information .......................................................... 11 AC Characteristics........................................................................ 4 Outline Dimensions ....................................................................... 12 Absolute Maximum Ratings............................................................ 6 Ordering Guide .......................................................................... 12 REVISION HISTORY 1/09—Revision 0: Initial Version Rev. 0 | Page 2 of 12 ADN4664 SPECIFICATIONS VDD = 3.0 V to 3.6 V; CL = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter 1 LVDS INPUT High Threshold at RINx+, RINx− 3 Low Threshold at RINx+, RINx−3 Input Current at RINx+, RINx− OUTPUT Output High Voltage Output Low Voltage Output Short-Circuit Current 4 Input Clamp Voltage POWER SUPPLY No Load Supply Current ESD PROTECTION RINx+, RINx− Pins All Pins Except RINx+, RINx− Symbol VTH VTL IIN VOH VOL IOS VCL ICC Min −100 −10 −10 −20 2.7 2.7 2.7 −15 −1.5 Typ 2 ±1 ±1 ±1 3.1 3.1 3.1 0.3 −47 −0.8 5.4 ±15 kV ±4 kV 1 Max Unit Conditions/Comments +100 mV mV μA μA μA VCM = 1.2 V, 0.05 V, 2.95 V VCM = 1.2 V, 0.05 V, 2.95 V VIN = 2.8 V, VCC = 3.6 V or 0 V VIN = 0 V, VCC = 3.6 V or 0 V VIN = 3.6 V, VCC = 0 V V V V V mA V IOH = −0.4 mA, VID = +200 mV IOH = −0.4 mA, input terminated IOH = −0.4 mA, input shorted IOL = 2 mA, VID = −200 mV Enabled, VOUT = 0 V ICL = −18 mA mA Inputs open +10 +10 +20 0.5 −100 9 Human body model Human body model Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified. All typicals are given for: VCC = 3.3 V, TA = 25°C. 3 VCC is always higher than RINx+ and RINx− voltage. RINx− and RINx+ are allowed to have a voltage range of −0.2 V to VCC − VID/2. However, to be compliant with ac specifications, the common voltage range is 0.1 V to 2.3 V. 4 Output short-circuit current (IOS) is specified as magnitude only; the minus sign indicates direction only. Only one output should be shorted at a time. Do not exceed maximum junction temperature specification. 2 Rev. 0 | Page 3 of 12 ADN4664 AC CHARACTERISTICS VDD = 3.0 V to 3.6 V; CL 1 = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Pulse Skew |tPHLD − tPLHD| 4 Differential Channel-to-Channel Skew (Same Device) 5 Differential Part-to-Part Skew 6 Differential Part-to-Part Skew 7 Rise Time Fall Time Maximum Operating Frequency 8 Symbol tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL fMAX Min 1.0 1.0 0 0 200 Typ 2 2.15 2.03 80 100 510 445 250 Max 2.5 2.5 400 500 Unit ns ns ps ps Conditions/Comments 3 CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3) CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3) CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3) CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3) 1.0 1.5 800 800 ns ns ps ps MHz CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3) CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3) CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3) CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3) All channels switching 1 CL includes probe and jig capacitance. All typicals are given for VCC = 3.3 V, TA = 25°C. 3 Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tTLH and tTHL (0% to 100%) ≤ 3 ns for RINx+, RINx−. 4 tSKD1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. 5 Channel-to-channel skew, tSKD2, is the defined as the difference between the propagation delay of one channel and the propagation delay of the other channel on the same chip with any event on the inputs. 6 tSKD3, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. 7 tSKD4, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |maximum − minimum| differential propagation delay. 8 fMAX generator input conditions: f = 200 MHz, tTLH = tTHL < 1 ns (0% to 100%), 50% duty cycle, differential (1.05 V to 1.35 V peak-to-peak). Output criteria: 60%/40% duty cycle, VOL (maximum 0.4 V), VOH (minimum 2.7 V), load = 15 pF (stray plus probes). 2 Rev. 0 | Page 4 of 12 ADN4664 Test Circuits and Timing Diagrams VCC RINx+ SIGNAL GENERATOR ROUTx RINx– 50Ω 50Ω CL 07961-002 RECEIVER IS ENABLED CL = LOAD AND TEST JIG CAPACITANCE Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time RINx– 1.3V 0V (DIFFERENTIAL) VID = 200mV 1.2V RINx+ 1.1V tPLHD tPHLD VOH 80% 1.5V 1.5V 20% 20% tTLH tTHL Figure 3. Receiver Propagation Delay and Transition Time Waveforms Rev. 0 | Page 5 of 12 VOL 07961-003 ROUTx 80% ADN4664 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VCC to GND Input Voltage (RINx+, RINx−) to GND Output Voltage (ROUTx) to GND Operating Temperature Range Industrial Temperature Range Storage Temperature Range Junction Temperature (TJ max) Power Dissipation SOIC Package θJA Thermal Impedance Reflow Soldering Peak Temperature Pb-Free Rating −0.3 V to +4 V −0.3 V to VCC + 3.9 V −0.3 V to VCC + 0.3 V −40°C to +85°C −65°C to +150°C 150°C (TJ max − TA)/θJA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 149.5°C/W 260°C ± 5°C Rev. 0 | Page 6 of 12 ADN4664 RIN1– 1 RIN1+ 2 RIN2+ 3 ADN4664 TOP VIEW RIN2– 4 (Not to Scale) 8 VCC 7 ROUT1 6 ROUT2 5 GND 07961-004 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic RIN1− 2 RIN1+ 3 RIN2+ 4 RIN2− 5 6 GND ROUT2 7 ROUT1 8 VCC Description Receiver Channel 1 Inverting Input. When this input is more negative than RIN1+, ROUT1 is high. When this input is more positive than RIN1+, ROUT1 is low. Receiver Channel 1 Noninverting Input. When this input is more positive than RIN1−, ROUT1 is high. When this input is more negative than RIN1−, ROUT1 is low. Receiver Channel 2 Noninverting Input. When this input is more positive than RIN2−, ROUT2 is high. When this input is more negative than RIN2−, ROUT2 is low. Receiver Channel 2 Inverting Input. When this input is more negative than RIN2+, ROUT2 is high. When this input is more positive than RIN2+, ROUT2 is low. Ground reference point for all circuitry on the part. Receiver Channel 2 Output (3 V TTL/CMOS). If the differential input voltage between RIN2+ and RIN2− is positive, this output is high. If the differential input voltage is negative, this output is low. Receiver Channel 1 Output (3 V TTL/CMOS). If the differential input voltage between RIN1+ and RIN− is positive, this output is high. If the differential input voltage is negative, this output is low. Power Supply Input. This part can be operated from 3.0 V to 3.6 V. Rev. 0 | Page 7 of 12 ADN4664 TYPICAL PERFORMANCE CHARACTERISTICS 0 3.6 ILOAD = –400µA TA = 25°C VID = 200mV 3.4 3.3 3.2 3.1 3.0 –10 –15 –20 –25 –30 –35 –40 –45 3.1 3.2 3.3 3.4 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) 07961-007 3.0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) Figure 5. Output High Voltage vs. Power Supply Voltage Figure 8. Threshold Voltage vs. Power Supply Voltage 33.60 50 45 POWER SUPPLY CURRENT, ICC (mA) 33.55 33.50 33.45 33.40 33.35 33.30 40 TA = 25°C VCC = 3.3V VID = 200mV CL = 15pF 35 30 BOTH CHANNELS SWITCHING 25 20 15 10 ONE CHANNEL SWITCHING 33.25 3.1 3.2 3.3 3.4 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) 07961-008 3.0 0 0.01 0.1 1 10 FREQUENCY (MHz) 100 07961-023 ILOAD = 2mA TA = 25°C VID = –200mV 5 1000 Figure 9. Power Supply Current vs. Frequency Figure 6. Output Low Voltage vs. Power Supply Voltage 10 VOUT = 0V TA = 25°C 9 POWER SUPPLY CURRENT, ICC (mA) –37 –39 –41 –43 –45 –47 –49 –51 –53 8 7 VCC = 3.3V VID = 200mV CL = 15pF FREQUENCY = 1MHz BOTH CHANNELS SWITCHING 6 5 4 3 2 07961-024 –35 1 –55 3.0 3.1 3.2 3.3 3.4 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) 0 –40 07961-009 OUTPUT SHORT-CIRCUIT CURRENT, IOS (mA) 07961-011 –50 2.9 OUTPUT LOW VOLTAGE, VOL (mV) VOUT = 0V TA = 25°C –5 THRESHOLD VOLTAGE, VTH (mV) OUTPUT HIGH VOLTAGE, VOH (V) 3.5 Figure 7. Output Short-Circuit Current vs. Power Supply Voltage –15 10 35 AMBIENT TEMPERATURE (°C) 60 Figure 10. Power Supply Current vs. Ambient Temperature Rev. 0 | Page 8 of 12 85 ADN4664 6.0 2.3 tPHLD 2.2 2.1 tPLHD 2.0 1.9 1.8 –40 –15 10 35 60 85 AMBIENT TEMPERATURE, TA (°C) Figure 11. Differential Propagation Delay vs. Ambient Temperature 4.5 4.0 3.5 3.0 tPHLD 2.0 1.5 0.5 1.0 1.5 2.0 2.5 DIFFERENTIAL INPUT VOLTAGE, VID (V) 3.0 Figure 14. Differential Propagation Delay vs. Differential Input Voltage 250 3.0 2.5 tPLHD tPHLD 0 0.5 1.0 1.5 150 100 50 0 –50 2.0 3.0 2.5 –100 3.1 3.2 3.3 3.4 3.5 3.6 85 POWER SUPPLY VOLTAGE, VCC (V) Figure 15. Differential Skew vs. Power Supply Voltage Figure 12. Differential Propagation Delay vs. Common-Mode Voltage 160 2.30 TA = 25°C VID = 200mV FREQUENCY = 200MHz CL = 15pF 2.20 2.15 tPHLD 2.10 2.05 2.00 1.95 VCC = 3.3V VID = 200mV FREQUENCY = 200MHz CL = 15pF 140 DIFFERENTIAL SKEW, tSKEW (ps) 2.25 tPLHD 120 100 80 60 40 20 3.1 3.2 3.3 3.4 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) 07961-016 1.90 1.85 3.0 3.0 07961-018 2.0 TA = 25°C VID = 200mV FREQUENCY = 200MHz CL = 15pF 200 07961-019 3.5 DIFFERENTIAL SKEW, tSKEW (ps) TA = 25°C FREQUENCY = 200MHz VID = 200mV CL = 15pF COMMON-MODE VOLTAGE, VCM (V) DIFFERENTIAL PROPAGATION DELAY, tPLHD , tPHLD (ns) tPLHD 2.5 0 07961-015 DIFFERENTIAL PROPAGATION DELAY, tPLHD , tPHLD (ns) 5.0 1.0 4.0 1.5 VCC = 3.3V CL = 15pF FREQUENCY = 200MHz VCM = 1.2V 5.5 07961-025 2.4 DIFFERENTIAL PROPAGATION DELAY, tPLHD , tPHLD (ps) VCC = 3.3V VID = 200mV FREQUENCY = 200MHz CL = 15pF 07961-014 DIFFERENTIAL PROPAGATION DELAY, tPLHD , tPHLD (ns) 2.5 0 –40 –15 10 35 60 AMBIENT TEMPERATURE, TA (°C) Figure 16. Differential Skew vs. Ambient Temperature Figure 13. Differential Propagation Delay vs. Power Supply Voltage Rev. 0 | Page 9 of 12 ADN4664 1800 580 VCC = 3.3V VID = 200mV 560 FREQUENCY = 25MHz CL = 15pF 540 tTLH 520 500 480 460 TA = 25°C VCC = 3.3V VID = 200mV FREQUENCY = 1MHz 1600 TRANSITION TIME, tTLH, tTHL (ps) tTHL 440 1400 1200 1000 tTLH 800 tTHL 600 3.1 3.2 3.3 3.4 3.5 3.6 POWER SUPPLY VOLTAGE, VCC (V) 200 07961-020 400 3.0 07961-027 400 420 10 30 35 40 45 40 45 2.9 DIFFERENTIALPROPAGATIONDELAY, tPLHD , tPHLD (ns) VCC = 3.3V VID = 200mV FREQUENCY = 200MHz CL = 15pF 500 tTLH 450 tTHL 400 350 –40 –15 10 35 60 85 AMBIENT TEMPERATURE, TA (°C) 2.7 2.5 2.3 tPLHD 2.1 1.9 1.7 10 2.9 1600 TRANSITION TIME, tTLH, tTHL (ps) 1800 tPHLD 2.5 tPLHD 2.3 2.1 10 15 20 07961-026 TA = 25°C VCC = 3.3V VID = 200mV FREQUENCY = 1MHz 1.7 25 30 LOAD (pF) 35 40 15 20 25 30 LOAD (pF) 35 Figure 21. Differential Propagation Delay vs. Load at 200 MHz 3.1 1.9 TA = 25°C VCC = 3.3V VID = 200mV FREQUENCY = 200MHz 1.5 Figure 18. Transition Time vs. Ambient Temperature 2.7 tPHLD 45 TA = 25°C VCC = 3.3V VID = 200mV FREQUENCY = 200MHz 1400 1200 tTLH 1000 800 600 tTHL 400 07961-029 550 07961-021 TRANSITION TIME, tTLH, tTHL (ps) 25 Figure 20. Transition Time vs. Load 600 DIFFERENTIALPROPAGATIONDELAY, tPLHD , tPHLD (ns) 20 LOAD (pF) Figure 17. Transition Time vs. Power Supply Voltage 1.5 15 07961-028 TRANSITION TIME, tTLH, tTHL (ps) 600 200 0 10 15 20 25 30 35 40 LOAD (pF) Figure 19. Differential Propagation Delay vs. Load at 1 MHz Figure 22. Transition Time vs. Load at 200 MHz Rev. 0 | Page 10 of 12 45 ADN4664 THEORY OF OPERATION A differential current input signal, received via a transmission medium, such as a twisted pair cable, develops a voltage across a terminating resistor, RT. This resistor is chosen to match the characteristic impedance of the medium, typically around 100 Ω. The differential voltage is detected by the receiver and converted back into a single-ended logic signal. When the noninverting receiver input, RINx+, is positive with respect to the inverting input RINx− (current flows through RT from RINx+ to RINx−), then ROUTx is high. When the noninverting receiver input RINx+ is negative with respect to the inverting input RINx− (current flows through RT from RINx− to RINx+), then ROUTx is low. The ADN4664 differential line receiver is capable of receiving signals of 100 mV over a ±1 V common-mode range centered around 1.2 V. This relates to the typical driver offset voltage value of 1.2 V. The signal originating from the driver is centered around 1.2 V and may shift ±1 V around this center point. This ±1 V shifting may be caused by a difference in the ground potential of the driver and receiver, the common-mode effect of coupled noise, or both. Using the ADN4663 as a driver, the received differential current is between 2.5 mA and 4.5 mA (typically 3.1 mA), developing between 250 mV and 450 mV across a 100 Ω termination resis- (1.2 V − [310 mV/2]) = 1.045 V for Logic 1. For Logic 0 the inverting and noninverting input voltages are reversed. Note that because the differential voltage reverses polarity, the peak-to-peak voltage swing across RT is twice the differential voltage. Current mode signaling offers considerable advantages over voltage mode signalling, such as RS-422. The operating current remains fairly constant with increased switching frequency, whereas with voltage mode drivers the current increases exponentially in most cases. This is caused by the overlap as internal gates switch between high and low, which causes currents to flow from VCC to ground. A current mode device simply reverses a constant current between its two outputs, with no significant overlap currents. This is similar to emitter-coupled logic (ECL) and positive emittercoupled logic (PECL), but without the high quiescent current of ECL and PECL. APPLICATIONS INFORMATION Figure 23 shows a typical application for point-to-point data transmission using the ADN4663 as the driver. + 0.1µF 3.3V 10µF TANTALUM VCC DINy Rev. 0 | Page 11 of 12 3.3V 10µF TANTALUM VCC ADN4663 tor. The received voltage is centered around the receiver offset of 1.2 V. In other words, the noninverting receiver input is typically (1.2 V + [310 mV/2]) = 1.355 V, and the inverting receiver input is + 0.1µF GND DOUTy+ RINx+ RT DOUTy– 100Ω RINx– ADN4664 ROUTx GND Figure 23. Typical Application Circuit 07961-119 The ADN4664 is a dual line receiver for low voltage differential signaling. It takes a differential input signal of 310 mV typically and converts it into a single-ended 3 V TTL/CMOS logic signal. ADN4664 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 5 1 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 1.75 (0.0688) 1.35 (0.0532) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 4.00 (0.1574) 3.80 (0.1497) Figure 24. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model ADN4664BRZ1 ADN4664BRZ-REEL71 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07961-0-1/09(0) Rev. 0 | Page 12 of 12 Package Option R-8 R-8