th Aug 18 , 2009 IRS2607DSPbF HIGH AND LOW SIDE DRIVER Features • • • • • • • • • • • • • Floating channel designed for bootstrap operation Integrated bootstrap diode suitable for Complimentary PWM switching schemes only IRS2607DSPBF is suitable for sinusoidal motor control applications IRS2607DSPBF is NOT recommended for Trapezoidal motor control applications Fully operational to +600 V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 V to 20 V Undervoltage lockout for both channels 3.3 V, 5 V, and 15 V input logic compatible Matched propagation delay for both channels Lower di/dt gate driver for better noise immunity Outputs in phase with inputs RoHS compliant Packages 8-Lead SOIC Applications: *Motor Control *Air Conditioners/ Washing Machines *General Purpose Inverters *Micro/Mini Inverter Drives Description The IRS2607D is a high voltage, high speed power MOSFET and IGBT drivers with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3 V logic. The output drivers feature a high-pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration which operates up to 600 V. Typical Connection www.irf.com 1 Qualification Information † Industrial†† Comments: This IC has passed JEDEC’s Industrial qualification. IR’s Consumer qualification level is granted by extension of the higher Industrial level. Qualification Level Moisture Sensitivity Level Human Body Model ESD Machine Model IC Latch-Up Test RoHS Compliant MSL2, 260°C (per IPC/JEDEC J-STD-020) Class 2 (per JEDEC standard JESD22-A114) Class B (per EIA/JEDEC standard EIA/JESD22-A115) Class I, Level A (per JESD78) Yes † Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ †† Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. www.irf.com 2 IRS2607DSPbF Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition VB High side floating supply voltage Min. Max. -0.3 620 Units VS High side floating supply offset voltage VB - 20 VB + 0.3 VHO High side floating output voltage VS - 0.3 VB + 0.3 VCC Low side and logic fixed supply voltage -0.3 20 VLO VIN dVS/dt Low side output voltage Logic input voltage Allowable offset supply voltage transient -0.3 COM -0.3 — VCC + 0.3 VCC + 0.3 50 V/ns — 0.625 W °C/W PD RthJA Package power dissipation @ TA ≤ +25 °C Thermal resistance, junction to ambient — 200 TJ Junction temperature — 150 TS Storage temperature -50 150 — 300 TL Lead temperature (soldering, 10 seconds) Note 1: Zener clamps are included between VCC & COM, VB & VS (20V). V °C Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. The VS offset ratings are tested with all supplies biased at a 15 V differential. Symbol Definition VB High side floating supply absolute voltage VS Static High side floating supply offset voltage VSt Transient High side floating supply offset voltage VHO High side floating output voltage VCC Low side and logic fixed supply voltage VLO Low side output voltage VIN Logic input voltage TA Ambient temperature Min. Max. VS +10 VS +20 COM- 8(Note 1) 600 -50 (Note2) VS 600 VB 10 20 0 VCC COM VCC -40 125 Units V °C Note 1: Logic operational for VS of -8 V to +600 V. Logic state held for VS of -8 V to – VBS. Note 2: Operational for transient negative VS of COM - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to the Application Information section of this datasheet for more details. www.irf.com 3 IRS2607DSPbF Static Electrical Characteristics VCC = VBS = 15 V and TA = 25 °C unless otherwise specified. The VIL, VIH, and IIN parameters are referenced to COM and are applicable to the respective input leads. The VO, IO, and RON parameters are referenced to COM and are applicable to the respective output leads: HO and LO. Symbol VIH Definition Min. Typ. Max. Units Test Conditions Logic “1” input voltage 2.2 — — VIL Logic “0” input voltage — — 0.8 VOH High level output voltage — 0.8 1.4 VOL Low level output voltage — 0.3 0.6 ILK Offset supply leakage current — — 50 — 45 70 V IO = 20 mA VB = VS = 600 V IQBS Quiescent VBS supply current IQCC Quiescent VCC supply current IIN+ Logic “1” input bias current — 5 20 VIN = 4 V Logic “0” input bias current VCC and VBS supply undervoltage positive going threshold VCC and VBS supply undervoltage negative going threshold — — 2 VIN = 0 V 8.0 8.9 9.8 6.9 7.7 8.5 VCC and VBS supply undervoltage hysteresis — 1.2 — IINVCCUV+ VBSUV+ VCCUVVBSUVVCCUVH VBSUVH 400 1100 1800 IO+ Output high short circuit pulsed current 120 200 — IO- Output low short circuit pulsed current 250 350 — RBS Bootstrap resistance†† — 200 — µA VIN = 0 V or 4 V V mA VO = 0 V, PW ≤ 10 µs VO = 15 V, PW ≤ 10 µs Ω †† Integrated bootstrap diode is suitable for Complimentary PWM schemes only. IRS2607D is suitable for sinusoidal motor control applications. IRS2607D is NOT recommended for Trapezoidal motor control applications. Refer to the Integrated Bootstrap Functionality section of this datasheet for more details. Dynamic Electrical Characteristics VCC = VBS = 15 V, CL = 1000 pF, TA = 25 °C Symbol Definition Min. Typ. Max. Units Test Conditions ton Turn-on propagation delay — 515 715 VS = 0 V or 600 V toff Turn-off propagation delay — 500 700 VS = 0 V or 600 V MT Delay matching, HS & LS turn-on/off — — 50 tr Turn-on rise time — 150 220 tf Turn-off fall time — 50 80 tfil Minimum pulse input filter time — 300 — www.irf.com ns VS = 0 V 4 IRS2607DSPbF Lead Definitions Symbol Description HIN LIN VB Logic input for high side gate driver output (HO), in phase Logic input for low side gate driver output (LO), in phase High side floating supply HO VS High side gate drive output High side floating supply return VCC Low side and logic fixed supply LO Low side gate drive output COM Low side return Lead Assignments 1 VCC VB 8 2 HIN HO 7 3 LIN VS 6 4 COM LO 5 8 Lead SOIC IRS2607DS www.irf.com 5 IRS2607DSPbF Functional Block Diagrams www.irf.com 6 IRS2607DSPbF Application Information and Additional Details Informations regarding the following topics are included as subsections within this section of the datasheet. • • • • • • • • • • • IGBT/MOSFET Gate Drive Switching and Timing Relationships Matched Propagation Delays Input Logic Compatibility Undervoltage Lockout Protection Advanced Input Filter Short-Pulse / Noise Rejection Integrated Bootstrap Functionality Negative VS Transient SOA PCB Layout Tips Additional Documentation IGBT/MOSFET Gate Drive The IRS2607D HVICs are designed to drive MOSFET or IGBT power devices. Figures 1 and 2 illustrate several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch is defined as VHO for the high-side power switch and VLO for the low-side power switch; this parameter is sometimes generically called VOUT and in this case does not differentiate between the high-side or low-side output voltage. VB (or VCC) VB (or VCC) IO+ HO (or LO) + HO (or LO) IO- VHO (or VLO) VS (or COM) - Figure 1: HVIC sourcing current www.irf.com VS (or COM) Figure 2: HVIC sinking current 7 IRS2607DSPbF Switching and Timing Relationships The relationships between the input and output signals of the IRS2607D are illustrated below in Figures 3, 4. From these figures, we can see the definitions of several timing parameters (i.e., PW IN, PW OUT, tON, tOFF, tR, and tF) associated with this device. LINx (or HINx) 50% 50% PWIN tON LOx (or HOx) tOFF tR tF PWOUT 90% 10% 90% 10% Figure 3: Switching time waveforms Figure 4: Input/output timing diagram Matched Propagation Delays The IRS2607D family of HVICs is designed with propagation delay matching circuitry. With this feature, the IC’s response at the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both the low-side channels and the high-side channels; the maximum difference is specified by the delay matching parameter (MT). The propagation turn-on delay (tON) of the IRS2607D is matched to the propagation turn-on delay (tOFF). www.irf.com 8 IRS2607DSPbF Figure 5: Delay Matching Waveform Definition Input Logic Compatibility The inputs of this IC are compatible with standard CMOS and TTL outputs. The IRS2607D has been designed to be compatible with 3.3 V and 5 V logic-level signals. Figure 8 illustrates an input signal to the IRS2607D, its input threshold values, and the logic state of the IC as a result of the input signal. Input Signal (IRS23364D) V IH Input Logic Level VIL High Low Low Figure 6: HIN & LIN input thresholds www.irf.com 9 IRS2607DSPbF Undervoltage Lockout Protection This family of ICs provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply and the VBS (high-side circuitry) power supply. Figure 7 is used to illustrate this concept; VCC (or VBS) is plotted over time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is enabled or disabled. Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turn-on. Additionally, if the VCC voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will recognize a fault condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition to the low state to inform the controller of the fault condition. Upon power-up, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turn-on. Additionally, if the VBS voltage decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will recognize a fault condition, and shutdown the high-side gate drive outputs of the IC. The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could be driven with a low voltage, resulting in the power switch conducting current while the channel impedance is high; this could result in very high conduction losses within the power device and could lead to power device failure. Figure 7: UVLO protection www.irf.com 10 IRS2607DSPbF Advanced Input Filter The advanced input filter allows an improvement in the input/output pulse symmetry of the HVIC and helps to reject noise spikes and short pulses. This input filter has been applied to the HIN ans LIN inputs. The working principle of the new filter is shown in Figures 8 and 9. Figure 8 shows a typical input filter and the asymmetry of the input and output. The upper pair of waveforms (Example 1) show an input signal with a duration much longer then tFIL,IN; the resulting output is approximately the difference between the input signal and tFIL,IN. The lower pair of waveforms (Example 2) show an input signal with a duration slightly longer then tFIL,IN; the resulting output is approximately the difference between the input signal and tFIL,IN. Figure 9 shows the advanced input filter and the symmetry between the input and output. The upper pair of waveforms (Example 1) show an input signal with a duration much longer then tFIL,IN; the resulting output is approximately the same duration as the input signal. The lower pair of waveforms (Example 2) show an input signal with a duration slightly longer then tFIL,IN; the resulting output is approximately the same duration as the input signal. Figure 8: Typical input filter Figure 9: Advanced input filter Short-Pulse / Noise Rejection Example 2 Example 1 This device’s input filter provides protection against short-pulses (e.g., noise) on the input lines. If the duration of the input signal is less than tFIL,IN, the output will not change states. Example 1 of Figure 10 shows the input and output in the low state with positive noise spikes of durations less than tFIL,IN; the output does not change states. Example 2 of Figure 10 shows the input and output in the high state with negative noise spikes of durations less than tFIL,IN; the output does not change states. Figure 10: Noise rejecting input filters www.irf.com 11 IRS2607DSPbF Figures 11 and 12 present lab data that illustrates the characteristics of the input filters while receiving ON and OFF pulses. The input filter characteristic is shown in Figure 11; the left side illustrates the narrow pulse ON (short positive pulse) characteristic while the left shows the narrow pulse OFF (short negative pulse) characteristic. The x-axis of Figure 11 shows the duration of PW IN, while the y-axis shows the resulting PW OUT duration. It can be seen that for a PW IN duration less than tFIL,IN, that the resulting PW OUT duration is zero (e.g., the filter rejects the input signal/noise). We also see that once the PW IN duration exceed tFIL,IN, that the PW OUT durations mimic the PW IN durations very well over this interval with the symmetry improving as the duration increases. To ensure proper operation of the HVIC, it is suggested that the input pulse width for the high-side inputs be ≥ 500 ns. Time (ns) The difference between the PW OUT and PW IN signals of both the narrow ON and narrow OFF cases is shown in Figure 12; the careful reader will note the scale of the y-axis. The x-axis of Figure 12 shows the duration of PW IN, while the yaxis shows the resulting PW OUT–PW IN duration. This data illustrates the performance and near symmetry of this input filter. Figure 11: IRS2607D input filter characteristic Figure 12: Difference between the input pulse and the output pulse www.irf.com 12 IRS2607DSPbF Integrated Bootstrap Functionality The IRS2607D embeds an integrated bootstrap FET that allows an alternative drive of the bootstrap supply for a wide range of applications. A bootstrap FET is connected between the floating supply VB and VCC (see Fig. 13). Vcc BootFet Vb Figure 13: Semplified BootFET connection The bootstrap FET is suitable for complimentary PWM switching schemes only. Complimentary PWM refers to PWM schemes where the HIN & LIN input signals are alternately switched on and off. IRS2607D is suitable for sinusoidal motor control and the integrated bootstrap feature can be used either in parallel with the external bootstrap network (diode and resistor) or as a replacement of it. The use of the integrated bootstrap as a replacement of the external bootstrap network may have some limitations at very high PWM duty cycle, corresponding to very short LIN pulses, due to the bootstrap FET equivalent resistance RBS. IRS2607D is NOT recommended for trapezoidal motor control, even if an external bootstrap network is employed in parallel. The summary for the bootstrap state follows: • Bootstrap turns-off (immediately) or stays off when at least one of the following conditions are met: 1- HO goes/is high 2- VB goes/is high (> 1.1*VCC) • Bootstrap turns-on when: 1- LO is high (low side is on) AND VB is low (< ~1.1(VCC)) 2- LO and HO are low after a LIN transition from H to L (HB output is in tri-state) AND VB goes low (<1.1*VCC) before a fixed time of 20us. 3- LO and HO are low after a HIN transition from H to L (HB output is in tri-state) AND VB goes low (<1.1(VCC)) before a retriggerable time of 20us. In this case the time counter is kept in reset state until VB goes high (>1.1VCC). Please refer to the BootFET timing diagram for more details. www.irf.com 13 IRS2607DSPbF 20 us timer Timer is reset counter Timer is reset Timer expired HIN LIN BootStrap Fet VB 1.1*Vcc + - Figure 14: BootFET timing diagram www.irf.com 14 IRS2607DSPbF Tolerant to Negative VS Transients A common problem in today’s high-power switching converters is the transient response of the switch node’s voltage as the power switches transition on and off quickly while carrying a large current. A typical 3-phase inverter circuit is shown in Figure 15; here we define the power switches and diodes of the inverter. If the high-side switch (e.g., the IGBT Q1 in Figures 16 and 17) switches off, while the U phase current is flowing to an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the low-side switch of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive DC bus voltage to the negative DC bus voltage. Figure 15: Three phase inverter DC+ BUS Q1 ON IU VS1 Q2 OFF D2 DC- BUS Figure 16: Q1 conducting Figure 17: D2 conducting Also when the V phase current flows from the inductive load back to the inverter (see Figures 18 and 19), and Q4 IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2, swings from the positive DC bus voltage to the negative DC bus voltage. www.irf.com 15 IRS2607DSPbF Figure 18: D3 conducting Figure 19: Q4 conducting However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather it swings below the level of the negative DC bus. This undershoot voltage is called “negative VS transient”. The circuit shown in Figure 20 depicts one leg of the three phase inverter; Figures 21 and 22 show a simplified illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from the die bonding to the PCB tracks are lumped together in LC and LE for each IGBT. When the high-side switch is on, VS1 is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic elements of the circuit. When the high-side power switch turns off, the load current momentarily flows in the low-side freewheeling diode due to the inductive load connected to VS1 (the load is not shown in these figures). This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative voltage between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the VS pin). Figure 20: Parasitic Elements Figure 21: VS positive Figure 22: VS negative In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS transient voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is greater than in normal operation. International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding applications. An indication of the IRS2607D’s robustness can be seen in Figure 23, where there is represented the IRS2607D Safe Operating Area at VBS=15V based on repetitive negative VS spikes. A negative VS transient voltage falling in the grey area (outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent damage to the IC do not appear if negative Vs transients fall inside SOA. At VBS=15V in case of -VS transients greater than -16.5 V for a period of time greater than 50 ns; the HVIC will hold by design the high-side outputs in the off state for 4.5 µs. www.irf.com 16 IRS2607DSPbF Figure 23: Negative VS transient SOA for IRS2607D @ VBS=15V Even though the IRS2607D has been shown able to handle these large negative VS transient conditions, it is highly recommended that the circuit designer always limit the negative VS transients as much as possible by careful PCB layout and component use. PCB Layout Tips Distance between high and low voltage components: It’s strongly recommended to place the components tied to the floating voltage pins (VB and VS) near the respective high voltage portions of the device. Please see the Case Outline information in this datasheet for the details. Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high voltage floating side. Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure 24). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect. www.irf.com 17 IRS2607DSPbF Figure 24: Antenna Loops Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and COM pins. A ceramic 1 µF ceramic capacitor is suitable for most applications. This component should be placed as close as possible to the pins in order to reduce parasitic elements. Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions, it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side emitter to negative bus rail stray inductance. However, where negative VS spikes remain excessive, further steps may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between the VS pin and the switch node (see Figure 25), and in some cases using a clamping diode between COM and VS (see Figure 26). See DT04-4 at www.irf.com for more detailed information. Figure 25: VS resistor Figure 26: VS clamping diode Additional Documentation Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search function and the document number to quickly locate them. Below is a short list of some of these documents. DT97-3: Managing Transients in Control IC Driven Power Stages AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality DT04-4: Using Monolithic High Voltage Gate Drivers AN-978: HV Floating MOS-Gate Driver ICs www.irf.com 18 IRS2607DSPbF 1500 Turn-off Propagation Delay (ns) Turn-on Propagation Delay (ns) Figures 27-48 provide information on the experimental performance of the IRS2607DS HVIC. The line plotted in each figure is generated from actual lab data. A large number of individual samples from multiple wafer lots were tested at three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The line labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have been connected together to illustrate the understood trend. The individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). 1200 900 Exp. 600 300 0 -50 -25 0 25 50 75 100 1000 800 600 Exp. 400 200 0 125 -50 -25 0 o 50 75 100 125 Temperature (oC) Temperature ( C) Fig. 27. Turn-on Propagation Delay vs. Temperature Fig. 28. Turn-off Propagation Delay vs. Temperature 250 125 Turn-Off fall Time (ns) Turn-On Rise Time (ns) 25 200 150 100 Exp. 100 75 50 Exp. 50 25 0 0 -50 -25 0 25 50 75 100 o Temperature ( C) Fig. 29. Turn-on Rise Time vs. Temperature www.irf.com 125 -50 -25 0 25 50 75 100 125 o Temperature ( C) Fig. 30. Turn-off Rise Time vs. Temperature 19 Output High SC pulsed current (A) 3 2 1 Exp. 0 -50 -25 0 25 50 75 100 125 Output low short circuit pulsed current (A) IRS2607DSPbF 3 2 1 Exp. 0 -50 -25 0 25 Temperature (oC) 4 VCC supply UV hysteresis ( V) Tbson_TYP (ns) 125 Fig. 32. Output Low Short Circuit Pulsed Current vs. Temperature 1200 900 Exp. 600 300 0 -50 -25 0 25 50 75 100 125 3 2 Exp. 1 0 -50 -25 0 25 Temperature ( C) 4 3 2 Exp. 0 0 25 50 75 100 125 Fig. 34. VCC Supply UV Hysteresis vs. Temperature 75 100 125 o Temperature ( C) Fig. 35. VBS Supply UV Hysteresis vs. Temperature V CC Quiescent Supply Current (mA) Fig. 33. Tbson_TYP vs. Temperature -25 50 Temperature (oC) o VBS supply UV hysteresis (V) 100 Temperature ( C) 1500 -50 75 o Fig. 31. Output High SC Pulsed Current vs. Temperature 1 50 10 8 6 4 2 Exp. 0 -50 -25 0 25 50 75 100 125 o Temperature ( C) Fig. 36. VCC Quiescent Supply Current vs. Temperature www.irf.com 20 12 100 80 VCCUV+ Threshold (V) VBS Quiescent Supply Current (uA) IRS2607DSPbF 60 Exp. 40 20 9 Exp. 6 3 0 0 -50 -25 0 25 50 75 100 -50 125 -25 0 25 o 50 75 100 125 o Temperature ( C) Temperature ( C) Fig. 37. VBS Quiescent Supply Current vs. Fig. 38. VCCUV+ Threshold vs. Temperature Temperature 12 9 V BSUV+ Threshold (V) VCCUV- Threshold (V) 12 Exp. 6 3 9 Exp. 6 3 0 0 -50 -25 0 25 50 75 100 -50 125 -25 0 25 75 100 125 Temperature ( C) Temperature ( C) Fig. 40. VBSUV+ Threshold vs. Temperature Fig. 39. VCCUV- Threshold vs. Temperature 1500 300 200 EXP. 100 0 -50 -25 0 25 50 75 100 Temperature (oC) Fig. Fig.22. 41.Low Low Level LevelOutput OutputVoltage Voltage vs.vs. Temperature Temperature www.irf.com 125 High level output voltage (mV). 400 Low level output voltage (mV) 50 o o 1200 900 Exp. 600 300 0 -50 -25 0 25 50 75 100 125 o Temperature ( C) Fig. 42. High Level Output Voltage vs. Temperature 21 12 500 400 VBSUV- Threshold (V) Bootstrap resistance VCC type (Ohm) IRS2607DSPbF 300 200 Exp. 100 9 Exp. 6 3 0 0 -50 -25 0 25 50 75 100 -50 125 -25 0 50 75 100 125 Temperature ( C) Temperature ( C) Fig. 43. Bootstrap Resistance VCC type vs. Fig. 44. VBSUV- Threshold vs. Temperature Temperature 8 8 6 6 Lin_VTH- (V) Lin_VTH+ (V) 25 o o 4 Exp. 2 4 2 Exp. 0 0 -50 -25 0 25 50 75 100 -50 125 -25 0 50 75 100 125 Fig. 46. Lin_VTH- vs. Temperature 8 8 6 6 Hin_VTH- (V) Hin_VTH+ (V) Fig. 45. Lin_VTH+ vs. Temperature 4 Exp. 2 25 Temperature (oC) Temperature (oC) 4 2 Exp. 0 0 -50 -25 0 25 50 75 100 o Temperature ( C) Fig. 47. Hin_VTH+ vs. Temperature www.irf.com 125 -50 -25 0 25 50 75 100 o Temperature ( C) Fig. 48. Hin_VTH- vs. Temperature 22 125 IRS2607DSPbF Case Outlines www.irf.com 23 IRS2607DSPbF Tape and Reel Details: 8L-SOIC LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR Metric Code Min Max A 7.90 8.10 B 3.90 4.10 C 11.70 12.30 D 5.45 5.55 E 6.30 6.50 F 5.10 5.30 G 1.50 n/a H 1.50 1.60 8SOICN Imperial Min Max 0.311 0.318 0.153 0.161 0.46 0.484 0.214 0.218 0.248 0.255 0.200 0.208 0.059 n/a 0.059 0.062 F D C B A E G H REEL DIMENSIONS FOR 8SOICN Metric Code Min Max A 329.60 330.25 B 20.95 21.45 C 12.80 13.20 D 1.95 2.45 E 98.00 102.00 F n/a 18.40 G 14.50 17.10 H 12.40 14.40 www.irf.com Imperial Min Max 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 n/a 0.724 0.570 0.673 0.488 0.566 24 IRS2607DSPbF ORDER INFORMATION 8-Lead SOIC IRS2607DSPbF 8-Lead SOIC Tape & Reel IRS2607DSTRPbF The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document supersedes and replaces all information previously supplied. For technical support, please contact IR’s Technical Assistance Center http://www.irf.com/technical-info/ WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 www.irf.com 25