IRF IR3500AMTRPBF

IR3500A
DATA SHEET
XPHASE3TM VR11.0 & AMD PVID CONTROL IC
DESCRIPTION
TM
The IR3500A Control IC combined with an xPHASE3 Phase IC provides a full featured and flexible way
to implement a complete VR11.0 or AMD PVID power solution. The Control IC provides overall system
control and interfaces with any number of Phase ICs which each drive and monitor a single phase of a
TM
multiphase converter. The XPhase3
architecture implements a power supply that is smaller, less
expensive, and easier to design while providing higher efficiency than conventional approaches.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1 to X phase operation with matching Phase IC
VID Select pin configures AMD 5 or 6 bit PVID, Intel VR11 with/out startup to 1.1V Boot voltage
0.5% overall system set point accuracy
Programmable 250kHz to 9MHz Daisy-chain digital phase timing clock oscillator frequency provides a
per phase switching frequency of 250kHz to 1.5MHz without external components
Programmable Dynamic VID Slew Rate
Programmable VID Offset or No Offset
Programmable Load Line Output Impedance
High speed error amplifier with wide bandwidth of 30MHz and fast slew rate of 12V/us
Programmable converter current limit during soft start, hiccup with delay during normal operation
Central over voltage detection with programmable threshold and communication to phase ICs
Over voltage signal output to system with overvoltage detection during powerup and normal operation
Detection and protection of open remote sense line and open control loop
IC bias linear regulator control with programmable output voltage and UVLO
Programmable VRHOT function monitors temperature of power stage through a NTC thermistor
Remote sense amplifier with true converter voltage sensing and less than 50uA bias current
Simplified PGOOD output provides indication of proper operation and avoids false triggering
Small thermally enhanced 32L 5mm x 5mm MLPQ package
RoHS Compliant
Optional
To Converter
FUSE
Q1
12V
VCCL
RVCCLFB1
RVCCLFB2
RVCCLDRV
CVCCL
4.7uF
ROVP1
Q3
SCR
Q2
ROVP2
PGOOD
VID3
CLKOUT
25
28
26
29
30
27
PHSIN
VCCL
VCCLFB
PHSOUT
VDAC
OCSET
VID2
VSETPT
EAOUT
VDRP
24
23
22
21
20
19
ROSC
CSS/DEL
RVDAC
CVDAC
6 Wire
Bus to
Phase
ICs
ROCSET
RVSETPT
VDAC
18
17
16
FB
15
VO
IIN
14
VID0
VOSEN+
VID1
VOSEN-
8
VID4
HOTSET
VID0
SS/DEL
IR3500A
CONTROL
IC
13
7
VID5
12
6
VID1
LGND
ROSC / OVP
9
VID2
VID6
11
5
VCCLDRV
32
4
VID3
VIDSEL
VID4
VID7
PGOOD
VID5
3
VRHOT
2
ENABLE
1
VID6
10
VID7
31
VIDSEL
ENABLE
VRHOT
RHOTSET2
RFB1
RFB
CFB
CDRP
RDRP
RCP
CCP
CCP1
RHOTSET1
VCC SENSE +
To Load
VSS SENSE -
RFB2
RTHERMISTOR1
RTHERMISTOR2
Close to
Power Stage
Figure 1 – Application Circuit
Page 1 of 48
July 28, 2009
IR3500A
ORDERING INFORMATION
Device
Package
Order Quantity
IR3500A MTRPBF
32 Lead MLPQ
3000 per reel
(5 x 5 mm body)
* IR3500A MPBF
32 Lead MLPQ
*Samples only
(5 x 5 mm body)
100 piece strips
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed below may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied.
o
o
Operating Junction Temperature…………….. 0 C to 150 C
o
o
Storage Temperature Range………………….-65 C to 150 C
ESD Rating………………………………………HBM Class 1C JEDEC Standard
MSL Rating………………………………………2
o
Reflow Temperature…………………………….260 C
PIN #
PIN NAME
VMAX
VMIN
ISOURCE
ISINK
1-8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
VID7-0
ENABLE
VRHOT
HOTSET
VOSENVOSEN+
VO
FB
EAOUT
VDRP
IIN
VSETPT
OCSET
VDAC
SS/DEL
ROSC/OVP
7.5V
3.5V
7.5V
7.5V
1.0V
7.5V
7.5V
7.5V
7.5V
7.5V
7.5V
3.5V
7.5V
3.5V
7.5V
7.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
1mA
1mA
1mA
1mA
5mA
5mA
5mA
1mA
25mA
35mA
100mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
50mA
1mA
1mA
1mA
25mA
1mA
10mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
24
LGND
n/a
n/a
20mA
1mA
25
26
27
CLKOUT
PHSOUT
PHSIN
7.5V
7.5V
7.5V
-0.3V
-0.3V
-0.3V
100mA
10mA
1mA
100mA
10mA
1mA
28
VCCL
7.5V
-0.3V
1mA
20mA
29
VCCLFB
3.5V
-0.3V
1mA
1mA
30
VCCLDRV
10V
-0.3V
1mA
50mA
31
PGOOD
VCCL + 0.3V
-0.3V
1mA
20mA
32
VIDSEL
7.5V
-0.3V
5mA
1mA
Page 2 of 48
July 28, 2009
IR3500A
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
o
o
4.75V ≤ VCCL ≤ 7.5V, -0.3V ≤ VOSEN- ≤ 0.3V, 0 C ≤ TJ ≤ 100 C, 7.75KΩ ≤ ROSC ≤ 50.0 KΩ
ELECTRICAL SPECIFICATIONS
The electrical characteristics involve the spread of values guaranteed within the recommended operating
conditions. Typical values represent the median values, which are related to 25°C. CSS/DEL = 0.1µF +/-10%.
PARAMETER
VDAC Reference
System Set-Point Accuracy
(Deviation from Tables 2 & 4
per test circuit in Fig.3 and
Table 3 per test circuit in Fig.2)
Source & Sink Currents
VR11 VIDx Input Threshold
AMD VIDx Input Threshold
VR11 VIDx Input Bias Current
AMD 6-bit VIDx Pull-down
Resistance
VIDx OFF State Blanking Delay
VIDSEL Threshold between
AMD 5-bit VID and AMD 6-bit
VID
VIDSEL Threshold between
AMD 6-bit VID and VR11 with
Boot Voltage
VIDSEL Threshold between
VR11 with/out Boot Voltage
VIDSEL Float Voltage
VIDSEL Pull-up Resistance
Oscillator
ROSC Voltage
CLKOUT High Voltage
CLKOUT Low Voltage
PHSOUT Frequency
PHSOUT Frequency
PHSOUT Frequency
PHSOUT High Voltage
PHSOUT Low Voltage
PHSIN Threshold Voltage
Page 3 of 48
TEST CONDITION
MIN
TYP
MAX
UNIT
%
mV
mV
mV
µA
mV
V
VID ≥ 1V
0.8V ≤ VID < 1V
0.5V ≤ VID < 0.8V
0.3V ≤ VID < 0.5V
Include OCSET and VSETPT currents
Float VIDSEL or tie VIDSEL to VCCL
R(VIDSEL) = 6.49kΩ or connect
VIDSEL to LGND.
Float VIDSEL, or connect VIDSEL to
VCCL or LGND. 0V≤V(VIDx)≤2.5V.
R(VIDSEL) = 6.49kΩ
-0.5
-5
-8
-8
30
500
0.85
44
600
1.00
0.5
5
8
8
58
700
1.15
-1
0
1
µA
100
175
250
kΩ
Measure time till PGOOD drives low
Note 3.
0.5
0.48
1.3
0.6
2.1
0.75
µs
V
84
87
90
%
2.97
3.30
3.63
V
77
83
89
%
3.0
4.0
5.0
KΩ
0.570
0.595
0.620
1
V
V
225
450
1.35
250
500
1.50
1
275
550
1.65
1
V
kHz
kHz
MHz
V
1
70
V
%
Relative to VIDSEL float voltage.
Note 3.
Note 3.
Relative to VIDSEL Threshold between
VR11 with/out Boot Voltage
I(CLKOUT)= -10 mA, measure V(VCCL)
– V(CLKOUT).
I(CLKOUT)= 10 mA
ROSC = 50.0 KΩ
ROSC = 24.5 KΩ
ROSC = 7.75 KΩ
I(PHSOUT)= -1 mA, measure V(VCCL)
– V(PHSOUT)
I(PHSOUT)= 1 mA
Compare to V(VCCL)
30
50
July 28, 2009
IR3500A
PARAMETER
Soft Start and Delay
Start Delay (TD1)
Soft Start Time (TD2)
VID Sample Delay (TD3)
PGOOD Delay (TD4 + TD5)
OC Delay Time
SS/DEL to FB Input Offset
Voltage
Charge Current
Discharge Current
Charge/Discharge Current Ratio
Charge Voltage
Delay Comparator Threshold
Delay Comparator Threshold
TEST CONDITION
To reach 1.1V
V(IIN) – V(OCSET) = 500 mV
With FB = 0V, adjust V(SS/DEL) until
EAOUT drives high
TYP
MAX
UNIT
1.0
0.8
0.3
0.5
75
0.7
2.9
2.2
1.2
1.2
125
1.4
3.5
3.25
3.0
2.3
300
1.9
Ms
Ms
Ms
Ms
us
V
35.0
2.5
10
52.5
4.5
12
3.75
80
70.0
6.5
16
µA
µA
µA/µA
V
mV
Relative to Charge Voltage, SS/DEL
rising
Relative to Charge Voltage, SS/DEL
falling
Delay Comparator Hysteresis
VID Sample Delay Comparator
Threshold
Discharge Comp. Threshold
Remote Sense Differential Amplifier
Unity Gain Bandwidth
Note 1
Input Offset Voltage
0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V
Source Current
0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V
Sink Current
0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V
Slew Rate
0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V
Note1
VOSEN+ Bias Current
0.5 V < V(VOSEN+) < 1.6V
VOSEN- Bias Current
-0.3V ≤ VOSEN- ≤ 0.3V, All VID Codes
VOSEN+ Input Voltage Range
V(VCCL)=7V
High Voltage
V(VCCL) – V(VO)
Low Voltage
V(VCCL)=7V
Error Amplifier
Input Offset Voltage
Measure V(FB) – V(VSETPT). Note 2
FB Bias Current
VSETPT Bias Current
ROSC= 24.5 KΩ
DC Gain
Note 1
Bandwidth
Note 1
Slew Rate
Note 1
Sink Current
Source Current
Minimum Voltage
Maximum Voltage
Measure V(VCCL) – V(EAOUT)
Page 4 of 48
MIN
110
mV
30
3.0
mV
V
150
200
275
mV
3.0
-3
0.5
2
2
6.4
0
1.0
12
4
9.0
3
1.7
18
8
MHz
mV
mA
mA
V/us
30
30
50
50
5.5
1
250
uA
uA
V
V
mV
1
1
25.50
120
40
20
1.00
12
250
950
mV
0.5
-1
-1
23.00
100
20
7
0.40
5
500
0
0
24.25
110
30
12
0.85
8
120
780
July 28, 2009
µA
µA
dB
MHz
V/µs
mA
mA
mV
mV
IR3500A
PARAMETER
Open Voltage Loop Detection
Threshold
Open Voltage Loop Detection
Delay
Enable Input
VR 11 Threshold Voltage
VR 11 Threshold Voltage
VR 11 Hysteresis
AMD Threshold Voltage
AMD Threshold Voltage
AMD Hysteresis
Bias Current
Blanking Time
TEST CONDITION
Measure V(VCCL) - V(EAOUT),
Relative to Error Amplifier maximum
voltage.
Measure PHSOUT pulse numbers from
V(EAOUT) = V(VCCL) to PGOOD =
low.
MIN
125
ENABLE rising
ENABLE falling
825
775
25
1.1
1.05
30
-5
75
850
800
50
1.2
1.14
50
0
250
875
825
75
1.3
1.23
80
5
400
mV
mV
mV
V
V
mV
-30
23.25
-13
24.50
4096
2048
1024
0
25.75
mV
-10
0.50
35
0.75
0
1.00
55
2.00
10
1.75
75
3.00
ENABLE rising
ENABLE falling
0V ≤ V(ENABLE) ≤ 3.3V
Noise Pulse < 100ns will not register an
ENABLE state change. Note 1
Over-Current Comparator
Input Offset Voltage
1V ≤ V(OCSET) ≤ 3.3V
OCSET Bias Current
ROSC= 24.5 KΩ
Over-Current Delay Counter
ROSC = 7.75 KΩ (PHSOUT=1.5MHz)
Over-Current Delay Counter
ROSC = 15.0 KΩ (PHSOUT=800kHZ)
Over-Current Delay Counter
ROSC = 50.0 KΩ (PHSOUT=250kHz)
Over-Current Limit Amplifier
Input Offset Voltage
Transconductance
Note 1
Sink Current
Unity Gain Bandwidth
Over Voltage Protection (OVP) Comparators
Threshold at Power-up
Threshold during Normal
Compare to V(VDAC)
Operation
OVP Release Voltage during
Compare to V(VDAC)
Normal Operation
Threshold during Dynamic VID
down
Dynamic VID Detect
Comparator Threshold
Propagation Delay to IIN
Measure time from V(VO) > V(VDAC)
(250mV overdrive) to V(IIN) transition to
> 0.9 * V(VCCL).
IIN Pull-up Resistance
Propagation Delay to OVP
Measure time from V(VO) > V(VDAC)
(250mV overdrive) to V(ROSC/OVP)
transition to >1V.
OVP High Voltage
Measure V(VCCL)-V(ROSC/OVP)
OVP Power-up High Voltage
V(VCCLDRV)=1.8V. Measure V(VCCL)V(ROSC/OVP)
Page 5 of 48
TYP
300
MAX
600
8
UNIT
mV
Pulses
µA
ns
µA
Cycle
Cycle
Cycle
mV
mA/V
uA
kHz
1.60
110
1.73
130
1.83
150
V
mV
-13
3
20
mV
1.70
1.73
1.75
V
25
50
75
mV
90
180
ns
5
90
0
0
15
180
Ω
ns
1.2
0.2
V
V
July 28, 2009
IR3500A
PARAMETER
TEST CONDITION
MIN
VDRP Buffer Amplifier
Input Offset Voltage
V(VDRP) – V(IIN), 0.5V ≤ V(IIN) ≤ 3.3V
-5
Source Current
0.5V ≤ V(IIN) ≤ 3.3V
2
Sink Current
0.5V ≤ V(IIN) ≤ 3.3V
0.2
Unity Gain Bandwidth
Note 1
Slew Rate
Note 1
IIN Bias Current
-1
PGOOD Output
Output Voltage
I(PGOOD) = 4mA
Leakage Current
V(PGOOD) = 5.5V
Under Voltage Threshold-VO
Reference to VDAC
-380
decreasing
Under Voltage Threshold-VO
Reference to VDAC
-315
increasing
Under Voltage Threshold
25
Hysteresis
VCCL_DRV Activation
I(PG)=4mA, V(PG)<300mV, V(VCCL)=0
1
Threshold
Open Sense Line Detection
Sense Line Detection Active
150
Comparator Threshold Voltage
Sense Line Detection Active
V(VO) < [V(VOSEN+) – V(LGND)] / 2
35
Comparator Offset Voltage
VOSEN+ Open Sense Line
Compare to V(VCCL)
87.5
Comparator Threshold
VOSEN- Open Sense Line
0.36
Comparator Threshold
Sense Line Detection Source
V(VO) = 100mV
200
Currents
VRHOT Comparator
Threshold Voltage
1.584
HOTSET Bias Current
-1
Hysteresis
75
Output Voltage
I(VRHOT) = 30mA
VRHOT Leakage Current
V(VRHOT) = 5.5V
VCCL Regulator Amplifier
Reference Feedback Voltage
1.15
VCCLFB Bias Current
-1
VCCLDRV Sink Current
10
UVLO Start Threshold
Compare to V(VCCL)
91
UVLO Stop Threshold
Compare to V(VCCL)
83
Hysteresis
Compare to V(VCCL)
7
General
VCCL Supply Current
3.0
Note 1: Guaranteed by design, but not tested in production
Note 2: VDAC Output is trimmed to compensate for Error Amplifier input offset errors
Note 3: See VIDSEL Functionality Table
Page 6 of 48
TYP
MAX
UNIT
3
11
30
0.6
mV
mA
mA
MHz
0.4
8
4.7
0
1
V/µs
µA
150
0
-330
300
10
-280
µA
mV
-265
-215
mV
95
mV
60
mV
2
3.6
V
200
250
mV
60
85
mV
90.0
92.5
%
0.40
0.44
V
500
700
uA
1.600
0
100
150
0
1.616
1
125
400
10
V
1.19
0
30
93
87
8.25
1.23
1
99
91
9.5
V
uA
mA
%
%
%
6.5
10.0
mA
July 28, 2009
µA
mV
mV
µA
IR3500A
SYSTEM SET POINT TEST
IR3500
ERROR
AMPLIFIER
VDAC
BUFFER
AMPLIFIER
EAOUT
1k
+
-
FB
+
VSETPT
ISOURCE
FAST
VDAC
RVDAC
VDAC
ISINK
OCSET ROCSET
-
IVDAC
IOCSET
IVSETPT
IROSC
IROSC
ROSC BUFFER
AMPLIFIER
0.6V
LGND
+
CURRENT
SOURCE
GENERATOR
CVDAC
IROSC
ROSC
ROSC
VO
EAOUT
SYSTEM
SET POINT
VOSNSVOLTAGE
REMOTE SENSE
AMPLIFIER
VOSEN+
+
VOSEN-
-
Figure 2 - System Set Point Test Circuit for VR11 VID
IR3500
ERROR
AMPLIFIER
VDAC
BUFFER
AMPLIFIER
EAOUT
+
-
FB
+
VSETPT RVSETPT
ISOURCE
FAST
VDAC
1k
VDAC
RVDAC
OCSET
ISINK
ROCSET
-
IVDAC
IOCSET
IVSETPT
IROSC
CURRENT
SOURCE
GENERATOR
CVDAC
ROSC BUFFER
AMPLIFIER
0.6V
LGND
+
IROSC
IROSC
ROSC
ROSC
VO
EAOUT
SYSTEM
SET POINT
VOSNSVOLTAGE
REMOTE SENSE
AMPLIFIER
VOSEN+
VOSEN-
+
-
Figure 3 - System Set Point Test Circuit for AMD VIDs (VDAC shifted +50 mV)
Page 7 of 48
July 28, 2009
IR3500A
PIN DESCRIPTION
PIN#
1-8
9
PIN SYMBOL
VID7-0
ENABLE
10
VRHOT
11
HOTSET
12
13
14
15
16
17
VOSENVOSEN+
VO
FB
EAOUT
VDRP
18
IIN
19
VSETPT
20
OCSET
21
VDAC
22
SS/DEL
23
ROSC/OVP
24
25
LGND
CLKOUT
26
PHSOUT
27
28
PHSIN
VCCL
29
VCCLFB
30
VCCLDRV
31
VRRDY
32
VIDSEL
Page 8 of 48
PIN DESCRIPTION
Inputs to VID D to A Converter.
Enable input. A logic low applied to this pin puts the IC into fault mode. Do not float this pin
as the logic state will be undefined.
Open collector output of the VRHOT comparator which drives low if HOTSET pin voltage is
lower than 1.6V. Connect external pull-up.
A resistor divider including thermistor senses the temperature, which is used for VRHOT
comparator.
Remote sense amplifier input. Connect to ground at the load.
Remote sense amplifier input. Connect to output at the load.
Remote sense amplifier output.
Inverting input to the error amplifier.
Output of the error amplifier.
Buffered IIN signal. Connect external RC network to FB to program converter output
impedance.
Average current input from the phase IC(s). This pin is also used to communicate over
voltage condition to phase ICs.
Error amplifier non-inverting input. Converter output voltage can be decreased from the
VDAC voltage with an external resistor connected between VDAC and this pin (there is an
internal sink current at this pin).
Programs the constant converter output current limit and hiccup over-current thresholds
through an external resistor tied to VDAC and an internal current source from this pin.
Over-current protection can be disabled by connecting a resistor from this pin to VDAC to
program the threshold higher than the possible signal into the IIN pin from the phase ICs
but no greater than VCCL – 2V (do not float this pin as improper operation will occur).
Regulated voltage programmed by the VID inputs. Connect external RC network to LGND
to program dynamic VID slew rate and provide compensation for the internal buffer amp.
Programs converter startup and over current protection delay timing. It is also used to
compensate the constant output current loop during soft start. Connect an external
capacitor to LGND to program.
Connect a resistor to LGND to program oscillator frequency and OCSET, VSETPT and
VDAC bias currents. Oscillator frequency equals switching frequency per phase. The pin is
0.6V during normal operation and higher than 1.6V if over-voltage condition is detected.
Local Ground for internal circuitry and IC substrate connection.
Clock output at switching frequency multiplied by phase number. Connect to CLKIN pins of
phase ICs.
Phase clock output at switching frequency per phase. Connect to PHSIN pin of the first
phase IC.
Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC.
Output of the voltage regulator, and power input for clock oscillator circuitry. Connect a
decoupling capacitor to LGND.
Non-inverting input of the voltage regulator error amplifier. Output voltage of the regulator
is programmed by the resistor divider connected to VCCL.
Output of the VCCL regulator error amplifier to control external transistor. The pin senses
12V power supply through a resistor.
Open collector output that drives low during startup and under any external fault condition.
Connect external pull-up.
The pin configures VIDs for AMD 6-bit, Intel VR11 8-bit with 1.1V Boot voltage, Intel VR11
8-bit without 1.1V Boot voltage or AMD 5-bit Opteron.
July 28, 2009
IR3500A
SYSTEM THEORY OF OPERATION
PWM Control Method
TM
The PWM block diagram of the XPhase3 architecture is shown in Figure 4. Feed-forward voltage mode control
with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is
used for the voltage control loop. Input voltage is sensed in phase ICs and feed-forward control is realized. The
PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage.
The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace
voltage drop related to changes in load current.
GATE DRIVE
VOLTAGE
CONTROL IC
VIN
PHSOUT
PHASE IC
CLOCK GENERATOR
CLKOUT
VCC
CLKIN
CLK Q
VCCH
D
PHSOUT
1
PHSIN
RESET
DOMINANT
2
1
PWM
COMPARATOR
CBST
VOUT
COUT
-
EAIN
VCCL
+
GND
PWM LATCH
GATEL
ENABLE
+
REMOTE SENSE
AMPLIFIER
BODY
BRAKING
COMPARATOR
+
VID6
PGND
VOSNS-
-
-
-
LDO AMPLIFIER
+
RAMP
DISCHARGE
CLAMP
VO
VOSNS+
SW
5
CLK Q
R
2
GATEH
4
Q
3
PHSIN
D
VDAC
SHARE ADJUST
ERROR AMPLIFIER
VDAC
CURRENT
SENSE
AMPLIFIER
+
EAOUT
ISHARE
-
VID6
VID6
-
+
+
-
3K
RCOMP
RFB1
RFB
+
CCOMP
FB
RVSETPT
IVSETPT
IROSC
VDRP
AMP
CSIN+
+
CCOMP1
VID6
VID6 +
CFB
RCS
CSIN-
DACIN
RDRP1
PHSOUT
PHASE IC
RDRP
VSETPT
CCS
-
+
-
LGND
ERROR
AMPLIFIER
CDRP
VDRP
VCC
CLK Q
CLKIN
+
-
D
IIN
1
1
Q
CLK Q
GATEH
4
CBST
5
SW
R
2
D
3
PWM
COMPARATOR
VCCH
RESET
DOMINANT
2
PHSIN
EAIN
+
VCCL
PWM LATCH
ENABLE
+
VID6
-
RAMP
DISCHARGE
CLAMP
GATEL
BODY
BRAKING
COMPARATOR
PGND
-
+
SHARE ADJUST
ERROR AMPLIFIER
CURRENT
SENSE
AMPLIFIER
+
-
VID6
VID6
+
CSIN+
VID6
VID6 +
+
DACIN
CCS
RCS
-
-
3K
+
ISHARE
CSIN-
Figure 4 - PWM Block Diagram
Frequency and Phase Timing Control
The oscillator and system clock frequency is programmable from 250kHz to 9MHZ by an external resistor (ROSC).
The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase timing of the
phase ICs is controlled by the daisy chain loop, where control IC phase clock output (PHSOUT) is connected to the
phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to PHSIN of the
Page 9 of 48
July 28, 2009
IR3500A
second phase IC, etc. and PHSOUT of the last phase IC is connected back to PHSIN of the control IC. During
power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and detects the feedback at
PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. Figure 5 shows the phase
timing for a four phase converter. The switching frequency is set by the resistor ROSC as shown in Figure 23. The
clock frequency equals the number of phase times the switching frequency.
Control IC CLKOUT
(Phase IC CLKIN)
Control IC PHSOUT
(Phase IC1 PHSIN)
Phase IC1
PWM Latch SET
Phase IC 1 PHSOUT
(Phase IC2 PHSIN)
Phase IC 2 PHSOUT
(Phase IC3 PHSIN)
Phase IC 3 PHSOUT
(Phase IC4 PHSIN)
Phase IC4 PHSOUT
(Control IC PHSIN)
Figure 5 - Four Phase Oscillator Waveforms
PWM Operation
The PWM comparator is located in the phase IC. Upon receiving the falling edge of a clock pulse, the PWM latch is
set; the PWM ramp voltage begins to increase; the low side driver is turned off, and the high side driver is then
turned on after the non-overlap time. When the PWM ramp voltage exceeds the error amplifier’s output voltage the
PWM latch is reset. This turns off the high side driver, then turns on the low side driver after the non-overlap time,
and activates the ramp discharge clamp. The ramp discharge clamp quickly discharges the PWM ramp capacitor to
the output voltage of the share adjust amplifier in the phase IC until the next clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode
input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This
arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required.
It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of
most systems. The inductor current will increase much more rapidly than decrease in response to load transients.
An additional advantage of the architecture is that differences in ground or input voltage at the phases have no
effect on operation since the PWM ramps are referenced to VDAC. Figure 6 depicts PWM operating waveforms
under various conditions
Page 10 of 48
July 28, 2009
IR3500A
.
The error amplifier is a high speed amplifier with 110 dB of open loop gain. It is not unity gain stable.
PHASE IC
CLOCK
PULSE
EAIN
PWMRMP
VDAC
GATEH
GATEL
STEADY-STATE
OPERATION
DUTY CYCLE INCREASE
DUE TO LOAD
INCREASE
DUTY CYCLE DECREASE
DUE TO VIN INCREASE
(FEED-FORWARD)
DUTY CYCLE DECREASE DUE TO LOAD
DECREASE (BODY BRAKING) OR FAULT
(VCC UV, OCP, VID FAULT)
STEADY-STATE
OPERATION
Figure 6 - PWM Operating Waveforms
Body Braking
TM
In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in
response to a load step decrease is;
TSLEW =
L * ( I MAX − I MIN )
VO
The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in
response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the
synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout +
VBODYDIODE. The minimum time required to reduce the current in the inductor in response to a load transient
decrease is now;
TSLEW =
L * ( I MAX − I MIN )
VO + VBODYDIODE
Since the voltage drop in the body diode is often comparable to the output voltage, the inductor current slew rate
can be increased significantly. This patented method is referred to as “body braking” and is accomplished through
the “body braking comparator” located in the phase IC. If the error amplifier’s output voltage drops below the output
voltage of the share adjust amplifier in the phase IC, this comparator turns off the low side gate driver.
Lossless Average Inductor Current Sensing
Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor
and measuring the voltage across the capacitor, as shown in Figure 7. The equation of the sensing network is,
Page 11 of 48
July 28, 2009
IR3500A
vC ( s ) = vL ( s )
1
RL + sL
= iL ( s )
1 + sRCS CCS
1 + sRCS CCS
Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time
constant of the inductor which is the inductance L over the inductor DCR (RL). If the two time constants match, the
voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense
resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of
inductor DC current, but affects the AC component of the inductor current.
vL
iL
Current
Sense Amp
L
RL
RCS
CCS
VO
CO
c
vCS
CSOUT
Figure 7 - Inductor Current Sensing and Current Sense Amplifier
The advantage of sensing the inductor current versus high side or low side sensing is that actual output current
being delivered to the load is obtained rather than peak or sampled information about the switch currents. The
output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in
series with the inductor, this is the only sense method that can support a single cycle transient response. Other
methods provide no information during either load increase (low side sensing) or load decrease (high side sensing).
An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer
from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency
variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and
the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier
bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional
sources of peak-to-average errors.
Current Sense Amplifier
A high speed differential current sense amplifier is located in the phase IC, as shown in Figure 7. Its gain is
nominally 32.5 and the 3850 ppm/ºC increase in inductor DCR should be compensated in the voltage loop feedback
path.
The current sense amplifier can accept positive differential input up to 50mV and negative up to -10mV before
clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the control IC and
other phases through an on-chip 3KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the phases are
tied together and the voltage on the share bus represents the average current through all the inductors and is used
by the control IC for voltage positioning and current limit protection. The input offset of this amplifier is calibrated to
+/- 1mV in order to reduce the current sense error.
The input offset voltage is the primary source of error for the current share loop. In order to achieve very small input
offset error and superior current sharing performance, the current sense amplifier continuously calibrates itself. This
calibration algorithm creates ripple on ISHARE bus with a frequency of fsw / 896 in a multiphase architecture.
Page 12 of 48
July 28, 2009
IR3500A
Average Current Share Loop
Current sharing between phases of the converter is achieved by the average current share loop in each phase IC.
The output of the current sense amplifier is compared with average current at the share bus. If current in a phase is
smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the PWM
ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average current,
the share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing its duty
cycle and output current. The current share amplifier is internally compensated so that the crossover frequency of
the current share loop is much slower than that of the voltage loop and the two loops do not interact.
IR3500A THEORY OF OPERATION
Block Diagram
The Block diagram of the IR3500A is shown in Figure 8, and specific features are discussed in the following
sections.
VID Control
The AMD 6-bit VID, VR11 8-bit VID, and AMD Opteron 5-bit VID are shown in Tables 2 to 4 respectively, and are
selected by different connections of VIDSEL pin shown in Table 1. The VID pins require an external bias voltage
and should not be floated. The VID input comparators monitor the VID pins and control the Digital-to-Analog
Converter (DAC) whose output is sent to the VDAC buffer amplifier. The output of the buffer amplifier is the VDAC
pin. The VDAC voltage, input offsets of error amplifier and remote sense differential amplifier are post-package
trimmed to provide 0.5% system set-point accuracy. The actual VDAC voltage does not determine the system
accuracy, which has a wider tolerance. VIDs of less than 0.5V are not supported.
The IR3500A can accept changes in the VID code while operating and vary the DAC voltage accordingly. The slew
rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC pin and LGND pin. A
resistor connected in series with this capacitor is required to compensate the VDAC buffer amplifier. Digital VID
transitions result in a smooth analog transition of the VDAC voltage and converter output voltage minimizing inrush
currents in the input and output capacitors and overshoot of the output voltage.
Adaptive Voltage Positioning
Adaptive voltage positioning is needed to reduce the output voltage deviations during load transients and the power
dissipation of the load at heavy load. The circuitry related to voltage positioning is shown in Figure 9. The output
voltage is set by the reference voltage VSETPT at the positive input to the error amplifier. This reference voltage
can be programmed to have a constant DC offset bellow the VDAC by connecting RSETPT between VDAC and
VSETPT. The IVSETPT is controlled by the ROSC as shown in Figure 24.
The voltage at the VDRP pin is a buffered version of the share bus IIN and represents the sum of the DAC voltage
and the average inductor current of all the phases. The VDRP pin is connected to the FB pin through the resistor
RDRP. Since the error amplifier will force the loop to maintain FB to be equal to the VSETPT, an additional current
will flow into the FB pin equal to (VDRP-VSETPT) / RDRP. When the load current increases, the adaptive positioning
voltage increases accordingly. More current flows through the feedback resistor RFB, and makes the output voltage
lower proportional to the load current. The positioning voltage can be programmed by the resistor RDRP so that the
droop impedance produces the desired converter output impedance. The offset and slope of the converter output
impedance are referenced to and therefore independent of the VDAC voltage.
Inductor DCR Temperature Compensation
Page 13 of 48
July 28, 2009
IR3500A
A negative temperature coefficient (NTC) thermistor should be used for inductor DCR temperature compensation.
The thermistor should be placed close to the inductor and connected in parallel with the feedback resistor, as
shown in Figure 10. The resistor in series with the thermistor is used to reduce the nonlinearity of the thermistor.
Page 14 of 48
July 28, 2009
IR3500A
VCCLDRV
ENABLE
COMPARATOR
250nS
BLANKING
POWER OK
LATCH
DELAY
COMPARATOR
+
1.19V
SS RESET
+
VCCL OUTPUT
0.86 COMPARATOR
OC DELAY
RESET
R
-
0.94
0.2V
8-Pulse
Delay
+
OPEN SENSE LINE
OPEN DAISY CHAIN
OPEN VOLTAGE LOOP
+
-
VID2
VID2
VID3
-
VID3
+
VID4
VID4
VID1AMD 1.0V
VID1
VID
FAULT
DIGITAL
VID7
VIDSEL VBOOT
TO ANALOG
LATCH
VID6
VID5
CONVERTER VBOOT
(1.1V) Q S
VIDSEL
VBOOT SET
VID4
DOMINANT
VID3
INTERNAL
VDAC
VID2
R
FAULT LATCH1
FAULT LATCH2
VID SAMPLE
DELAY
COMPARATOR
SAMPLE DELAY
DVID
OV FAULT
F A ST VD A C
R
IDCHG
4.5uA
3.2V
Q
1.6V
VDAC
UV
VO
ISINK
-
25k
R
OV@START
+
VOSEN+
RESET
VOSENIVOSENVCCL
VCCL
OPEN SENSE
LINE DETECT
COMPARATORS
VCCL*0.9
+
+
-
200mV
VDAC
OV FAULT
IVOSEN+ IVOSEN-
PULSE
+
ROSC/OVP
Q
25k
REMOTE SENSE
VIDSEL
AMPLIFIER DETECTION
-
VCCLDRV
OV@START
CURRENT
SOURCE
GENERATOR
ISOURCE
OPEN SENSE
LINE DETECT
COMPARATORS
+
+
0.6V
VCCL UVLO
S
SET
DOMINANT
POWER-UP OV
1.73V COMPARATOR
25k
60mV
-
IROSC
ROSC BUFFER
AMPLIFIER
OV@OPERATION
UNDER
VOLTAGE
COMPARATOR
-
-
OV@OPERATION
VDAC BUFFER
AMPLIFIER
ISETPT
OV FAULT
LATCH
+
IROSC
VCCL-1.2V
VSETPT
25k
50mV
PHSOUT
PHSIN
LGND
275mV
315mV
DYNAMIC VID DETECT
COMPARATOR
PHSIN
EAOUT
FB
IROSC
PULSE
VO
OPEN DAISY
CHAIN
PHSOUT
VDRP
DISABLE
OVER
130mV VOLTAGE
3mV
COMPARATOR DETECTION
-
FAULT
CLKOUT
SOFT
START 1.4V
CLAMP
DIS
+
VCCL UVLO
IOCSET
ERROR
AMPLIFIER
S
VID0
CLKOUT
VID0
VDRP AMPLIFIER
S
VID1
VID0
VID0
1.3uS
BLANKING
VR11 NoBOOT
INTEL 0.6V
OCSET
IROSC
Q
-
VID5
OV@OPERATION
+
VID6
VID7
VID INPUT
VID6
COMPARATORS
VID5
(1/8 SHOWN)
R
SET
DOMINANT
VR11 BOOT
VCCL
OV@START
-
VIDSEL
VID7
1.6V
1.5V
Q
SET
DOMINANT
+
VIDSEL
R
AMD 6-BIT
+
IIN
OC LIMIT
AMPLIFIER
+
VIDSEL
VIDSEL
COMPARATORS
3.3V
VIDSEL
3.5k
VID FAULT
LATCH
AMD 5-BIT
0.86
VCCL UVLO
OC LIMIT
COMPARATOR
-
EAOUT
LATCH
VIDSEL
S
-
-
0.6V
HOTSET
VRHOT
UV CLEARED
FAULT LATCH2
OC
1.08V
VCCL
VCCL UVLO
OC DELAY
PHSOUT
COUNTER
SS/DEL
Float
Voltage
VRHOT COMPARATOR
R
IROSC
S AM PLE D ELAY
+
4.0V
SS RESET
5
+
VCCLFB
DISCHARGE
COMPARATOR
UV
Q
SET
DOMINANT
6
+
80mV
120mV
VCCL REGULATOR
AMPLIFIER
S
Q
RESET
DOMINANT
-
VCCLDRV
S
VID FAULT LATCH
VCCL UVLO
OC before VRRDY
-
AMD 1.2V
1.14V
PGOOD
1
2
FAULT LATCH2 3
OV FAULT 4
+
INTEL
850mV
800mV
OC after VRRDY
DISABLE
VID FAULT
+
+
+
400K
-
-
SS CLEARED POWER NOT OK
FAULT LATCH1 FAULT LATCH1
-
VBIAS
+
VCCL
ENABLE
OPEN SENSE LINE
ENABLE 0.4V
-
VO
+
Figure 8 - Block Diagram
Page 15 of 48
July 28, 2009
IR3500A
TABLE 1 - VIDSEL FUNCTIONALITY
VIDSEL
Connection
LGND (<0.5V)
6.49 kΩ to GND
(0.7V to 83% of
FLOAT)
FLOAT (typ.
83% of
VR11w/wo boot
Threshold)
VCCL (4.5V-7V)
VID Table
Ignore VID Fault
during soft start?
NO
NO
VID Fault Latch?
AMD 5-BIT OPTERON
AMD 6-BIT
1.1V Boot Voltage
during soft start?
NO
NO
VR11 8-BIT
YES
YES
YES
VR11 8-BIT
NO
NO
NO
NO
NO
TABLE 2 - AMD 6-BIT VID TABLE
VID5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vout (V)
1.5500
1.5250
1.5000
1.4750
1.4500
1.4250
1.4000
1.3750
1.3500
1.3250
1.3000
1.2750
1.2500
1.2250
1.2000
1.1750
1.1500
1.1250
1.1000
1.0750
1.0500
1.0250
1.0000
0.9750
0.9500
0.9250
0.9000
0.8750
0.8500
0.8250
0.8000
0
1
1
1
1
1
0.7750
VID5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vout(V)
0.7625
0.7500
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
1
1
1
1
1
1
n/a
Note: 6.49kΩ connected between VID_SEL and LGND. V(VDAC) is pre-positioned 50mV higher than VID
values listed above for load line positioning. VID is measured at EAOUT with EAOUT shorted to FB,
ROSC=50 KΩ and a 4200 Ω resistor connecting VSETPT to VDAC to cancel the 50 mV pre-position offset, as
shown in Fig. 3.
Page 16 of 48
July 28, 2009
IR3500A
TABLE 3 - VR11 VID TABLE (PART1)
Hex (VID7:VID0)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Page 17 of 48
Dec (VID7:VID0)
00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
00010000
00010001
00010010
00010011
00010100
00010101
00010110
00010111
00011000
00011001
00011010
00011011
00011100
00011101
00011110
00011111
00100000
00100001
00100010
00100011
00100100
00100101
00100110
00100111
00101000
00101001
00101010
00101011
00101100
00101101
00101110
00101111
00110000
00110001
00110010
00110011
00110100
00110101
00110110
00110111
00111000
00111001
00111010
00111011
00111100
00111101
00111110
00111111
Voltage
Fault
Fault
1.60000
1.59375
1.58750
1.58125
1.57500
1.56875
1.56250
1.55625
1.55000
1.54375
1.53750
1.53125
1.52500
1.51875
1.51250
1.50625
1.50000
1.49375
1.48750
1.48125
1.47500
1.46875
1.46250
1.45625
1.45000
1.44375
1.43750
1.43125
1.42500
1.41875
1.41250
1.40625
1.40000
1.39375
1.38750
1.38125
1.37500
1.36875
1.36250
1.35625
1.35000
1.34375
1.33750
1.33125
1.32500
1.31875
1.31250
1.30625
1.30000
1.29375
1.28750
1.28125
1.27500
1.26875
1.26250
1.25625
1.25000
1.24375
1.23750
1.23125
1.22500
1.21875
Hex (VID7:VID0)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Dec (VID7:VID0)
01000000
01000001
01000010
01000011
01000100
01000101
01000110
01000111
01001000
01001001
01001010
01001011
01001100
01001101
01001110
01001111
01010000
01010001
01010010
01010011
01010100
01010101
01010110
01010111
01011000
01011001
01011010
01011011
01011100
01011101
01011110
01011111
01100000
01100001
01100010
01100011
01100100
01100101
01100110
01100111
01101000
01101001
01101010
01101011
01101100
01101101
01101110
01101111
01110000
01110001
01110010
01110011
01110100
01110101
01110110
01110111
01111000
01111001
01111010
01111011
01111100
01111101
01111110
01111111
July 28, 2009
Voltage
1.21250
1.20625
1.20000
1.19375
1.18750
1.18125
1.17500
1.16875
1.16250
1.15625
1.15000
1.14375
1.13750
1.13125
1.12500
1.11875
1.11250
1.10625
1.10000
1.09375
1.08750
1.08125
1.07500
1.06875
1.06250
1.05625
1.05000
1.04375
1.03750
1.03125
1.02500
1.01875
1.01250
1.00625
1.00000
0.99375
0.98750
0.98125
0.97500
0.96875
0.96250
0.95625
0.95000
0.94375
0.93750
0.93125
0.92500
0.91875
0.91250
0.90625
0.90000
0.89375
0.88750
0.88125
0.87500
0.86875
0.86250
0.85625
0.85000
0.84375
0.83750
0.83125
0.82500
0.81875
IR3500A
TABLE 3 - VR11 VID TABLE (PART 2)
Hex (VID7:VID0)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
Page 18 of 48
Dec (VID7:VID0)
10000000
10000001
10000010
10000011
10000100
10000101
10000110
10000111
10001000
10001001
10001010
10001011
10001100
10001101
10001110
10001111
10010000
10010001
10010010
10010011
10010100
10010101
10010110
10010111
10011000
10011001
10011010
10011011
10011100
10011101
10011110
10011111
10100000
10100001
10100010
10100011
10100100
10100101
10100110
10100111
10101000
10101001
10101010
10101011
10101100
10101101
10101110
10101111
10110000
10110001
10110010
10110011
10110100
10110101
10110110
10110111
10111000
10111001
10111010
10111011
10111100
10111101
10111110
10111111
Voltage
0.81250
0.80625
0.80000
0.79375
0.78750
0.78125
0.77500
0.76875
0.76250
0.75625
0.75000
0.74375
0.73750
0.73125
0.72500
0.71875
0.71250
0.70625
0.70000
0.69375
0.68750
0.68125
0.67500
0.66875
0.66250
0.65625
0.65000
0.64375
0.63750
0.63125
0.62500
0.61875
0.61250
0.60625
0.60000
0.59375
0.58750
0.58125
0.57500
0.56875
0.56250
0.55625
0.55000
0.54375
0.53750
0.53125
0.52500
0.51875
0.51250
0.50625
0.50000
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Hex (VID7:VID0)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Dec (VID7:VID0)
11000000
11000001
11000010
11000011
11000100
11000101
11000110
11000111
11001000
11001001
11001010
11001011
11001100
11001101
11001110
11001111
11010000
11010001
11010010
11010011
11010100
11010101
11010110
11010111
11011000
11011001
11011010
11011011
11011100
11011101
11011110
11011111
11100000
11100001
11100010
11100011
11100100
11100101
11100110
11100111
11101000
11101001
11101010
11101011
11101100
11101101
11101110
11101111
11110000
11110001
11110010
11110011
11110100
11110101
11110110
11110111
11111000
11111001
11111010
11111011
11111100
11111101
11111110
11111111
July 28, 2009
Voltage
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
FAULT
FAULT
IR3500A
TABLE 4 - AMD 5-BIT TABLE FOR OPTERON
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Voltage (V)
1.550
1.525
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.300
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
FAULT
Note: VID_SEL tied to LGND. V(VDAC) is pre-positioned 50mV higher than VID values listed above for load
line positioning. VID is measured at EAOUT with EAOUT shorted to FB, ROSC=50 KΩ and a 4200 Ω resistor
connecting VSETPT to VDAC to cancel the 50 mV pre-position offset, as shown in Fig. 3.
Page 19 of 48
July 28, 2009
IR3500A
Control IC
VDAC
VDAC
Phase IC
Current Sense
Amplif ier
ISHARE
3k
VDAC
+
... ...
FB
RFB
VDRP
Amplifier
VDRP
Phase IC
RDRP
Current Sense
Amplif ier
ISHARE
VO
VDAC
+
VOSEN+
-
VOSEN-
3k
CSIN+
-
+
IIN
+
-
Remote
Sense
Amplifier
CSIN-
EAOUT
-
IVSETPT
CSIN+
-
VSETPT
Error
Amplifier
+
RSETPT
CSIN-
Figure 9 - Adaptive voltage positioning
Control IC
VDAC
VDAC
RSETPT
VSETPT
Error
Amplifier
+
EAOUT
RFB
-
IVSETPT
FB
VDRP
Amplifier
+
RFB1
Rt
RDRP
VDRP
IIN
VO
+
VOSEN+
-
Remote
Sense
Amplifier
VOSEN-
Figure 10 - Temperature compensation of inductor DCR
Remote Voltage Sensing
VOSEN+ and VOSEN- are used for remote sensing and connected directly to the load. The remote sense
differential amplifier with high speed, low input offset and low input bias current ensures accurate voltage sensing
and fast transient response.
Start-up Sequence
The IR3500A has a programmable soft-start function to limit the surge current during the converter start-up. A
capacitor connected between the SS/DEL and LGND pins controls soft start timing, over-current protection delay
and hiccup mode timing. A charge current of 52.5uA and discharge current of 4uA control the up slope and down
slope of the voltage at the SS/DEL pin respectively.
Page 20 of 48
July 28, 2009
IR3500A
Figure 11 depicts start-up sequence of converter with VR 11 VID with boot voltage, which is selected by VIDSEL pin
based on Table 1. If there is no fault, the SS/DEL pin will start charging when the enable crosses the threshold. The
error amplifier output EAOUT is clamped low until SS/DEL reaches 1.4V. The error amplifier will then regulate the
converter’s output voltage to match the SS/DEL voltage less the 1.4V offset until the converter output reaches the
1.1V boot voltage. The SS/DEL voltage continues to increase until it rises above the 3.0V threshold of VID delay
comparator. The VID set inputs are then activated and VDAC pin transitions to the level determined by the VID
inputs. The SS/DEL voltage continues to increase until it rises above 3.92V and allows the PGOOD signal to be
asserted. SS/DEL finally settles at 4.0V, indicating the end of the soft start.
Figure 12 shows start-up sequence of converter VR 11 VID without boot voltage or AMD Opteron, AMD 6-bit VID
which is selected by VIDSEL pin based on Table 1. If there is no fault, the SS/DEL pin will start charging. The error
amplifier output EAOUT is clamped low until SS/DEL reaches 1.4V. The error amplifier will then regulate the
converter’s output voltage to match the SS/DEL voltage less the 1.4V offset until the converter output reaches the
level determined by the VID inputs. The SS/DEL voltage continues to increase until it rises above 3.92V and allows
the PGOOD signal to be asserted. SS/DEL finally settles at 4.0V, indicating the end of the soft start.
VCC
(12V)
ENABLE
VID
1.1V
VDAC
4.0V
3.92V
3V
1.4V
SS/DEL
EAOUT
VOUT
VRRDY
START DELAY (TD1)
SOFT START
TIME (TD2)
VID SAMPLE
TIME (TD3)
VRRDY DELAY
TIME (TD4+TD5)
TD4
NORMAL OPERATION
TD5
Figure 11 - Start-up sequence of converter with boot voltage
VCCL under voltage lock-out, VID fault modes, over current, as well as a low signal on the ENABLE input
immediately sets the fault latch, which causes the EAOUT pin to drive low turning off the phase IC drivers. The
PGOOD pin also drives low, and SS/DEL begin to discharge until the voltage reaches 0.2V. If the fault has cleared
the fault latch will be reset by the discharge comparator allowing a normal soft start to occur.
Other fault conditions, such as over voltage, open sense lines, open loop monitor, and open daisy chain, set
different fault latches, which start discharging SS/DEL, pull down EAOUT voltage and drive PGOOD low. However,
the latches can only be reset by cycling VCCL power.
Page 21 of 48
July 28, 2009
IR3500A
VCC
(12V)
ENABLE
VID
VDAC
4.0V
3.92V
1.4V
SS/DEL
EAOUT
VOUT
VRRDY
START DELAY (TD1)
SOFT START
TIME (TD2)
VRRDY DELAY
TIME (TD3)
NORMAL OPERATION
Figure 12 - Start-up sequence of converter without boot voltage
Constant Over-Current Control during Soft Start
The over current limit threshold is set by a resistor connected between OCSET and VDAC. If the IIN pin voltage,
which is proportional to the average current plus VDAC voltage, exceeds the OCSET voltage during soft start, the
constant over-current control is activated. Figure 13 shows the constant over-current control with delay during soft
start. The delay time is set by the ROSC resistor, which sets the number of switching cycles for the delay counter.
The delay is required since over-current conditions can occur as part of normal operation due to inrush current. If an
over-current occurs during soft start (before PGOOD is asserted), the SS/DEL voltage is regulated by the over
current amplifier to limit the output current below the threshold set by OCSET voltage. If the over-current condition
persists after delay time is reached, the fault latch will be set pulling the error amplifier’s output low and inhibiting
switching in the phase ICs. The SS/DEL capacitor will discharge until it reaches 0.2V and the fault latch is reset
allowing a normal soft start to occur. If an over-current condition is again encountered during the soft start cycle, the
constant over-current control actions will repeat and the converter will be in hiccup mode. The delay time is
controlled by a counter which is triggered by clock. The counter values vary with switching frequency per phase in
order to have a similar delay time for different switching frequencies.
Over-Current Hiccup Protection after Soft Start
The over current limit threshold is set by a resistor connected between OCSET and VDAC pins. Figure 13 shows
the constant over-current control with delay after PGOOD is asserted. The delay is required since over-current
conditions can occur as part of normal operation due to load transients or VID transitions.
If the IIN pin voltage, which is proportional to the average current plus VDAC voltage, exceeds the OCSET voltage
after PGOOD is asserted, it will initiate the discharge of the capacitor at SS/DEL. The magnitude of the discharge
current is proportional to the voltage difference between IIN and OCSET and has a maximum nominal value of
55uA. If the over-current condition persists long enough for the SS/DEL capacitor to discharge below the 120mV
offset of the delay comparator, the fault latch will be set pulling the error amplifier’s output low and inhibiting
switching in the phase ICs and de-asserting the PGOOD signal. The output current is not controlled during the
delay time. The SS/DEL capacitor will discharge until it reaches 200 mV and the fault latch is reset allowing a
normal soft start to occur. If an over-current condition is again encountered during the soft start cycle, the overcurrent action will repeat and the converter will be in hiccup mode.
Page 22 of 48
July 28, 2009
IR3500A
ENABLE
INTERNAL
OC DELAY
SS/DEL
4.0V
3.92V
3.88V
1.1V
EA
VOUT
VRRDY
OCP THRESHOLD
IOUT
START-UP WITH
OUTPUT SHORTED
HICCUP OVER-CURRENT
PROTECTION (OUTPUT
SHORTED)
NORMAL
START-UP
OCP
DELAY
OVER-CURRENT
NORMAL
NORMAL
PROTECTION
START-UP OPERATION POWER-DOWN
(OUTPUT SHORTED)
(OUTPUT
NORMAL
OPERATION SHORTED)
Figure 13 - Over Current Protection waveforms during and after soft start
Linear Regulator Output (VCCL)
The IR3500A has a built-in linear regulator controller, and only an external NPN transistor is needed to create a
linear regulator. The output voltage of the linear regulator can be programmed between 4.75V and 7.5V by the
resistor divider at VCCLFB pin. The regulator output powers the gate drivers and other circuits of the phase ICs
along with circuits in the control IC, and the voltage is usually programmed to optimize the converter efficiency. The
linear regulator can be compensated by a 4.7uF capacitor at the VCCL pin. As with any linear regulator, due to
stability reasons, there is an upper limit to the maximum value of capacitor that can be used at this pin and it’s a
function of the number of phases used in the multiphase architecture and their switching frequency. Figure 14
provides Bode plots for the linear regulator with 5 phases switching at 750 kHz.
An external 5V can be connected to this pin to replace the linear regulator with appropriate selection of the VCCLFB
resistor divider, and VCCLDRV resistor. While using an external VCCL its essential to adjust it such that VCCLFB is
slightly lower than the 1.19V reference voltage. This condition ensures that the VCCLDRV pin doesn’t load the
ROSC pin. The switching frequency, VSETPT, and OCSET are derived from the loading current of ROSC pin.
Figure 14 - VCCL regulator stability with 5 phases and PHSOUT equals 750 kHz.
Page 23 of 48
July 28, 2009
IR3500A
VCCL Under Voltage Lockout (UVLO)
The IR3500A has no under voltage lockout for converter input voltage (VCC), but monitors the VCCL voltage
instead, which is used for the gate drivers of phase ICs and circuits in control IC and phase ICs. During power up,
the fault latch will be reset if VCCL is above 94% of the voltage set by resistor divider at VCCLFB pin. If VCCL
voltage drops below 86% of the set value, the fault latch will be set.
VID Fault Codes
VID codes of 0000000X and 1111111X for VR11, and 11111 for AMD 5-bit Opteron will set the fault latch and
disable the error amplifier. A 1.3us delay is provided to prevent a fault condition from occurring during Dynamic VID
changes. A VID FAULT condition is latched for VR 11 with boot voltage and can only be cleared by cycling power to
VCCL.
Voltage Regulator Ready (PGOOD)
The PGOOD pin is an open-collector output and should be pulled up to a voltage source through a resistor. After
soft start cycle is complete, the PGOOD remains high until the output voltage is within regulation and SS/DEL is
above 3.92V. The PGOOD pin becomes low if the fault latch, over voltage latch, open sense line latch, or open
daisy chain latch is set. A high level at the PGOOD pin indicates that the converter is in operation and has no fault.
The PGOOD stays high as long as the output voltage is within 300 mV of the programmed VID. During start-up, it is
pulled low with an input voltage as low as 2 V. It stays low until the startup sequence has completed, and the output
voltage has moved to the programmed VID.
Open Voltage Loop Detection
The output voltage range of error amplifier is detected all the time to ensure the voltage loop is in regulation. If any
fault condition forces the error amplifier output above VCCL-1.08V for 8 switching cycles, the fault latch is set. The
fault latch can only be cleared by cycling power to VCCL.
Load Current Indicator Output
The VDRP pin voltage represents the average current of the converter plus the VDAC voltage. The load current
information can be retrieved by a differential amplifier which subtracts the VDAC voltage from the VDRP voltage.
Enable Input
For Intel VID codes, pulling the ENABLE pin below 0.8V sets the Fault Latch and a voltage above 0.85V enables
the soft start of the converter. For AMD VID codes, pulling the ENABLE pin below 1.14V sets the Fault Latch and a
voltage above 1.2V enables the soft start of the converter.
Thermal Monitoring (VRHOT)
A resistor divider including a thermistor at the HOTSET pin sets the VRHOT threshold. The thermistor is usually
placed at the temperature sensitive region of the converter, and is linearized by a series resistor. The IR3500A
compares the HOTSET pin voltage with a reference voltage of 1.6V. The VRHOT pin is an open-collector output
and should be pulled up to a voltage source through a resistor. If the thermal trip point is reached the VRHOT
output drives low. The hysteresis of the VRHOT comparator is added to eliminate toggling of VRHOT output.
Over Voltage Protection (OVP)
The output over-voltage happens during normal operation if a high side MOSFET short occurs or if output voltage is
out of regulation. The over-voltage protection comparator monitors Vo pin voltage. If Vo pin voltage exceeds VDAC
by 130mV, as shown in Figure 14, IR3500A raises ROSC/OVP pin voltage to V(VCCL) - 1V, which sends over
voltage signal to system. The ROSC/OVP pin can also be connected to a thyrister in a crowbar circuit, which pulls
the converter input low in over voltage conditions. The over voltage condition also sets the over voltage fault latch,
Page 24 of 48
July 28, 2009
IR3500A
which pulls error amplifier output low to turn off the converter output. At the same time IIN pin (ISHARE of phase
ICs) is pulled up to VCCL to communicate the over voltage condition to phase ICs, as shown in Figure 15. In each
phase IC, the OVP circuit overrides the normal PWM operation and will fully turn-on the low side MOSFET within
approximately 150ns. The low side MOSFET will remain on until ISHARE pin voltage drops below V(VCCL) 800mV, which signals the end of over voltage condition. An over voltage fault condition is latched in the IR3500A
and can only be cleared by cycling power to the IR3500A VCCL.
OUTPUT
VOLTAGE
(VO)
OVP
THRESHOLD
130mV
VCCL-800 mV
IIN
(ISHARE)
GATEH
(PHASE IC)
GATEL
(PHASE IC)
FAULT
LATCH
ERROR
AMPLIFIER
OUTPUT
(EAOUT)
VDAC
NORMAL OPERATION
OVP CONDITION
AFTER
OVP
Figure 15 - Over-voltage protection during normal operation
In the event of a high side MOSFET short before power up, the OVP flag is activated with as little supply voltage as
possible, as shown in Figure 16. The VOSEN+ pin is compared against a fixed voltage of 1.73V (typical) for OVP
conditions at power-up. The ROSC/OVP pin will be pulled higher than 1.6V with VCCLDRV voltage as low as 1.8V.
An external MOSFET or comparator should be used to disable the silver box, activate a crowbar, or turn off the
supply source. The 1.8V threshold is used to prevent false over-voltage triggering caused by pre-charging of output
capacitors.
Pre-charging of converter output voltage may trigger OVP. If the converter output is pre-charged above 1.73V as
shown in Figure 17, ROSC/OVP pin voltage will be higher than 1.6V when VCCLDRV voltage reaches 1.8V.
ROSC/OVP pin voltage will be VCCLDRV-1V and rise with VCCLDRV voltage until VCCL is above UVLO threshold,
after which ROSC/OVP pin voltage will be VCCL-1V. The converter cannot start unless the over voltage condition
stops and VCCL is cycled. If the converter output is pre-charged 130mV above VDAC but lower than 1.73V, as
shown in Figure 17, the converter will soft start until SS/DEL voltage is above 3.92V (4.0V-0.08V). Then, over
voltage comparator is activated and fault latch is set.
Page 25 of 48
July 28, 2009
IR3500A
12V
VCCL+0.7V
VCC
VCCL+0.7V
12V
VCCLDRV
1.8V
OUTPUT
VOLTAGE
(VOSEN+)
VCCL UVLO
ROSC/OVP
1.6V
Figure 16 - Over-voltage protection during power-up
12V
VCCL+0.7V
VCC
VCCL+0.7V
VCCLDRV
1.8V
OUTPUT
VOLTAGE
(VOSEN+)
1.73V
VCCL UVLO
ROSC/OVP
1.6V
Figure 17 - Over-voltage protection with pre-charging converter output Vo > 1.73V
Page 26 of 48
July 28, 2009
IR3500A
12V
VCC
VCCL+0.7V
VCCL+0.7V
VCCLDRV
OUTPUT
VOLTAGE
(VOSEN+)
1.73V
VID + 0.13V
VCCL UVLO
VCCL - 1V
ROSC/OVP
0.6V
3.92V (4V-0.08V)
SS/DEL
Figure 18 - Over-voltage protection with pre-charging converter output VID + 0.13V <Vo < 1.73V
During dynamic VID down, OVP may be triggered when output voltage can not follow VDAC voltage change at light
load with large output capacitance. Therefore, over-voltage threshold is raised to 1.73V from VDAC+130mV
whenever dynamic VID is detected and the difference between output voltage and VDAC is more than 50mV, as
shown in Figure 19. The over-voltage threshold is changed back to VDAC+130mV if the difference is smaller than
50mV.
The overall system must be considered when designing for OVP. In many cases the over-current protection of the
AC-DC or DC-DC converter supplying the multiphase converter will be triggered and provide effective protection
without damage as long as all PCB traces and components are sized to handle the worst-case maximum current. If
this is not possible, a fuse can be added in the input supply to the multiphase converter.
Open Remote Sense Line Protection
If either remote sense line VOSEN+ or VOSEN- or both are open, the output of remote sense amplifier (VO) drops.
The IR3500A monitors VO pin voltage continuously. If VO voltage is lower than 200 mV, two separate pulse
currents are applied to VOSEN+ and VOSEN- pins respectively to check if the sense lines are open. If VOSEN+ is
open, a voltage higher than 90% of V(VCCL) will be present at VOSEN+ pin and the output of open line detect
comparator will be high. If VOSEN- is open, a voltage higher than 700mV will be present at VOSEN- pin and the
output of open-line-detect comparator will be high. The open sense line fault latch is set, which pulls error amplifier
output low immediately and shut down the converter. The SS/DEL voltage is discharged and the fault latch can only
be reset by cycling VCCL power.
Page 27 of 48
July 28, 2009
IR3500A
VID
(FAST
VDAC)
VDAC
OV
THRESHOLD
1.73V
VDAC + 130mV
OUTPUT
VOLTAGE
(VO)
VDAC
50mV
50mV
NORMAL
OPERATION
VID DOWN
LOW VID
VID UP
NORMAL
OPERATION
Figure 19 - Over-voltage protection during dynamic VID
Open Daisy Chain Protection
IR3500A checks the daisy chain every time it powers up. It starts a daisy chain pulse on the PHSOUT pin and
detects the feedback at PHSIN pin. If no pulse comes back after 32 CLKOUT pulses, the pulse is restarted again. If
the pulse fails to come back the second time, the open daisy chain fault is registered, and SS/DEL is not allowed to
charge. The fault latch can only be reset by cycling the power to VCCL.
After powering up, the IR3500A monitors PHSIN pin for a phase input pulse equal or less than the number of
phases detected. If PHSIN pulse does not return within the number of phases in the converter, another pulse is
started on PHSOUT pin. If the second started PHSOUT pulse does not return on PHSIN, an open daisy chain fault
is registered.
Phase Number Determination
After a daisy chain pulse is started, the IR3500A checks the timing of the input pulse at PHSIN pin to determine the
phase number. This information is used to have symmetrical phase delay between phase switching without the
need of any external component.
Single Phase Operation
In an architecture where only a single phase is needed the switching frequency is determined by the clock
frequency.
Page 28 of 48
July 28, 2009
IR3500A
APPLICATIONS INFORMATION
FUSE
CVCC1
Q1
12V
ROVP1
RVCCLDRV
RVCCLFB1
RVCCLFB2
CVCCL
4.7uF
Q3
13
VC C
16
15
C SIN -
EAIN
GATEL
PGN D
C LKIN
VOUT+
9
DISTRIBUTION
IMPEDANCE
U12
COUT
8
5
VOUT SENSE+
CVCC2
13
VC C
EAIN
ISHARE
LGND
PHSIN
RHOTSET2
5
CCP1
SW
IR3505
PHASE
IC
DACIN
GATEH
BOOST
GAT EL
CCP
CIN2
U21
VCCL
12
RCS2
CCS2
11
CBST2
L2
10
9
U22
8
4
RCP
15
16
1
C SIN -
U20
C SIN +
RDRP1 CDRP
PGN D
17
14
RVSETPT
18
C LKIN
19
VOUT SENSECVDAC
RVDAC
ROCSET
PH SOU T
21
7
22
20
2
CFB
CCS1
L1
10
CVCCL1
ENABLE
RFB1
VCCL
RCS1
CBST1
CSS/DEL
RDRP
RFB
BOOST
12
11
VOUTROSC
6
EAOU T
VDRP
23
3
VRHOT
PHSIN
GATEH
24
16
FB
IIN
VO
VSETPT
VID1
VID0
LGND
U11
SW
IR3505
PHASE
IC
DACIN
25
C LKOU T
27
26
30
28
VC C L
PH SIN
VC C LF B
VC C LD R V
VR R D Y
VID SEL
PH SOU T
OCSET
VID2
VOSEN +
VID0
8
VID3
VDAC
15
7
14
6
VID1
SS/DEL
IR3500
CONTROL
IC
VID4
13
VID2
VID5
VOSEN -
5
H OT SET
4
VID3
LGND
ROSC / OVP
12
3
VID4
VID6
9
VID5
VID7
VR H OT
2
EN ABLE
VID6
11
1
10
VID7
31
4
29
VIDSEL
32
VR READY
3
CIN1
ISHARE
PH SOU T
2
7
1
C SIN +
U10
6
ROVP2
14
SCR
Q2
RFB2
RHOTSET1
CVCCL2
13
16
15
EAIN
C SIN -
VC C
GATEH
GAT EL
BOOST
VCCL
12
RCS3
CCS3
11
CBST3
L3
10
9
U32
8
PGN D
PHSIN
C LKIN
LGND
5
4
U31
SW
IR3505
PHASE
IC
DACIN
PH SOU T
3
CIN3
ISHARE
7
2
6
1
C SIN +
U30
14
CVCC3
CVCCL3
RTHERM1
RTHERM2
CLOSE TO
POWER
STAGE
Figure 20 - IR3500A / IR3505 Three Phase AMD Opteron Converter
Page 29 of 48
July 28, 2009
IR3500A
FUSE
CVCC1
Q1
12V
ROVP1
RVCCLDRV
RVCCLFB1
RVCCLFB2
CVCCL
4.7uF
Q3
14
16
13
VCC
CSIN-
EAIN
GATEL
PGND
CLKIN
VOUT+
DISTRIBUTION
IMPEDANCE
U12
COUT
8
5
VOUT SENSE+
9
CVCC2
CCP
VCC
13
ISHARE
LGND
PHSIN
RHOTSET2
5
CCP1
SW
IR3505
PHASE
IC
DACIN
GATEH
BOOST
GATEL
4
RCP
CIN2
U21
VCCL
12
RCS2
CCS2
11
CBST2
L2
10
9
U22
8
1
14
16
U20
EAIN
RDRP1 CDRP
CSIN-
17
15
RVSETPT
18
CSIN+
19
VOUT SENSE-
CVDAC
RVDAC
PGND
26
27
CCS1
L1
ROCSET
CLKIN
20
PHSOUT
21
2
CFB
RCS1
CBST1
10
CVCCL1
3
RFB1
VCCL
12
11
CSS/DEL
RDRP
RFB
BOOST
VOUTROSC
7
EAOUT
VDRP
23
22
ENABLE
VRHOT
PHSIN
GATEH
24
16
FB
15
14
VO
IIN
VOSEN+
VSETPT
VID1
VOSEN-
VID2
VID0
LGND
U11
SW
IR3505
PHASE
IC
DACIN
25
CLKOUT
VCCL
PHSIN
30
28
29
VCCLFB
PHSOUT
VDAC
OCSET
CIN1
ISHARE
6
VID3
13
8
IR3500
CONTROL
IC
VID4
12
VID0
VCCLDRV
7
SS/DEL
HOTSET
6
VID1
VRRDY
VID2
VIDSEL
5
ROSC / OVP
VID5
VRHOT
4
VID3
LGND
VID6
ENABLE
VID4
VID7
9
3
11
2
VID5
10
1
VID6
31
VIDSEL
4
32
3
PHSOUT
2
7
1
VR READY
CSIN+
U10
6
ROVP2
VID7
15
SCR
Q2
RFB2
RHOTSET1
CVCCL2
VCC
13
16
EAIN
14
GATEH
GATEL
BOOST
VCCL
12
RCS3
CCS3
11
CBST3
L3
10
9
U32
8
PGND
PHSIN
CLKIN
LGND
U31
SW
IR3505
PHASE
IC
DACIN
5
4
CIN3
ISHARE
PHSOUT
3
7
2
6
1
CSIN-
U30
CSIN+
15
CVCC3
CVCCL3
VCC
13
16
EAIN
14
GATEH
GATEL
BOOST
VCCL
12
RCS4
CCS4
11
CBST4
L4
10
9
U42
8
PGND
PHSIN
CLKIN
LGND
U41
SW
IR3505
PHASE
IC
DACIN
5
4
CIN4
ISHARE
PHSOUT
3
7
2
6
1
CSIN-
U40
CSIN+
15
CVCC4
CVCCL4
VCC
13
16
EAIN
14
GATEH
GATEL
BOOST
VCCL
12
RCS5
CCS5
11
CBST5
L5
10
9
U52
8
PGND
PHSIN
CLKIN
LGND
U51
SW
IR3505
PHASE
IC
DACIN
5
4
CIN5
ISHARE
PHSOUT
3
7
2
6
1
CSIN-
U50
CSIN+
15
CVCC5
CVCCL5
VCC
13
16
EAIN
14
GATEH
GATEL
BOOST
VCCL
12
RCS6
CCS6
11
CBST6
L6
10
9
U62
8
PGND
PHSIN
CLKIN
LGND
U61
SW
IR3505
PHASE
IC
DACIN
5
4
CIN6
ISHARE
PHSOUT
3
7
2
6
1
CSIN-
U60
CSIN+
15
CVCC6
CVCCL6
RTHERM1
RTHERM2
CLOSE TO
POWER
STAGE
Figure 21 - IR3500A / IR3505 Six Phase VRM11.0 / VRD11.0 / EVRD11.0 Converter
Page 30 of 48
July 28, 2009
IR3500A
DESIGN PROCEDURE
Oscillator Resistor Rosc
The oscillator of IR500 generates square-wave pulses to synchronize the phase ICs. The switching frequency of
each phase converter equals the PHSOUT frequency, which is set by the external resistor ROSC according to the
curve in Figure 23. The CLKOUT frequency equals the switching frequency multiplied by the phase number. The
Rosc sets the reference current used for the no load offset and OCSET which is given by Figure 23 and equals:
ISETPT = IOCSET =
0.595
Rosc
(1)
Soft Start Capacitor CSS/DEL
The soft start capacitor CSS/DEL programs five different time parameters. They include soft start delay time, soft
start time, VID sample delay time, VR ready delay time and over-current fault latch delay time after VR ready.
For the converter using VR11 VID with boot voltage, the SS/DEL pin voltage controls the slew rate of the
converter output voltage, as shown in Figure 10. After the ENABLE pin voltage rises above 0.85V, there is a softstart delay time TD1, after which the error amplifier output is released to allow the soft start of output voltage. The
soft start time TD2 represents the time during which converter voltage rises from zero to 1.1V. The VID sample
delay time (TD3) is the time period when VID stays at boot voltage of 1.1V. VID rise or fall time (TD4) is the time
when VID changes from boot voltage to the final voltage. The VR ready delay time (TD5) is the time period from
VR reaching the final voltage to the VR ready signal being issued, which is determined by the delay comparator
threshold.
CSS/DEL = 0.1uF meets all the specifications of TD1 to TD5, which are determined by (2) to (6) respectively.
TD1 =
C SS / DEL *1.4 C SS / DEL *1.4
=
I CHG
52.5 *10 −6
(2)
TD 2 =
C SS / DEL *1.1 C SS / DEL *1.1
=
I CHG
52.5 *10 −6
(3)
TD3 =
TD 4 =
C SS / DEL * (3 − 1.4 − 1.1) C SS / DEL * 0.7
=
I CHG
52.5 * 10 −6
C SS / DEL * V DAC − 1.1
TD5 =
I CHG
=
C SS / DEL * V DAC − 1.1
52.5 *10 − 6
C SS / DEL * (3.92 − 3)
C
* 0.92
− TD4 = SS / DEL −6 − TD4
I CHG
52.5 * 10
(4)
(5)
(6)
For the converter using VR 11 VID without boot voltage or AMD 5-bit and 6-bit VIDs, the SS/DEL pin voltage
controls the slew rate of the converter output voltage, as shown in Figure 11. After the ENABLE pin voltage rises
above 0.85V/1.2V, there is a soft-start delay time TD1, after which the error amplifier output is released to allow
the soft start. The soft start time TD2 represents the time during which converter voltage rises from zero to Vo. VR
ready delay time (TD3) is the time period from VR reaching the final voltage to the VR ready signal being issued.
Calculate CSS/DEL based on the required soft start time (TD2).
CSS / DEL =
Page 31 of 48
TD 2 * I CHG TD 2 * 52.5 *10 −6
=
VO
VO
(7)
July 28, 2009
IR3500A
The soft start delay time (TD1) and VR ready delay time (TD3) are determined by (8) to (9) respectively.
C
*1.4 CSS / DEL *1.4
(8)
TD1 = SS / DEL
=
I CHG
52.5 *10− 6
TD3 =
C SS / DEL * ( 4.0 − VO ) C SS / DEL * ( 4.0 − VO )
=
I CHG
52.5 *10 − 6
(9)
Once CSS/DEL is chosen, the minimum over-current fault latch delay time tOCDEL is fixed and can be quantified as
t OCDEL =
C SS / DEL * 0.12 C SS / DEL * 0.12
=
I DISCHG
55 * 10 −6
(10)
VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC
The slew rate of VDAC down-slope SRDOWN can be programmed by the external capacitor CVDAC as defined in
(11), where ISINK is the sink current of VDAC pin. The slew rate of VDAC up-slope is the same as that of downslope. The resistor RVDAC is used to compensate VDAC circuit and can be calculated as follows
CVDAC =
I SINK
44 *10 −6
=
SR DOWN
SR DOWN
RVDAC = 0.5 +
3.2 ∗ 10 −15
CVDAC 2
(11)
(12)
Over Current Setting Resistor ROCSET
The inductor DC resistance is utilized to sense the inductor current. The copper wire of inductor has a constant
temperature coefficient of 3850 ppm/°C, and therefore the maximum inductor DCR can be calculated from (13),
where RL_MAX and RL_ROOM are the inductor DCR at maximum temperature TL_MAX and room temperature
T_ROOM respectively.
R L _ MAX = R L _ ROOM ∗ [1 + 3850 * 10 −6 ∗ (TL _ MAX − TROOM )]
(13)
The total input offset voltage (VCS_TOFST) of current sense amplifier in phase ICs is the sum of input offset
(VCS_OFST) of the amplifier itself and that created by the amplifier input bias current flowing through the current
sense resistor RCS.
VCS _ TOFST = VCS _ OFST + I CSIN + ∗ RCS
(14)
The over-current limit is set by the external resistor ROCSET and is given by (15). In a multiphase architecture the
peak to peak ripple of the net inductor current is much smaller than the stand alone phase due to interleaving.
The ratio of the peak to average current in this case can be approximated using (16).
ROCSET = [
I LIMIT
∗ RL _ MAX ∗ (1 + K P ) + VCS _ TOFST ] ∗ GCS / I OCSET
n
m m +1


VI ⋅ D ⋅ (1 − D) ⋅ n ⋅ ( D − n ) ⋅ ( n − D)


KP =
(I LIMIT / n) ⋅ L ⋅ f sw ⋅ 2 ⋅ D ⋅ (1 − D)
(15)
(16)
Where; ILIMIT=Over current limit, n=Number of phases, KP=Ratio of the peak to average current for the inductor,
GCS=Gain of the current sense amplifier, IOCSET= Determined by the ROSC and given by Figure 24,
D=Vo/VI, m=Maximum integer that doesn’t exceed (n*D)
Page 32 of 48
July 28, 2009
IR3500A
No Load Output Voltage Setting Resistor RVSETPT,
A resistor between VSETPT pin and VDAC is used to create output voltage offset VO_NLOFST, which is the
difference between VDAC voltage and output voltage at no load condition. RVSETPT is determined by (17), where
IVSETPT is the current flowing out of VSETPT pin as shown in Figure 23.
RVSETPT =
VO _ NLOFST
(17)
IVSETPT
VCCL Capacitor CVCCL
The capacitor is selected based on the stability requirement of the linear regulator and the load current to be
driven. The linear regulator supplies the bias and gate drive current of the phase ICs. A 4.7uF normally ensures
stable VCCL performance for Intel VR11 and AMD applications.
VCCL Programming Resistor RVCCLFB1 and RVCCLFB2
Since VCCL voltage is proportional to the MOSFET gate driver loss and inversely proportional to the
MOSFET conduction loss, the optimum voltage should be chosen to maximize the converter efficiency. VCCL
linear regulator consists of an external NPN transistor, a ceramic capacitor and a programmable resistor
divider. Pre-select RVCCLFB1, and calculate RVCCLFB2 from (18).
RVCCLFB 2 =
RVCCLFB1 *1.19
VCCL − 1.19
(18)
VCCL Regulator Drive Resistor RVCCLDRV
The drive resistor is primarily dependent on the load current requirement of the linear regulator and the
minimum input voltage requirements. The following equation gives an estimate of the average load current of
the switching phase ICs.
[
]
I drive _ avg = (Q gb + Q gt ) ⋅ f sw + 10 mA ⋅ n
(19)
Qgb and Qgt are the gate charge of the top and bottom FET. For a minimum input voltage and a maximum
VCCL, the maximum RVCCLDRV required to use the full pull-down current of the VCCL driver is given by
RVCCLDRV =
V I (min) − 0.7 − VCCL(max)
I drive _ avg / β min
(20)
Due to limited pull down capability of the VCCLDRV pin, make sure the following condition is satisfied.
VI (max) − 0.7 − VCCL (min)
< 10 mA
RVCCLDRV
(21)
In the above equation, VI( min) and VI( max) is the minimum and maximum anticipated input voltage. If the
above condition is not satisfied there is a need to use a device with higher βmin or Darlington configuration can
be used instead of a single NPN transistor.
Thermistor RTHERM and Over Temperature Setting Resistors RHOTSET1 and RHOTSET2
The threshold voltage of VRHOT comparator is fixed at 1.6V, and a negative temperature coefficient (NTC)
thermistor RTHERM is required to sense the temperature of the power stage. If we pre-select RTHERM, the NTC
thermistor resistance at allowed maximum temperature TMAX is calculated from (22).
Page 33 of 48
July 28, 2009
IR3500A
RTMAX = RTHERM * EXP[ BTHERM * (
1
T L _ MAX
−
1
T _ ROOM
(22)
)]
Select the series resistor RHOTSET2 to linearize the NTC thermistor, which has non-linear characteristics in the
operational temperature range. Then calculate RHOTSET1 corresponding to the allowed maximum temperature
TMAX from (23).
R HOTSET 1 =
( RTMAX + R HOTSET 2 ) * (VCCL − 1.6)
1.6
(23)
VOLTAGE LOOP COMPENSATION
The adaptive voltage positioning (AVP) is usually adopted in the computer applications to improve the transient
response and reduce the power loss at heavy load. Like current mode control, the adaptive voltage positioning
loop introduces an extra zero to the voltage loop and splits the double poles of the power stage, which makes the
voltage loop compensation much easier.
Adaptive voltage positioning lowers the converter voltage by RO*IO, where RO is the required output impedance of
the converter. Pre-select feedback resistor RFB, and calculate the droop resistor RDRP,
RDRP =
RFB ∗ RL _ MAX * GCS
(25)
n ∗ RO
The selection of compensation types depends on the output capacitors used in the converter. For applications
using Electrolytic, Polymer or AL-Polymer capacitors and running at lower frequency, type II compensation shown
in Figure 22(a) is usually enough. While for the applications using only ceramic capacitors and running at higher
frequency, type III compensation shown in Figure 22(b) is preferred.
For applications where AVP is not required, the compensation is the same as for the regular voltage mode
control. For converters using Polymer, AL-Polymer, and ceramic capacitors, which have much higher ESR zero
frequency, type III compensation is required as shown in Figure 22(b) with RDRP and CDRP removed.
CCP1
CCP1
RFB
RCP
CCP
VO+
RCP
CCP
RFB1
CFB
FB
-
RFB
VO+
FB
EAOUT
-
RDRP
EAOUT
RDRP
VDRP
VDAC
+
(a) Type II compensation
EAOUT
VDAC
VDRP
EAOUT
+
CDRP
(b) Type III compensation
Figure 22 - Voltage loop compensation network
Type II Compensation for AVP Applications
Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between
1/10 and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor across
the output inductors matches that of the inductor, and determine RCP and CCP from (26) and (27), where LE and
CE are the equivalent inductance of output inductors and the equivalent capacitance of output capacitors
respectively.
Page 34 of 48
July 28, 2009
IR3500A
(2π ∗ fC ) 2 ∗ LE ∗ CE ∗ RFB ∗ 5
RCP =
(26)
VI * 1 + ( 2π * fC * C * RC ) 2
10 ∗ LE ∗ C E
CCP =
(27)
RCP
CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise.
A ceramic capacitor between 10pF and 220pF is usually enough.
Type III Compensation for AVP Applications
Determine the compensation at no load, the worst case condition. Assume the time constant of the resistor and
capacitor across the output inductors matches that of the inductor, the crossover frequency and phase margin of
the voltage loop can be estimated by (28) and (29), where RLE is the equivalent resistance of inductor DCR.
f C1 =
RDRP
2π * CE ∗ GCS * RFB ∗ RLE
θ C1 = 90 − A tan(0.5) ∗
(28)
180
(29)
π
Choose the desired crossover frequency fc around fc1 estimated by (28) or choose fc between 1/10 and 1/5 of
the switching frequency per phase, and select the components to ensure the slope of close loop gain is -20dB
per decade around the crossover frequency. Choose resistor RFB1 according to (30), and determine CFB and
CDRP from (31) and (32).
1
R FB
2
R FB1 =
CFB =
to
R FB1 =
2
R FB
3
1
4π ∗ fC ∗ RFB1
C DRP =
( R FB + R FB1 ) ∗ C FB
R DRP
(30)
(31)
(32)
RCP and CCP have limited effect on the crossover frequency, and are used only to fine tune the crossover
frequency and transient load response. Determine RCP and CCP from (33) and (34).
RCP =
CCP =
(2π ∗ fC ) 2 ∗ LE ∗ CE ∗ RFB ∗ 5
VI
10 ∗ LE ∗ C E
RCP
(33)
(34)
CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise.
A ceramic capacitor between 10pF and 220pF is usually enough.
Type III Compensation for Non-AVP Applications
Resistor RDRP and capacitor CDRP are not needed. Choose the crossover frequency fc between 1/10 and 1/5 of
the switching frequency per phase and select the desired phase margin θc. Calculate K factor from (35), and
determine the component values based on (36) to (40),
π
θ
K = tan[ ∗ ( C + 1.5)]
4 180
Page 35 of 48
(35)
July 28, 2009
IR3500A
RCP = RFB ∗
( 2π ∗ LE ∗ CE ∗ fC ) 2 ∗ 5
VI ∗ K
(36)
CCP =
K
2π ∗ fC ∗ RCP
(37)
CCP1 =
1
2π ∗ fC ∗ K ∗ RCP
(38)
CFB =
K
2π ∗ fC ∗ RFB
(39)
R FB1 =
1
2π ∗ f C ∗ K ∗ C FB
(40)
DESIGN EXAMPLE 1 – AMD OPTERON CONVERTER (FIGURE 20)
SPECIFICATIONS
Input Voltage: VI=12 V
DAC Voltage: VDAC=1.3 V
No Load Output Voltage Offset: VO_NLOFST=10 mV
Output Current: IO=120 ADC
Maximum Output Current: IOMAX=135 ADC
Output Impedance: RO=0.7 mΩ
Soft Start Delay Time: TD1=1-5mS
Soft Start Time: TD2=2 mS
VR Ready Delay Time: TD3=0-10mS
Maximum Over Current Delay: tOCDEL<2.5mS
Dynamic VID Down-Slope Slew Rate: SRDOWN=2.5mV/uS
Over Temperature Threshold: TMAX=115 ºC
POWER STAGE
Phase Number: n=3
Switching Frequency: fSW =250 kHz
Output Inductors: L=470 nH, RL= 1mΩ
Output Capacitors: Polymer, C=560uF, RC= 7mΩ, Number Cn=12
IR3500A EXTERNAL COMPONENTS
Oscillator Resistor Rosc
Once the switching frequency is chosen, ROSC can be determined from the curve in Figure 23. For a switching
frequency of 250kHz per phase, choose ROSC=50kΩ. The reference current for VSETPT and OCSET is given by
11.9 uA.
Soft Start Capacitor CSS/DEL
Determine the soft start capacitor from the required soft start time.
CSS / DEL =
TD 2 * I CHG 2 *10−3 * 52.5 *10−6
=
= 0.1uF
VO
1.3
Page 36 of 48
July 28, 2009
IR3500A
The soft start delay time is
TD1 =
C SS / DEL *1.4 0.1*10 −6 *1.4
=
= 2.67 mS
I CHG
52.5 *10 −6
The VR ready delay time is
TD3 =
C SS / DEL * ( 4.0 − VO ) 0.1*10 −6 * ( 4.0 − 1.3)
=
= 5.14mS
I CHG
52.5 *10 −6
The minimum over current fault latch delay time is
t OCDEL =
C SS / DEL * 0.12 0.1 * 10 −6 * 0.12
=
= 0.2ms
I DISCHG
55 * 10 −6
VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC
Calculate the VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate. The
up-slope slew rate is the same as the down-slope slew rate.
CVDAC =
I SINK
44 *10 −6
=
= 18nF
SR DOWN 2.5 *10 −3 / 10 −6
Calculate the programming resistor.
RVDAC = 0.5 +
3.2 *10−15
CVDAC 2
= 0.5 +
3.2 *10−15
= 10Ω
(18 *10−9 ) 2
Over Current Setting Resistor ROCSET
The room temperature is 25ºC and the target PCB temperature is 100 ºC. The phase IC die temperature is about
1 ºC higher than that of phase IC, and the inductor temperature is close to PCB temperature.
Calculate Inductor DC resistance at 100 ºC,
RL _ MAX = RL _ ROOM ∗ [1 + 3850*10−6 ∗ (TL _ MAX − TROOM )] = 1*10−3 ∗ [1 + 3850*10−6 ∗ (100 − 25)] = 1.29mΩ
Set the over current limit at 135A. From Figure 24, the bias current of OCSET pin (IOCSET) is 11.9uA with
ROSC=50kΩ. The total current sense amplifier input offset voltage is 0.3mV, which includes the offset created by
the current sense amplifier (CSA) input bias current through the resistor RCS.
VCS _ TOFST = 0.3mV
Calculate constant KP, the ratio of inductor peak current over average current in each phase,
m m +1


VI ⋅ D ⋅ (1 − D) ⋅ n ⋅ ( D − n ) ⋅ ( n − D)
=
KP = 
(I LIMIT / n ) ⋅ L ⋅ f sw ⋅ 2 ⋅ D ⋅ (1 − D)
0 0 +1


12 ⋅ 0.108 ⋅ (1 − 0.108) ⋅ 3 ⋅ (0.108 − 3 ) ⋅ ( 3 − 0.108)

 = 0.082
(135 / 3) ⋅ 0.47u ⋅ 250k ⋅ 2 ⋅ 0.108 ⋅ (1 − 0.108)
I LIMIT
∗ RL _ MAX ∗ (1 + K P ) + VCS _ TOFST ] ∗ GCS / I OCSET
n
135
=(
∗ 1.29 * 10 −3 ∗ 1.082 + 0.3 * 10 −3 ) ∗ 34 /(11.9 * 10 − 6 ) = 181kΩ
3
ROCSET = [
Page 37 of 48
July 28, 2009
IR3500A
No Load Output Voltage Setting Resistor RVSETPT and Adaptive Voltage Positioning Resistor RDRP
From Figure 24, the bias current of VSETPT pin is 11.9uA with ROSC=50kΩ.
V CS _ TOFST
RVSETPT =
I VSETPT
=
10 * 10 −3
= 840 Ω , choose RVSETPT=825Ω.
11 .9 * 10 − 6
VCCL Programming Resistor RVCCLFB1 and RVCCLFB2
Choose VCCL=7V to maximize the converter efficiency. Pre-select RVCCLFB1=20kΩ, and calculate RVCCLFB2.
RVCCLFB 2 =
RVCCLFB 1 *1.19 20 *103 *1.19
=
= 4.05kΩ
VCCL − 1.19
7 − 1.19
VCCL Drive Resistor RVCCLDRV
The maximum drive current for the linear regulator is dependent on the type of MosFET used. For this
example its assumed that IR6622/ IRF6691 are used as buck switches.
I drive _ avg = [( 47 n + 11n ) ⋅ 250 k + 10 mA ] ⋅ 3 = 75 mA
(19)
The minimum input voltage is assumed to be 10 V and VCCL is fixed at 6.5V for this design.
RVCCLDRV =
10V − 0.7V − 6.5V
= 1.8kΩ
75mA / 50
(20)
Assuming the maximum input voltage to as 14 V,
14V − 0.7 − 6.5
= 3mA < 10 mA
1 .8 k Ω
(21)
Thermistor RTHERM and Over Temperature Setting Resistors RHOTSET1 and RHOTSET2
Choose NTC thermistor RTHERM=2.2kΩ, which has a constant of BTHERM=3520, and the NTC thermistor
resistance at the allowed maximum temperature TMAX is,
RTMAX = RTHERM * EXP[ BTHERM * (
1
T L _ MAX
−
1
T _ ROOM
)] = 2.2 *10 3 * EXP[3520 * (
1
1
−
)] = 142Ω
273 + 115 273 + 25
Select RHOTSET2 = 931Ω to linearize the NTC, which has non-linear characteristics in the operational temperature
range. Then calculate RHOTSET1 corresponding to the allowed maximum temperature TMAX.
R HOTSET 1 =
( RTMAX + R HOTSET 2 ) * (VCCL − 1.6) (142 + 931) * (7 − 1.6)
=
= 3.63kΩ ,
1 .6
1.6
choose
RHOTSET1=3.65kΩ.
VOLTAGE LOOP COMPENSATION
Type II compensation is used for the converter with Polymer output capacitors. Choose the crossover frequency
fc=25kHz, which is 1/10 of the switching frequency per phase, and determine Rcp and CCP.
Pre-select RFB=2.00kΩ, and calculate RDRP, RCP and CCP.
Page 38 of 48
July 28, 2009
IR3500A
R DRP =
RCP =
CCP =
R FB ∗ R L _ MAX * GCS
n ∗ RO
2000 * 1.29 * 10 −3 * 34
=
= 41.8kΩ , choose RDRP=42.2kΩ
3 * 0.7 * 10 −3
(2π ∗ fC )2 ∗ LE ∗ CE ∗ RFB ∗ 5
VI * 1 + (2π * fC * C * RC )2
10 ∗ LE ∗ CE
=
=
(2π ∗ 25 ∗103 )2 ∗ (470 ∗10−9 / 3) ∗ (560 ∗10−6 ∗12) ∗ 2000 ∗ 5
12 * 1 + (2π * 25 *103 * 560 *10−6 * 7 *10−3 )2
10 ∗ (470 ∗ 10−9 / 3) ∗ (560 ∗ 10 −6 *12)
RCP
21.5 ∗103
Choose CCP1=47pF to reduce high frequency noise.
= 21.5kΩ ,
= 15nF
DESIGN EXAMPLE 2 – VR11 HIGH FREQUENCY ALL-CERAMIC CONVERTER (FIG. 21)
SPECIFICATIONS
Input Voltage: VI=12 V
DAC Voltage: VDAC=1.3 V
No Load Output Voltage Offset: VO_NLOFST=20 mV
Output Current: IO=105 ADC
Maximum Output Current: IOMAX=120 ADC
Output Impedance: RO=0.91 mΩ
Soft Start Delay Time: TD1=1-5mS
Soft Start Time: TD2=0-3mS
VID Sample Delay Time: TD3=0.05-3mS
VID Rise Time: TD4=0-2.5mS
VR Ready Delay Time: TD5=0-3mS
Maximum Over Current Delay Time: tOCDEL<2.5mS
Dynamic VID Down-Slope Slew Rate: SRDOWN=2.5mV/uS
Over Temperature Threshold: TMAX=115 ºC
POWER STAGE
Phase Number: n=6
Switching Frequency: fSW = 800 kHz
Output Inductors: L=100 nH, RL=0.5 mΩ
Output Capacitors: Ceramic, C=22uF, RC= 2mΩ, Number Cn=62
IR3500A EXTERNAL COMPONENTS
Oscillator Resistor Rosc
Once the switching frequency is chosen, ROSC can be determined from the curve in Figure 23 data sheet. For a
switching frequency of 800kHz per phase, choose ROSC = 15.0 kΩ. The reference current is given by 40uA.
Soft Start Capacitor CSS/DEL
Determine the soft start capacitor to meet the specifications of the delay time.
Choose CSS/DEL=0.1uF. The soft start delay time is
TD1 =
C SS / DEL * 1.4 0.1 * 10 −6 * 1.4
=
= 2.67mS
I CHG
52.5 * 10 −6
Page 39 of 48
July 28, 2009
IR3500A
The soft start time is
TD 2 =
C SS / DEL *1.1 0.1*10 −6 *1.1
=
= 2.1mS
I CHG
52.5 *10 − 6
The VID sample delay time is
TD3 =
C SS / DEL * (3.2 − 1.4 − 1.1) 0.1*10 −6 * 0.7
=
= 1.33mS
I CHG
52.5 *10 − 6
VID rise time is
TD 4 =
C SS / DEL * V DAC − 1.1
I CHG
=
0.1*10 −6 * 1.3 − 1.1
52.5 *10 − 6
= 0.38mS
The VR ready delay time is
TD5 =
C SS / DEL * (3.92 − 3)
0.1 * 10 −6 * 0.92
− TD 4 =
− TD 4 = 1.37 mS
I CHG
52.5 * 10 −6
Minimum over current fault latch delay time is
t OCDEL =
C SS / DEL * 0.12 0.1 * 10 −6 * 0.12
=
= 0.21ms
I OCDISCHG
55 * 10 −6
VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC
Calculate the VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate. The
up-slope slew rate is the same as the down-slope slew rate.
CVDAC =
I SINK
44 *10 −6
=
= 18nF
SR DOWN 2.5 *10 −3 / 10 − 6
Calculate the programming resistor.
RVDAC = 0.5 +
3.2 *10−15
CVDAC 2
= 0.5 +
3.2 *10−15
(18 *10−9 ) 2
= 10Ω
Over Current Setting Resistor ROCSET
The room temperature is 25ºC and the target PCB temperature is 100 ºC. The phase IC die temperature is about
1 ºC higher than that of phase IC, and the inductor temperature is close to PCB temperature.
Calculate Inductor DC resistance at 100 ºC,
RL _ MAX = RL _ ROOM ∗ [1 + 3850*10−6 ∗ (TL _ MAX − TROOM )] = 0.5 *10−3 ∗ [1 + 3850*10−6 ∗ (100 − 25)] = 0.64mΩ
Set the over current limit at 135A. From Figure 22, the bias current of OCSET pin (IOCSET) is 40uA with
ROSC=15kΩ. The total current sense amplifier input offset voltage is 0.3mV, which includes the offset created by
the current sense amplifier (CSA) input bias current through the resistor RCS.
VCS _ TOFST = 0.3mV
Page 40 of 48
July 28, 2009
IR3500A
Calculate constant KP, the ratio of inductor peak current over average current in each phase,
m m +1


V I ⋅ D ⋅ (1 − D) ⋅ n ⋅ ( D − n ) ⋅ ( n − D)


KP =
=
(I LIMIT / n) ⋅ L ⋅ f sw ⋅ 2 ⋅ D ⋅ (1 − D)
ROCSET = [
=(
0 0 +1


12 ⋅ 0.108 ⋅ (1 − 0.108) ⋅ 6 ⋅ (0.108 − 6 ) ⋅ ( 6 − 0.108)


= 0.126
(135 / 6) ⋅ 0.1u ⋅ 800k ⋅ 2 ⋅ 0.108 ⋅ (1 − 0.108)
I LIMIT
∗ RL _ MAX ∗ (1 + K P ) + VCS _ TOFST ] ∗ GCS / I OCSET
n
135
∗ 0.64 * 10 − 3 ∗ 1.126 + 0.3 * 10 − 3 ) ∗ 34 /( 40 * 10 − 6 ) = 14 kΩ
6
Calculate constant KP, the ratio of inductor peak current over average current in each phase,
No Load Output Voltage Setting Resistor RVSETPT and Adaptive Voltage Positioning Resistor RDRP
From Figure 24, the bias current of VSETPT pin is 40uA with ROSC=15kΩ.
RVSETPT =
VO _ NLOFST
I VSETPT
=
20 * 10 −3
= 500Ω
40 * 10 −6
VCCL Programming Resistor RVCCLFB1 and RVCCLFB2
Choose VCCL=7V to maximize the converter efficiency. Pre-select RVCCLFB1=20kΩ, and calculate RVCCLFB2.
RVCCLFB 2 =
RVCCLFB1 *1.19 20 *103 *1.19
=
= 4.05kΩ
VCCL − 1.19
7 − 1.19
VCCL Drive Resistor RVCCLDRV
The maximum drive current for the linear regulator is dependent on the type of MosFET used. For this
example, it’s assumed that IR6622/ IRF6691 are used as buck switches.
I drive _ avg = [( 47 n + 11n ) ⋅ 800 k + 10 mA ] ⋅ 6 = 350 mA
(19)
The minimum input voltage is assumed to be 10.5 V and VCCL is fixed at 6.5V for this design.
RVCCLDRV =
10.5V − 0.7V − 6.5V
= 660Ω
350mA / 70
(20)
Choose a transistor with β(min) of 70. The maximum input voltage is assumed 13.5 V,
13.5V − 0.7 − 6.5
= 9.5mA < 10 mA
660Ω
(21)
Thermistor RTHERM and Over Temperature Setting Resistors RHOTSET1 and RHOTSET2
Choose NTC thermistor RTHERM=2.2kΩ, which has a constant of BTHERM=3520, and the NTC thermistor
resistance at the allowed maximum temperature TMAX is,
RTMAX = RTHERM * EXP[ BTHERM * (
1
1
1
1
−
)] = 2.2 *10 3 * EXP[3520 * (
−
)] = 142Ω
T L _ MAX T _ ROOM
273 + 115 273 + 25
Select RHOTSET2 = 931Ω to linearize the NTC, which has non-linear characteristics in the operational temperature
range. Then calculate RHOTSET1 corresponding to the allowed maximum temperature TMAX.
Page 41 of 48
July 28, 2009
IR3500A
R HOTSET 1 =
( RTMAX + R HOTSET 2 ) * (VCCL − 1.6) (142 + 931) * (7 − 1.6)
=
= 3.63kΩ , choose RHOTSET1=3.65kΩ.
1.6
1.6
VOLTAGE LOOP COMPENSATION
Type III compensation is used for the converter with only ceramic output capacitors. The crossover frequency and
phase margin of the voltage loop can be estimated as follows.
Choose RFB = 1.65kΩ, and calculate RDRP.
RDRP =
RFB ∗ RL _ MAX * GCS
n ∗ RO
=
1.65 *103 * 0.64 *10−3 * 34
= 6.58kΩ , choose RDRP=6.65kΩ.
6 * 0.91 *10 −3
R DRP
6.65 *10 3
=
= 165 kHz
2π ∗ C E ∗ G CS ∗ R FB ∗ R LE
2π ∗ ( 62 ∗ 22 * 10 − 6 ) ∗ 34 ∗ 1.65 *10 3 ∗ ( 0.5 * 10 − 3 / 6)
f C1 =
θC1 = 90 − A tan(0.5) ∗
Choose RFB1 =
180
π
= 63°
2
2
∗ RFB = ∗ 1.65 *103 = 1.10kΩ
3
3
Choose the desired crossover frequency fc (=150kHz) around fc1 estimated above, and calculate
1
CFB =
4π ∗ fC ∗ RFB1
CDRP =
RCP =
=
1
= 4.8nF , choose CFB=4.7nF.
4π ∗ 150 *103 ∗ 1.1 *103
( RFB + RFB1 ) ∗ CFB (1.65 *103 + 1.1 *103 ) ∗ 4.7 *10−9
=
= 2.0nF
RDRP
6.65 *103
, choose CDRP=2.2nF.
( 2π ∗ fC ) 2 ∗ LE ∗ CE ∗ RFB ∗ 5 ( 2π ∗150 *103 ) 2 ∗ (100 *10−9 / 6) ∗ ( 22 *10−6 ∗ 62) ∗ 1.65 *103 * 5
=
= 13.9kΩ
VI
12
Choose RFB=13.7kΩ.
CCP =
10 ∗ LE ∗ CE
RCP
=
10 ∗ (100 *10−9 / 6) ∗ (22 *10 −6 * 62)
13.7 ∗ 103
= 3.5nF , choose CCP=3.3nF.
Choose CCP1=47pF to reduce high frequency noise.
Page 42 of 48
July 28, 2009
IR3500A
Figure 23 - Frequency variation with ROSC.
Figure 24 - ISETPT, OCSET with ROSC.
Page 43 of 48
July 28, 2009
IR3500A
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout, therefore minimizing the noise coupled to the IC.
To
Phase
ICs
RVCCL2
Page 44 of 48
VOSNS+
VCCLFB
VOSNS-
VCCLDRV
HOTSET
VID0
VID1
VID2
ENABLE
VID3
VIDSEL
VID4
VRHOT
VID5
VRRDY
CCP1
CFB1
RFB2
VO
VCCL
RFB1
PHSIN
To
Thermistor
RHOTSET1
FB
VID7
RCP
RFB
RDRP
VDRP
IIN
VSETPT
OCSET
VDAC
EAOUT
PHSOUT
VID6
To
LGND
SS/DEL
CLKOUT
ROSC / OVP
LGND
CSS/DEL
To OVP
Circuit
RHOTSET2
ROSC/OVP
CCP
CDRP
To
Phase ICs
RVDAC
LGND
PLANE
CVDAC
•
•
RVCCL1
•
RVCCLDRV
•
Dedicate at least one middle layer for a ground plane LGND.
Connect the ground tab under the control IC to LGND plane through a via.
Place VCCL decoupling capacitor VCCL as close as possible to VCCL and LGND pins.
Place the following critical components on the same layer as control IC and position them as close as possible
to the respective pins, ROSC, ROCSET, RVDAC, CVDAC, and CSS/DEL. Avoid using any via for the connection.
Place the compensation components on the same layer as control IC and position them as close as possible to
EAOUT, FB, VO and VDRP pins. Avoid using any via for the connection.
Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS-, and avoid crossing over
the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes.
Avoid analog control bus signals, VDAC, IIN, and especially EAOUT, crossing over the fast transition nodes.
Separate digital bus, CLKOUT, PHSOUT and PHSIN from the analog control bus and other compensation
components.
CVCCL
•
•
•
•
To Voltage
Remote
Sense
To VCCL
To
Thermistor
To VIN
To SYSTEM
July 28, 2009
IR3500A
PCB METAL AND COMPONENT PLACEMENT
• Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥
0.2mm to minimize shorting.
• Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm inboard
extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard extension will
accommodate any part misalignment and ensure a fillet.
• Center pad land length and width should be equal to maximum part pad length and width. However, the minimum
metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥ 0.23mm for 3 oz.
Copper)
• Four 0.3mm diameter vias shall be placed in the pad land spaced at 1.2mm, and connected to ground to minimize
the noise effect on the IC and to transfer heat to the PCB.
• No PCB traces should be routed nor vias placed under any of the 4 corners of the IC package. Doing so can cause
the IC to rise up from the PCB resulting in poor solder joints to the IC leads.
Page 45 of 48
July 28, 2009
IR3500A
SOLDER RESIST
• The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist
mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non Solder Mask
Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads.
• The minimum solder resist width is 0.13mm.
• At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a
solder resist width of ≥ 0.17mm remains.
• The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper
of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable to have the solder
resist opening for the land pad to be smaller than the part pad.
• Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of
the solder resist strip separating the lead lands from the pad land.
• The four vias in the land pad should be tented or plugged from bottom board side with solder resist.
Page 46 of 48
July 28, 2009
IR3500A
STENCIL DESIGN
• The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the
amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the leads
are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are
difficult to maintain repeatable solder release.
• The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land.
• The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately 50% area
of solder on the center pad. If too much solder is deposited on the center pad the part will float and the lead lands
will be open.
• The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus
an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is
pushed into the solder paste.
Page 47 of 48
July 28, 2009
IR3500A
PACKAGE INFORMATION
o
o
32L MLPQ (5 x 5 mm Body) – θJA = 28 C/W, θJC = 2 C/W
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. www.irf.com
www.irf.com
Page 48 of 48
July 28, 2009