Data Sheet, Rev. 1.2, April 2009 TLE7278-2 Low Dropout Voltage Regulator Automotive Power Low Dropout Voltage Regulator 1 TLE7278-2 Overview Features • • • • • • • • • • • • • • Output Voltage 5 V, 3.3 V or 2.6 V Output Voltage Tolerance ±2% Output Current Up To 180 mA Ultra Low Quiescent Current Consumption < 36 µA Enable Function Very Low Dropout voltage Reset With Adjustable Power-On Delay Standard Watchdog With Current Dependent Deactivation Output Current Limitation Wide Operation Range Up To 45 V Wide Temperature Range From -40 °C To 150 °C Overtemperature Shutdown Green Product (RoHS compliant) AEC Qualified PG-DSO-14 PG-SSOP-14 Exposed Pad Description The TLE7278-2 is a monolithic integrated voltage regulator with integrated standard watchdog and reset dedicated for microcontroller supplies under harsh automotive environment conditions. The watchdog circuit is deactivated for very low loads at the device’s output (e.g. microcontroller in standby mode). Due to its ultra low quiescent current the TLE7278-2 is perfectly suited for applications that are permanently connected to battery. In addition, the regulator can be shut down via the Enable input causing the current consumption to drop below 3 µA. The TLE7278-2 is equipped with an overtemperature shutdown and an output current limitation protecting the device against overload, short circuit and overtemperature. It operates in the wide junction temperature range from -40 °C to 150 °C. Type Package Marking TLE7278-2GV50 PG-DSO-14 TLE7278-2GV50 TLE7278-2GV33 PG-DSO-14 TLE7278-2GV33 TLE7278-2GV26 PG-DSO-14 TLE7278-2GV26 TLE7278-2EV50 PG-SSOP-14 Exposed Pad 7278 V50 Data Sheet 2 Rev. 1.2, 2009-04-28 TLE7278-2 Block Diagram 2 Block Diagram TLE7278-2 I Q Overtemperature shutdown RO Bandgap Reference 1 WDI WM1 Charge Pump EN Reset Generator and Watchdog WM2 Enable GND Figure 1 Data Sheet Block Diagram 3 Rev. 1.2, 2009-04-28 TLE7278-2 Pin Configuration 3 Pin Configuration 3.1 Pin Assignment (PG-DSO-14) RO GND GND GND GND WM2 WM1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 EN I GND GND GND Q WDI AEP02113_7278 Figure 2 Pin Configuration 3.2 Pin Definitions and Functions (PG-DSO-14) Pin Symbol Function 1 RO Reset Output TLE7278-2GV33, TLE7278-2GV26: open drain output; TLE7278-2GV50: integrated 20 kΩ pull-up resistor 2-5, 10-12 GND Ground connect pin 2 and 3 to GND; connect pin 4-5, 10-12 to PCB heat sink area with GND potential 7 WM1 Watchdog Mode Bit 1 watchdog and Reset mode selection, see Figure 5; connect to Q or GND 6 WM2 Watchdog Mode Bit 2 watchdog and reset mode selection, see Figure 5; connect to Q or GND 8 WDI Watchdog Input trigger input for watchdog pulses; pull down to GND if not needed and turn off the watchdog with WM1 and WM2 pin 9 Q Output Voltage block to GND with a ceramic capacitor close to the IC terminals, respecting the values given for its capacitance CQ and ESR in “Functional Range” on Page 7 13 I Input Voltage block to ground directly at the IC with a 100 nF ceramic capacitor 14 EN Enable Input low level disables the IC; integrated pull-down resistor to GND Data Sheet 4 Rev. 1.2, 2009-04-28 TLE7278-2 Pin Configuration 3.3 Pin Assignments (PG-SSOP-14 Exposed Pad) 52 *1' (1 , QF QF QF QF *1' QF :0 4 :0 :', 7/(B3,1&21),*B6623 69* Figure 3 Pin Assignment PG-SSOP-14 Exposed Pad (top view) 3.4 Pin Definitions and Functions (PG-SSOP-14 Exposed Pad) Table 1 Pin Definitions and Functions Pin No. Symbol Function 1 RO Reset Output integrated 20 kΩ pull-up resistor; leave open if not needed 2, 5 GND Ground connect to GND 3, 4, 10, 11, 12 n.c. not connected leave open or connect to GND 6 WM2 Watchdog Mode Bit 2 watchdog and reset mode selection, see Figure 5; connect to Q or GND 7 WM1 Watchdog Mode Bit 1 watchdog and Reset mode selection, see Figure 5; connect to Q or GND 8 WDI Watchdog Input trigger input for watchdog pulses; pull down to GND if not needed and turn off the watchdog with WM1 and WM2 pin 9 Q Output Voltage block to GND with a ceramic capacitor close to the IC terminals, respecting the values given for its capacitance CQ and ESR in “Functional Range” on Page 7 13 I Input Voltage block to ground directly at the IC with a 100 nF ceramic capacitor 14 EN Enable Input low level disables the IC; integrated pull-down resistor Pad – Exposed Pad connect to heatsink area; connect to GND on PCB Data Sheet 5 Rev. 1.2, 2009-04-28 TLE7278-2 General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Absolute Maximum Ratings 1) Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions V – Min. Max. VI -0.3 45 VQ VQ -0.3 5.5 V permanent -0.3 6.2 V t < 10 s2) VEN IEN -1 45 V – -1 1 mA – VRO -1 7 V permanent VWM1 VWM1 IWM1 -0.3 5.5 V permanent -0.3 6.2 V t < 10 s2) -5 5 mA – Voltage – 3 kV – Voltage – 1.5 kV – Tj Tstg -40 150 °C – -50 150 °C – Input I 4.1.1 Voltage Output Q, Reset Output RO, Watchdog Mode 2 4.1.2 Voltage 4.1.3 Voltage Enable Input EN 4.1.4 Voltage 4.1.5 Current Watchdog Input WDI 4.1.6 Voltage Watchdog Mode 1 4.1.7 Voltage 4.1.8 Voltage 4.1.9 Current ESD Susceptibility 4.1.10 4.1.11 Human Body Model (HBM)3) Charge Device Model (CDM) 4) Temperatures 4.1.12 Junction temperature 4.1.13 Storage temperature 1) 2) 3) 4) not subject to production test, specified by design exposure to these absolute maximum ratings for extended periods (t > 10 s) may affect device reliability ESD HBM Test according to JEDEC JESD22-A114 ESD CDM Test according AEC/ESDA ESD-STM5.3.1-1999 Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 6 Rev. 1.2, 2009-04-28 TLE7278-2 General Product Characteristics 4.2 Pos. Functional Range Parameter Symbol Limit Values Unit Conditions Min. Max. 5.5 45 V TLE7278-2GV50, TLE7278-2EV50 4.2.2 4.2 45 V TLE7278-2GV33 4.2.3 4.5 45 V TLE7278-2GV26 – nF –1) 3 Ω –2) 150 °C – 4.2.1 4.2.4 4.2.5 Input voltage Output Capacitor’s Requirements for Stability Junction Temperature VI CQ 470 ESR(CQ) – Tj -40 1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30% 2) relevant ESR value at f = 10 kHz Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. 4.3 Pos. Thermal Resistance Parameter Symbol Limit Values Min. Typ. Max. Unit Conditions Package PG-DSO-14 4.3.1 Junction to Soldering Point1) RthJSP – 30 – K/W measured to group of pins 3, 4, 5, 10, 11, 12 4.3.2 Junction to Ambient1) RthJA – 53 – K/W 2) 4.3.3 – 105 – K/W footprint only3) 4.3.4 – 74 – K/W 300 mm2 heatsink area on PCB3) 4.3.5 – 65 – K/W 600 mm2 heatsink area on PCB3) Package PG-SSOP-14 Exposed Pad 4.3.6 Junction to Case1) RthJC – 14 – K/W measured to exposed pad 4.3.7 Junction to Ambient1) RthJA – 47 – K/W 2) 4.3.8 – 141 – K/W footprint only3) 4.3.9 – 66 – K/W 300 mm2 heatsink area on PCB3) 4.3.10 – 56 – K/W 600 mm2 heatsink area on PCB3) 1) not subject to production test, specified by design 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. 3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu). Data Sheet 7 Rev. 1.2, 2009-04-28 TLE7278-2 Block Description and Electrical Characteristics 5 Block Description and Electrical Characteristics 5.1 Circuit Description 5.1.1 Power On Reset and Reset Output For an output voltage level VQ ≥ 1 V the reset output is hold low. When the level of VQ reaches the reset threshold VRT, the signal at RO remains low for the power-up reset delay time tRD. The reset function and timing is illustrated in Figure 4. The reset reaction time tRR avoids wrong triggering caused by short “glitches” on the VQ-line. In case of VQ power down (VQ < VRT for t > tRR) a logic low signal is generated at the pin RO to reset an external micro controller. The TLE7278-2GV50 and TLE7278-2EV50 feature an integrated pull-up resistor on the reset output while the TLE7278-2GV33 and TLE7278-2GV26 have an open drain output requiring an external pull-up resistor. When connected to a voltage level of Vext = 5 V, a recommended value for this external resistor is ≥ 5.6 kΩ. But it’s also possible calculating its value by using the following formula, based on the reset sink current (Example: external pull-up resistor connected to Vext = 5 V): Rextmin = ∆V / IRO = (Vext - VROmin) / IRO = (5 V - 0.25 V) / 1.0 mA = 4.75 kΩ At low output voltage levels VQ < 1 V the integrated pull-up resistor of the TLE7278-2GV50 is switched off setting the reset output high ohmic. VI VRTI t VQ < tRR VRT VRO t RR tRD tRR t VROH VROL t AET03526NEW.VSD Figure 4 Data Sheet Reset Function and Timing Diagram 8 Rev. 1.2, 2009-04-28 TLE7278-2 Block Description and Electrical Characteristics 5.1.2 Watchdog Operation The watchdog uses a fraction of the charge pump oscillator’s clock signal as timebase. The watchdog timebase can be adjusted using the pins WM1 and WM2 (see Figure 5). The watchdog can be turned off setting WM1 and WM2 to high level. The timing values used this text refer to typ. values with WM1 and WM2 connected to GND (fast watchdog and reset timing). If the timebase is switched by changing the condition on the WM pins, the new timing is valid from the beginning of the new period on. From this time on, the frequency on the WDI pin must be adapted. Figure 5 shows the state diagram of the watchdog (WD) and the mode selection. After power-on, the reset output signal at the RO pin (microcontroller reset) is kept LOW for the reset delay time TRD of typ. 16 ms. With the LOW to HIGH transition of the signal at RO the device starts the ignore window time tCW (32 ms). Next the WD starts the Watchdog Period (time frame within a trigger at WDI must occur). From now on the timing of the signal on WDI from the micro controller must correspond the WD-Period tWD,p correspondent the electrical characteristics and based on the setting on the WM pins. A Re-Trigger of the WD-Period is done with a HIGH-to-LOW Transient at the WDI-pin within the set tWD,p. A HIGH to LOW transition of the watchdog trigger signal on pin WDI is taken as a trigger. To avoid wrong triggering due to parasitic glitches two HIGH samples followed by two LOW samples (sample period tsam typ. 0.5 ms) are decoded as a valid trigger. A reset is generated (RO goes LOW) if there is no trigger pulse during the Watchdog Period. VI t VQ VRT t IQ V RO IQ, WD_OFF IQ, WD_ON t TRD TRD Normal operation No Reset during Current shut down trr Power Fail trr t Trigger Window WDI tsam Ingnore Wnd Don’t care WDI during IW t 1. Correct Trigger tWD,p No Trigger causing reset Current Controlled WD-turn off t WM1 L L H H WM2 L H L H Watchdog Mode Fast Slow Fast Off Reset Mode Fast Slow Slow Slow 7278 Timing Figure 5 Data Sheet Watchdog Timing Diagram, Watchdog and Reset Modes 9 Rev. 1.2, 2009-04-28 TLE7278-2 Block Description and Electrical Characteristics 5.2 Electrical Characteristics Electrical Characteristics VI = 13.5 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Typ. Max. Unit Conditions Output Q 5.2.1 Output voltage VQ 4.90 5.00 5.10 V TLE7278-2GV50, TLE7278-2EV50 1 mA < IQ < 180 mA 6 V < VI < 16 V 5.2.2 Output voltage VQ 4.90 5.00 5.10 V TLE7278-2GV50, TLE7278-2EV50 IQ = 10 mA 6 V < VI < 45 V 5.2.3 Output voltage VQ 3.234 3.30 3.366 V TLE7278-2GV33 1 mA < IQ < 180 mA 4.5 V < VI < 16 V 5.2.4 Output voltage VQ 3.234 3.30 3.366 V TLE7278-2GV33 IQ = 10 mA 4.5 V < VI < 45 V 5.2.5 Output voltage VQ 2.548 2.60 2.652 V TLE7278-2GV26 1 mA < IQ < 180 mA 4.5 V < VI < 16 V 5.2.6 Output voltage VQ 2.548 2.60 2.652 V TLE7278-2GV26 IQ = 10 mA 4.5 V < VI < 45 V 5.2.7 Output current limitation IQ 200 – 500 mA 200 – 600 mA – 250 500 mV VQ = 2.0 V VQ = 0 V IQ = 180 mA1) 5.2.8 Dropout Voltage; VDR = VI - VQ VDR TLE7278-2GV50, TLE7278-2EV50 5.2.9 Load regulation ∆VQ,Lo – 50 90 mV 1 mA < IQ < 180 mA 5.2.10 Line regulation ∆VQ,Li – 10 50 mV IQ = 1 mA; 10 V < VI < 32 V 5.2.11 Power-Supply-Ripple-Rejection PSRR – 60 – dB 5.2.12 Reverse Output Current Clamping VQ,REV – – 5.5 V fr = 100 Hz; Vr = 0.5 Vpp IQ,REV = -1 mA; VEN = 0 V Current Consumption 5.2.13 Quiescent current; Iq = II - IQ Iq – 28 36 µA 5.2.14 Quiescent current; Disabled Iq – 1 3 µA VEN,H 3.0 – – V IQ = 100 µA; Tj < 80 °C VEN = 0 V; Tj < 80 °C Enable Input EN 5.2.15 High Level Input Voltage Data Sheet 10 VQ on Rev. 1.2, 2009-04-28 TLE7278-2 Block Description and Electrical Characteristics Electrical Characteristics (cont’d) VI = 13.5 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions VQ = 0.02 V; IQ = 5 mA; Tj < 125 °C VQ = 0.02 V IQ = 5 mA VEN = 5 V Min. Typ. Max. – – 0.5 V – – 0.3 V IEN,H – 3 4 µA VWM1,H 4.00 – – V TLE7278-2GV50, TLE7278-2EV50 5.2.20 2.65 – – V TLE7278-2GV33 5.2.21 2.30 – – V TLE7278-2GV26 VWM1,L – – 0.80 V – VWM2,H 4.00 – – V TLE7278-2GV50, TLE7278-2EV50 5.2.24 2.65 – – V TLE7278-2GV33 5.2.25 2.30 – – V TLE7278-2GV26 VWM2,L – – 0.80 V – VWDI,H 4.0 – – V TLE7278-2GV50, TLE7278-2EV50 5.2.28 2.65 – – V TLE7278-2GV33 5.2.29 2.30 – – V TLE7278-2GV26 – – 0.80 V – – 3 4 µA – 0.5 1 µA VWDI = 5 V VWDI = 0 V; Tj < 80 °C 0.40 0.50 0.60 ms fast watchdog timing 0.80 1.00 1.20 ms slow watchdog timing 25.6 32.0 38.4 ms fast watchdog timing 5.2.16 Low Level Input Voltage VEN,L 5.2.17 5.2.18 High Level Input Current Watchdog Mode Bit 1 5.2.19 5.2.22 High Level Input Voltage Low Level Input Voltage Watchdog Mode Bit 2 5.2.23 5.2.26 High Level Input Voltage Low Level Input Voltage Watchdog Input WDI 5.2.27 High Level Input Voltage 5.2.30 Low Level Input Voltage 5.2.31 High Level Input Current 5.2.32 Low Level Input Current 5.2.33 Watchdog sampling time VWDI,L IWDI,H IWDI,L tsam 5.2.34 Ignore window time tOW 5.2.35 Watchdog Period tWD,p 5.2.36 Watchdog deactivation current threshold IQ,WD_off 51.2 64.0 76.8 ms slow watchdog timing 25.6 32 38.4 ms fast watchdog timing 51.2 64 76.8 ms slow watchdog timing 0.5 – – mA IQ decreasing VI > VI, WD_on > 6.0 V for TLE7278-2GV50, TLE7278-2EV50 VI > VI,WD_on > 4.5 V for TLE7278-2GV33, TLE7278-2GV26 Data Sheet 11 Rev. 1.2, 2009-04-28 TLE7278-2 Block Description and Electrical Characteristics Electrical Characteristics (cont’d) VI = 13.5 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 5.2.37 Parameter Watchdog activation current threshold Symbol IQ,WD_on Limit Values Min. Typ. Max. – – 5 Unit Conditions mA IQ increasing VI > VI,WD_on > 6.0 V for TLE7278-2GV50, TLE7278-2EV50 VI > VI,WD_on > 4.5 V for TLE7278-2GV33, TLE7278-2GV26 Reset Output RO 5.2.38 Output Voltage Reset Switching Threshold VRT 4.50 4.60 4.70 V TLE7278-2GV50, TLE7278-2EV50 VQ decreasing 5.2.39 3.00 3.07 3.13 V TLE7278-2GV332) VQ decreasing 5.2.40 2.35 2.38 2.45 V TLE7278-2GV262) VQ decreasing 5.2.41 Input Voltage Reset Switching Threshold VRT_VI – 3.9 4.0 V TLE7278-2GV262) TLE7278-2GV332) VQ > VRT, VI decreasing 5.2.42 Reset Hysteresis VRH – 45 – mV TLE7278-2GV26 5.2.43 – 60 – mV TLE7278-2GV33 5.2.44 – 90 – mV TLE7278-2GV50, TLE7278-2EV50 1.75 – – mA TLE7278-2GV50, TLE7278-2EV50 VQ = 4.5 V, VRO = 0.25 V 1.3 – – mA 5.2.45 Maximum Reset Sink Current IRO 5.2.46 TLE7278-2GV33 VQ = 3.0 V, VRO = 0.25 V 5.2.47 1.0 – – mA TLE7278-2GV26 VQ = 2.35 V, VRO = 0.25 V VQ ≥ 1 V; IRO < 200 µA 5.2.48 Reset output low voltage VROL – 0.15 0.25 V 5.2.49 Reset high voltage VROH 4.5 – – V TLE7278-2GV50, TLE7278-2EV50 5.2.50 Reset high leakage current IROLK – – 1 µA TLE7278-2GV33 TLE7278-2GV26 Data Sheet 12 Rev. 1.2, 2009-04-28 TLE7278-2 Block Description and Electrical Characteristics Electrical Characteristics (cont’d) VI = 13.5 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Typ. Max. Unit Conditions 5.2.51 Integrated reset pull-up resistor RRO 10 20 40 kΩ TLE7278-2GV50, TLE7278-2EV50 internally connected to VQ 5.2.52 Power-on Reset delay time TRD 12.8 16.0 19.2 ms fast reset timing 25.6 32.0 38.4 ms slow reset timing – 4 12 µs – 5.2.53 Reset Reaction Time TRR 1) measured when the output voltage has dropped 100 mV from the nominal Value obtained at VI = 13.5 V 2) reset output triggered when output voltage VQ is lower than output voltage reset switching threshold VRT or is also triggered, when input voltage is decreasing to VI < 4.0 V and VQ > VRT Data Sheet 13 Rev. 1.2, 2009-04-28 TLE7278-2 Typical Performance Characteristics Current Consumption Iq versus Junction Temperature Tj (EN=ON) Current Consumption Iq versus Output Current IQ (EN=ON) 1_Iq-Tj.vsd 2 _ IQ -IQ .V S D 45 Iq [µA] T j = 2 5 °C VI = 13.5V 40 35 100 IQ = 100 µA T j = -4 0 °C I q [µA] 30 10 25 20 15 10 1 5 0 0.01 -40 -20 0 0 ,1 20 40 60 80 100 120 140 1 Current Consumption Iq versus Input Voltage VI at Tj=25°C (EN=ON) 3A_IQ-VI_25.VSD 3A_IQ-VI_-40.VSD 200 Tj = 25 °C Tj = -40°C Iq [µA] 150 150 100 100 IQ = 100mA IQ = 100mA I Q = 10mA I Q = 10mA 50 IQ = 0.2mA 0 10 20 30 40 IQ = 0.2mA 0 VI [V] Data Sheet 1000 Current Consumption Iq versus Input Voltage VI at Tj=-40°C (EN=ON) 200 50 100 I Q [m A ] Tj [°C] Iq [µA] 10 10 20 30 40 VI [V] 14 Rev. 1.2, 2009-04-28 TLE7278-2 Typical Performance Characteristics (cont´d) Load Regulation dVQ versus Output Current Change dIQ Load Regulation dVQ versus Output Current Change dIQ 18b_dVQ-dIQ_Vi135V.vsd 0 VI = 13.5V ∆VQ 18a_dVQ-dIQ_Vi6V.vsd 0 VI = 6V ∆VQ [mV] [mV] Tj = 25 °C Tj = -40 °C -2 Tj = 150 °C -2 Tj = -40 °C Tj = 25 °C Tj = 150 °C -3 -3 -4 -4 -5 -5 -6 0 -6 200 100 200 100 0 IQ [mA] IQ [mA] Power Supply Ripple Rejection PSRR Load Regulation dVQ versus Output Current Change dIQ 13_PSRR.VSD 80 PSRR IQ = 0.1 mA [dB] 18c_dVQ-dIQ_Vi28V.vsd 0 Tj = 25 °C ∆VQ [mV] IQ = 10 mA VI = 28 IQ = 100 mA 60 -2 50 -3 40 -4 30 10 VRIPPLE = 1 V VIN = 13.5 V CQ = 470nF Ceramics Tj = 25 °C 100 1k Tj = 150 °C -5 10k -6 100k 0 100 200 IQ [mA] f [Hz] Data Sheet Tj = -40 °C 15 Rev. 1.2, 2009-04-28 TLE7278-2 Typical Performance Characteristics (cont´d) Line Regulation dVQ versus Input Voltage Change dVI Line Regulation dVQ versus Input Voltage Change dVI 19_dVQ-dVI__150C.vsd 6 ∆ VQ Tj = 150 °C IQ = 10mA [mV] 19_dVQ-dVI_25C_.vsd 6 Tj = 25 °C ∆ VQ IQ = 1mA [mV] IQ = 10mA IQ = 1mA 2 2 IQ = 100mA 0 0 -2 -2 -4 -4 -6 0 5 -6 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 35 40 45 VI [V] VI [V] Line Regulation dVQ versus Input Voltage Change dVI Enable Input Current IEN versus Enable Input Voltage VEN 24_IINH vs VINH.vsd 19_dVQ-dVI_-40C.vsd 6 Tj = -40 °C ∆VQ IEN [mV] [µA] 50 2 40 Tj = 150°C Tj = 25°C Tj = -40°C IQ = 100mA IQ = 10mA 0 30 IQ = 1mA -2 20 -4 10 -6 0 5 10 10 15 20 25 30 35 40 45 VI [V] Data Sheet 20 30 40 VEN [V] 16 Rev. 1.2, 2009-04-28 TLE7278-2 Typical Performance Characteristics (cont´d) Enable Input Current IEN versus Input Voltage VI, EN=Off Enable High Level / Low Level Input Voltage VEN,H / VEN,L versus Junction Temperature Tj 25_IINH vs VIN INH_off.vsd 25a_VINH_Tj_ INH_on.vsd IEN [µA] 1.0 VEN 0.8 2.0 0.6 1.5 Tj = 150°C 0.4 1.0 Tj = 25°C 0.2 20 30 VEN increasing VEN decreasing 0.5 Tj = -40°C 10 VI = 13.5V [V] 2.5 EN = OFF 40 -40 -20 0 20 40 60 80 100 120 140 VIN [V] Tj [°C] Reset Threshold VRT versus Junction Temperature Tj (5V-Version) Reset Hysteresis versus Junction Temperature Tj (5V-Version) 26_VRT_VS_TEMP_5V.VSD VI = 13.5 V VQ [V] 29_VRT_HYSTERESIS-_VS_TEMP_5V.VSD 120 VI = 13.5 V ∆V [mV] 4.90 80 4.80 60 Reset Release Threshold 40 4.70 20 4.60 Reset Trigger Threshold -40 -20 0 -40 -20 20 40 60 80 100 120 140 Data Sheet 0 20 40 60 80 100 120 140 Tj [°C] Tj [°C] 17 Rev. 1.2, 2009-04-28 TLE7278-2 Typical Performance Characteristics (cont´d) Reset Threshold VRT versus Junction Temperature Tj (3.3V-Version) Reset Hysteresis versus Junction Temperature Tj (3.3V-Version) 26_VRT_VS_TEMP_33V.VSD VI = 13.5 V VQ [V] 29_VRT_HYSTERESIS-_VS_TEMP_33V.VSD 120 VI = 13.5 V ∆V [mV] 3.20 80 Reset Release Threshold 3.10 3.00 60 40 Reset Trigger Threshold 2.90 20 -40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140 Tj [°C] Tj [°C] Reset Threshold VRT versus Junction Temperature Tj (2.6V-Version) Reset Hysteresis versus Junction Temperature Tj (2.6V-Version) 26_VRT_VS_TEMP_26V.VSD VI = 13.5 V VQ [V] 2.50 Reset Release Threshold 80 60 Reset Trigger Threshold 40 2.20 -40 -20 20 0 20 40 60 80 100 120 140 -40 -20 Tj [°C] Data Sheet VI = 13.5 V ∆V [mV] 2.40 2.30 29_VRT_HYSTERESIS-_VS_TEMP_26V.VS D 120 0 20 40 60 80 100 120 140 Tj [°C] 18 Rev. 1.2, 2009-04-28 TLE7278-2 Typical Performance Characteristics (cont´d) Reset Delay tRD Time versus Junction Temperature Tj Reset Reaction Time trr versus Junction Temperature Tj 27_RESETDELAY VS TEMP.VSD 60 VI = 13.5 V tRD [ms] 40 8 SLOW Timing 6 4 20 FAST Timing 2 10 -40 -20 VI = 13.5 V tRR [µs] 30 28_RESETREACTION_VS_TEMP.VSD 12 0 -40 -20 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140 Tj [°C] Tj [°C] Reset Output Sink Current IRO versus Junction Temperature Tj Watchdog Timing tWD versus Junction Temperature Tj 30_IRO_VS_TEMP.VSD 4,40 VI = 13.5 V IRO tWD [mA] [ms] 3,60 60 3,20 50 2,80 40 2,40 30 -40 -20 0 VI = 13.5 V Timing for Ignore-, Open- Closed- Window -40 -20 20 40 60 80 100 120 140 SLOW Timing FAST Timing 0 20 40 60 80 100 120 140 Tj [°C] Tj [°C] Data Sheet 44_TWD_VS_TEMP.VSD 80 19 Rev. 1.2, 2009-04-28 TLE7278-2 Typical Performance Characteristics (cont´d) Region of Stability ESR(CQ) versus Output Current IQ 12_ESR-IQ.VSD 100 CQ = 470nF Tj = -40...150 °C ESRCQ [Ω] 10 1 Stable Region 0.1 0.01 0 100 200 IQ [mA] Data Sheet 20 Rev. 1.2, 2009-04-28 TLE7278-2 Package Outlines 6 Package Outlines 1.75 MAX. C 1) 4 -0.2 B 1.27 0.64 ±0.25 0.1 2) 0.41+0.10 -0.06 6±0.2 0.2 M A B 14x 14 0.2 M C 8 1 7 1) 8.75 -0.2 8˚MAX. 0.19 +0.06 0.175 ±0.07 (1.47) 0.35 x 45˚ A Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area GPS01230 Figure 6 Data Sheet PG-DSO-14 (Plastic/Plastic Green - Dual Small Outline Package) 21 Rev. 1.2, 2009-04-28 TLE7278-2 Package Outlines 0.19 +0.06 0.08 C 0.64 ±0.25 0.15 M C A-B D 14x 1 8 1 7 0.2 M D 8x Bottom View 3 ±0.2 A 14 6 ±0.2 D Exposed Diepad B 0.1 C A-B 2x 14 7 8 2.65 ±0.2 0.25 ±0.05 2) 0.1 C D 8˚ MAX. C 0.65 3.9 ±0.11) 1.7 MAX. Stand Off (1.45) 0 ... 0.1 0.35 x 45˚ 4.9 ±0.11) Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion PG-SSOP-14-1,-2,-3-PO V02 Figure 7 PG-SSOP-14 Exposed Pad Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Data Sheet 22 Dimensions in mm Rev. 1.2, 2009-04-28 TLE7278-2 Revision History 7 Revision History Revision Date Changes 1.2 2009-04-28 2.6V version, 5V version in PG-SSOP-14 package and all related description added: In “Features” on Page 2 “or 2.6V” added In “Features” on Page 2 package drawing for PG-DSO-14 updated, package drawing for PG-SSOP-14 added In “Overview” on Page 2 in table at the bottom types “TLE7278-2GV26” and TLE7278-2EV50” added In Table 3.2 “Pin Definitions and Functions (PG-DSO-14)” on Page 4 in description for Pin 1 “, TLE7273-2GV26” added In “Pin Assignment (PG-DSO-14)” on Page 4 “(PG-DSO-14)” added; In “Pin Definitions and Functions (PG-DSO-14)” on Page 4 “(PG-DSO-14)” added; In Table 3.2 “Pin Definitions and Functions (PG-DSO-14)” on Page 4 in description for pin 8 “; pull down to GND if not needed and turn off the watchdog with WM1 and WM2 pin” added “Pin Assignments (PG-SSOP-14 Exposed Pad)” on Page 5 and “Pin Definitions and Functions (PG-SSOP-14 Exposed Pad)” on Page 5 added In “Functional Range” on Page 7 Item 4.2.3 added, in Item 4.2.1 “, TLE72782EV50” added In Table 4.3 “Thermal Resistance” on Page 7 above Item 4.3.1 line with “Package PG-DSO-14” and values for PG-SSOP-14 package added: Item 4.3.6, Item 4.3.7, Item 4.3.8, Item 4.3.9 and Item 4.3.10 added In “Power On Reset and Reset Output” on Page 8 “and TLE7278-2EV50” in description added In “Electrical Characteristics” on Page 10 all specific items for 2.6V version added: Item 5.2.5, Item 5.2.6, Item 5.2.21, Item 5.2.25, Item 5.2.29, Item 5.2.40, Item 5.2.42 and Item 5.2.47 added; In Item 5.2.36, Item 5.2.37, Item 5.2.41 and Item 5.2.50 conditions for 2.6V version added; In Item 5.2.1, Item 5.2.2, Item 5.2.8, Item 5.2.19, Item 5.2.23, Item 5.2.27, Item 5.2.36, Item 5.2.37, Item 5.2.38, Item 5.2.44, Item 5.2.45, Item 5.2.49 and Item 5.2.51 in conditions “, TLE7278-2EV50” added In “Typical Performance Characteristics” on Page 14 Graphs “Reset Threshold VRT versus Junction Temperature Tj (3.3V-Version)” on Page 18, “Reset Hysteresis versus Junction Temperature Tj (3.3V-Version)” on Page 18, “Reset Threshold VRT versus Junction Temperature Tj (2.6VVersion)” on Page 18 and “Reset Hysteresis versus Junction Temperature Tj (2.6V-Version)” on Page 18 added In “Package Outlines” on Page 21 Outlines for PG-SSOP-14 package added: Figure 7 Data Sheet 23 Rev. 1.2, 2009-04-28 TLE7278-2 Revision History Revision Date Changes 1.1 2008-07-25 3.3V version and all related description added: In “Features” on Page 2“ 3.3V” added In “Overview” on Page 2 in table at the bottom type “TLE7273-2GV33” added In “Pin Definitions and Functions (PG-DSO-14)” on Page 4 in description for Pin 1 “TLE7273-2GV33: open drain output;” added In “Functional Range” on Page 7 Item 4.2.2 added In “Power On Reset and Reset Output” on Page 8 description for dimensioning external pull-up resistor at RO added; In “Electrical Characteristics” on Page 10 all specific Items for 3.3V version added: Item 5.2.3, Item 5.2.4, Item 5.2.20, Item 5.2.24, Item 5.2.28, Item 5.2.39, Item 5.2.41, Item 5.2.43, Item 5.2.46 and Item 5.2.50 added; In Item 5.2.36 and Item 5.2.37 Conditions for 3.3V version added; 1.0 Data Sheet 2008-04-10 final version data sheet 24 Rev. 1.2, 2009-04-28 Edition 2009-04-28 Published by Infineon Technologies AG 81726 Munich, Germany © 2009 Infineon Technologies AG All Rights Reserved. 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