5962-0153001QXA SMD

REVISIONS
LTR
DESCRIPTION
A
DATE (YR-MO-DA)
APPROVED
08-01-10
Thomas M. Hess
Update boilerplate to current MIL-PRF-38535 requirements. - CFS
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PMIC N/A
PREPARED BY
Charles F. Saffle
STANDARD
MICROCIRCUIT
DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
CHECKED BY
Charles F. Saffle
APPROVED BY
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
Thomas M. Hess
DRAWING APPROVAL DATE
MICROCIRCUIT, DIGITAL, CMOS, FIXED-POINT
DIGITAL SIGNAL PROCESSOR, MONOLITHIC
SILICON
03-04-22
AMSC N/A
REVISION LEVEL
A
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
1 OF
5962-01530
49
5962-E154-08
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)
and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
-
01530
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
Q
X
X
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
01
Circuit function
320VC5416
Fixed-point digital signal processor
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant,
non-JAN class level B microcircuits in accordance with MIL-PRF-38535,
appendix A.
Q or V
Certification and qualification to MIL-PRF-38535.
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X
Descriptive designator
Terminals
Package style
See figure 1
164
Flat pack
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
2
1.3 Absolute maximum ratings.
1/
Supply voltage I/O range (DVDD) .............................................................
Supply voltage core range (CVDD) ...........................................................
Input voltage range (VIN)..........................................................................
Output voltage range (VOUT) ....................................................................
Thermal resistance, junction-to-case (θJC)...............................................
Operating case temperature range (TC)...................................................
Storage temperature range (Tstg).............................................................
-0.3 V dc to +4.0 V dc
-0.3 V dc to +2.0 V dc
-0.3 V dc to +4.5 V dc
-0.3 V dc to +4.5 V dc
1.82°C/W
-55°C to +115°C
-55°C to +150°C
1.4 Recommended operating conditions.
Supply voltage I/O range (DVDD) .............................................................
Supply voltage core range (CVDD) ...........................................................
Supply voltage ground (DVSS, CVSS) .......................................................
High level input voltage, I/O (VIH):
Inputs 2/ ............................................................................................
All other inputs .....................................................................................
Low level input voltage (VIL):
X2/CLKIN .............................................................................................
All other inputs .....................................................................................
Maximum high level output current (IOH) ..................................................
Maximum low level output current (IOL)....................................................
Operating case temperature range (TC)...................................................
+2.75 V dc to +3.6 V dc
+1.45 V dc to +1.65 V dc
+0.0 V dc
+2.4 V to DVDD +0.3 V
+2.0 V to DVDD +0.3 V
3/
3/
-0.3 V to +0.42 V 4/
-0.3 V to +0.8 V 4/
-8 mA 5/
+8 mA 5/
-55°C to +115°C
______
1/
2/
3/
4/
5/
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
For inputs: RS, INTn, NMI, X2/CLKIN, CLKMDn, BCLKRn, BCLKXn, HCS, HDS1, HDS2, HAS, TRST, BIO, Dn, An, HDn,
and TCK
Maximum limit not production tested.
Minimum limit not production tested.
Maximum output currents are DC values only. Transient currents may exceed these values.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
3
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535
-
Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883
MIL-STD-1835
-
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103
MIL-HDBK-780
-
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from
the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in
MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Block diagram. The block diagram shall be as specified on figure 3.
3.2.4 Test circuit and switching waveforms. The test circuit and switching waveforms shall be as specified on figure 4.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are defined in table I.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
4
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 105 (see MIL-PRF-38535, appendix A).
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
5
TABLE I. Electrical performance characteristics.
Test
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Symbol
Group A
subgroups
Device
type
1, 2, 3
All
Limits
Min
High level output
voltage
VOH
1/
DVDD = 2.75 V to 3 V, IOH = -8 mA
Low level output
voltage
VOL
1/
IOL = 8 mA
1, 2, 3
All
Input current
(VIN = DVSS to
DVDD)
IIN
X2/CLKIN
1, 2, 3
All
DVDD = 3 V to 3.6 V, IOH = -8 mA
Unit
Max
2.2
V
2.4
0.4
V
-40
40
μA
TRST, HPI16
With internal pulldown.
-10
800
HPIENA
With internal pulldown, RS = 0
-10
400
TMS, TCK,
TDI, HPI 2/
With internal pullups
-400
10
A[17:0],
D[15:0],
HD[7:0]
Bus holders enabled,
DVDD = 3.6 V 3/
-275
275
-5
5
All other inputonly pins
Supply current,
core CPU
IDDC
CVDD = 1.6 V, fx = 100 MHz, TC = 25°C
4/
1, 2, 3
All
60 TYP
5/ 6/
mA
Supply current
pins
IDDP
DVDD = 3.0 V, fx = 100 MHz, TC = 25°C
4/
1, 2, 3
All
40 TYP
6/ 7/
mA
Supply current,
standby
IDD
IDLE2
PLL X 1 mode, 20 MHz input
1, 2, 3
All
2 TYP
6/
IDLE3 Divideby-two mode,
CLKIN
stopped
TC = 25°C
1 TYP
6/
TC = 115°C
38 TYP
6/
Input
capacitance
CIN
Output
capacitance
COUT
See 4.4.1b
See 4.4.1b
DVDD = 2.75 V to 3.6 V
CVDD = 1.45 V to 1.65 V
See 4.4.1c
Functional tests
mA
4
All
15
pF
4
All
15
pF
7, 8
All
9, 10, 11
All
20
9/
MHz
Input Clock Frequency Characteristics
Input clock
frequency
fx
10
8/
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
6
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
Divide-By-2 and Divide-By-4 Clock Options Timing Requirements (H = 0.5tc(CO))
Cycle time, X2/CLKIN
tc(CI)
9, 10, 11
All
Fall time, X2/CLKIN
tf(CI)
9, 10, 11
All
4.0
10/
ns
Rise time, X2/CLKIN
tr(CI)
9, 10, 11
All
4.0
10/
ns
Pulse duration, X2/CLKIN
low
tw(CIL)
9, 10, 11
All
4.0
10/
ns
Pulse duration, X2/CLKIN
high
tw(CIH)
9, 10, 11
All
4.0
10/
ns
9, 10, 11
All
10.0
11/
8/
ns
4.0
11.0
ns
See figure 4
20.0
ns
Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics (H = 0.5tc(CO))
Cycle time, CLKOUT
tc(CO)
Delay time, X2/CLKIN high
to CLKOUT high/low
td(CIH-CO)
9, 10, 11
All
Fall time, CLKOUT
tf(CO)
9, 10, 11
All
2.0
10/
ns
Rise time, CLKOUT
tr(CO)
9, 10, 11
All
2.0
10/
ns
Pulse duration, CLKOUT
low
tw(COL)
9, 10, 11
All
H-3
10/
H+1
10/
ns
Pulse duration, CLKOUT
high
tw(COH)
9, 10, 11
All
H-2
10/
H+1
10/
ns
9, 10, 11
All
20.0
200.0
ns
20.0
100.0
20.0
50.0
See figure 4
Multiply-By-N Clock Option Timing Requirements (H = 0.5tc(CO))
Cycle time, X2/CLKIN
tc(CI)
See figure 4
Integer PLL multiplier N
(N = 1-15) 12/
See figure 4
PLL multiplier N = x.5
12/
See figure 4
PLL multiplier N = x.25, x.75
12/
Fall time, X2/CLKIN
tf(CI)
Rise time, X2/CLKIN
See figure 4
9, 10, 11
All
4.0
10/
ns
tr(CI)
9, 10, 11
All
4.0
10/
ns
Pulse duration, X2/CLKIN
low
tw(CIL)
9, 10, 11
All
4.0
10/
ns
Pulse duration, X2/CLKIN
high
tw(CIH)
9, 10, 11
All
4.0
10/
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
7
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
Multiply-By-N Clock Option Switching Requirements (H = 0.5tc(CO))
Cycle time, CLKOUT
tc(CO)
9, 10, 11
All
10.0
Delay time, X2/CLKIN
high/low to CLKOUT
high/low
td(CI-CO)
9, 10, 11
All
4.0
Fall time, CLKOUT
tf(CO)
9, 10, 11
Rise time, CLKOUT
tr(CO)
Pulse duration, CLKOUT
low
See figure 4
ns
11.0
ns
All
2.0
10/
ns
9, 10, 11
All
2.0
10/
ns
tw(COL)
9, 10, 11
All
H-3
10/
H+1
10/
ns
Pulse duration, CLKOUT
high
tw(COH)
9, 10, 11
All
H-2
10/
H+1
10/
ns
Transitory phase, PLL
lock-up time
tp
9, 10, 11
All
30.0
10/
μs
9, 10, 11
All
4H-9
ns
2H-9
ns
Memory Read Timing Requirements (MSTRB = 0 and H = 0.5tc(CO))
Access time, read data
access from address valid,
first read access
ta(A)M1
13/
Access time, read data
access from address valid,
consecutive read accesses
ta(A)M2
13/
9, 10, 11
All
Setup time, read data valid
before CLKOUT low
tsu(D)R
9, 10, 11
All
7.0
ns
Hold time, read data valid
after CLKOUT low
th(D)R
9, 10, 11
All
0.0
ns
9, 10, 11
All
-1.0
10/
4.0
ns
See figure 4
Memory Read Switching Characteristics (MSTRB = 0 and H = 0.5tc(CO))
Delay time, CLKOUT low
to address valid
td(CLKL-A)
13/
Delay time, CLKOUT low
to MSTRB low
td(CLKL-MSL)
9, 10, 11
All
-1.0
10/
4.0
ns
Delay time, CLKOUT low
to MSTRB high
td(CLKL-MSH)
9, 10, 11
All
-1.0
10/
4.0
10/
ns
See figure 4
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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REVISION LEVEL
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SHEET
8
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Unit
Min
Max
4.0
Memory Write Switching Characteristics (MSTRB = 0 and H = 0.5tc(CO))
Delay time, CLKOUT low
to address valid
td(CLKL-A)
13/
Setup time, address valid
before MSTRB low
See figure 4
9, 10, 11
All
-1.0
10/
ns
tsu(A)MSL
13/
9, 10, 11
All
2H-3
Delay time, CLKOUT low
to data valid
td(CLKL-D)W
9, 10, 11
All
-1.0
10/
4.0
ns
Setup time, data valid
before MSTRB high
tsu(D)MSH
9, 10, 11
All
2H-5
2H+6
ns
Hold time, data valid
after MSTRB high
th(D)MSH
9, 10, 11
All
2H-5
10/
2H+6
10/
ns
Delay time, CLKOUT low
to MSTRB low
td(CLKL-MSL)
9, 10, 11
All
-1.0
10/
4.0
ns
Pulse duration, MSTRB
low
tw(SL)MS
9, 10, 11
All
2H-3.2
10/
Delay time, CLKOUT low
to MSTRB high
td(CLKL-MSH)
9, 10, 11
All
-1.0
10/
9, 10, 11
All
ns
ns
4.0
10/
ns
4H-9
ns
I/O Read Timing Requirements (IOSTRB = 0 and H = 0.5tc(CO))
Access time, read data
access from address valid,
first read access
ta(A)M1
13/
Setup time, read data valid
before CLKOUT low
tsu(D)R
9, 10, 11
All
7.0
ns
Hold time, read data valid
after CLKOUT low
th(D)R
9, 10, 11
All
0.0
ns
9, 10, 11
All
-1.0
10/
4.0
ns
9, 10, 11
All
-1.0
10/
4.0
ns
9, 10, 11
All
-1.0
10/
4.0
ns
See figure 4
I/O Read Switching Characteristics (IOSTRB = 0 and H = 0.5tc(CO))
Delay time, CLKOUT low
to address valid
td(CLKL-A)
13/
Delay time, CLKOUT low
to IOSTRB low
td(CLKL-IOSL)
Delay time, CLKOUT low
to IOSTRB high
See figure 4
td(CLKL-IOSH)
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
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COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
9
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Unit
Min
Max
4.0
I/O Write Switching Characteristics (IOSTRB = 0 and H = 0.5tc(CO))
Delay time, CLKOUT low
to address valid
td(CLKL-A)
13/
Setup time, address valid
before IOSTRB low
See figure 4
9, 10, 11
All
-1.0
10/
tsu(A)IOSL
13/
9, 10, 11
All
2H-3
Delay time, CLKOUT low
to write data valid
td(CLKL-D)W
9, 10, 11
All
-1.0
10/
4.0
ns
Setup time, data valid
before IOSTRB high
tsu(D)IOSH
9, 10, 11
All
2H-5
2H+6
10/
ns
Hold time, data valid
after IOSTRB high
th(D)IOSH
9, 10, 11
All
2H-5
10/
2H+6
10/
ns
Delay time, CLKOUT low
to IOSTRB low
td(CLKL-IOSL)
9, 10, 11
All
-1.0
10/
4.0
ns
Pulse duration, IOSTRB
low
tw(SL)IOS
9, 10, 11
All
2H-2
10/
Delay time, CLKOUT low
to IOSTRB high
td(CLKL-IOSH)
9, 10, 11
All
-1.0
10/
9, 10, 11
All
7.0
ns
9, 10, 11
All
0.0
ns
Ready Timing Requirements for Externally Generated Wait States (H = 0.5tc(CO))
Setup time, READY before
CLKOUT low
tsu(RDY)
Hold time, READY after
CLKOUT low
th(RDY)
See figure 4
ns
ns
ns
4.0
ns
14/
Valid time, READY after
MSTRB low
tv(RDY)MSTRB
15/
9, 10, 11
All
Hold time, READY after
MSTRB low
th(RDY)MSTRB
15/
9, 10, 11
All
Valid time, READY after
IOSTRB low
tv(RDY)IOSTRB
15/
9, 10, 11
All
Hold time, READY after
IOSTRB low
th(RDY)IOSTRB
15/
9, 10, 11
All
4H
10/
9, 10, 11
All
-1.0
10/
4.0
ns
9, 10, 11
All
-1.0
10/
4.0
ns
Ready Switching Characteristics for Externally Generated Wait States (H = 0.5tc(CO))
Delay time, CLKOUT low
to MSC low
td(MSCL)
Delay time, CLKOUT low
to MSC high
td(MSCH)
See figure 4
4H-6.2
10/
ns
4H
10/
ns
4H-6
10/
ns
ns
14/
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
10
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
HOLD and HOLDA Timing Requirements (H = 0.5tc(CO))
Pulse duration,
HOLD low duration
tw(HOLD)
Setup time,
HOLD before CLKOUT low
tsu(HOLD)
16/
See figure 4
9, 10, 11
All
4H+8
10/
ns
9, 10, 11
All
7.0
ns
9, 10, 11
All
3.0
10/
ns
HOLD and HOLDA Switching Characteristics (H = 0.5tc(CO))
Disable time, Address,
PS, DS, IS high impedance
from CLKOUT low
tdis(CLKL-A)
See figure 4
Disable time, R/W high
impedance from CLKOUT
low
tdis(CLKL-RW)
9, 10, 11
All
3.0
10/
ns
Disable time, MSTRB,
IOSTRB high impedance
from CLKOUT low
tdis(CLKL-S)
9, 10, 11
All
3.0
10/
ns
Enable time, Address,
PS, DS, IS valid from
CLKOUT low
ten(CLKL-A)
9, 10, 11
All
2H+3
10/
ns
ten(CLKL-RW)
9, 10, 11
All
2H+3
10/
ns
Enable time, MSTRB,
IOSTRB enabled from
CLKOUT low
ten(CLKL-S)
9, 10, 11
All
2.0
2H+3
10/
ns
Valid time, HOLDA low
afterCLKOUT low
tv(HOLDA)
9, 10, 11
All
-1.0
10/
4.0
ns
9, 10, 11
All
-1.0
10/
4.0
10/
ns
9, 10, 11
All
2H-3
10/
Enable time, R/W enabled
CLKOUT low
Valid time, HOLDA high
afterCLKOUT low
Pulse duration, HOLDA
low duration
tw(HOLDA)
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
11
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
Reset, BIO, Interrupt, and MP/MC Timing Requirements (H = 0.5tc(CO))
Hold time, RS after
CLKOUT low
th(RS)
17/
Hold time, BIO after
CLKOUT low
See figure 4
9, 10, 11
All
2.0
10/
ns
th(BIO)
17/
9, 10, 11
All
4.0
ns
Hold time, INTn, NMI after
CLKOUT low
th(INT)
17/ 18/
9, 10, 11
All
0.0
ns
Hold time, MP/MC after
CLKOUT low
th(MPMC)
17/
9, 10, 11
All
4.0
10/
ns
Pulse duration, RS low
tw(RSL)
19/ 20/
9, 10, 11
All
4H+3
10/
ns
Pulse duration, BIO low,
synchronous
tw(BIO)S
9, 10, 11
All
2H+3
10/
ns
Pulse duration, BIO low,
asynchronous
tw(BIO)A
9, 10, 11
All
4H
10/
ns
Pulse duration, INTn, NMI
high (synchronous)
tw(INTH)S
9, 10, 11
All
2H+2
10/
ns
Pulse duration, INTn, NMI
high (asynchronous)
tw(INTH)A
9, 10, 11
All
4H
10/
ns
Pulse duration, INTn, NMI
low (synchronous)
tw(INTL)S
9, 10, 11
All
2H+2
10/
ns
Pulse duration, INTn, NMI
low (asynchronous)
tw(INTL)A
9, 10, 11
All
4H
10/
ns
Pulse duration, INTn, NMI
low for IDLE2/IDLE3
wakeup
tw(INTL)WKP
9, 10, 11
All
7.0
10/
ns
Setup time, RS before
X2CLKIN low
tsu(RS)
17/ 21/
9, 10, 11
All
3.0
10/
ns
Setup time, BIO before
CLKOUT low
tsu(BIO)
17/
9, 10, 11
All
7.0
ns
Setup time, INTn, NMI,
RS before CLKOUT low
tsu(INT)
17/
9, 10, 11
All
7.0
ns
Setup time, MP/MC
before CLKOUT low
tsu(MPMC)
17/
9, 10, 11
All
5.0
10/
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
12
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics (H = 0.5tc(CO))
Delay time, CLKOUT low
to IAQ low
td(CLKL-IAQL) See figure 4
9, 10, 11
All
-1.0
10/
4.0
ns
Delay time, CLKOUT low
to IAQ high
td(CLKL-IAQH)
9, 10, 11
All
-1.0
10/
4.0
ns
Delay time, CLKOUT low
to IACK low
td(CLKL-IACKL)
9, 10, 11
All
-1.2
10/
4.0
ns
Delay time, CLKOUT low
to IACK high
td(CLKL-IACKH)
9, 10, 11
All
-1.0
10/
4.0
ns
4.0
ns
Delay time, CLKOUT low
to address valid
td(CLKL-A)
9, 10, 11
All
-1.0
10/
Pulse duration, IAQ low
tw(IAQL)
9, 10, 11
All
2H-2
10/
ns
Pulse duration, IACK low
tw(IACKL)
9, 10, 11
All
2H-3
10/
ns
9, 10, 11
All
-1.0
10/
4.0
ns
9, 10, 11
All
-1.0
10/
4.0
ns
External Flag (XF) and TOUT Switching Characteristics (H = 0.5tc(CO))
Delay time, CLKOUT low
to XF high
td(XF)
See figure 4
Delay time, CLKOUT low
to XF low
Delay time, CLKOUT low
to TOUT high
td(TOUTH)
9, 10, 11
All
-1.0
10/
4.0
10/
ns
Delay time, CLKOUT low
to TOUT low
td(TOUTL)
9, 10, 11
All
-1.0
10/
4.0
ns
Pulse duration, TOUT
tw(TOUT)
9, 10, 11
All
2H-4
10/
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
13
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
McBSP Transmit and Receive Timing Requirements
tc(BCKRX)
23/
Pulse duration, BCLKR/X
high or BCLKR/X low
Setup time, external BFSR
high before BCLKR low
th(BCKRL-
BCLKR int
Setup time, BDR valid
before BCLKR low
Hold time, BDR valid
after BCLKR low
Setup time, external BFSX
high before BCLKX low
Hold time, external BFSX
high after BCLKX low
Max
22/
Cycle time, BCLKR/X
Hold time, external BFSR
high after BCLKR low
Unit
See figure 4
BCLKR/X ext
9, 10, 11
All
4P
24/
ns
tw(BCKRX)
23/
BCLKR/X ext
9, 10, 11
All
2P-1
10/ 24/
ns
tsu(BFRH-
BCLKR int
9, 10, 11
All
8.0
ns
BCKRL)
BCLKR ext
9, 10, 11
All
9, 10, 11
All
9, 10, 11
All
9, 10, 11
All
9, 10, 11
All
BFRH)
BCLKR ext
tsu(BDRV-
BCLKR int
BCKRL)
BCLKR ext
th(BCKRL-
BCLKR int
BDRV)
BCLKR ext
tsu(BFXH-
BCLKX int
BCKXL)
BCLKX ext
th(BCKXL-
BCLKX int
BFXH)
BCLKX ext
1.0
1.0
ns
2.0
7.0
ns
1.0
2.0
ns
3.0
8.0
ns
1.0
0.0
ns
2.0
Rise time, BCKR/X
tr(BCKRX)
BCLKR/X ext
9, 10, 11
All
6.0
10/
ns
Fall time, BCKR/X
tf(BCKRX)
BCLKR/X ext
9, 10, 11
All
6.0
10/
ns
BCLKR/X int
9, 10, 11
All
4P
24/
McBSP Transmit and Receive Switching Characteristics
See figure 4
22/
Cycle time, BCLKR/X
tc(BCKRX)
23/
Pulse duration, BCLKR/X
high
tw(BCKRXH)
23/
BCLKR/X int
9, 10, 11
All
D-1
10/ 25/
D+1
10/ 25/
ns
Pulse duration, BCLKR/X
low
tw(BCKRXL)
23/
BCLKR/X int
9, 10, 11
All
C-1
10/ 25/
C+1
10/ 25/
ns
Delay time, BCLKR high to
internal BFSR valid
td(BCKRH-
BCLKR int
9, 10, 11
All
-3.0
10/
3.0
ns
BFRV)
0.0
10/
11.0
-1.0
10/
5.0
3.0
10/
11.0
BCLKR ext
Delay time, BCLKX high to
internal BFSX valid
td(BCKXH-
BCLKX int
9, 10, 11
All
BFXV)
BCLKX ext
Disable time, BCLKX high
to BDX high impedance
following last data bit of
transfer
tdis(BCKXH-
BCLKX int
9, 10, 11
ns
ns
ns
6.0
10/
All
BDXHZ)
BCLKX ext
10.0
10/
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
14
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
td(BCKXHBDXV)
DXENA = 0
See figure 4
DXENA = 1
See figure 4
Delay time, BFSX high to
BDX valid (Only applies
when in data delay 0
(XDATDLY = 00b) mode.)
td(BFXH-
See figure 4
Device
type
Limits
Unit
Min
Max
-1.0
10/ 26/
10.0
BCLKX ext
3.0
10/
20.0
BCLKX int
-1.0
10/ 26/
20.0
BCLKX ext
2.8
10/
30.0
-1.2
10/ 26/
7.0
10/
3.0
10/
11.0
10/
McBSP Transmit and Receive Switching Characteristics - Continued
Delay time, BCLKX high
to BDX valid
Group A
subgroups
22/
BCLKX int
9, 10, 11
BFSX int
9, 10, 11
All
All
BDXV)
BFSX ext
ns
ns
McBSP General-Purpose I/O Timing Requirements
Setup time, BGPIOx input
mode before CLKOUT high
tsu(BGPIO-
Hold time, BGPIOx input
mode after CLKOUT high
th(COH-
See figure 4
9, 10, 11
All
7.0
ns
9, 10, 11
All
0.0
ns
9, 10, 11
All
-2.0
10/
COH)
27/
BGPIO)
27/
McBSP General-Purpose I/O Switching Characteristics
Delay time, CLKOUT high
to BGPIOx output mode
td(COH-
See figure 4
BGPIO)
4.0
ns
28/
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
15
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
Setup time, BDR valid
before BCLKX low
tsu(BDRVBCKXL)
All
12.0
th(BCKXLBDRV)
9, 10, 11
MASTER
See figure 4
All
4.0
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
th(BCKXLBFXL)
30/
Delay time, BFSX low to
BCLKX high
td(BFXLBCKXH)
32/
Delay time, BCLKX high to
BDX valid
td(BCKXHBDXV)
MASTER 31/
See figure 4
29/
9, 10, 11
All
T-3
10/
T+4
ns
9, 10, 11
All
C-4
10/
C+3
10/
ns
9, 10, 11
All
-4.0
10/
5.0
ns
6P+2
10/ 24/
10P+17
24/
C-2
10/
C+3
10/
SLAVE
See figure 4
MASTER 31/
See figure 4
SLAVE
See figure 4
MASTER 31/
See figure 4
SLAVE
See figure 4
Disable time, BDX high
impedance following last
data bit from BCLKX low
tdis(BCKXL-
Disable time, BDX high
impedance following last
data bit from BFSX high
tdis(BFXH-
Delay time, BFSX low to
BDX valid
td(BFXL-
BDXHZ)
ns
5+12P
10/ 24/
SLAVE
See figure 4
Hold time, BFSX low after
BCLKX low
ns
2.2-6P
10/ 24/
SLAVE
See figure 4
Hold time, BDR valid
after BCLKX low
Max
29/
9, 10, 11
MASTER
See figure 4
Unit
MASTER 31/
See figure 4
9, 10, 11
All
9, 10, 11
All
ns
SLAVE
See figure 4
BDXHZ)
MASTER 31/
See figure 4
ns
2P-4
10/ 24/
SLAVE
See figure 4
BDXV)
9, 10, 11
MASTER 31/
See figure 4
6P+17
10/ 24/
All
ns
4P+2
10/ 24/
SLAVE
See figure 4
8P+17
10/ 24/
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
16
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
Setup time, BDR valid
before BCLKX low
tsu(BDRVBCKXL)
All
12.0
th(BCKXHBDRV)
9, 10, 11
MASTER
See figure 4
All
4.0
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
th(BCKXLBFXL)
30/
Delay time, BFSX low to
BCLKX high
td(BFXLBCKXH)
32/
Delay time, BCLKX low to
BDX valid
td(BCKXLBDXV)
MASTER 31/
See figure 4
29/
9, 10, 11
All
C-3
10/
C+4
ns
9, 10, 11
All
T-4
10/
T+3
10/
ns
9, 10, 11
All
-4.0
10/
5.0
ns
6P+2
10/ 24/
10P+17
24/
-2.0
10/
4.0
10/
6P-4
10/ 24/
10P+17
10/ 24/
D-2
10/
D+4
10/
4P+2
10/ 24/
8P+17
10/ 24/
SLAVE
See figure 4
MASTER 31/
See figure 4
SLAVE
See figure 4
MASTER 31/
See figure 4
SLAVE
See figure 4
Disable time, BDX high
impedance following last
data bit from BCLKX low
tdis(BCKXL-
Delay time, BFSX low to
BDX valid
td(BFXL-
BDXHZ)
9, 10, 11
MASTER 31/
See figure 4
All
SLAVE
See figure 4
BDXV)
ns
5+12P
10/ 24/
SLAVE
See figure 4
Hold time, BFSX low after
BCLKX low
ns
2.2-6P
10/ 24/
SLAVE
See figure 4
Hold time, BDR valid
after BCLKX high
Max
29/
9, 10, 11
MASTER
See figure 4
Unit
9, 10, 11
MASTER 31/
See figure 4
All
SLAVE
See figure 4
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
17
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
Setup time, BDR valid
before BCLKX high
tsu(BDRVBCKXH)
All
12.0
th(BCKXHBDRV)
9, 10, 11
MASTER
See figure 4
All
4.0
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
th(BCKXHBFXL)
30/
Delay time, BFSX low to
BCLKX low
td(BFXLBCKXL)
32/
Delay time, BCLKX low to
BDX valid
td(BCKXLBDXV)
MASTER 31/
See figure 4
29/
9, 10, 11
All
T-3
10/
T+4
ns
9, 10, 11
All
D-4
10/
D+3
10/
ns
9, 10, 11
All
-4.0
10/
5.0
ns
6P+2
10/ 24/
10P+17
24/
D-2
10/
D+3
10/
SLAVE
See figure 4
MASTER 31/
See figure 4
SLAVE
See figure 4
MASTER 31/
See figure 4
SLAVE
See figure 4
Disable time, BDX high
impedance following last
data bit from BCLKX high
tdis(BCKXH-
Disable time, BDX high
impedance following last
data bit from BFSX high
tdis(BFXH-
Delay time, BFSX low to
BDX valid
td(BFXL-
BDXHZ)
ns
5+12P
10/ 24/
SLAVE
See figure 4
Hold time, BFSX low after
BCLKX high
ns
2-6P
10/ 24/
SLAVE
See figure 4
Hold time, BDR valid
after BCLKX high
Max
29/
9, 10, 11
MASTER
See figure 4
Unit
MASTER 31/
See figure 4
9, 10, 11
All
9, 10, 11
All
ns
SLAVE
See figure 4
BDXHZ)
MASTER 31/
See figure 4
ns
2P-4
10/ 24/
SLAVE
See figure 4
BDXV)
9, 10, 11
MASTER 31/
See figure 4
6P+17
10/ 24/
All
ns
4P+2
10/ 24/
SLAVE
See figure 4
8P+17
10/ 24/
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
18
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
Setup time, BDR valid
before BCLKX low
tsu(BDRVBCKXL)
All
12.0
th(BCKXLBDRV)
9, 10, 11
MASTER
See figure 4
All
4.0
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
th(BCKXHBFXL)
30/
Delay time, BFSX low to
BCLKX low
td(BFXLBCKXL)
32/
Delay time, BCLKX high to
BDX valid
td(BCKXHBDXV)
MASTER 31/
See figure 4
29/
9, 10, 11
All
D-3
10/
D+4
ns
9, 10, 11
All
T-4
10/
T+3
10/
ns
9, 10, 11
All
-4.0
10/
5.0
ns
6P+2
10/ 24/
10P+17
24/
-2.0
10/
4.0
10/
6P-4
10/ 24/
10P+17
10/ 24/
C-2
10/
C+4
10/
4P+2
10/ 24/
8P+17
10/ 24/
SLAVE
See figure 4
MASTER 31/
See figure 4
SLAVE
See figure 4
MASTER 31/
See figure 4
SLAVE
See figure 4
Disable time, BDX high
impedance following last
data bit from BCLKX high
tdis(BCKXH-
Delay time, BFSX low to
BDX valid
td(BFXL-
BDXHZ)
9, 10, 11
MASTER 31/
See figure 4
All
SLAVE
See figure 4
BDXV)
ns
5+12P
10/ 24/
SLAVE
See figure 4
Hold time, BFSX low after
BCLKX high
ns
2-6P
10/ 24/
SLAVE
See figure 4
Hold time, BDR valid
after BCLKX low
Max
29/
9, 10, 11
MASTER
See figure 4
Unit
9, 10, 11
MASTER 31/
See figure 4
All
SLAVE
See figure 4
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
HPI8 Mode Timing Requirements
Setup time, HBIL valid
before DS low (when HAS
is not used), or HBIL valid
before HAS low
tsu(HBV-DSL) See figure 4
9, 10, 11
All
6.0
ns
Hold time, HBIL valid
after DS low (when HAS
is not used), or HBIL valid
after HAS low
th(DSL-HBV)
9, 10, 11
All
3.0
ns
Setup time, HAS low
before DS low
tsu(HSL-DSL)
9, 10, 11
All
8.0
10/
ns
Pulse duration, DS low
tw(DSL)
9, 10, 11
All
13.0
10/
ns
Pulse duration, DS high
tw(DSH)
9, 10, 11
All
7.0
10/
ns
Setup time, HD valid before
DS high, HPI write
tsu(HDV-DSH)
9, 10, 11
All
3.0
ns
th(DSH-
9, 10, 11
All
2.0
ns
9, 10, 11
All
6.0
10/
ns
9, 10, 11
All
0.0
10/
ns
Hold time, HD valid after
DS high, HPI write
HDV)W
tsu(GPIO-
Setup time, HDx input valid
before CLKOUT high,
HDx configured as
general-purpose input
COH)
Hold time, HDx input valid
before CLKOUT high,
HDx configured as
general-purpose input
COH)
tsu(GPIO-
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Unit
Min
Max
0.0
10/
10.0
10/
ns
36P+10
-tw(DSH)
10/
ns
HPI8 Mode Switching Characteristics
Enable time, HD driven
from DS low
ten(DSL-HD)
Delay time, DS low to HD
valid for first byte of an HPI
read
td(DSL-HDV1) See figure 4
Case 1a: Memory accesses
when DMAC is active in
32-bit mode and
tw(DSH) < 36P. 33/
See figure 4
9, 10, 11
All
9, 10, 11
All
See figure 4
Case 1b: Memory accesses
when DMAC is active in
32-bit mode and
tw(DSH) ≥ 36P. 33/
10.0
10/
See figure 4
Case 1c: Memory accesses
when DMAC is active in
16-bit mode and
tw(DSH) < 18P. 33/
18P+10
-tw(DSH)
10/
See figure 4
Case 1d: Memory accesses
when DMAC is active in
16-bit mode and
tw(DSH) ≥ 18P. 33/
10.0
10/
See figure 4
Case 2a: Memory accesses
when DMAC is inactive
and tw(DSH) < 10P. 33/
10P+10
-tw(DSH)
10/
See figure 4
Case 2b: Memory accesses
when DMAC is inactive
and tw(DSH) ≥ 10P. 33/
10.0
10/
See figure 4
Case 3: Register accesses.
10.0
10/
Delay time, DS low to HD
valid for second byte of
an HPI read
td(DSL-HDV2) See figure 4
9, 10, 11
All
Hold time, HD valid after
DS high, for a HPI read
td(DSH-
9, 10, 11
All
Valid time, HD valid after
HRDY high
tv(HYH-HDV)
9, 10, 11
All
2.0
10/
ns
Delay time, DS high to
HRDY low
td(DSH-HYL)
34/
9, 10, 11
All
8.0
10/
ns
10.0
10/
ns
0.0
10/
HDV)R
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
HPI8 Mode Switching Characteristics - Continued.
Delay time, DS high to
HRDY high
td(DSH-HYH) See figure 4
Case 1a: Memory accesses
34/
when DMAC is active in
16-bit mode. 33/
Delay time, HCS low/high
to HRDY low/high
td(HCS-
Delay time, CLKOUT high
to HRDY high
9, 10, 11
All
18P+6
10/
See figure 4
Case 1b: Memory accesses
when DMAC is active in
32-bit mode. 33/
36P+6
10/
See figure 4
Case 2: Memory accesses
when DMAC is inactive.
33/
10P+6
10/
See figure 4
Case 3: Write accesses
to HPIC register. 35/
6P+6
10/
See figure 4
ns
9, 10, 11
All
6.0
10/
ns
td(COH-HYH)
9, 10, 11
All
9.0
ns
Delay time, CLKOUT high
to HINT change
td(COH-HTX)
9, 10, 11
All
6.0
ns
Delay time, CLKOUT high
to HDx output change.
HDx is configured as a
general-purpose output.
td(COH-GPIO)
9, 10, 11
All
5.0
10/
ns
HRDY)
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
HPI16 Mode Timing Requirements
Setup time, HR/W valid
before DS falling edge
tsu(HBV-DSL) See figure 4
9, 10, 11
All
6.0
ns
Hold time, HR/W valid
after DS falling edge
th(DSL-HBV)
9, 10, 11
All
5.0
ns
Setup time, address valid
before DS rising edge
(write)
tsu(HAV-DSH)
9, 10, 11
All
5.0
10/
ns
Setup time, address valid
before DS falling edge
(read)
tsu(HAV-DSL)
9, 10, 11
All
-(4P-6)
10/
ns
Hold time, address valid
after DS rising edge
th(DSH-HAV)
9, 10, 11
All
1.0
10/
ns
Pulse duration, DS low
tw(DSL)
9, 10, 11
All
30.0
10/
ns
Pulse duration, DS high
tw(DSH)
9, 10, 11
All
10.0
10/
ns
Cycle time, DS rising edge
to next DS rising edge
tc(DSH-DSH) See figure 4
Memory accesses
with no DMA
activity
Reads
9, 10, 11
All
10P+30
10/
ns
Writes
10P+10
10/
See figure 4
Memory accesses
with 16-bit DMA
activity
Reads
16P+30
10/
Writes
16P+10
10/
See figure 4
Memory accesses
with 32-bit DMA
activity
Reads
24P+30
10/
Writes
24P+10
10/
Setup time, HD valid before
DS rising edge (write)
DSH)W
tsu(HDV-
Hold time, HD valid after
DS rising edge (write)
HDV)W
See figure 4
th(DSH-
9, 10, 11
All
8.0
ns
9, 10, 11
All
2.0
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Unit
Min
Max
0.0
10/
10.0
10/
ns
48P+20
-tw(DSH)
10/
ns
HPI16 Mode Switching Characteristics
Delay time, DS low
to HD driven
td(DSL-HDD)
Delay time, DS low to HD
valid for first word of an
HPI read
td(DSL-HDV1) See figure 4
Case 1a: Memory accesses
initiated immediately
following a write when
DMAC is active in 32-bit
mode and tw(DSH) was < 26P.
See figure 4
9, 10, 11
All
9, 10, 11
All
See figure 4
Case 1b: Memory accesses
not immediately following
a write when DMAC is
active in 32-bit mode.
24P+20
10/
See figure 4
Case 1c: Memory accesses
initiated immediately
following a write when
DMAC is active in 16-bit
mode and tw(DSH) was < 18P.
32P+20
-tw(DSH)
10/
16P+20
10/
See figure 4
Case 1d: Memory accesses
not immediately following
a write when DMAC is
active in 16-bit mode.
Delay time, DS high
to HRDY high
See figure 4
Case 2a: Memory accesses
initiated immediately
following a write when
DMAC is inactive and
tw(DSH) was < 10P.
20P+20
-tw(DSH)
10/
See figure 4
Case 2b: Memory accesses
not immediately following
a write when DMAC is
inactive.
10P+20
10/
9, 10, 11
td(DSH-HYH) See figure 4
Memory writes when no
DMA is active.
All
10P+5
10/
See figure 4
Memory writes with one or
more 16-bit DMA channels
active.
16P+5
10/
See figure 4
Memory writes with one or
more 32-bit DMA channels
active.
24P+5
10/
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +115°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
HPI16 Mode Switching Characteristics - Continued.
Valid time, HD valid
after HRDY high
tv(HYH-HDV)
Hold time, HD valid
after DS rising edge (read)
th(DSH-
Delay time, CLKOUT rising
edge to HRDY high
9, 10, 11
All
9, 10, 11
All
td(COH-HYH)
9, 10, 11
Delay time, DS low
to HRDY low
td(DSL-HYL)
Delay time, DS high
to HRDY low
td(DSH-HYL)
See figure 4
7.0
10/
ns
6.0
10/
ns
All
5.0
ns
9, 10, 11
All
12.0
10/
ns
9, 10, 11
All
12.0
10/
ns
1.0
10/
HDV)R
1/ All input and output voltage levels except RS, INT0 - INT3, NMI, X2/CLKIN, CLKMD1 - CLKMD3, BCLKRn, BCLKXn, HCS,
HAS, HDS1, HDS2, BIO, TCK, TRST, Dn, An, and HDn are LVTTL-compatible.
2/ HPI input signals except for HPIENA and HPI16, when HPIENA = 0.
3/ VIL(MIN) ≤ VIN ≤ VIL(MAX) or VIH(MIN) ≤ VIN ≤ VIH(MAX).
4/ Clock mode: PLL x 1 with external source.
5/ This value was obtained with 50% usage of MAC and 50%usage of NOP instructions. Actual operating current varies with
program being executed.
6/ TYP = typical value, which is neither a minimum value or a maximum value. The value provided as a typical value is a
normal operating value.
7/ This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF.
8/ This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞.
9/ It is recommended that the PLL multiply by N clocking option be used for maximum frequency operation.
10/ This parameter is not production tested. This parameter is established by design, or is only characterized at initial release
and after changes which may affect performance.
11/ It is recommended that the PLL clocking option be used for maximum frequency operation.
12/ N is the multiplication factor.
13/ Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
14/ The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To
generate wait states by READY, at least two software wait states must be programmed. READY is not sampled until the
completion of the internal software wait states.
15/ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
16/ This input can be driven from an asynchronous source, therefore, there are no specific timing requirements with respect to
CLKOUT, however, if this timing is met, the input will be recognized on the CLKOUT edge referenced.
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TABLE I. Electrical performance characteristics – Continued.
17/ These inputs can be driven from an asynchronous source, therefore, there are no specific timing requirements with respect
to CLKOUT, however, if setup and hold timings are met, the input will be recognized on the CLKOUT edge referenced.
18/ The external interrupts (INT0-INT3, NMI) are synchronized to the core CPU by way of a two flip-flop synchronizer that
samples these inputs with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 10-0 sequence at the timing that is corresponding to three CLKOUTs sampling sequence.
19/ If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 μs to
ensure synchronization and lock-in of the PLL.
20/ Note that RS may cause a change in clock frequency, therefore changing the value of H.
21/ The diagram assumes clock mode is divide-by-2 and the CLKOUT divide factor is set to no-divide mode (DIVFCT = 00 field
in the BSCR).
22/ CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
23/ Note that in some cases, for example when driving another 54x device McBSP, maximum serial port clocking rates may not
be achievable at maximum CPU clock frequency due to transmitted data timings and corresponding receive timing
requirements. A separate detailed timing analysis should be performed for each specific McBSP interface.
24/ P = 1/(2 x processor clock).
25/ T = BCLKRX period = (1 + CLKGDV) x 2P.
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) x 2P when CLKGDV is even.
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) x 2P when CLKGDV is even.
26/ Minimum delay times also represent minimum output hold times.
27/ BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
28/ BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
29/ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
30/ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the
active-low signal input on BFSX and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP.
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP.
31/ T = BCLKX period = (1 + CLKGDV) x 2P.
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) x 2P when CLKGDV is even.
32/ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge
of the master clock (BCLKX).
33/ DMAC stands for direct memory access controller (DMAC). The HPI8 shares the internal DMA bus with the DMAC, thus
HPI8 access times are affected by DMAC activity.
34/ The HRDY output is always high when the HCS input is high, regardless of DS timings.
35/ This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur
asynchronously, and do not cause HRDY to be deasserted.
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Case X
FIGURE 1. Case outline.
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Case outline
Symbol
X
Millimeters
Min
A
A1
A2
b
c
D1/E1
D2/E2
e
F
H
J
K
L
P
Q
T
Inches
Max
3.30
2.67
0.36
0.25
0.23
Min
Max
0.130
0.105
0.002
0.014
0.006
0.010
0.004
0.009
1.000 BSC
1.120
1.140
0.025
0.275
0.325
0.018
0.030
0.040
0.020
2.485
2.505
0.059
0.061
1.480
1.520
1.150 BSC
0.05
0.15
0.10
25.40 BSC
28.45
28.96
0.64
6.99
8.26
0.46
0.76
1.02
0.51
63.12
63.63
1.50
1.55
37.59
38.61
29.21 BSC
NOTES:
1. Ceramic quad flatpack with flat leads brazed to non-conductive tie bar carrier.
2. This package is hermetically sealed with a metal lid.
3. The leads are gold plated and can be solder dipped.
4. Leads not shown for clarity purposes.
FIGURE 1. Case outline – Continued.
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Device type
Case outline
Terminal number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Terminal symbol
VSS
NC
A22
NC
VSS
DVDD
A10
HD7
A11
A12
A13
A14
A15
NC
CVDD
HAS
VSS
CVDD
HCS
HR/W
READY
PS
CVDD
DS
VSS
IS
R/W
MSTRB
IOSTRB
MSC
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
DVDD
NC
VSS
BDR1
01
X
Terminal number
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Terminal symbol
BFSR1
VSS
BCLKR1
HCNTL0
VSS
BCLKR0
BCLKR2
BFSR0
BFSR2
BDR0
HCNTL1
VSS
BDR2
CVDD
BCLKX0
BCLKX2
NC
VSS
HINT
NC
CVDD
BFSX0
BFSX2
HRDY
DVDD
VSS
HD0
BDX0
BDX2
CVDD
IACK
VSS
HBIL
NMI
INT0
INT1
INT2
INT3
NC
CVDD
NC = No connection
FIGURE 2. Terminal connections.
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Device type
Case outline
Terminal number
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
Terminal symbol
HD1
NC
VSS
BCLKX1
BFSX1
BDX1
DVDD
CLKMD1
CLKMD2
CLKMD3
HPI16
HD2
TOUT
EMU0
EMU1/OFF
TD0
VSS
TDI
CVDD
TRST
TCK
TMS
VSS
NC
CVDD
HPIENA
VSS
CVDD
CLKOUT
HD3
X1
X2/CLKIN
RS
D0
D1
D2
D3
D4
D5
A16
VSS
A17
01
X
Terminal number
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
Terminal symbol
A18
A19
A20
NC
VSS
DVDD
D6
D7
D8
D9
D10
D11
VSS
CVDD
D12
HD4
D13
D14
D15
HD5
VSS
NC
HDS1
VSS
HDS2
DVDD
A0
A1
CVDD
A2
VSS
A3
HD6
A4
A5
A6
A7
A8
A9
CVDD
A21
VSS
NC = No connection
FIGURE 2. Terminal connections – Continued.
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FIGURE 3. Block diagram.
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3.3 V Test Load Circuit
Where: IOL = 1.5 mA (all outputs)
IOH = 300 μA (all outputs)
VLOAD = 1.5 V
CT = 20 pF typical load circuit capacitance
FIGURE 4. Test circuit and switching waveforms.
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Note: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured
as 00 (CLKOUT not divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Note: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured
as 00 (CLKOUT not divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Note 1. Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
FIGURE 4. Test circuit and switching waveforms – Continued.
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33
Note 1. Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Note 1. Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
FIGURE 4. Test circuit and switching waveforms – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
34
Note 1. Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Note 1. Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
FIGURE 4. Test circuit and switching waveforms – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
35
FIGURE 4. Test circuit and switching waveforms – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
36
FIGURE 4. Test circuit and switching waveforms – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
37
FIGURE 4. Test circuit and switching waveforms – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
38
FIGURE 4. Test circuit and switching waveforms – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
39
FIGURE 4. Test circuit and switching waveforms – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
40
FIGURE 4. Test circuit and switching waveforms – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
41
Note 1. BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
Note 2. BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx or BDXx when configured as a general-purpose output.
FIGURE 4. Test circuit and switching waveforms – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
42
FIGURE 4. Test circuit and switching waveforms – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
43
Note 1. HAD refers to HCNTL0, HCNTL1, and HR/W.
Note 2. When HAS is not used (HAS always high).
FIGURE 4. Test circuit and switching waveforms – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
44
Note 1. GPIOx refers to HD0, HD1, HD2, HD7, when the HD bus is configured for general-purpose input/output (I/O).
FIGURE 4. Test circuit and switching waveforms – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
45
FIGURE 4. Test circuit and switching waveforms – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
46
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015.
(2) TA = +125°C, minimum.
b.
Interim and final electrical test parameters shall be as specified in table II herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table II herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
47
4.4.1 Group A inspection.
a.
Tests shall be as specified in table II herein.
b.
Subgroup 4 (CIN, COUT) shall be measured only for the initial test and after process or design changes which may affect
input capacitance. One pin of each input/output driver (buffer) type shall be tested on each sample device. A minimum
sample size of 5 devices with zero rejects shall be required.
c.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the functionality of the device. For device
classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device.
TABLE II. Electrical test requirements.
Test requirements
Interim electrical
parameters (see 4.2)
Final electrical
parameters (see 4.2)
Group A test
requirements (see 4.4)
Group C end-point electrical
parameters (see 4.4)
Group D end-point electrical
parameters (see 4.4)
Group E end-point electrical
parameters (see 4.4)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Device
class M
1, 7, 9
Device
class Q
1, 7, 9
Device
class V
1, 7, 9
1, 2, 3, 7, 8, 9, 10, 11
1/
1, 2, 3, 7, 8, 9,
10, 11 1/
1, 2, 3, 7, 8,
9, 10, 11 2/
1, 2, 3, 4, 7, 8, 9, 10,
11
1, 2, 3, 4, 7, 8,
9, 10, 11
1, 2, 3, 4, 7,
8, 9, 10, 11
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
---
---
---
1/ PDA applies to subgroup 1.
2/ PDA applies to subgroups 1 and 7.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
b.
TA = +125°C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
48
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table II herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table I at
TA = +25°C ±5°C, after exposure, to the subgroups specified in table II herein.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-01530
A
REVISION LEVEL
A
SHEET
49
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 08-01-10
Approved sources of supply for SMD 5962-01530 are listed below for immediate acquisition information only and shall
be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised
to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate
of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of
supply at http://www.dscc.dla.mil/Programs/Smcr/ .
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-0153001QXA
01295
SMJ320VC5416HFG
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
Vendor CAGE
number
01295
Vendor name
and address
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Ln.
P.O. Box 660199
Dallas, TX 75243
Point of contact:
U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
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