REVISIONS LTR DESCRIPTION DATE APPROVED A Correct lead finish on last page. Update boilerplate. - CFS 05-11-08 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 12-03-22 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV B B B B B PAGE 40 41 42 43 44 REV B B B B B B B B B B B B B B B B B B B B B B PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV B B B B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 REV STATUS OF PAGES PMIC N/A PREPARED BY Phu H. Nguyen Original date of drawing CHECKED BY Phu H. Nguyen YY MM DD 04-04-08 APPROVED BY Thomas M. Hess SIZE A REV AMSC N/A CODE IDENT. NO. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 TITLE MICROCIRCUIT, DIGITAL, FIXED POINT DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON DWG NO. V62/04610 16236 B PAGE 1 OF 44 5962-V045-12 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance Fixed-Point Digital Signal Processor microcircuit, with an operating temperature range of -40C to +100C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04610 - Drawing number 1.2.1 Device type(s). 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1/ Device type Generic 01 Circuit function SM320VC5416-EP Fixed Point Digital Signal Processor 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins Package style X Y 144 144 Plastic ball grid array Plastic quad flatpack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z 1.3 Absolute maximum ratings. Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other 2/ 3/ Supply voltage I/O range, (DVDD) ............................................................................................. Supply voltage core range, (CVDD) ........................................................................................... Input voltage range, (VI) ........................................................................................................... Output voltage range (VO) ....................................................................................................... Operating case temperature ranges, (TC): (Extended) ............................................................. Storage temperature range, (TSTG)............................................................................................ 1/ 2/ 3/ -0.3 V to +4.0 V -0.3 V to +2.0 V -0.3 V to +4.5 V -0.3 V to +4.0 V -40C to +100C -55C to +150C Users are cautioned to review the manufacturers data manual for additional user information relating to this device. Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to DVSS. Long term high temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See manufacturer data for additional information on enhanced plastic packaging. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 2 1.4 Recommended operating conditions. Device supply voltage, I/O (DVDD) .............................................................................. +2.7 V to +3.6 V Device supply voltage, core (CVDD) (VC5416-160) .................................................... +1.55 V to +1.65 V Device supply voltage, core (CVDD) (VC5416-120) .................................................... +1.42 V to +1.65 V Supply voltage, GND (CVSS, DVSS) ............................................................................ 0 V High level input voltage, I/O (VIH): 4/ (DVDD = 2.7 V to 3.6 V) .................................................................................. 2.4 V to DVDD + 0.3 V All other inputs ...................................................................................................... 2.0 V to DVDD + 0.3 V Low level input voltage, I/O (VIL): ................................................................................ -0.3 V to +0.8 V Maximum high level output current, (IOH) ................................................................... -8 mA 5/ Maximum low level output current, (IOL) ..................................................................... 8 mA 5/ Operating case temperature (TC) ............................................................................... -40C to +100C Junction to air (RJA) Case X ................................................................................................................ +38C/W Case Y ................................................................................................................ +56C/W Junction to case (RJC) Case X ................................................................................................................ +5C/W Case Y ................................................................................................................ +5C/W 2. APPLICABLE DOCUMENTS JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 – Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103 North 10th Street, Suite 240–S, Arlington, VA 22201.) 4/ 5/ RS , INTn , NMI , X2/CLKIN, CLKMDn, BCLKRn, BCLKXn, HCS , HDS1 , HDS2 , HAS , TRST , BIO , Dn, An, HDn, TCK, DVDD = 2.7 V to 3.6 V Note that maximum output currents are DC values only. Transient currents may exceed these values. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 3 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 . 3.5.3 Terminal connections. The terminal connections shall be as shown in figure 2 Block diagram. The block diagram shall be as specified in figure 3. 3.5.4 Load circuit. The load circuit shall be as specified in figure 4. 3.5.5 Timing waveforms. The timing waveforms shall be as shown in figure 5-24. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 4 TABLE I. Electrical performance characteristics. Test Symbol High level output voltage 2/ VOH Low level output voltage 2/ VOL Test condition -40C TC +100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Limits Min DVDD = 2.7 to 3.0 V, IOH = Max 2.2 DVDD = 3.0 to 3.6 V, IOH = Max 2.4 Max V IOL = Max 0.4 V A -40 40 TRST , HPI16 -10 800 HPIENA With internal pull down, RS = 0 -10 400 TMS, TCK, TDI, HPI II 3/ With internal pull ups A[17:0], D[15:0], HD[7:0] Bus holder enabled, DVDD = Max 7/ -400 10 -275 275 All other input only pins -5 IDDC CVDD = 1.6 V, fx = 160, TC = 25C Supply current .pins IDDP DVDD = 3.0 V, fx = 160 MHz, TC = 25C PLL x 1 mode, 20 MHz input 2 Typ IDD TC = 25C 1 Typ TC = 100C 30 Typ IDLE2 IDLE3 Divide by two mode, CLKIN stopped Input capacitance CI Output capacitance CO Input clock frequency 4/, 5 Supply current, core CPU Supply current, standby Unit With internal pull down X2/CLKIN Input current (VI = DVSS to DVDD) 1/ 4/, 60 Typ 5/ mA 40 Typ 6/ mA mA 5 Typ pF 5 Typ fx 10 8/ 20 pF 9/ MHz See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 5 TABLE I. Electrical performance characteristics - Continued. Test 1/ Test condition -40C TC +100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Symbol Limits Min Unit Max CLOCK OPTION Divide by 2 and divide by 4 clock options timing requirements 10/ 11/ Cycle time, X2/CLKIN tc(CI) See figure 5 20 ns Fall time, X2/CLKIN tf(CI) 4 Rise time, X2/CLKIN tr(CI) 4 Pulse duration, X2/CLKIN low tW(CIL) 4 Pulse duration, X2/CLKIN high tW(CIH) 4 Divide by 2 and divide by 4 clock options switching characteristics Cycle time, CLKOUT 10/ 11/ tc(CO) Delay time, X2/CLKIN high/low to CLKOUT high/low See figure 5 6.25 td(CI-CO) 12/ 13/ 4 ns 11 Fall time, CLKOUT tf(CO) 1 Typ Rise time, CLKOUT tr(CO) 1 Typ Pulse duration , CLKOUT low tW(COL) H-2 H-1 Pulse duration , CLKOUT high tW(COH) H-2 H-1 20 200 20 100 20 50 MULTIPLY BY N CLOCK OPTION (PLL ENABLED) Multiply by N clock option timing requirements 11/ Integer PLL multiplier N (N = 1-15) Cycle time, X2/CLKIN PLL multiplier N = x.5 14/ PLL multiplier N = x.25, x.75 See figure 6 tc(CI) 14/ 14/ Fall time, X2/CLKIN tf(CI) 4 Rise time, X2/CLKIN tr(CI) 4 Pulse duration, X2/CLKIN low tW(CIL) 4 Pulse duration, X2/CLKIN high tW(CIH) 4 Multiply by N clock option switching characteristics ns 11/ Cycle time, CLKOUT Delay time, X2/CLKIN high/low to CLKOUT high/low tc(CO) See figure 6 6.25 td(CI-CO) ns 4 11 Fall time, CLKOUT tf(CO) 2 Typ Rise time, CLKOUT tr(CO) 2 Typ Pulse duration , CLKOUT low tW(COL) H-2 H-1 Pulse duration , CLKOUT high tW(COH) H-2 H-1 Transitory phase, PLL lock up time tp s 30 See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 6 TABLE I. Electrical performance characteristics - Continued. Test Symbol 1/ Test condition -40C TC +100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max MEMORY AND PARALLEL I/O INTERFACE TIMING Memory read timing requirements 12/ Access time, read data access from address valid, first read access 16/ ta(A)M1 Access time, read data access from address valid, consecutive read accesses 16/ ta(A)M2 Setup time, read data valid before CLKOUT low tsu(D)R 7 Hold time, read data valid after CLKOUT low th(D)R 0 Memory read switching characteristics 12/ Delay time, CLKOUT low to address valid 16/ td(CLKL-A) See figure 7 4H-9 2H-9 See figure 7 -1 4 Delay time, CLKOUT low to MSTRB low td(CLKL-MSL) -1 4 Delay time, CLKOUT low to MSTRB high td(CLKL-MSH) 0 4 -1 4 Memory write switching characteristics 12/ Delay time, CLKOUT low to address valid 16/ td(CLKL-A) See figure 8 tsu(A)MSL 2H-3 td(CLKL-D)W -1 4 Setup time, data valid before MSTRB high tsu(D)MSH 2H-5 2H+6 Hold time, data valid after MSTRB high th(D)MSH 2H-5 2H+6 Delay time, CLKOUT low to MSTRB low td(CLKL-MSL) -1 4 tw(SL)MS 2H-3.2 td(CLKL-MSH) 0 Setup time, address valid before MSTRB low 16/ Delay time, CLKOUT low to data valid Pulse duration, MSTRB low Delay time, CLKOUT low to MSTRB high I/O read timing requirements ns ns ns 4 17/ Access time, read data access from address valid, first read access 16/ ta(A)M1 Setup time, read data valid before CLKOUT low tsu(D)R 7 Hold time, read data valid after CLKOUT low th(D)R 0 I/O read switching characteristics See figure 9 4H-9 ns -1 4 ns 4 4 17/ Delay time, CLKOUT low to address valid 16/ td(CLKL-A) See figure 9 Delay time, CLKOUT low to IOSTRB low td(CLKL-IOSL) -1 Delay time, CLKOUT low to IOSTRB high td(CLKL-IOSH) 0 See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 7 TABLE I. Electrical performance characteristics - Continued. Test 1/ Test condition -40C TC +100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Symbol Limits Unit Min Max -1 4 MEMORY AND PARALLEL I/O INTERFACE TIMING – CONTINUED I/O write switching characteristics 17/ Delay time, CLKOUT low to address valid 16/ td(CLKL-A) See figure 10 tsu(A)IOSL 2H-3 Delay time, CLKOUT low to write data valid td(CLKL-D)W -1 4 Setup time, data valid before IOSTRB high tsu(D)IOSH 2H-5 2H+6 Hold time, data valid after IOSTRB high th(D)IOSH 2H-5 2H+6 Delay time, CLKOUT low to IOSTRB low td(CLKL-IOSL) -1 4 tw(SL)IOS 2H-2 td(CLKL-IOSH) 0 Setup time, address valid before IOSTRB low 16/ Pulse duration, IOSTRB low Delay time, CLKOUT low to IOSTRB high ns 4 READY TIMING FOR EXTERNAL GENERATED WAIT STATES Ready timing requirements for external generated wait states 11/ 18/ Setup time, READY before CLKOUT low tsu(RDY) Hold time, READY after CLKOUT low th(RDY) See figure 11-12 19/ tv(RDY)MSTRB Hold time, READY after MSTRB low 19/ th(RDY)MSTRB Valid time, READY after IOSTRB low 19/ tv(RDY)IOSTRB Hold time, READY after IOSTRB low 19/ th(RDY)IOSTRB td(MSCL) Delay time, CLKOUT low to MSC high td(MSCH) ns 0 Valid time, READY after MSTRB low Delay time, CLKOUT low to MSC low 7 4H-6.2 4H 4H-6 4H See figure 11-12 0 4 0 4 ns See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 8 TABLE I. Electrical performance characteristics - Continued. Test 1/ Test condition -40C TC +100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Symbol Limits Unit Min Max HOLD AND HOLDA TIMINGS HOLD and HOLDA timing requirements 11/ tw(HOLD) Pulse duration, HOLD low duration Setup time, HOLD before CLKOUT low 4H+8 tsu(HOLD) 20/ HOLD and HOLDA switching characteristics See figure 13 ns 7 11/ Disable time, Address, PS , DS , IS high impedance from CLKOUT low tdis(CLKL-A) See figure 13 3 Disable time, R/ W high impedance from CLKOUT low tdis(CLKL-RW) 3 Disable time, MSTRB , IOSTRB high impedance from CLKOUT low tdis(CLKL-S) 3 Enable time, Address, PS , DS , IS valid from CLKOUT low ten(CLKL-A) 2H+3 ten(CLKL-RW) 2H+3 Enable time, R/ W enabled from CLKOUT low Enable time, MSTRB , IOSTRB enabled from CLKOUT low ten(CLKL-S) Valid time, HOLD low after CLKOUT low tv(HOLDA) Valid time, HOLDA low after CLKOUT low Pulse duration, HOLDA low duration tw(HOLDA) 2 2H+3 -1 4 -1 4 ns 2H-3 See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 9 TABLE I. Electrical performance characteristics - Continued. Test Symbol 1/ Test condition -40C TC +100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Limits Min Unit Max RESET, BIO , INTERRUPT, AND MP/ MC TIMINGS Reset, BIO interrupt, and MP/ MC timing requirements Hold time, RS after CLKOUT low Hold time, BIO after CLKOUT low 11/ th(RS) 20/ 20/ Hold time, INTn , NMI after CLKOUT low 20/ 21/ See figure 14 2 th(BIO) 4 th(INT) 0 ns th(MPMC) 4 tw(RSL) 4H+3 Pulse duration, BIO low, synchronous tw(BIO)S 2H+3 Pulse duration, BIO low, asynchronous tw(BIO)A 4H Pulse duration, INTn , NMI high (synchronous) tw(INTH)S 2H+2 Pulse duration, INTn , NMI high (asynchronous) tw(INTH)A 4H Pulse duration, INTn , NMI low (synchronous) tw(INTL)S 2H+2 Pulse duration, INTn , NMI low (asynchronous) tw(INTL)A 4H tw(INTL)WKP 7 20/ 24/ tsu(RS) 3 20/ tsu(BIO) 7 tsu(INT) 7 tsu(MPMC) 5 Hold time, MP/ MC after CLKOUT low Pulse duration, RS low 20/ 22/ 23/ Pulse duration, INTn , NMI low for IDLE2/IDLE3 wakeup Setup time, RS before X2/CLKIN low Setup time, BIO before CLKOUT low Setup time, INTn , NMI , RS before CLKOUT low Setup time, MP/ MC before CLKOUT low 20/ 20/ INSTRUCTION ACQUISITION ( IAQ ) AND INTERRUPT ACKNOWLEDGE ( IACK ) TIMINGS Instruction acquisition ( IAQ ) and interrupt acknowledge ( IACK ) switching characteristics 11/ -1 4 td(CLKL-IAQH) -1 4 Delay time, CLKOUT low to IACK low td(CLKL-IACKL) -1.2 4 Delay time, CLKOUT low to IACK high td(CLKL-IACKH) -1 4 td(CLKL-A) -1 4 Pulse duration, IAQ low tw(IAQL) 2H-2 Pulse duration, IACK low tw(IACKL) 2H-3 Delay time, CLKOUT low to IAQ low td(CLKL-IAQL) Delay time, CLKOUT low to IAQ high Delay time, CLKOUT low to address valid See figure 15 ns See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 10 TABLE I. Electrical performance characteristics - Continued. Test Symbol 1/ Test condition -40C TC +100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max -1 4 -1 4 EXTERNAL FLAG (XF) AND TOUT TIMINGS External flag (XF) and TOUT switching characteristics 11/ Delay time, CLKOUT low to XF high td(XF) Delay time, CLKOUT low to XF low See figure 16 Delay time, CLKOUT low to TOUT high td(TOUTH) -1 4 Delay time, CLKOUT low to TOUT low td(TOUTL) -1 4 Pulse duration, TOUT tw(TOUT) 2H-4 ns MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING McBSP transmit and receive timing requirements 25/ Cycle time, BCLKR/X 26/ Pulse duration, BCLKR/X high or BCLKR/X low tc(BCKRX) 26/ Setup time, external BFSR high before BCLKR low See figure 17 tw(BCKRX) tsu(BFRH-BCKRL) Hold time, external BFSR high after BCLKR low th(BCKRL-BFRH) Setup time, BDR valid before BCKR low tsu(BDRV-BCKRL) Hold time, BDR valid after BCKR low th(BCKRL-BDRV) Setup time, external BFSR high before BCLKX low tsu(BFXH-BCKXL) Hold time, external BFSR high after BCLKX low th(BCKXL-BFXH) BCLKR/X ext 4P 27/ BCLKR/X ext 2P-1 27/ BCLKR int 8 BCLKR ext 1 BCLKR int 1 BCLKR ext 2 BCLKR int 7 BCLKR ext 1 BCLKR int 2 BCLKR ext 3 BCLKR int 8 BCLKR ext 1 BCLKR int 0 BCLKR ext 2 ns Rise time, BCKR/X tr(BCKRX) BCLKR/X ext 6 Fall time, BCKR/X tf(BCKRX) BCLKR/X ext 6 See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 11 TABLE I. Electrical performance characteristics - Continued. Test Symbol 1/ Test condition -40C TC +100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Limits Min Unit Max MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING McBSP transmit and receive switching characteristics 25/ Cycle time, BCLKR/X 26/ Pulse duration, BCLKR/X high Pulse duration, BCLKR/X low tc(BCKRX) 26/ 26/ Delay time, BCLKR high to internal BFSR valid BCLKR/X int 4P 27/ tw(BCKRXH) BCLKR/X int D-1 28/ D+1 28/ tw(BCKRXL) BCLKR/X int C-1 28/ C+1 28/ -3 3 td(BCKXH-BFXV) Disable time, BCLKX high to BDX high impedance following last data bit of transfer td(BCKXH-BDXHZ) DXENA = 0 BCLKR int td(BCKRH-BFRV) Delay time, BCLKX high to internal BFSX valid Delay time, BCLKX high to BDX valid See figure 17 tdis(BCKXH-BDXV) DXENA = 0 Delay time, BFSX high to BDX valid Only applies when in data delay 0 (XDATDLY = 00b) mode td(BFXH-BDXV) ns BCLKR ext 0 11 BCLKR int -1 5 BCLKR ext 3 11 BCLKR int 6 BCLKR ext 10 BCLKR int -1 29/ 10 BCLKR ext 3 20 BCLKR int -1 29/ 20 BCLKR ext 2.8 30 BCLKR int -1.2 29/ 7 BCLKR ext 3 11 McBSP GENERAL PURPOSE I/O TIMING McBSP general purpose I/O timing requirements Setup time, BGPIOx input mode before CLKOUT high 30/ tsu(BGPIO-COH) Hold time, BGPIOx input mode after CLKOUT high 30/ th(COH-BGPIO) See figure 18 7 ns 0 McBSP general purpose I/O switching characteristics Delay time, CLKOUT high to BGPIOx output mode 31/ td(COH-BGPIO) See figure 18 -2 4 ns See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 12 TABLE I. Electrical performance characteristics - Continued. Test Test condition -40C TC +100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Symbol 1/ Limits Unit Master Min Slave Max Min Max McBSP GENERAL PURPOSE I/O TIMING – CONTINUED McBSP as SPI Master or Slave timing requirements (CLKSTP = 10b, CLKXP = 0) 32/ Setup time, BDR valid before BCLKX low tsu(BDRV-BCKXL) Hold time, BDR valid after BCLKX low th(BCKXL-BDRV) See figure 19 McBSP as SPI Master or Slave switching characteristics (CLKSTP = 10b, CLKXP = 0) Hold time, BFSX low after BCLKX low 33/ th(BCKXL-BFXL) Delay time, BFSX low to BCLKX high 34/ 2.2-6P 27/ 4 5+12P 27/ T+4 td(BFXL-BCKXH) C-4 C+3 td(BCKXH-BDXV) -4 5 Disable time, BDX high impedance following last data bit from BCLKX low tdis(BCKXL- C-2 C+3 Disable time, BDX high impedance following last data bit from BFSX high tdis(BFXH- Delay time, BFSX low to BDX valid Setup time, BDR valid before BCLKX low tsu(BDRV-BCKXL) Hold time, BDR valid after BCLKX high th(BCKXH-BDRV) 34/ Delay time, BCLKX low to BDX valid Disable time, BDX high impedance following last data bit from BCLKX low Delay time, BFSX low to BDX valid 10P+17 27/ 2P-4 27/ 6P+17 27/ 4P+2 27/ 8P+17 27/ 32/ See figure 19 McBSP as SPI Master or Slave switching characteristics (CLKSTP = 11b, CLKXP = 0) Delay time, BFSX low to BCLKX high 6P+2 27/ BDXHZ) McBSP as SPI Master or Slave timing requirements (CLKSTP = 11b, CLKXP = 0) 33/ ns BDXHZ) td(BFXL-BDXV) Hold time, BFSX low after BCLKX low ns 32/ T-3 Delay time, BCLKX high to BDX valid See figure 19 12 th(BCKXL-BFXL) See figure 19 12 2.2-6P 27/ 4 5+12P 27/ ns 32/ C-3 C+4 ns td(BFXL-BCKXH) T-4 T+3 td(BCKXL-BDXV) -4 5 6P+2 27/ 10P+17 27/ tdis(BCKXL- -2 4 6P-4 27/ 10P+17 27/ D-2 D+4 4P+2 27/ 8P+17 27/ BDXHZ) td(BFXL-BDXV) See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 13 TABLE I. Electrical performance characteristics - Continued. Test Test condition -40C TC +100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Symbol 1/ Limits Unit Master Min Slave Max Min Max McBSP GENERAL PURPOSE I/O TIMING – CONTINUED McBSP as SPI Master or Slave timing requirements (CLKSTP = 10b, CLKXP = 1) 32/ Setup time, BDR valid before BCLKX high tsu(BDRV-BCKXH) Hold time, BDR valid after BCLKX high th(BCKXH-BDRV) See figure 20 McBSP as SPI Master or Slave switching characteristics (CLKSTP = 10b, CLKXP = 1) Hold time, BFSX low after BCLKX high 5+12P 27/ D-4 D+3 td(BCKXL-BDXV) -4 5 Disable time, BDX high impedance following last data bit from BCLKX high tdis(BCKXH- D-2 D+3 Disable time, BDX high impedance following last data bit from BFSX high tdis(BFXH- Delay time, BFSX low to BDX valid Setup time, BDR valid before BCLKX low tsu(BDRV-BCKXL) Hold time, BDR valid after BCLKX low th(BCKXL-BDRV) 34/ Delay time, BCLKX high to BDX valid Disable time, BDX high impedance following last data bit from BCLKX high Delay time, BFSX low to BDX valid 10P+17 27/ 2P-4 27/ 6P+17 27/ 4P+2 27/ 8P+17 27/ 32/ See figure 20 McBSP as SPI Master or Slave switching characteristics (CLKSTP = 11b, CLKXP = 1) Delay time, BFSX low to BCLKX low 6P+2 27/ BDXHZ) td(BFXL-BDXV) 33/ ns BDXHZ) McBSP as SPI Master or Slave timing requirements (CLKSTP = 11b, CLKXP = 1) Hold time, BFSX low after BCLKX high ns 32/ td(BFXL-BCKXL) Delay time, BCLKX low to BDX valid See figure 20 4 T+4 34/ th(BCKXH-BFXL) 2-6P 27/ T-3 Delay time, BFSX low to BCLKX low 33/ 12 th(BCKXH-BFXL) See figure 20 12 2-6P 27/ 4 5+12P 27/ ns 32/ D-3 D+4 ns td(BFXL-BCKXL) T-4 T+3 td(BCKXH-BDXV) -4 5 6P+2 27/ 10P+17 27/ tdis(BCKXH- -2 4 6P-4 27/ 10P+17 27/ C-2 C+4 4P+2 27/ 8P+17 27/ BDXHZ) td(BFXL-BDXV) See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 14 TABLE I. Electrical performance characteristics - Continued. Test 1/ Test condition -40C TC +100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Symbol Limits Min Unit Max HOST PORT INTERFACE TIMING HP18 mode timing requirements Setup time, HBIL valid before DS low (when HAS is not tsu(HBV-DSL) See figure 21-22 6 ns used), or HBIL valid before HAS low th(DSL-HBV) 3 tsu(HSL-DSL) 8 Pulse duration, DS low tw(DSL) 13 Pulse duration, DS high tw(DSH) 7 Setup time, HD valid before DS high, HPI write tsu(HDV-DSH) 3 Hold time, HD valid after DS high, HPI write th(DSH-HDV)W 2 Setup time, HDx input valid before CLKOUT high, HDx configured as general purpose input tsu(GPIO-COH) 6 Hold time, HDx input valid before CLKOUT high, HDx configured as general purpose input th(GPIO-COH) 0 Hold time, HBIL valid after DS low (when HAS is not used), or HBIL valid after HAS low Setup time, HAS low before DS low See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 15 TABLE I. Electrical performance characteristics - Continued. Test Symbol 1/ Test condition -40C TC +100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Limits Min Unit Max HOST PORT INTERFACE TIMING - CONTINUED HP18 mode switching characteristics Enable time, HD driven from DS low ten(DSL-HD) See figure 21-22 0 10 Delay time, DS low to HD valid for first byte of an HPI read Case 1b: Memory accesses when DMAC is active in 32 bit mode and tw(DSH) 36 P 35/ 10 td(DSL-HDV1) Case 1c: Memory accesses when DMAC is active in 16 bit mode and tw(DSH) < 18P 35/ 18P+38/ Case 1d: Memory accesses when DMAC is active in 16 bit mode and tw(DSH) 18P 35/ 10 Case 2a: Memory accesses when DMAC is inactive and tw(DSH) < 10P 35/ 10P+38/ Case 2b: Memory accesses when DMAC is inactive and tw(DSH) 10P 35/ 10 Case 3: Register accesses 10 Delay time, DS low to HD valid for second byte of an HPI read td(DSL-HDV2) Hold time, HD valid after DS high, for a HPI read th(DSH-HDV)R Valid time, HD valid after HRDY high tv(HYH-HDV) Delay time, DS high to HRDY low td(DSH-HYL) Delay time, DS high to HRDY high 36/ ns 36P+38/ Case 1a: Memory accesses when DMAC is active in 32 bit mode and tw(DSH) < 36 P 35/ 36/ 10 0 2 8 18P+6 Case 1a: Memory accesses when DMAC is active in 16 bit mode 35/ Case 1b: Memory accesses when DMAC is active in 32 bit mode 35/ 36P+6 td(DSH-HYH) Case 2: Memory accesses when DMAC is inactive 35/ Case 3: Write accesses to HPIC register 10P+6 37/ 6P+6 Delay time, HCS low/high to HRDY low/high td(HCS-HRDY) 6 Delay time, CLKOUT high to HRDY high td(COH-HYH) 9 Delay time, CLKOUT high to HINT change td(COH-HTX) 6 Delay time, CLKOUT high to HDx output change. HDx is configured as a general purpose output td(COH-GPIO) 5 See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 16 TABLE I. Electrical performance characteristics - Continued. Test Symbol 1/ Test condition -40C TC +100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Limits Min Unit Max HOST PORT INTERFACE TIMING - CONTINUED HP16 mode timing requirements Setup time, HR/ W valid before DS falling edge tsu(HBV-DSL) 6 Hold time, HR/ W valid after DS falling edge th(DSL-HBV) 5 Setup time, address valid before DS rising edge (write) tsu(HAV-DSH) 5 Setup time, address valid before DS falling edge (read) tsu(HAV-DSL) -(4P-6) Hold time, address valid after DS rising edge. th(DSH-HAV) 1 Pulse duration, DS low tw(DSL) 30 Pulse duration, DS high tw(DSH) 10 Cycle time, DS rising edge to next DS rising edge ns Memory accesses with no DMA activity Reads 10P+30 Writes 10P+10 Memory accesses with 16 bit DMA activity Reads Writes 16P+10 Memory accesses with 32 bit DMA activity Reads 24P+30 Writes 24P+10 tc(DSH-DSH) 16P+30 Setup time, HD valid before DS rising edge tsu(HDV-DSH)W 8 Hold time, HD valid after DS rising edge, write th(DSH-HDV)W 2 See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 17 TABLE I. Electrical performance characteristics - Continued. Test Symbol 1/ Test condition -40C TC +100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Limits Min Unit Max HOST PORT INTERFACE TIMING - CONTINUED HP18 mode switching characteristics Delay time, DS low to HD driven Delay time, DS low to HD valid for first word of an HPI read Delay time, DS high to HRDY high td(DSL-HDD) See figure 21-22 0 10 Case 1b: Memory accesses not immediately following a write when DMAC is active in 32 bit mode ns 48P+39/ Case 1a: Memory accesses initiated immediately following a write when DMAC is active in 32 bit mode and tw(DSH) < 26 P 24P+20 td(DSL-HDV1) Case 1c: Memory accesses initiated immediately following a write when DMAC is active in 16 bit mode and tw(DSH) < 18P 32P+39/ Case 1d: Memory accesses not immediately following a write when DMAC is active in 16 bit mode 16P+20 Case 2a: Memory accesses initiated immediately following a write when DMAC is inactive and tw(DSH) < 10P 20P+39/ Case 2b: Memory accesses not immediately following a write when DMAC is inactive 10P+20 Memory writes when no DMA is active 10P+5 Memory writes with one or more 16 bit DMA channels active td(DSH-HYH) 16P+5 Memory writes with one or more 32 bit DMA channels active 24P+5 Valid time, HD valid after HRDY high tv(HYH-HDV) Hold time, HD valid after DS rising edge, read td(DSH-HDV)R 7 Delay time, CLKOUT rising edge to HRDY high td(COH-HYH) 5 Delay time, DS low to HRDY low td(DSL-HYL) 12 Delay time, DS low to HRDY low td(DSH-HYL) 12 1 6 See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 18 TABLE I. Electrical performance characteristics - Continued. 1/ 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ All input and output voltage level except RS , INT 0 - INT 3 , NMI , X2/CLKIN, CLKMD1-CLKMD3, BCLKRn, BCLKXn, HCS , 3/ 4/ 5/ 6/ 7/ 8/ 9/ 10/ HAS , HDS1 , HDS2 , BIO , TCK, , TRST , Dn, An, HDn are LVTTL compatible. HPI input signals except for HPIENA and HPI16, when HPIENA = 0. Clock mode: PLL x 1 with external source. This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being executed. This value was obtained with single cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed refer to the manufacturer data TMS320LC54x Power Dissipation application report (literature number SPRA164). VIL(MIN) VI VIL(MAX) or VIH(MIN) VI VIH(MAX). This device utilizes a fully static design and therefore can operate with tc(CI) approaching . It is recommended that the PLL multiply by N clocking option be used for maximum frequency operation. Clock mode pin settings for the divide by 2 and by divide by 4 clock options CLKMD1 11/ 12/ 13/ 14/ CLKMD1 CLKMD1 CLOCK MODE 0 0 0 ½, PLL disabled 1 0 1 1/4, PLL disabled 1 1 1 ½, PLL disabled H = 0.5tc(CO). It is recommended that the PLL clocking option to be used for maximum frequency operation. This device utilizes a fully static design and therefore can operate with tc(CI) approaching . N is the multiplication factor. 15/ MSTRB = 0 and H = 0.5tc(CO). 16/ Address, R/ W , PS , DS , and IS timing are all included in timing referenced as address. 17/ 18/ IOSTRB = 0 and H = 0.5tc(CO). The hardware wait states can be used only in conjunction with the software wait states extend the bus cycles. To generate wait states by READY, at least two software wait states must be programmed. READY is not sampled until the condition of the internal software wait states. These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT. These inputs can be driven from an asynchronous source, therefore, there are no specific timing requirements with respect to CLKOUT, however, if this timing is met, the input will recognized on the CLKOUT edge referenced. 19/ 20/ 21/ The external interrupts ( INT 0 - INT 3 , NMI ) are synchronized to the core CPU by way of a two flip-flop synchronizer that samples these inputs with consecutive falling edges of CLKOUT. The input to interrupt pins is required to represent a 1-0-0 sequence at the timing that is corresponding to three CLKOUTs sampling sequence. 22/ If the PLL mode is selected, then at power on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 s to ensure synchronization and lock in of the PLL. 23/ 24/ Note that RS may cause a change in clock frequency, therefore changing the value of H. The diagram assumes clock mode is divide by 2 and the CLKOUT divide factor is set to no divide mode (DIVFCT = 00 field in the BSCR). CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any signals is inverted, then the timing references of that signal are also inverted. 25/ DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 19 TABLE I. Electrical performance characteristics - Continued. 26/ 27/ 28/ 29/ 30/ 31/ 32/ 33/ 34/ 35/ 1/ Note that in some cases, for example when driving another 54x device McBSP, maximum serial port clocking rates may not be achievable at maximum CPU clock frequency due to transmitted data timings and corresponding receive timing requirements. A separate detailed timing analysis should be performed for each specific McBSP interface. P = 1/(2 * processor clock). T = BCLKRX period = (1 + CLKGDV) * 2P C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even. Minimum delay times also represent minimum output hold times. BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configure as a general purpose input. BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDRx when configure as a general purpose output. For all SPI slave modes, CLKG is programmed as ½ of the CPU clock by setting CLKSM = CLKGDV = 1. FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active low slave enable output. As a slave, the active low signal input on BFSX and BFSR is inverted before being used internally. CLKXM = BFXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP. BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master (BCLKX). DMAC stands for direct memory access controller (DMAC). The HP18 shares the internal DMA bus with the DMAC, thus HP18 access times are affected by DMAC activity. 36/ The HRDY output is always high when HCS input is high, regardless of DS timings. 37/ This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur asynchronously, and do not cause HRDY to be deasserted. 10-tw(DSH) 20- tw(DSH) 38/ 39/ DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 20 Case X Symbol Millimeters Min Max A1 0.85 0.95 A2 0.35 0.45 b 0.45 0.55 D/E 11.90 12.10 A Notes: 1. 2. 1.40 D1/E1 9.60 Typ e 0.80 Typ All linear dimensions are in millimeters. This drawing is subject to change without notice. FIGURE 1. Case outlines. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 21 Case Y Symbol A A1 A2 b c Notes: 1. 2. 3. Dimensions Millimeters Symbol Min Max 1.60 1.35 1.45 0.05 0.17 0.27 0.13 Nom D/E D1/E1 D2/E2 e L Millimeters Min Max 21.80 22.20 19.80 20.20 17.50 Typ 0.50 Typ 0.45 0.75 All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MO-136 FIGURE 1. Case outlines - Continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 22 Case X Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name A1 CVSS B1 A22 C1 DVDD D1 A12 A2 A21 B2 DVSS C2 CVSS D2 A11 A3 A8 B3 A9 C3 CVDD D3 HD7 A4 A5 B4 A6 C4 A7 D4 A10 A5 A2 B5 A3 C5 HD6 D5 A4 A6 HDS2 B6 DVDD C6 A0 D6 A1 A7 CVSS B7 CVDD C7 HDS1 D7 DVSS A8 HD5 B8 D15 C8 D14 D8 D13 A9 HD4 B9 D12 C9 D11 D9 D10 A10 D9 B10 D8 C10 D7 D10 D6 A11 DVDD B11 CVSS C11 DVSS D11 D4 A12 A20 B12 A18 C12 A16 D12 D3 A13 A19 B13 A17 C13 D5 D13 D2 E1 CVDD F1 CVDD G1 HR/ W H1 DS E2 A15 F2 CVSS G2 HCS H2 IS E3 A14 F3 DVSS G3 READY H3 R/ W E4 A13 F4 HAS G4 PS H4 MSTRB E10 D1 F10 X1 G10 HPIENA H10 TDO E11 D0 F11 HD3 G11 CVDD H11 TDI E12 RS F12 CLKOUT G12 TMS H12 TRST E13 X2/CLKIN F13 DVSS G13 CVSS H13 TCK J1 IOSTRB J3 XF J10 HD2 J12 EMU0 J2 MCS J4 HOLDA J11 TOUT J13 EMU1/ OFF K1 IAQ L1 MP/ MC M1 BDR1 N1 CVSS K2 HOLD L2 DVDD M2 BFSR1 N2 BCLKR1 K3 BIO L3 CVSS M3 HCNTL0 N3 DVSS K4 BCLKR0 L4 BCLKR2 M4 BFSR0 N4 BFSR0 K5 BDR0 L5 HCNTL1 M5 BDR2 N5 BCLKX0 K6 BCLKX2 L6 CVSS M6 N6 CVDD N7 BFSX2 N8 DVSS IACK K7 DVDD L7 HRDY M7 HINT BFSX0 K8 BDX2 L8 BDX0 M8 HD0 HBIL N9 INT2 HD1 N10 INT1 N11 CVDD K9 INT0 L9 NMI M9 K10 CLKMD1 L10 INT 3 M10 K11 CLKMD2 L11 CVSS M11 K12 CLKMD3 L12 DVDD M12 DVSS N12 BCLKX1 K13 HPI16 L13 DVSS M13 BDX1 N13 BFSX1 DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. FIGURE 2. Terminal connections. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 23 Case Y Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 1 CVSS 37 CVSS 73 BFSX1 109 A19 2 A22 38 BCLKR1 74 BDX1 110 A20 3 CVSS 39 HCNTL0 75 DVDD 111 CVSS 4 DVDD 40 DVSS 76 DVSS 112 DVDD 5 A10 41 BCLKR0 77 CLKMD1 113 D6 6 HD7 42 BCLKR2 78 CLKMD2 114 D7 7 A11 43 BFSR0 79 CLKMD3 115 D8 8 A12 44 BFSR2 80 HPI16 116 D9 9 A13 45 BDR0 81 HD2 117 D10 10 A14 46 HCNTL1 82 TOUT 118 D11 11 A15 47 BDR2 83 EMU0 119 D12 12 CVDD 48 BCLKX0 84 EMU1/ OFF 120 HD4 13 HAS 49 BCLKX2 85 TDO 121 D13 14 DVSS 50 CVSS 86 TDI 122 D14 15 CVSS 51 TRST 123 D15 CVDD 52 HINT CVDD 87 16 88 TCK 124 HD5 17 HCS 53 BFSX0 89 TMS 125 CVDD 18 HR/ W READY 54 BFSX2 90 CVSS 126 CVSS 55 HRDY 91 CVDD 127 HDS1 20 PS 56 DVDD 92 HPIENA 128 DVSS 21 DS 57 DVSS 93 DVSS 129 HDS2 22 IS 58 HD0 94 CLKOUT 130 DVDD 23 R/ W 59 BDX0 95 HD3 131 A0 24 MSTRB 60 BDX2 96 X1 132 A1 25 19 IOSTB 61 IACK 97 X2/CLKIN 133 A2 26 MCS 62 HBIL 98 RS 134 A3 27 XF 63 NMI 99 D0 135 HD6 28 HOLDA 64 INT 0 100 D1 136 A4 29 IAQ 65 INT1 101 D2 137 A5 30 HOLD 66 INT2 102 D3 138 A6 31 BIO 67 INT 3 103 D4 139 A7 32 MP/ MC 68 CVDD 104 D5 140 A8 33 DVDD 69 HD1 105 A16 141 A9 34 CVSS 70 CVSS 106 DVSS 142 CVDD 35 BDR1 71 BCLKX1 107 A17 143 A21 36 BFSR1 72 DVSS 108 A18 144 DVSS DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both I/O pins and the core CPU FIGURE 2. Terminal connections - Continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 24 FIGURE 3. Block diagram. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 25 Where: IOL IOH VLoad CT = 1.5 mA (all outputs) = 300 A (all outputs) = 1.5 V = 20 pF typical load circuit capacitance. FIGURE 4. Load circuit. Note: 1. The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not divided). DIVFCT is configured as CLKOUT divided by 4 mode following reset. FIGURE 5. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 26 Note: 1. The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not divided). DIVFCT is configured as CLKOUT divided by 4 mode following reset. FIGURE 6. Timing waveforms. Note 1. Address, R/ W , PS , DS , and IS timing are included in timings referenced as address. FIGURE 7. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 27 Note 1. Address, R/ W , PS , DS , and IS timing are included in timings referenced as address. FIGURE 7. Timing waveforms - Continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 28 Note 1. Address, R/ W , PS , DS , and IS timing are included in timings referenced as address. FIGURE 8. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 29 Note 1. Address, R/ W , PS , DS , and IS timing are included in timings referenced as address. FIGURE 9. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 30 Note 1. Address, R/ W , PS , DS , and IS timing are included in timings referenced as address. FIGURE 10. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 31 FIGURE 11. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 32 FIGURE 12. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 33 FIGURE 13. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 34 FIGURE 14. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 35 FIGURE 15. Timing waveforms. FIGURE 16. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 36 FIGURE 17. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 37 Note: 1. BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general purpose input. 2. BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDRx when configured as a general purpose output. FIGURE 18. Timing waveforms. FIGURE 19. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 38 FIGURE 20. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 39 Note: 1. HAD refers to HCNTL0, HCNTL1, and HR/ W . 2. When HAS is not used ( HAS always high). FIGURE 21. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 40 Note: 1. GPIOx refers to HD0, HD1, HD2, ….HD7, when the HD bus is configured for general purpose input/output (I/O). FIGURE 22. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 41 FIGURE 23. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 42 FIGURE 24. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 43 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. 1/ Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/04610-01XA 01295 SM320VC5416GGU16EP V62/04610-01YE 01295 SM320VC5416PGE16EP The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 01295 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04610 PAGE 44