PEMD3; PIMD3; PUMD3 NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ Rev. 10 — 15 November 2009 Product data sheet 1. Product profile 1.1 General description NPN/PNP Resistor-Equipped Transistors (RET). Table 1. Product overview Type number Package NXP JEITA PNP/PNP complement NPN/NPN complement PEMD3 SOT666 - PEMB11 PEMH11 PIMD3 SOT457 SC-74 - - PUMD3 SOT363 SC-88 PUMB11 PUMH11 1.2 Features Built-in bias resistors Simplifies circuit design Reduces component count Reduces pick and place costs 1.3 Applications Low current peripheral driver Control of IC inputs Replaces general-purpose transistors in digital applications 1.4 Quick reference data Table 2. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VCEO collector-emitter voltage open base - - 50 V IO output current (DC) - - 100 mA R1 bias resistor 1 (input) 7 10 13 kΩ R2/R1 bias resistor ratio 0.8 1 1.2 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ 2. Pinning information Table 3. Pinning Pin Description Simplified outline 1 GND (emitter) TR1 2 input (base) TR1 3 output (collector) TR2 4 GND (emitter) TR2 5 input (base) TR2 6 output (collector) TR1 6 5 4 Symbol 6 5 R1 4 R2 TR2 1 2 3 TR1 001aab555 R2 1 R1 2 3 006aaa143 3. Ordering information Table 4. Ordering information Type number Package Name Description Version PEMD3 - plastic surface mounted package; 6 leads SOT666 PIMD3 SC-74 plastic surface mounted package; 6 leads SOT457 PUMD3 SC-88 plastic surface mounted package; 6 leads SOT363 4. Marking Table 5. Marking codes Type number Marking code[1] PEMD3 D3 PIMD3 M7 PUMD3 D*3 [1] * = -: made in Hong Kong * = p: made in Hong Kong * = t: made in Malaysia * = W: made in China PEMD3_PIMD3_PUMD3_10 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 10 — 15 November 2009 2 of 11 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ 5. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per transistor; for the PNP transistor with negative polarity VCBO collector-base voltage open emitter - 50 V VCEO collector-emitter voltage open base - 50 V VEBO emitter-base voltage open collector - 10 V VI input voltage TR1 positive - +40 V negative - −10 V positive - +10 V negative - −40 V input voltage TR2 IO output current (DC) - 100 mA ICM peak collector current - 100 mA Ptot total power dissipation [1] - 200 mW SOT457 [2] - 300 mW SOT666 [1][3] - 200 mW Tamb ≤ 25 °C SOT363 Tstg storage temperature −65 +150 °C Tj junction temperature - 150 °C Tamb ambient temperature −65 +150 °C [1] - 300 mW SOT457 [2] - 600 mW SOT666 [1][3] - 300 mW Per device Ptot total power dissipation Tamb ≤ 25 °C SOT363 [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. [2] Device mounted on an FR4 PCB with 65 μm copper strip line, standard footprint. [3] Reflow soldering is the only recommended soldering method. PEMD3_PIMD3_PUMD3_10 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 10 — 15 November 2009 3 of 11 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ 6. Thermal characteristics Table 7. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Per transistor Rth(j-a) thermal resistance from junction to ambient in free air SOT363 [1] - - 625 K/W SOT457 [2] - - 417 K/W SOT666 [1][3] - - 625 K/W SOT363 [1] - - 416 K/W SOT457 [2] - - 208 K/W SOT666 [1][3] - - 416 K/W Per device Rth(j-a) thermal resistance from junction to ambient in free air [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [2] Device mounted on an FR4 PCB with 65 μm copper strip line, standard footprint. [3] Reflow soldering is the only recommended soldering method. 7. Characteristics Table 8. Characteristics Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Per transistor; for the PNP transistor with negative polarity ICBO collector-base cut-off current VCB = 50 V; IE = 0 A - - 100 nA ICEO collector-emitter cut-off current VCE = 30 V; IB = 0 A - - 1 μA VCE = 30 V; IB = 0 A; Tj = 150 °C - - 50 μA μA IEBO emitter-base cut-off current VEB = 5 V; IC = 0 A - - 400 hFE DC current gain VCE = 5 V; IC = 5 mA 30 - - VCEsat collector-emitter saturation voltage IC = 10 mA; IB = 0.5 mA - - 150 mV VI(off) off-state input voltage VCE = 5 V; IC = 100 μA - 1.1 0.8 V VI(on) on-state input voltage VCE = 0.3 V; IC = 10 mA 2.5 1.8 - V R1 bias resistor 1 (input) 7 10 13 kΩ 0.8 1 1.2 - - - TR1 (NPN) - - 2.5 pF TR2 (PNP) - - 3 pF R2/R1 bias resistor ratio Cc collector capacitance VCB = 10 V; IE = ie = 0 A; f = 1 MHz PEMD3_PIMD3_PUMD3_10 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 10 — 15 November 2009 4 of 11 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ 006aaa034 103 (1) (2) (3) hFE 006aaa035 1 VCEsat (V) 102 (1) (2) (3) 10−1 10 1 10−1 1 102 10 10−2 1 IC (mA) VCE = 5 V IC/IB = 20 (1) Tamb = 150 °C (1) Tamb = 100 °C (2) Tamb = 25 °C (2) Tamb = 25 °C (3) Tamb = −40 °C (3) Tamb = −40 °C Fig 1. 102 10 IC (mA) TR1 (NPN): DC current gain as a function of collector current; typical values Fig 2. 006aaa036 10 VI(on) (V) TR1 (NPN): Collector-emitter voltage as a function of collector current; typical values 006aaa037 10 VI(off) (V) (1) (2) (1) (3) 1 (2) 1 (3) 10−1 10−1 1 102 10 10−1 10−2 10−1 IC (mA) VCE = 0.3 V VCE = 5 V (1) Tamb = −40 °C (2) Tamb = 25 °C (2) Tamb = 25 °C (3) Tamb = 100 °C (3) Tamb = 100 °C TR1 (NPN): On-state input voltage as a function of collector current; typical values Fig 4. TR1 (NPN): Off-state input voltage as a function of collector current; typical values PEMD3_PIMD3_PUMD3_10 Product data sheet 10 IC (mA) (1) Tamb = −40 °C Fig 3. 1 © NXP B.V. 2009. All rights reserved. Rev. 10 — 15 November 2009 5 of 11 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ 006aaa046 −103 hFE VCEsat (V) (1) −102 (3) 006aaa047 −1 (2) −10−1 (1) −10 (3) −1 −10−1 −1 −10 IC (mA) −102 −10−2 −1 VCE = −5 V −10 (1) Tamb = 100 °C (2) Tamb = 25 °C (2) Tamb = 25 °C (3) Tamb = −40 °C −102 (3) Tamb = −40 °C TR2 (PNP): DC current gain as a function of collector current; typical values 006aaa048 −102 VI(on) (V) Fig 6. TR2 (PNP): Collector-emitter voltage as a function of collector current; typical values 006aaa049 −10 VI(off) (V) −10 (1) (1) −1 −1 (2) (2) (3) (3) −10−1 −10−1 −1 −10 IC (mA) −102 −10−1 −10−2 VCE = −0.3 V −10−1 (1) Tamb = −40 °C (2) Tamb = 25 °C (2) Tamb = 25 °C (3) Tamb = 100 °C (3) Tamb = 100 °C TR2 (PNP): On-state input voltage as a function of collector current; typical values Fig 8. IC (mA) −10 TR2 (PNP): Off-state input voltage as a function of collector current; typical values PEMD3_PIMD3_PUMD3_10 Product data sheet −1 VCE = −5 V (1) Tamb = −40 °C Fig 7. IC (mA) IC/IB = 20 (1) Tamb = 150 °C Fig 5. (2) © NXP B.V. 2009. All rights reserved. Rev. 10 — 15 November 2009 6 of 11 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ 8. Package outline 2.2 1.8 6 2.2 1.35 2.0 1.15 1.1 0.8 5 3.1 2.7 0.45 0.15 4 6 3.0 2.5 pin 1 index 1 2 1 0.25 0.10 4 2 3 0.6 0.2 0.40 0.25 0.95 1.3 0.26 0.10 1.9 Dimensions in mm Fig 9. 5 pin 1 index 3 0.3 0.2 0.65 1.7 1.3 1.1 0.9 06-03-16 Package outline SOT363 (SC-88) Dimensions in mm 04-11-08 Fig 10. Package outline SOT457 (SC-74) 1.7 1.5 6 0.6 0.5 5 4 0.3 0.1 1.7 1.5 1.3 1.1 pin 1 index 1 2 3 0.27 0.17 0.5 0.18 0.08 1 Dimensions in mm 04-11-08 Fig 11. Package outline SOT666 PEMD3_PIMD3_PUMD3_10 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 10 — 15 November 2009 7 of 11 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ 9. Packing information Table 9. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 3000 4000 8000 10000 PEMD3 - - -315 - SOT666 2 mm pitch, 8 mm tape and reel 4 mm pitch, 8 mm tape and reel PIMD3 PUMD3 SOT457 SOT363 - -115 - - 4 mm pitch, 8 mm tape and reel; T1 [2] -115 - - -135 4 mm pitch, 8 mm tape and reel; T2 [3] -125 - - -165 4 mm pitch, 8 mm tape and reel; T1 [2] -115 - - -135 4 mm pitch, 8 mm tape and reel; T2 [3] -125 - - -165 [1] For further information and the availability of packing methods, see Section 12. [2] T1: normal taping [3] T2: reverse taping PEMD3_PIMD3_PUMD3_10 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 10 — 15 November 2009 8 of 11 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ 10. Revision history Table 10. Revision history Document ID Release date PEMD3_PIMD3_ PUMD3_10 20091115 Modifications: Data sheet status Change notice Supersedes Product data sheet - PEMD3_PIMD3_ PUMD3_9 • This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content. • Figure 9 “Package outline SOT363 (SC-88)”: updated PEMD3_PIMD3_ PUMD3_9 20050518 Product data sheet - PEMD3_PIMD3_ PUMD3_8 PEMD3_PIMD3_ PUMD3_8 20041206 Product data sheet - PEMD3_PUMD3_7 PEMD3_PIMD3_PUMD3_10 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 10 — 15 November 2009 9 of 11 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ 11. Legal information 11.1 Data sheet status Document status[1][2] Product status[3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. Definition [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 11.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 11.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 11.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 12. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PEMD3_PIMD3_PUMD3_10 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 10 — 15 November 2009 10 of 11 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ 13. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 11 11.1 11.2 11.3 11.4 12 13 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 Packing information . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Contact information. . . . . . . . . . . . . . . . . . . . . 10 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 15 November 2009 Document identifier: PEMD3_PIMD3_PUMD3_10