LT5514 Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LT®5514 is a programmable gain amplifier (PGA) with bandwidth extending from low frequency (LF) to 850MHz. It consists of a digitally controlled variable attenuator, followed by a high linearity amplifier. The amplifier is configured with two identical transconductance amplifiers, hard wired in parallel with individual dedicated enable pins. When both amplifiers are enabled (Standard mode), the LT5514 offers an OIP3 of +47dBm (at 100MHz). Power dissipation can be reduced when a single amplifier is enabled (Low Power mode). Four parallel digital inputs control the gain over a 22.5dB range with 1.5dB step resolution. An on-chip power supply regulator/filter helps isolate the amplifier signal path from external noise sources. Output IP3 at 100MHz: 47dBm Maximum Output Power: 21dBm Bandwidth: LF to 850MHz Propagation Delay: 0.8ns Maximum Gain: 33dB Noise Figure: 7.3dB (Max Gain) Gain Control Range: 22.5dB Gain Control Step: 1.5dB Gain Control Settling Time: 500ns Output Noise Floor: –134dBm/Hz (Max Gain) Reverse Isolation: –80dB Single Supply: 4.75V to 5.25V Low Power Mode Shutdown Mode Enable/Disable Time: 1µs Differential I/O Interface 20-Lead TSSOP Package The LT5514’s open-loop architecture offers stable operation for any practical load conditions, including peakingfree AC response when driving capacitive loads, and excellent reverse isolation. U APPLICATIO S ■ ■ ■ ■ High Linearity ADC Driver IF Sampling Receivers VGA IF Power Amplifier 50Ω Driver Instrumentation Applications , LTC and LT are registered trademarks of Linear Technology Corporation. U ■ The LT5514 may be operated broadband, where the output differential RC time constant sets the bandwidth, or it may be used as a narrowband driver with the appropriate output filter. TYPICAL APPLICATIO Output IP3 vs Frequency (Standard Mode) 56 5V 53 CHOKE RF INPUT IF BPF LO IF AMP 50 0.1µF 100Ω LT5514 0.1µF 0.1µF GAIN CONTROL ADC 5514 TA01 OIP3 (dBm) 0.1µF CHOKE ROUT = 200Ω 47 ROUT = 100Ω 44 41 4 LINES 38 35 0 50 100 FREQUENCY (MHz) 150 200 5514 TA02 5514f 1 LT5514 U W W W U U W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION (Notes 1, 2) Power Supply Voltage (VCC1, VCC2) .......................... 6V Output Supply Voltage (OUT+, OUT–) ....................... 8V Control Input Voltage (ENA, ENB, PGAx) .. –0.5V to VCC Signal Input Voltage (IN+, IN–) ................... –0.5V to 3V Operating Ambient Temperature Range .. – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C TOP VIEW ENA 1 20 ENB VCC1 2 19 VCC2 GND 3 18 GND GND 4 17 GND IN + IN – 5 6 21 ORDER PART NUMBER LT5514EFE 16 OUT – 15 OUT + GND 7 14 GND GND 8 13 GND PGA0 9 12 PGA3 PGA1 10 11 PGA2 FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 150°C, θJA = 38°C/W EXPOSED PAD (PIN 21) IS GND MUST BE SOLDERED TO PCB Consult LTC Marketing for parts specified with wider operating temperature ranges. W U ODES OF OPERATIO MODES Full Power (Standard) Low Power A Low Power B Shutdown ENA High High Low Low AMP A On On Off Off WW U PROGRA ENB High Low High Low AMP B On Off On Off LT5514 STATE Enable Amp A and Amp B Enable Amp A Enable Amp B Sleep, All Amps Disabled U 1 2 3 4 ABLE GAI SETTI GS ATTENUATION STEP RELATIVE TO MAX GAIN 1 0dB 2 –1.5dB 3 –3.0dB 4 –4.5dB 5 –6.0dB 6 –7.5dB 7 –9.0dB 8 –10.5dB 9 –12.0dB 10 –13.5dB 11 –15.0dB 12 –16.5dB 13 –18.0dB 14 –19.5dB 15 –21.0dB 16 –22.5dB *ROUT = 200Ω **ROUT = 400Ω PGA0 High Low High Low High Low High Low High Low High Low High Low High Low PGA1 High High Low Low High High Low Low High High Low Low High High Low Low PGA2 High High High High Low Low Low Low High High High High Low Low Low Low PGA3 High High High High High High High High Low Low Low Low Low Low Low Low POWER GAIN STANDARD MODE* LOW POWER MODE** 33.0dB 30.0dB 31.5dB 28.5dB 30.0dB 27.0dB 28.5dB 25.5dB 27.0dB 24.0dB 25.5dB 22.5dB 24.0dB 21.0dB 22.5dB 19.5dB 21.0dB 18.0dB 19.5dB 16.5dB 18.0dB 15.0dB 16.5dB 13.5dB 15.0dB 12.0dB 13.5dB 10.5dB 12.0dB 9.0dB 10.5dB (Note 3) 7.5dB (Note 3) 5514f 2 LT5514 DC ELECTRICAL CHARACTERISTICS VCC = 5V, VCCO = 5V, ENA = ENB = 3V, TA = 25°C, unless otherwise noted. (Note 7) (Test circuits shown in Figures 9 and 10) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Normal Operating Conditions VCC Supply Voltage (Pins 2, 19) (Note 4) 4.75 5 5.25 V VCCO OUT+, OUT– Output Pin DC Common Mode Voltage OUT+, OUT– Connected to VOSUP via Choke Inductors or Resistors (Note 5) 3 5 6 V VOUT OUT+, OUT– Pin Instantaneous Voltage with Respect to GND Min/Max Limits Apply 2 8 V 1.5 V Shutdown DC Characteristics, ENA = ENB = 0.6V VIN(BIAS) IN+, IN– Bias Voltage Max Gain (Note 6) IIL(PGA) PGAO, PGA1, PGA2, PGA3 Input Current VIN = 0.6V 20 µA IIH(PGA) PGAO, PGA1, PGA2, PGA3 Input Current VIN = 5V 20 µA IOUT OUT+, OUT– Current All Gain Settings 20 µA ICC VCC Supply Current All Gain Settings (Note 4) 100 µA 0.6 V 20 µA 15 30 µA 1.15 1.3 44 Enable and PGA Inputs DC Characteristics VIL ENA, ENB and PGAx Input Low Voltage x = 0, 1, 2, 3 VIH ENA, ENB and PGAx Input High Voltage x = 0, 1, 2, 3 IIL(PGA) PGAO, PGA1, PGA2, PGA3 Input Current VIN = 0.6V IIH(PGA) PGAO, PGA1, PGA2, PGA3 Input Current VIN = 3V and 5V IIL(EN) ENA, ENB Input Current VIN = 0.6V 4 20 µA IIH(EN) ENA, ENB Input Current VIN = 3V VIN = 5V 18 38 100 µA µA 1.49 1.65 V 3 V Standard Mode DC Characteristics, ENA = ENB = 3V VIN(BIAS) IN+, IN– Bias Voltage Max Gain (Note 6) RIN Input Differential Resistance All Gain Settings (DC) gm Amplifier Transconductance Max Gain IOUT OUT+, OUT– Quiescent Current All Gain Settings, VOUT = 5V 1.34 Ω 108 0.3 33 40 S 47 mA µA IOUT(OFFSET) Output Current Mismatch All Gain Settings, IN+, IN– Open 200 ICC VCC1 + VCC2 Supply Current Max Gain (Note 4) Min Gain (Note 4) 64 68 75 80 mA mA ICC(TOTAL) Total Supply Current ICC + 2 • IOUT (Max Gain) 148 174 mA 1.48 1.65 V Low Power Mode DC Characteristics, ENA = O.6V, ENB = 3V or ENA = 3V, ENB = 0.6V VIN(BIAS) IN+, IN– Bias Voltage Max Gain (Note 6) RIN Input Differential Resistance All Gain Settings (DC) gm Amplifier Transconductance Max Gain IOUT OUT+, OUT– Quiescent Current All Gain Settings, VOUT = 5V 1.34 Ω 122 0.15 17 20 S 24 mA µA IOUT(OFFSET) Output Current Mismatch All Gain Settings, IN+, IN– Open 100 ICC VCC1 + VCC2 Supply Current Max Gain (Note 4) Min Gain (Note 4) 34 36 40 43 mA mA ICC(TOTAL) Total Supply Current ICC + 2 • IOUT (Max Gain) 76 91 mA 5514f 3 LT5514 AC ELECTRICAL CHARACTERISTICS (Standard Mode) VCC = 5V, VCCO = 5V, ENA = ENB = 3V, TA = 25°C, ROUT = 200Ω. Maximum gain specifications are with respect to differential inputs and differential outputs, unless otherwise noted. (Note 7) (Test circuits shown in Figures 9 and 10) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Dynamic Performance BW Large-Signal –3dB Bandwidth All Gain Settings (Note 8) ROUT = 100Ω ROUT = 200Ω; L1, L2 = 33nH (Figure 9) LF to 850 LF to 500 MHz MHz 21 dBm POUT(MAX) Clipping Limited Maximum Sinusoidal Output Power All Gain Settings, Single Tone, ROUT = 150Ω fIN = 100MHz (Note 10) gm Amplifier Transconductance Max Gain, fIN = 100MHz PGA1 = Low, fIN = 100MHz 0.30 0.21 S S S12 Reverse Isolation fIN = 100MHz (Note 9) fIN = 400MHz (Note 9) –92 –78 dB dB tr, tf Step Response Rise and Fall Time All Gain Settings, 10% to 90%, ROUT = 100Ω 500 ps Group Delay All Gain Settings, ROUT = 100Ω 800 ps Group Delay Variation 30MHz to 300MHz Frequency Range, ROUT = 100Ω ±50 ps PGA Settling Time 500 ns Enable/Disable Time 600 ns Distortion and Noise OIP3 Output Third Order Intercept Point for PGA0 = High (PGA1, PGA2, PGA3 Any State) POUT = 9dBm (Each Tone), 200kHz Tone Spacing fIN = 100MHz fIN = 200MHz +47.0 +40.5 dBm dBm Output Third Order Intercept Point for PGA0 = Low (PGA1, PGA2, PGA3 Any State) POUT = 9dBm (Each Tone), 200kHz Tone Spacing fIN = 100MHz fIN = 200MHz +42.0 +37.5 dBm dBm Second Harmonic Distortion POUT = 11dBm (Single Tone), fIN = 50MHz –82 dBc HD3 Third Harmonic Distortion POUT = 11dBm (Single Tone), fIN = 50MHz –72 dBc NFLOOR Output Noise Floor (PGAO, PGA2, PGA3 Any State) PGA1 = High, fIN = 100MHz PGA1 = Low, fIN = 100MHz –134 –136 dBm/Hz dBm/Hz NF Noise Figure Max Gain, fIN = 100MHz –3dB Step, fIN = 100MHz HD2 7.4 7.7 dB dB Amplifier Power Gain and Gain Step GMAX Maximum Gain fIN = 20MHz and 200MHz 33 dB GMIN Minimum Gain fIN = 20MHz and 200MHz 10.5 dB GSTEP Gain Step Size fIN = 20MHz and 200MHz Gain Step Accuracy fIN = 20MHz and 200MHz 1.05 1.5 1.95 dB ±0.1 dB Ω Amplifier I/O Impedance (Parallel Values Specified Differentially) RIN Input Resistance fIN = 100MHz 108 CIN Input Capacitance fIN = 100MHz 2.8 pF RO Output Resistance fIN = 100MHz 3.4 kΩ CO Output Capacitance fIN = 100MHz 1.9 pF 5514f 4 LT5514 AC ELECTRICAL CHARACTERISTICS (Low Power Mode) VCC = 5V, VCCO = 5V, ENA = 3V, ENB = 0.6V, TA = 25°C, ROUT = 200Ω. Maximum gain specifications are with respect to differential inputs and differential outputs, unless otherwise noted. (Note 7) (Test circuits shown in Figures 9 and 10) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Dynamic Performance BW Large-Signal –3dB Bandwidth All Gain Settings (Note 8), ROUT = 100Ω LF to 540 MHz 16 dBm POUT(MAX) Clipping Limited Maximum Sinusoidal Output Power All Gain Settings, Single Tone, fIN = 100MHz (Note 10) gm Amplifier Transconductance Max Gain, fIN = 100MHz 0.15 S S12 Reverse Isolation fIN = 100MHz (Note 9) –92 dB Output Third Order Intercept Point for PGA0 = High (PGA1, PGA2, PGA3 Any State) POUT = 4dBm (Each Tone), 200kHz Tone Spacing, fIN = 100MHz +40 dBm Output Third Order Intercept Point for PGA0 = Low (PGA1, PGA2, PGA3 Any State) POUT = 4dBm (Each Tone), 200kHz Tone Spacing, fIN = 100MHz +36 dBm Second Harmonic Distortion POUT = 5dBm (Single Tone), fIN = 50MHz –76 dBc HD3 Third Harmonic Distortion POUT = 5dBm (Single Tone), fIN = 50MHz –72 dBc NFLOOR Output Noise Floor (PGAO, PGA2, PGA3 Any State) PGA1 = High, fIN = 100MHz PGA1 = Low, fIN = 100MHz –138 –140 dBm/Hz dBm/Hz NF Noise Figure Max Gain Setting, fIN = 100MHz 8.6 dB 27 dB Distortion and Noise OIP3 HD2 Amplifier Power Gain and Gain Step GMAX Maximum Gain fIN = 20MHz and 200MHz GMIN Minimum Gain fIN = 20MHz and 200MHz GSTEP Gain Step Size fIN = 20MHz and 200MHz Gain Step Accuracy fIN = 20MHz and 200MHz ±0.1 dB 4.5 1.05 1.5 dB 1.95 dB Amplifier I/O Impedance RIN Input Resistance fIN = 100MHz, Parallel Values Specified Differentially 122 Ω CIN Input Capacitance fIN = 100MHz, Parallel Values Specified Differentially 2 pF RO Output Resistance fIN = 100MHz, Parallel Values Specified Differentially 5 kΩ CO Output Capacitance fIN = 100MHz, Parallel Values Specified Differentially 1.7 pF Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to ground. Note 3: Default state for open PGA inputs. Note 4: VCC1 and VCC2 (Pins 2 and 19) are internally connected. Note 5: External VOSUP is adjusted such that VCCO output pin common mode voltage is as specified when resistors are used. For choke inductors or transformer, VOSUP = VCCO = 5V typ. Note 6: Internally generated common mode input bias voltage requires capacitive or transformer coupling to the signal source. Note 7: Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Gain always refers to power gain. Input matching is assumed. PIN is the available input power. POUT is the power into the external load, ROUT, as seen by the LT5514 differential outputs. All dBm figures are with respect to 50Ω. Note 8: High frequency operation is limited by the RC time constants at the input and output ports. The low frequency (LF) roll-off is set by I/O interface choice. Note 9: Limited by package and board isolation. Note 10: See “Clipping Free Operation” in the Applications Information section. Refer to Figure 7. 5514f 5 LT5514 U W TYPICAL PERFOR A CE CHARACTERISTICS (Standard Mode) TA = 25°C, VCC = 5V, VCCO = 5V, ENA = ENB = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown in Figure 9) 36 36 30 33 33 27 30 30 24 27 27 21 18 15 12 POWER GAIN (dB) 33 9 24 21 18 15 12 21 18 15 12 9 9 6 6 6 3 3 0 0 0 100 FREQUENCY (MHz) 1000 100 FREQUENCY (MHz) 10 5514 G01 1000 0.8 33 30 27 Gain Error vs Attenuation at 100MHz, ROUT = 200Ω 0.8 COUT = OPEN COUT = 2.2pF COUT = 4.7pF COUT = 10pF COUT = 22pF 6 3 0.2 0 –0.2 10 100 FREQUENCY (MHz) –0.6 –0.6 1000 0 3 12 15 6 9 18 ATTENUATION STEP (dB) 5514 G04 –0.8 3 12 15 6 9 18 ATTENUATION STEP (dB) POWER GAIN (dB) 21 1544 G06 POUT vs PIN at 50MHz, Max Gain 25 25°C –40°C 85°C 20 ROUT = 200Ω ROUT = 100Ω 0 1544 G05 13 ROUT = 200Ω 30 21 Minimum Gain vs Frequency, ROUT = 100Ω and 200Ω 25°C –40°C 85°C 33 –0.2 –0.4 Maximum Gain vs Frequency, ROUT = 100Ω and 200Ω 36 0 –0.4 –0.8 0 0.2 10 15 POUT (dBm) 9 0.4 GAIN ERROR (dB) GAIN ERROR (dB) 18 15 25°C –40°C 85°C 0.6 0.4 21 1000 5514 G03 25°C –40°C 85°C 0.6 24 100 FREQUENCY (MHz) 10 Gain Error vs Attenuation at 25MHz, ROUT = 200Ω 36 12 COUT = OPEN COUT = 2.2pF COUT = 4.7pF COUT = 10pF COUT = 22pF 5514 G02 Frequency Response at 3dB Attenuation Step with COUT as Parameter, ROUT = 200Ω POWER GAIN (dB) 24 3 10 POWER GAIN (dB) Max Gain Frequency Response with COUT as Parameter, ROUT = 200Ω Frequency Response for All Gain Steps, ROUT = 200Ω POWER GAIN (dB) POWER GAIN (dB) Frequency Response for All Gain Steps, ROUT = 100Ω ROUT = 100Ω 10 5 7 STANDARD ROUT = 100Ω STANDARD ROUT = 200Ω LOW POWER ROUT = 200Ω 0 27 4 10 100 FREQUENCY (MHz) 1000 5514 G07 10 100 FREQUENCY (MHz) 1000 5514 G08 –5 –31 –28 –25 –22 –19 –16 –13 –10 PIN (dBm) –7 5514 G09 5514f 6 LT5514 U W TYPICAL PERFOR A CE CHARACTERISTICS (Standard Mode) TA = 25°C, VCC = 5V, VCCO = 5V, ENA = ENB = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown in Figure 9) 7.8 30.4 7.6 30.2 85°C 29.8 25°C 29.6 6.8 29.4 6.6 29.2 4.7 4.9 5.1 4.7 4.9 5.1 0 HD3 PGA0 = HIGH –40 –40 –45 –45 –50 –50 –55 –55 –60 –60 –65 –70 HD3 –75 HD2 –65 –75 HD5 –85 HD4 –95 –95 –90 –100 –100 18 21 –3 0 3 9 12 6 POUT (dBm) 15 5514 G12 21 18 –5 –2 1 7 10 4 POUT (dBm) HD4 13 30 FIGURE 10 TEST CIRCUIT 19 16 5514 G15 5514 G14 Output Noise Floor vs Attenuation Step, Freq = 100MHz, ROUT = 200Ω NF vs Attenuation Step at Freq = 100MHz Noise Figure vs Frequency 9.0 HD5 –90 –90 12 9 15 6 ATTENUATION STEP (dB) HD2 –80 –80 –85 21 HD3 –70 –87 3 18 Harmonic Distortion vs POUT at 50MHz, Max Gain, ROUT = 100Ω HD (dBc) HD (dBc) –78 –81 12 9 15 6 ATTENUATION STEP (dB) 5514 G12 Harmonic Distortion vs POUT at 50MHz, Max Gain, ROUT = 200Ω HD3 PGA0 = LOW 0 3 5514 G11 –72 HD (dBc) –90 5.5 5.3 5514 G10 HD2 HD2 VCC (V) Harmonic Distortion vs Attenuation Step at POUT = 7dBm, Freq = 50MHz, ROUT = 200Ω –84 –81 –87 29.0 4.5 5.5 5.3 HD3 PGA0 = HIGH –84 85°C VCC (V) –75 HD3 PGA0 = LOW –78 HD (dBc) 25°C 6.4 4.5 FIGURE 10 TEST CIRCUIT –75 –40°C 7.2 7.0 –72 30.0 –40°C GAIN (dB) GAIN (dB) 7.4 Harmonic Distortion vs Attenuation Step at POUT = 7dBm, Freq = 50MHz, ROUT = 200Ω Maximum Gain vs VCC at 120MHz, ROUT = 100Ω Minimum Gain vs VCC at 120MHz, ROUT = 100Ω –133 FIGURE 10 TEST CIRCUIT FIGURE 10 TEST CIRCUIT 27 8.5 7.5 18 15 12 MAX GAIN 7.0 NOISE FLOOR (dBm/Hz) 21 NF (dB) 8.0 NF (dB) –134 24 1.5dB ATTENUATION STEP (PGA0 = LOW) 9 3dB ATTENUATION STEP (PGA1 = LOW) 6.5 6 PGA1 = HIGH –135 –136 PGA1 = LOW –137 –138 3 6.0 0 50 100 150 200 250 300 350 400 FREQUENCY (MHz) 5514 G16 0 –139 0 3 15 6 9 12 18 ATTENUATION STEP (dB) 21 5514 G17 0 3 6 9 12 15 18 ATTENUATION STEP (dB) 21 5514 G18 5514f 7 LT5514 U W TYPICAL PERFOR A CE CHARACTERISTICS (Standard Mode) Two tones, 200kHz spacing, TA = 25°C, ENA = ENB = 5V, VCC = 5V, VCCO = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown in Figure 10) OIP3 vs Frequency at PIN = –23dBm Max Gain, ROUT = 200Ω 57 57 25°C –40°C 85°C 54 54 48 45 51 OIP3 (dBm) 51 OIP3 (dBm) OIP3 (dBm) 57 25°C –40°C 85°C 54 51 48 45 MAX GAIN 48 45 42 42 42 39 39 39 36 36 50 0 100 150 200 50 100 70 48 60 47 Total ICC vs Attenuation Step 160 155 85°C CURRENT (µA) 44 1.5dB ATTENUATION STEP (PGA0 = LOW) CURRENT (mA) 50 45 25°C 40 30 –40°C 20 0 3 12 15 6 9 18 ATTENUATION STEP (dB) 0 4.5 21 85°C 150 25°C 145 140 –40°C 135 10 42 200 150 5514 G21 ICC Shutdown Current vs VCC, ENA = ENB = 0.6V 3dB ATTENUATION STEP (PGA0 = HIGH) 100 5514 G20 49 41 50 0 FREQUENCY (MHz) 5514 G19 43 200 150 FREQUENCY (MHz) OIP3 vs Attenuation Step at Freq = 100MHz, PIN = –23dB, ROUT = 200Ω 46 1.5dB ATTENUATION STEP 36 0 FREQUENCY (MHz) OIP3 (dBm) OIP3 vs Frequency at PIN = –23dBm Max Gain and 1.5dB Attenuation Step, ROUT = 200Ω OIP3 vs Frequency at PIN = –23dBm Max Gain, ROUT = 100Ω 130 4.7 4.9 5.1 5.5 5.3 0 3 INPUT VCC (V) 1544 G22 6 9 12 15 18 ATTENUATION STEP (dB) 5514 G24 5514 G23 Single-Ended Output Current vs Attenuation Step 21 VIN(BIAS) vs Attenuation Step 41 1.60 VIN(BIAS) (V) CURRENT (mA) 1.55 40 85°C 25°C –40°C 1.50 25°C 39 1.45 –40°C 38 0 3 6 9 12 15 18 ATTENUATION STEP (dB) 21 5514 G25 1.40 85°C 0 3 6 9 12 15 18 ATTENUATION STEP (dB) 21 5514 G26 5514f 8 LT5514 U W TYPICAL PERFOR A CE CHARACTERISTICS (Standard Mode) TA = 25°C, VCC = 5V, VCCO = 5V, ENA = ENB = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. Test circuit shown in Figure 10 unless otherwise noted. Note 1: Subtract 0.75ns calibration delay from output plots to estimate the LT5514 group delay. Note 2: When specified, COUT is connected differentially across the LT5514 OUT+, OUT– output pins. Pulse Response vs COUT at Max Gain. Output Level is 2VP-P into 50Ω External Load 0pF INPUT 22pF TO GROUND EACH OUTPUT Pulse Response vs Output Level at Max Gain. Indicated Voltage Levels are into 50Ω External Load COUT 0pF 1pF 1.8pF 3.3pF 4.7pF 6.8pf 10pF 11pF 18pF Pulse Response vs Attenuation, Output Level is 4VP-P at Max Gain into 50Ω External Load COUT = 0.82pF 4VP-P 3VP-P 2VP-P MAX GAIN 1.5dB STEP 3dB STEP 6dB STEP 12dB STEP INPUT INPUTS RMATCH = 255Ω 2ns/DIV 2ns/DIV 5514 G27 Pulse Response vs Attenuation, Output Level is 2VP-P at Max Gain into 50Ω External Load RMATCH = 255Ω 1ns/DIV 5514 G28 5514 G29 Pulse Response vs Attenuation, Output Level is 2VP-P at Max Gain into 50Ω External Load RMATCH = 255Ω, COUT = 1.8pF MAX GAIN 1.5dB STEP 3dB STEP 6dB STEP 12dB STEP INPUT 1ns/DIV INPUT 1ns/DIV 5514 G30 Pulse Response vs Attenuation, LT5514 Levels are: VIN = 66mVP-P, VOUT = 2VP-P at Max Gain ROUT = 100Ω MAX GAIN 1.5dB STEP 3dB STEP 6dB STEP 12dB STEP 5514 G31 Pulse Response vs Attenuation, LT5514 Levels are: VIN = 66mVP-P, VOUT = 4VP-P at Max Gain ROUT = 200Ω MAX GAIN 1.5dB STEP 3dB STEP 6dB STEP 12dB STEP INPUT INPUT FIGURE 9 TEST CIRCUIT FIGURE 9 TEST CIRCUIT 1ns/DIV MAX GAIN 1.5dB STEP 3dB STEP 6dB STEP 12dB STEP 5514 G32 1ns/DIV 5514 G33 5514f 9 LT5514 U W TYPICAL PERFOR A CE CHARACTERISTICS (Low Power Mode) TA = 25°C, VCC = 5V, VCCO = 5V, ENA = 3V, ENB = 0.6V or ENA = 0.6V, ENB = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown in Figure 10) OIP3 vs Frequency at Pin = –23dBm, Max Gain and 1.5dB Attenuation Step, ROUT = 200Ω Harmonic Distortion vs POUT at 50MHz, Max Gain, ROUT = 200Ω Noise Figure vs Frequency –40 54 10.0 –45 51 –50 9.5 MAX GAIN 42 39 –65 HD3 –70 HD2 –75 –80 1.5dB ATTENUATION STEP 36 9.0 NF (dB) 45 HD(dBc) OIP3 (dBm) –60 8.5 HD5 –90 HD4 3dB ATTENUATION STEP (PGA1 = LOW) 7.5 –95 –100 0 100 50 7.0 –6 200 150 –3 FREQUENCY (MHz) 0 6 POUT (dBm) 3 9 0 15 12 50 100 150 200 250 300 350 400 FREQUENCY (MHz) 5514 G36 5514 G35 5514 G34 NF vs Attenuation Step at Freq = 100MHz Pulse Response vs Output Level at Max Gain. Indicated Voltage Levels are into 50Ω External Load Output Noise Floor vs Attenuation Step, Freq = 100MHz, ROUT = 200Ω –136 30 COUT = 0.82pF 27 –137 NOISE FLOOR (dBm/Hz) 24 21 NF (dB) MAX GAIN 8.0 –85 33 30 1.5dB ATTENUATION STEP (PGA0 = LOW) –55 48 18 15 12 9 6 2VP-P 1.5VP-P 1VP-P PGA1 = HIGH –138 INPUTS –139 PGA1 = LOW –140 –141 3 –142 0 3 15 6 9 12 18 ATTENUATION STEP (dB) 21 0 3 6 9 12 15 18 ATTENUATION STEP (dB) Single-Ended Output Current vs Attenuation Step Total ICC vs VCC 75 25°C CURRENT (mA) CURRENT (mA) 80 85°C 73 –40°C 70 5514 G39 VIN(BIAS) vs Attenuation Step 21.0 1.60 20.5 1.55 20.0 85°C 1.50 –40°C 1.45 85°C 25°C 25°C 19.5 –40°C 68 65 2ns/DIV 5514 G38 5514 G37 78 21 VIN(BIAS) (V) 0 0 3 6 9 12 15 18 ATTENUATION STEP (dB) 21 5514 G40 19.0 1.40 0 3 6 9 12 15 18 ATTENUATION STEP (dB) 21 5514 G41 0 3 6 9 12 15 18 ATTENUATION STEP (dB) 21 5514 G42 5514f 10 LT5514 U U U PI FU CTIO S ENA (Pin 1): Enable Pin for Amplifier A. When the input voltage is higher than 3V, amplifier A is turned on. When the input voltage is less than or equal to 0.6V, amplifier A is turned off. This pin is internally pulled to ground if not connected. Input is high when input voltage is greater than 3V. Input is low when input voltage is less than or equal to 0.6V. This pin is internally pulled to ground if not connected. PGA3 (Pin 12): Amplifier PGA Control Input Pin for 12dB Attenuation Step (see Programmable Gain table). Input is high when input voltage is greater than 3V. Input is low when input voltage is less than or equal to 0.6V. This pin is internally pulled to ground if not connected. VCC1 (Pin 2): Power Supply. This pin is internally connected to VCC2 (Pin 19). Decoupling capacitors (1000pF and 0.1µF for example) may be required in some applications. OUT+ (Pin 15): Positive Amplifier Output. A transformer with center tap tied to VCC or a choke inductor is recommended to source the DC quiescent current. GND (Pins 3, 4, 7, 8, 13, 14, 17, 18): Ground. IN+ (Pin 5): Positive Signal Input Pin with Internal DC Bias. OUT– (Pin 16): Negative Amplifier Output. A transformer with center tap tied to VCC or a choke inductor is recommended to source the DC quiescent current. IN– (Pin 6): Negative Signal Input Pin with Internal DC Bias. PGA0 (Pin 9): Amplifier PGA Control Input Pin for the 1.5dB Attenuation Step (see Programmable Gain table). Input is high when input voltage is greater than 3V. Input is low when input voltage is less than or equal to 0.6V. This pin is internally pulled to ground if not connected. VCC2 (Pin 19): Power Supply. This pin is internally connected to VCC1 (Pin 2). ENB (Pin 20): Enable Pin for Amplifier B. When the input voltage is higher than 3V, amplifier B is turned on. When the input voltage is less than or equal to 0.6V, amplifier B is turned off. This pin is internally pulled to ground if not connected. PGA1 (Pin 10): Amplifier PGA Control Input Pin for the 3dB Attenuation Step (see Programmable Gain table). Input is high when input voltage is greater than 3V. Input is low when input voltage is less than or equal to 0.6V. This pin is internally pulled to ground if not connected. Exposed Pad (Pin 21): Ground. This pin must be soldered to the printed circuit board ground plane for good heat transfer. PGA2 (Pin 11): Amplifier PGA Control Input Pin for the 6dB Attenuation Step (see Programmable Gain table). W BLOCK DIAGRA LT5514 5 6 IN+ ATTENUATOR IN– RIN 100Ω AMPLIFIER A OUT – OUT+ 16 15 AMPLIFIER B GAIN CONTROL LOGIC VOLTAGE REGULATOR AND BIAS GND (3, 4, 7, 8 13, 14, 17, 18) VCC1 2 VCC2 19 PGA3 12 ENABLE CONTROL PGA2 PGA1 11 10 PGA0 9 ENA ENB 20 1 21 5514 F01 Figure 1. Functional Block Diagram 5514f 11 LT5514 U W U U APPLICATIO S I FOR ATIO Circuit Operation The LT5514 is a high linearity amplifier with high impedance output (Figure 1). It consists of the following sections: • An input variable attenuator “gain-control” block with 100Ω input impedance • Two parallel, differential transconductance amplifiers, each with independent enable inputs • An internal bias block with internal voltage regulator • A gain control logic block The LT5514 amplifier provides amplification with very low distortion using a linearized open-loop architecture. In contrast with high linearity amplifiers employing negative feedback, the LT5514 offers: where: gm is the LT5514 transconductance = 0.3S in Standard mode (0.15S in Low Power mode). RIN is the LT5514 differential input impedance ≅ 108Ω in Standard mode (122Ω in Low Power mode). Input impedance matching is assumed. ROUT is the external differential output impedance as seen by the LT5514’s differential outputs. ROUT should be distinguished from the actual load impedance, RLOAD, which will typically be coupled to the LT5514 output by an impedance transformation network. The power gain as a function of ROUT is plotted in Figure␣ 2. The ideal curves are straight lines. The curved lines indicate the roll-off due to the finite (noninfinite) output resistance of the LT5514. • Stable operation for any practical load 45 • A capacitive output reactance (not inductive) that provides peaking free AC response to capacitive loads 40 35 The LT5514 is a transconductance amplifier and its operation can be understood conceptually as consisting of two steps: First, the input signal voltage is converted to an output current. The intermodulation distortion (in dBc) of the LT5514 output current is determined by the input signal level, and is almost independent of the output load conditions. Thus, the LT5514’s input IP3 is also nearly independent of the output load. Next, the external output load (ROUT) converts the output current to output voltage (or power). The LT5514’s voltage and power gain both increase with increasing ROUT. Accordingly, the output power and output IP3 also improve with increasing ROUT. The actual output linearity performance in the application will thus be set by the choice of output load, as well as by the output network. Maximum Gain Calculation The maximum power gain (with the 0dB attenuation step) is: GAIN (dB) 30 • Exceptional reverse isolation of –100dB at 50MHz and –78dB at 300MHz (package and board leakage limited) 25 20 15 STANDARD MODE LOW POWER MODE STD WITH RO LP WITH RO 10 5 0 20 100 1000 2000 ROUT (Ω) 5514 F02 Figure 2. Power Gain as a Function of ROUT The actual available output power (as well as power gain and OIP3) will be reduced by losses in the output interface, consisting of: • The insertion loss of the output impedance transformation network (for example the transformer insertion loss in Figure 6) • About –3dB loss if a matching resistor (RMATCH in Figure 6) is used to provide output load impedance back-matching (for example when driving transmission lines) GPWR(dB) = 10 • log(gm2 • RIN • ROUT) 5514f 12 LT5514 U W U U APPLICATIO S I FOR ATIO VOSUP Input Interface C3 For the lowest noise and highest linearity, the LT5514 should be driven with a differential input signal. Singleended drive will severely degrade linearity and noise performance. • Match the source impedance to the LT5514, RIN ≅ 108Ω • Provide well balanced differential input drive (capacitor C2 in Figure 4) • Minimize insertion loss to avoid degrading the noise figure (NF) RLOAD 50Ω C2 RLOAD 50Ω ROUT + LT5514 F05 Figure 5. Output Impedance-Matched and Capacitively Coupled to a Differential Load Input matching network design criteria are: • DC block the LT5514 internal bias voltage (see Input Bias Voltage section for DC coupling information) R2 51Ω C1 – RIN 100Ω IN– Example input matching networks are shown in Figures 3 and 4. R1 51Ω LT5514 IN+ Note: In Figure 5, (choke) inductors may be placed in parallel with or used to replace resistors R1 and R2, thus eliminating the DC voltage drop across these resistors. VOSUP IN+ IN– LT5514 – RIN 100Ω C1 RMATCH 255Ω (OPTIONAL) ROUT + RLOAD 50Ω T2 4:1 • • • LT5514 F06 R1 50Ω C1 IN VSRC R2 50Ω C2 LT5514 + Figure 6. Output Impedance-Matched and Transformer-Coupled to a Single-Ended Load – RIN 100Ω IN– + LT5514 F03 Figure 3. Input Capacitively-Coupled to a Differential Source RSRC 50Ω T1 1:2 • VSRC IN • • + IN– C2 0.33µF • Provide DC isolation between the LT5514 DC output voltage and RLOAD. • Provide a path for the output DC current from the output voltage source VOSUP. LT5514 – RIN 100Ω + Output network design criteria are: LT5514 F04 Figure 4. Input Transformer-Coupled to a Single-Ended Source Output Interface The output interface network provides an impedance transformation between the actual load impedance, RLOAD, and the LT5514 output loading, ROUT, chosen to maximize power or linearity, or to minimize output noise, or for some other criteria as explained in the following sections. Two examples of output matching networks are shown in Figures 5 and 6 (as implemented in the LT5514 demo boards). • Provide an impedance transformation, if required, between the load impedance, RLOAD, and the optimum ROUT loading. • Set the bandwidth of the output network. • Optional: Provide board output impedance matching using resistor RMATCH (when driving a transmission line). • Use high linearity passive parts to avoid introducing noninearity. Note that there is a noise penalty of up to 6dB when using power delivered by only one output in Figure 5. 5514f 13 LT5514 U W U U APPLICATIO S I FOR ATIO Clipping Free Operation The LT5514 is a class A amplifier. To avoid signal distortion, the user must ensure that the LT5514 outputs do not enter into current or voltage limiting. The following discussion applies to standard mode operation at maximum gain. To avoid current clipping, the output signal current should not exceed the DC quiescent current, IOUT = 40mA (typical). Correspondingly, the maximum input voltage, VIN(MAX), is IOUT/gm = 133mV (peak). In power terms, PIN(MAX) = –10.8dBm (assuming RIN = 108Ω). To avoid output voltage clipping (due to LT5514 output stage saturation or breakdown), the single-ended output voltage swing should stay within the specified limits; i.e., 2V ≤ VOUT ≤ 8V. For a DC output bias of 5V, the maximum single ended swing will be 3Vpeak and the maximum differential swing will be 6Vpeak. The simultaneous onset of both current and voltage limiting occurs when ROUT = 6Vpeak/40mA =150Ω (typ) for a maximum POUT = 20.8dBm. This calculation applies for a sinusoidal signal. For nonsinusoidal signals, use the appropriate crest factor to calculate the actual maximum power that avoids output clipping. For nonoptimal ROUT values, the maximum available output power will be lower and can be calculated (considering current limiting for ROUT < 150Ω, and voltage limiting for ROUT > 150Ω). The result of this calculation is shown in Figure 7. The LT5514 input should not be overdriven (PIN > –10dBm). The consequences of overdrive are reduced 25 VCC = VCCO = 5V CURRENT LIMIT POUT(MAX) (dBm) 20 VOLTAGE LIMIT 15 10 5 STANDARD MODE LOW POWER MODE 0 20 100 1000 2000 ROUT (Ω) 5514 F07 Figure 7. Maximum Output Power as a Function of ROUT bandwidth and, when the frequency is greater than 50MHz, reduced output power. Input Bias Voltage The LT5514 IN+, IN– signal inputs are internally biased to 1.48V common mode when enabled, and to 1.26V in shutdown mode. These inputs are typically coupled by means of a capacitor or a transformer to a signal source, and impedance matching is assumed. In shutdown mode, the internal bias can handle up to 1µA leakage on the input coupling capacitors. This reduces the turn-on delay due to the input coupling RC time constant when exiting shutdown mode. If DC coupling to the input is required, the external common mode bias should track the LT5514’s internal common mode level. The DC current from the LT5514 inputs should not exceed IIN(SINK) = –400µA and IIN(SOURCE) = 800µA in Standard mode and half of these values in Low Power mode. Stability Considerations The LT5514’s open-loop architecture allows it to drive any practical load. Note that LT5514 gain is proportional to the load impedance, and may exceed the reverse isolation at frequencies above 1GHz if the LT5514’s outputs are left unloaded, with instability as the undesirable consequence. In such cases, placing a resistive differential load (e.g., 2k) or a small capacitor at the LT5514 outputs can be used to limit the maximum gain. The LT5514 has about 30GHz gain-bandwidth product. Hence, attention must be paid to the printed circuit board layout to avoid output pin to input pin signal coupling (the evaluation board layout is a good example). Due to the LT5514’s internal power supply regulator, external supply decoupling capacitors typically are not required. Likewise, decoupling capacitors on the LT5514 control inputs typically are not needed. Note, however, that the Exposed Pad on the LT5514 package must be soldered to a good ground plane on the PCB. PGA Function, Linearity and NF As described in the Circuit Operation section, the LT5514 consists of a variable (step) attenuator followed by a high 5514f 14 LT5514 U W U U APPLICATIO S I FOR ATIO gain output amplifier. The overall gain of the LT5514 is digitally controlled by means of four gain control pins with internal pull-down. Minimum gain is programmed when the gain control pins are set low or left floating. In shutdown mode, these PGA inputs draw <10µA leakage current, regardless of the applied voltage. The 6dB and 12dB attenuation steps (PGA2 and PGA3) are implemented by switching the amplifier inputs to an input attenuator tap. The 3dB attenuation step (PGA1) changes the amplifier transconductance. The output IP3 is approximately independent of the PGA1, PGA2 and PGA3 gain settings. However, the 1.5dB attenuation step utilizes a current steering technique that disables the internal linearity compensation circuit, and the OIP3 can be reduced by as much as 6dB when PGA0 is low. Therefore, to achieve the LT5514’s highest linearity performance, the PGA0 pin should be set high. The LT5514 noise figure is 7.3dB in the maximum gain state. For the –3dB attenuation setting, the NF is 7.6dB. The noise figure increases in direct proportion to the amount of programmed gain reduction for the 1.5dB, 6dB and 12dB steps. values. A solution is outlined in the Bandpass Applications section. The LT5514 linearity degrades when common mode signal is present. The input transformer center tap should be decoupled to ground to provide a balanced input differential signal and to avoid linearity degradation for high attenuation steps. When the signal frequency is lower than 50MHz, and there is significant common mode signal, then high attenuation settings may result in degraded linearity. At signal frequencies below 100MHz, the LT5514’s internal linearity compensation circuitry may provide “sweet spots” with very high OIP3, in excess of +60dBm. This almost perfect distortion correction cannot be sustained over the full operating temperature range and with variations of the LT5514 output load (complex impedance ZOUT). Users are advised to rely on data shown in the Typical Performance Characteristics curves to estimate the dependable linearity performance. Wideband Applications The output noise floor is proportional to the output load impedance, ROUT. It is almost constant for PGA1 = high and for any PGA0, PGA2, PGA3 state. When PGA1 = low, the output noise floor is 2.7dB lower (see Typical Performance Characteristics). At low frequencies, the value of the decoupling capacitors, choke inductors and choice of transformer will set the minimum frequency of operation. Output DC coupling is possible, but this typically reduces the LT5514’s output DC bias voltage, and thus the output swing and available power. Other Linearity Considerations At high frequencies, the output RC time constants set an upper limit to the maximum frequency of operation in the case of the wideband output networks presented so far. For example the LT5514 output capacitance, COUT = 1.9pF, and a pure resistive load, ROUT = 200Ω, will set the –3dB bandwidth to about 400MHz. In an actual application, the RLOAD • CLOAD product may be even more restrictive. The use of wideband output networks will not only limit the bandwidth, but will also degrade linearity because part of the available power is wasted driving the capacitive load. LT5514 linearity is a strong function of signal frequency. OIP3 decreases about 13dB for every octave of frequency increase above 100MHz. As noted in the Circuit Operation section, at any given frequency and input level, the LT5514 provides a current output with fairly constant intermodulation distortion figure in dBc, regardless of the output load value. For higher ROUT values, more gain and output power is available, and better OIP3 figures can be achieved. However, high ROUT values are not easily implemented in practice, limited by the availability of high ratio output impedance transformation networks. Linearity can also be limited by the output RC time constant (bandwidth limitations), particularly for high ROUT The LT5514’s output reactance is capacitive. Therefore improved AC response is possible by using external series output inductors. When driving purely resistive loads, an inductor in series with the LT5514 output may help to achieve maximally flat AC response as exemplified in the characterization setup schematic (Figure 9). 5514f 15 LT5514 U W U U APPLICATIO S I FOR ATIO For example, for ROUT = 200Ω, L1, L2 = 33nH results in 500MHz bandwidth. The LC network is a bandpass filter, a useful feature in many applications. The series inductor can extend the application bandwidth, but it provides no improvement in linearity performance. A variety of bandpass matching network configurations are conceivable, depending on the requirements of the particular application. The design of these networks is facilitated by the fact that the LT5514 outputs are not destabilized by reactive loading. Series inductance may also produce peaking in the AC response. This can be the case when (high Q) choke inductors are used in an output interface such as in Figure␣ 5, and the PCB trace (connection) to the load is too long. Since the LT5514’s output impedance is relatively high, the PCB trace acts as a series inductor. The most direct solution is to shorten the connection lines by placing the driver closer to the load. Another solution to flatten the AC response is to place resistance close to the LT5514 outputs. In this way the connection line behaves more like a terminated transmission line, and the AC peaking due to the capacitive load can be removed. Bandpass Applications For narrow band IF applications, the LT5514’s output capacitance and the application load capacitance can be incorporated as part of an LC impedance transformation network, giving improved linearity performance for signal frequencies greater than 100MHz. Figure 8 is an example of such a network. The network consists of two parallel resonant LC tank circuits critically coupled by capacitors C1 and C2. The ROUT to RLOAD transformation ratio in this particular implementation is 2. The choice of impedance transformation ratio is more flexible than in the wideband case. ENA VSRC TC2-1T In some applications the maximum output noise floor is specified. The LT5514 output noise floor is elevated above the available noise power (–174dBm/Hz into 50Ω) by the NF + Gain. Consequently, reduction of the LT5514’s power gain is the only way to reduce the output noise floor. In fixed gain applications, the LT5514 can be set to 3dB attenuation relative to maximum gain. As shown in the Typical Performance Characteristics, this gives a 2.8dB reduction in the output noise floor with no loss of linearity. In general, the output noise floor can be reduced by decreasing ROUT (and hence power gain), at the cost of reduced OIP3. In some situations, it may be feasible to use two LT5514 parts in parallel. In this case, the effective gm doubles, NOTE: C3 + CLOAD = 12pF C4 + CLOAD = 12pF L5 56nH C8 0.1µF IN+ 100 RSRC 50Ω Low Output Noise Floor Applications ENB VCC T1 1:2 Note that these LC networks may distort the output signal if their amplitude and phase response exhibit nonlinear behavior. For example, if resistors R1 and R2 in Figure 5 are replaced with LC resonant tank circuits, then severe OIP3 degradation may occur (e.g., 4dB to 6dB at 200MHz). C9 0.33µF PGA0 PGA1 PGA2 PGA3 L3 56nH C3 LT5514 – DUT IN– L6 C1 56nH 12pF VOSUP C7 0.1µF + ROUT 200Ω C6 2.2pF C2 12pF C5 5.6pF L4 56nH RLOAD 100Ω C4 GAIN = 33dB OIP3 (LOAD) = +41dBm UP TO 9dBm PER TONE RLOAD 50Ω CLOAD RLOAD 50Ω CLOAD 1dB BANDWIDTH: fL = 130MHz fU = 220MHz 5514 F08 Figure 8. Bandpass Output Transformation Network Example 5514f 16 LT5514 U W U U APPLICATIO S I FOR ATIO allowing all impedances to be scaled downward by a factor of two. The NF and power gain remain the same in this case, but the OIP3 increases by 3dB. Then, with a further reduction of ROUT by a factor of two, the gain and output noise floor decrease by 3dB, while yielding the same linearity as for one part. As an added benefit, two LT5514 parts in parallel can drive an ROUT reduced by a factor of four, thus relaxing or eliminating the need in some cases for an output impedance transformation network. refers to circuit operation with only a single block enabled. An amplifier in Low Power mode will have the same basic characteristics as in Standard mode (both gain blocks enabled), except that the gm decreases from 0.3S to 0.15S, and the maximum output current is halved. In Low Power mode, the standard LT5514 evaluation board will produce about 6dB less gain, (because the LT5514’s gm is reduced, while RIN and ROUT are the same) and 6dB lower OIP3. LT5514 Characterization Low Power Mode The LT5514’s typical performance data are based on the test circuits shown in Figures 9 and 10. Figure 9 does not necessarily reflect the use of the LT5514 in an actual application. (For that, see the Application Boards section.) As described in the Circuit Operation section, the LT5514 consists of two parallel gain blocks. These blocks are independently enabled or disabled. “Low Power mode” ENA VCC R9 35.7Ω C1 0.33µF C7 47nF T1 1:1 RSRC 50Ω VSRC R10 35.7Ω C2 0.1µF IN+ R8 35.7Ω LT5514 IN– L1 (OPT) R3 37.4Ω L2 (OPT) R4 37.4Ω ROUT + R5 51k R6 51k VOSUP C3 4.7µF C5 47nF T1 1:1 C6 47nF RLOAD 50Ω COUT (OPT) ETC-11-13 ROUT R3, R4 ATT 100Ω 37.4Ω 9dB 200Ω 87.4Ω 12dB VCCO MONITOR PGA0 PGA1 PGA2 PGA3 C4 0.1µF R1 25Ω – DUT ATT = 7.7dB ETC-11-13 R1 25Ω COUT (OPT) R7 35.7Ω C8 47nF ENB 5514 F09 Figure 9. Characterization Board (Simplified Schematic) VCC C2 0.1µF IF IN T1 1:2 J1 0 C1 0.47µF TC2-1T TRANSFORMER DEMO BOARD ENA 1 2 3 4 5 6 7 8 9 10 PGA0 PGA1 ENB ENA ENB VCC1 VCC2 GND GND LT5514 GND GND IN+ OUT– IN– OUT+ GND GND GND GND PGA0 PGA3 PGA1 PGA2 20 19 18 17 16 15 14 13 12 11 VOSUP C4 0.1µF C3 4.7µF IF OUT T2 4:1 ROUT 100Ω • • RMATCH 255Ω • TC4-1W RLOAD 50Ω J2 0 PGA2 PGA3 5514 F10 Figure 10. Output Transformer Application Board (Simplified Schematic) 5514f 17 LT5514 U W U U APPLICATIO S I FOR ATIO Rather, it represents a compromise that most accurately measures the actual operation of the part by itself, undistorted by the artifacts of the impedance transformation network, or by external bandwidth limiting factors. Balun transformers are used to interface with single-ended test equipment. Input and output resistive attenuators (not shown) provide broadband I/O impedance control. The L1, L2 inductors are selected for maximally flat AC output response. COUT (normally open) shows the placement of capacitive loading when this is specified as a characterization variable. The VCCO monitor pin allows setting the output DC level (5V typical) by adjusting voltage VOSUP. in that case, T1 should be changed to a 1:1 center-tap transformer to preserve 50Ω input matching. The demo board is shipped with optional output back-matching resistor RMATCH = 255Ω. This results in a net output load, ROUT = 100Ω, presented to the LT5514. The Output Transformer Application Board (Figure 10) is one example of an output impedance transformation (T2 transformer). For the Typical Performance Characteristics curves, all linearity tests are performed on this board. By removing RMATCH, the performance with ROUT = 200Ω can be evaluated (provided the lack of impedance back-matching is suitably remedied). Measured OIP3 for both cases, ROUT = 100Ω and 200Ω, is shown in Figure 12. Application (Demo) Boards 58 The LT5514 demo boards are provided in the versions shown in Figure 10 (with output transformer) and Figure␣ 11 (without output transformer). All I/O signal ports are matched to 50Ω. Moreover, 1k resistors (not shown) connect all six control pins (ENA, ENB, PGA0, PGA1, PGA2, PGA3) to VCC, such that the LT5514 is shipped in maximum gain state and with both amplifier blocks enabled (Standard mode). OIP3 (dBm) 52 C2 0.1µF IF IN T1 1:2 J1 0 TC2-1T DIFFERENTIAL OUTPUT RESISTIVE DEMO BOARD C1 0.47µF ENA 49 46 43 40 37 The gain setting can be changed by connecting the control pins to ground. Test points (TP1, TP2, TP3) are provided to monitor the input and output DC bias voltage. Jumper J1 can be removed when differential input is desired, but VCC DUT RMATCH = 255Ω BOARD RMATCH = 255Ω DUT RMATCH = OPEN BOARD RMATCH = OPEN 55 34 0 100 50 200 150 FREQUENCY (MHz) 5514 F12 Figure 12. Typical OIP3 for Transformer Board ENB VOSUP 1 2 3 4 5 6 7 8 9 10 PGA0 PGA1 ENA ENB VCC1 VCC2 GND GND LT5514 GND GND IN+ OUT– IN– OUT+ GND GND GND GND PGA0 PGA3 PGA1 PGA2 20 19 18 17 16 15 14 13 12 11 R1 50Ω ROUT 50Ω R2 50Ω C4 0.1µF C5 47nF C6 47nF C3 4.7µF IF OUT RLOAD 100Ω J2 0PEN PGA2 PGA3 5514 F11 Figure 11. Wideband Differential Output Application Board (Simplified Schematic) 5514f 18 LT5514 U W U U APPLICATIO S I FOR ATIO At high frequency, the difference between the top and bottom curves in Figure 12 is simply power loss. Starting from the LT5514 intrinsic performance at ROUT = 200Ω (top curve), the next lower curve takes into account the transformer insertion loss. The next curve below this shows the LT5514 OIP3 with ROUT = 100Ω. The bottom curve in the plot includes the effects of transformer insertion loss, with ROUT = 100Ω, and the additional effect of loss due to RMATCH. The transformer board can provide a differential output when Jumper J2 is removed. The Wideband Differential Output Application Board (Figure 11) is an example of direct coupling (no transformer) to the load, and has wider output bandwidth. This board gives direct access to the LT5514’s output pins, and was used for stability tests. Higher VOSUP (7V) is required to compensate for the DC voltage drop on R1 and R2. Use TP2, TP3 to monitor the actual LT5514 output bias voltage. By replacing R1 and R2 with inductors, this board can operate with a 5V supply. However, this may limit the minimum signal frequency. For example, an 820nH choke inductor will limit the lowest signal frequency to 40MHz. U PACKAGE DESCRIPTIO FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation CB 6.40 – 6.60* (.252 – .260) 3.86 (.152) 3.86 (.152) 20 1918 17 16 15 14 13 12 11 6.60 ±0.10 2.74 (.108) 4.50 ±0.10 6.40 2.74 (.252) (.108) BSC SEE NOTE 4 0.45 ±0.05 1.05 ±0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.09 – 0.20 (.0035 – .0079) 0.25 REF 0.50 – 0.75 (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 1.20 (.047) MAX 0° – 8° 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE20 (CB) TSSOP 0204 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 5514f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LT5514 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT5511 High Linearity Upconverting Mixer RF Output to 3GHz, 17dBm IIP3, Integrated LO Buffer LT5512 DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer LT5515 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator 20dBm IIP3, Integrated LO Quadrature Generator LT5516 0.8GHz to 1.5GHz Direct Conversion Quadrature Demodulator 21.5dBm IIP3, Integrated LO Quadrature Generator LT5517 40MHz to 900MHz Quadrature Demodulator 21dBm IIP3, Integrated LO Quadrature Generator LT5519 0.7GHz to 1.4GHz High Linearity Upconverting Mixer 17.1dBm IIP3 at 1GHz, Integrated RF Output Transformer with 50Ω Matching, Single-Ended LO and RF Ports Operation LT5520 1.3GHz to 2.3GHz High Linearity Upconverting Mixer 15.9dBm IIP3 at 1.9GHz, Integrated RF Output Transformer with 50Ω Matching, Single-Ended LO and RF Ports Operation LT5522 600MHz to 2.7GHz High Signal Level Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50Ω Single-Ended RF and LO Ports Infrastructure RF Power Detectors LT5504 800MHz to 2.7GHz RF Measuring Receiver 80dB Dynamic Range, Temperature Compensated, 2.7V to 5.25V Supply LTC®5505 RF Power Detectors with >40dB Dynamic Range 300MHz to 3GHz, Temperature Compensated, 2.7V to 6V Supply LTC5507 100kHz to 1000MHz RF Power Detector 100kHz to 1GHz, Temperature Compensated, 2.7V to 6V Supply LTC5508 300MHz to 7GHz RF Power Detector 44dB Dynamic Range, Temperature Compensated, SC70 Package LTC5509 300MHz to 3GHz RF Power Detector 36dB Dynamic Range, Low Power Consumption, SC70 Package LTC5530 300MHz to 7GHz Precision RF Power Detector Precision VOUT Offset Control, Shutdown, Adjustable Gain LTC5531 300MHz to 7GHz Precision RF Power Detector Precision VOUT Offset Control, Shutdown, Adjustable Offset LTC5532 300MHz to 7GHz Precision RF Power Detector Precision VOUT Offset Control, Adjustable Gain and Offset Low Voltage RF Building Blocks LT5500 1.8GHz to 2.7GHz Receiver Front End 1.8V to 5.25V Supply, Dual-Gain LNA, Mixer, LO Buffer LT5502 400MHz Quadrature IF Demodulator with RSSI 1.8V to 5.25V Supply, 70MHz to 400MHz IF, 84dB Limiting Gain, 90dB RSSI Range LT5503 1.2GHz to 2.7GHz Direct IQ Modulator and Upconverting Mixer 1.8V to 5.25V Supply, Four-Step RF Power Control, 120MHz Modulation Bandwidth LT5506 500MHz Quadrature IF Demodulator with VGA 1.8V to 5.25V Supply, 40MHz to 500MHz IF, –4dB to 57dB Linear Power Gain, 8.8MHz Baseband Bandwidth LT5546 500MHz Ouadrature IF Demodulator with VGA and 17MHz Baseband Bandwidth 17MHz Baseband Bandwidth, 40MHz to 500MHz IF, 1.8V to 5.25V Supply, –7dB to 56dB Linear Power Gain 5514f 20 Linear Technology Corporation LT/TP 0504 1K • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2004