4 Ω RON, 4-/8-Channel ±15 V/+12 V/±5 V iCMOS Multiplexers ADG1408-EP/ADG1409-EP FEATURES FUNCTIONAL BLOCK DIAGRAM 4.7 Ω maximum on resistance @ 25°C 0.5 Ω on resistance flatness Up to 190 mA continuous current Fully specified at ±15 V/+12 V/±5 V 3 V logic-compatible inputs Rail-to-rail operation Break-before-make switching action 16-lead TSSOP ADG1409-EP ADG1408-EP S1A S1 DA S4A D S1B DB S4B S8 1-OF-8 DECODER Supports defense and aerospace applications (AQEC standard) Military temperature range: −55°C to +125°C Controlled manufacturing baseline One assembly and test site One fabrication site Enhanced product change notification Qualification data available on request 1-OF-4 DECODER A0 A1 A2 EN A0 A1 EN 09248-001 ENHANCED PRODUCT FEATURES Figure 1. GENERAL DESCRIPTION The ADG1408-EP/ADG1409-EP are monolithic iCMOS® analog multiplexers comprising eight single channels and four differential channels, respectively. The ADG1408-EP switches one of eight inputs to a common output, as determined by the 3-bit binary address lines, A0, A1, and A2. The ADG1409-EP switches one of four differential inputs to a common differential output, as determined by the 2-bit binary address lines, A0 and A1. An EN input on both devices is used to enable or disable the device. When disabled, all channels are switched off. The ultralow on resistance and on resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications where low distortion is critical. iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments. The iCMOS (industrial CMOS) modular manufacturing process combines high voltage CMOS (complementary metal-oxide semiconductor) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no other generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. PRODUCT HIGHLIGHTS Full details about this enhanced product are available in the ADG1408/ADG1409 data sheet, which should be consulted in conjunction with this data sheet. 1. 2. 3. 4. 4 Ω on resistance 0.5 Ω on resistance flatness 3 V logic-compatible digital input, VINH = 2.0 V, VINL = 0.8 V 16-lead TSSOP package Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. ADG1408-EP/ADG1409-EP TABLE OF CONTENTS Features .............................................................................................. 1 5 V Dual Supply .............................................................................7 Enhanced Product Features ............................................................ 1 Continuous Current per Channel, S or D ..................................8 Functional Block Diagram .............................................................. 1 Absolute Maximum Ratings ............................................................9 General Description ......................................................................... 1 ESD Caution...................................................................................9 Product Highlights ........................................................................... 1 Pin Configurations and Function Descriptions ......................... 10 Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 12 Specifications..................................................................................... 3 Test Circuits..................................................................................... 14 15 V Dual Supply .......................................................................... 3 Outline Dimensions ....................................................................... 16 12 V Single Supply ........................................................................ 5 Ordering Guide .......................................................................... 16 REVISION HISTORY 3/11—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADG1408-EP/ADG1409-EP SPECIFICATIONS 15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (ΔRON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current +25°C −55°C to +125°C VSS to VDD 4 4.7 0.2 0.78 0.5 0.72 ±0.04 ±0.2 ±0.04 ±0.45 ±0.1 ±1.5 6.7 1.1 0.92 ±5 ±30 ±30 2.0 0.8 ±0.005 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION Break-Before-Make Time Delay, tBBM 4 140 170 50 240 19 tON (EN) tOFF (EN) Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion, THD + N −3 dB Bandwidth ADG1408-EP ADG1409-EP Insertion Loss CS (Off ) CD (Off ) ADG1408-EP ADG1409-EP CD, CS (On) ADG1408-EP ADG1409-EP 100 120 100 120 −50 −70 −70 0.025 165 170 Unit V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max µA typ µA max pF typ ns typ ns max ns typ ns min ns typ ns max ns typ ns max pC typ dB typ dB typ % typ Test Conditions/Comments VS = ±10 V, IS = −10 mA; see Figure 12 VDD = +13.5 V, VSS = −13.5 V VS = ±10 V, IS = −10 mA VS = ±10 V, IS = −10 mA VDD = +16.5 V, VSS = −16.5 V VS = ±10 V, VD = ∓10 V; see Figure 13 VS = ±10 V, VD = ∓10 V; see Figure 13 VS = VD = ±10 V; see Figure 14 VIN = VGND or VDD RL = 100 Ω, CL = 35 pF VS = 10 V, see Figure 15 RL = 100 Ω, CL = 35 pF VS1 = VS2 = 10 V; see Figure 16 RL = 100 Ω, CL = 35 pF VS = 10 V; see Figure 17 RL = 100 Ω, CL = 35 pF VS = 10 V; see Figure 17 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 18 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 19 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 20 RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz; see Figure 22 RL = 50 Ω, CL = 5 pF; see Figure 21 60 115 0.24 14 MHz typ MHz typ dB typ pF typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 21 f = 1 MHz 80 40 pF typ pF typ f = 1 MHz f = 1 MHz 135 90 pF typ pF typ f = 1 MHz f = 1 MHz Rev. 0 | Page 3 of 16 ADG1408-EP/ADG1409-EP Parameter POWER REQUIREMENTS IDD +25°C −55°C to +125°C 0.002 1 220 420 ISS 0.002 VDD/VSS 1 1 ±4.5/±16.5 Unit µA typ µA max µA typ µA max µA typ µA max V min/max Guaranteed by design, not subject to production test. Rev. 0 | Page 4 of 16 Test Conditions/Comments VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 0 V, 5 V or VDD ADG1408-EP/ADG1409-EP 12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (ΔRON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current +25°C −55°C to +125°C 0 to VDD 6 8 0.2 0.82 1.5 2.5 ±0.04 ±0.2 ±0.04 ±0.45 ±0.06 ±0.44 11.2 1.1 2.8 ±5 ±37 ±32 2.0 0.8 ±0.005 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 Transition Time, tTRANSITION Break-Before-Make Time Delay, tBBM 5 200 260 90 380 40 tON (EN) tOFF (EN) Charge Injection Off Isolation Channel-to-Channel Crosstalk −3 dB Bandwidth ADG1408-EP ADG1409-EP Insertion Loss CS (Off ) CD (Off ) ADG1408-EP ADG1409-EP CD, CS (On) ADG1408-EP ADG1409-EP 160 210 115 145 −12 −70 −70 285 200 Unit V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max µA typ µA max pF typ ns typ ns max ns typ ns min ns typ ns max ns typ ns max pC typ dB typ dB typ Test Conditions/Comments VS = 0 V to 10 V, IS = −10 mA; see Figure 12 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = −10 mA VS = 0 V to 10 V, IS = −10 mA VDD = 13.2 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 13 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 13 VS = VD = 1 V or 10 V; see Figure 14 VIN = VGND or VDD RL = 100 Ω, CL = 35 pF VS = 8 V; see Figure 15 RL = 100 Ω, CL = 35 pF VS1 = VS2 = 8 V; see Figure 16 RL = 100 Ω, CL = 35 pF VS = 8 V; see Figure 17 RL = 100 Ω, CL = 35 pF VS = 8 V; see Figure 17 VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 18 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 19 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 20 RL = 50 Ω, CL = 5 pF; see Figure 21 36 72 0.5 25 MHz typ MHz typ dB typ pF typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 21 f = 1 MHz 165 80 pF typ pF typ f = 1 MHz f = 1 MHz 200 120 pF typ pF typ f = 1 MHz f = 1 MHz Rev. 0 | Page 5 of 16 ADG1408-EP/ADG1409-EP Parameter POWER REQUIREMENTS IDD +25°C −55°C to +125°C 0.002 1 220 VDD 1 420 5/16.5 Unit µA typ µA max µA typ µA max V min/max Guaranteed by design, not subject to production test. Rev. 0 | Page 6 of 16 Test Conditions/Comments VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 V VSS = 0 V, GND = 0 V ADG1408-EP/ADG1409-EP 5 V DUAL SUPPLY VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (ΔRON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current +25°C −55°C to +125°C VSS to VDD 7 9 0.3 0.78 1.5 2.5 ±0.02 ±0.2 ±0.02 ±0.45 ±0.04 ±0.3 12 1.1 3 ±5 ±20 ±22 2.0 0.8 ±0.005 Break-Before-Make Time Delay, tBBM 5 330 440 100 550 45 tON (EN) tOFF (EN) Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion, THD + N −3 dB Bandwidth ADG1408-EP ADG1409-EP Insertion Loss CS (Off ) CD (Off ) ADG1408-EP ADG1409-EP CD, CS (On) ADG1408-EP ADG1409-EP 245 330 215 285 –10 –70 –70 0.06 440 370 V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 Transition Time, tTRANSITION Unit V min V max µA typ µA max pF typ ns typ ns max ns typ ns min ns typ ns max ns typ ns max pC typ dB typ dB typ % typ Test Conditions/Comments VS = ±4.5 V, IS = −10 mA; see Figure 12 VDD = +4.5 V, VSS = −4.5 V VS = ±4.5 V, IS = −10 mA VS = ±4.5 V; IS = −10 mA VDD = +5.5 V, VSS = −5.5 V VS = ±4.5 V, VD = ∓4.5 V; see Figure 13 VS = ±4.5 V, VD = ∓4.5 V; see Figure 13 VS = VD = ±4.5 V; see Figure 14 VIN = VGND or VDD RL = 100 Ω, CL = 35 pF VS = 5 V; see Figure 15 RL = 100 Ω, CL = 35 pF VS1 = VS2 = 5 V; see Figure 16 RL = 100 Ω, CL = 35 pF VS = 5 V; see Figure 17 RL = 100 Ω, CL = 35 pF VS = 5 V; see Figure 17 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 18 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 19 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 20 RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz; see Figure 22 RL = 50 Ω, CL = 5 pF; see Figure 21 40 80 0.5 20 MHz typ MHz typ dB typ pF typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 21 f = 1 MHz 130 65 pF typ pF typ f = 1 MHz f = 1 MHz 180 120 pF typ pF typ f = 1 MHz f = 1 MHz Rev. 0 | Page 7 of 16 ADG1408-EP/ADG1409-EP Parameter POWER REQUIREMENTS IDD −55°C to +125°C +25°C 0.001 1 ISS 0.001 1 ±4.5/±16.5 VDD/VSS 1 Unit µA typ µA max µA typ µA max V min/max Test Conditions/Comments VDD = +5.5 V, VSS = −5.5 V Digital inputs = 0 V or VDD Digital inputs = 0 V, 5 V or VDD Guaranteed by design, not subject to production test. CONTINUOUS CURRENT PER CHANNEL, S OR D Table 4. Parameter CONTINUOUS CURRENT, S or D1 15 V Dual Supply ADG1408-EP ADG1409-EP 12 V Single Supply ADG1408-EP ADG1409-EP 5 V Dual Supply ADG1408-EP ADG1409-EP 1 25°C 85°C 125°C Unit 190 140 105 85 50 45 mA max mA max 160 120 95 75 50 40 mA max mA max 155 115 90 70 45 40 mA max mA max Test Conditions/Comments VDD = +13.5 V, VSS = −13.5 V VDD = 10.8 V, VSS = 0 V VDD = +4.5 V, VSS = −4.5 V Guaranteed by design, not subject to production test. Rev. 0 | Page 8 of 16 ADG1408-EP/ADG1409-EP ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs, Digital Inputs 1 Continuous Current, S or D Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle Maximum) Operating Temperature Range Storage Temperature Range Junction Temperature θJA θJC Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) 1 Rating 35 V −0.3 V to +25 V +0.3 V to −25 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first Table 4 data + 10% 350 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION −55°C to +125°C −65°C to +150°C 150°C 150.4°C/W 50°C/W 215°C 220°C Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. 0 | Page 9 of 16 ADG1408-EP/ADG1409-EP A0 1 16 A1 EN 2 15 A2 ADG1408-EP 14 GND TOP VIEW (Not to Scale) 13 VDD 12 S5 S3 6 11 S6 S4 7 10 S7 D 8 9 S8 VSS 3 S1 4 S2 5 09248-002 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 2. ADG1408-EP Pin Configuration Table 6. ADG1408-EP Pin Function Descriptions Pin No. TSSOP LFCSP 1 15 2 16 Mnemonic A0 EN 3 1 VSS 4 5 6 7 8 9 10 11 12 13 14 15 16 2 3 4 5 6 7 8 9 10 11 12 13 14 EP S1 S2 S3 S4 D S8 S7 S6 S5 VDD GND A2 A1 Exposed pad Description Logic Control Input. Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. Most Negative Power Supply Potential. In single supply applications, it can be connected to ground. Source Terminal 1. Can be an input or an output. Source Terminal 2. Can be an input or an output. Source Terminal 3. Can be an input or an output. Source Terminal 4. Can be an input or an output. Drain Terminal. Can be an input or an output. Source Terminal 8. Can be an input or an output. Source Terminal 7. Can be an input or an output. Source Terminal 6. Can be an input or an output. Source Terminal 5. Can be an input or an output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input. Logic Control Input. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS. Table 7. ADG1408-EP Truth Table A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 Rev. 0 | Page 10 of 16 On Switch None 1 2 3 4 5 6 7 8 A0 1 16 A1 EN 2 15 GND ADG1409-EP 14 VDD TOP VIEW (Not to Scale) 13 S1B 12 S2B 11 S3B 7 10 S4B 8 9 VSS 3 S1A 4 S2A 5 S3A 6 S4A DA DB 09248-003 ADG1408-EP/ADG1409-EP Figure 3. ADG1409-EP Pin Configuration (TSSOP) Table 8. ADG1409-EP Pin Function Descriptions Pin No. TSSOP LFCSP 1 15 2 16 Mnemonic A0 EN 3 1 VSS 4 5 6 7 8 9 10 11 12 13 14 15 16 2 3 4 5 6 7 8 9 10 11 12 13 14 EP S1A S2A S3A S4A DA DB S4B S3B S2B S1B VDD GND A1 Exposed pad Description Logic Control Input. Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. Most Negative Power Supply Potential. In single supply applications, it can be connected to ground. Source Terminal 1A. Can be an input or an output. Source Terminal 2A. Can be an input or an output. Source Terminal 3A. Can be an input or an output. Source Terminal 4A. Can be an input or an output. Drain Terminal A. Can be an input or an output. Drain Terminal B. Can be an input or an output. Source Terminal 4B. Can be an input or an output. Source Terminal 3B. Can be an input or an output. Source Terminal 2B. Can be an input or an output. Source Terminal 1B. Can be an input or an output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS. Table 9. ADG1409-EP Truth Table A1 X 0 0 1 1 A0 X 0 1 0 1 EN 0 1 1 1 1 On Switch Pair None 1 2 3 4 Rev. 0 | Page 11 of 16 ADG1408-EP/ADG1409-EP TYPICAL PERFORMANCE CHARACTERISTICS 8 400 350 +85°C 4 +25°C 3 –40°C VDD = +12V VSS = 0V 250 200 150 –55°C 2 VDD = +5V VSS = –5V 300 +125°C 5 TIME (ns) ON RESISTANCE (Ω) 6 VDD = +15V VSS = –15V 100 1 50 –10 –5 0 5 10 15 SOURCE OR DRAIN VOLTAGE (V) 0 –55 09248-004 0 –15 1.0 VDD = +5V VSS = –5V 25 45 65 IS (OFF) +– ID (OFF) +– IS (OFF) –+ ID (OFF) –+ ID, IS (ON) ++ ID, IS (ON) –– 0.8 10 0.6 LEAKAGE CURRENT (nA) ON RESISTANCE (Ω) 5 85 105 125 Figure 7. Transition Time vs. Temperature 12 +125°C +85°C 6 +25°C –40°C 4 –15 TEMPERATURE (°C) Figure 4. On Resistance vs. VD, VS for Different Temperatures; 15 V Dual Supply 8 –35 09248-007 7 450 VDD = +15V VSS = –15V –55°C 0.4 VDD = +15V VSS = –15V VBIAS = +10V/–10V 0.2 0 –0.2 –0.4 –0.6 2 –2 –1 0 1 2 3 4 5 SOURCE OR DRAIN VOLTAGE (V) –1.0 0 14 9 12 8 LEAKAGE CURRENT (nA) +85°C 6 –40°C 3 –55°C 1 VDD = 12V VSS = 0V 0 0 2 40 50 60 70 80 IS (OFF) +– ID (OFF) +– IS (OFF) –+ ID (OFF) –+ ID, IS (ON) ++ ID, IS (ON) –– 10 VDD = +15V VSS = –15V VBIAS = +10V/–10V 8 6 4 2 0 2 –2 4 6 8 10 12 SOURCE OR DRAIN VOLTAGE (V) 09248-006 ON RESISTANCE (Ω) +125°C 7 4 30 Figure 8. Leakage Current vs. Temperature; 15 V Dual Supply 10 +25°C 20 TEMPERATURE (°C) Figure 5. On Resistance vs. VD, VS for Different Temperatures; 5 V Dual Supply 5 10 Figure 6. On Resistance vs. VD, VS for Different Temperatures; 12 V Single Supply –4 0 20 40 60 80 100 TEMPERATURE (°C) Figure 9. Leakage Current vs. Temperature; 15 V Dual Supply Rev. 0 | Page 12 of 16 120 09248-012 –3 09248-005 –4 09248-011 –0.8 0 –5 ADG1408-EP/ADG1409-EP 18 10 IS (OFF) +– ID (OFF) +– IS (OFF) –+ ID (OFF) –+ ID, IS (ON) ++ ID, IS (ON) –– 7 14 6 5 4 3 2 12 VDD = 12V VSS = 0V VBIAS = 1V/10V 10 8 6 4 0 0 –1 –2 0 20 40 60 80 100 TEMPERATURE (°C) 120 0 20 40 60 80 100 TEMPERATURE (°C) Figure 10. Leakage Current vs. Temperature; 5 V Dual Supply Figure 11. Leakage Current vs. Temperature; 12 V Single Supply Rev. 0 | Page 13 of 16 120 09248-013 2 1 09248-015 LEAKAGE CURRENT (nA) 8 IS (OFF) +– ID (OFF) +– IS (OFF) –+ ID (OFF) –+ ID, IS (ON) ++ ID, IS (ON) –– 16 LEAKAGE CURRENT (nA) 9 VDD = +5V VSS = –5V VBIAS = +4.5V/–4.5V ADG1408-EP/ADG1409-EP TEST CIRCUITS V 09248-020 IDS VS D A VS NC VD Figure 12. On Resistance ID (ON) ID (OFF) S A 09248-021 D A VD Figure 14. On Leakage tr < 20ns tf < 20ns 50% D NC = NO CONNECT Figure 13. Off Leakage 3V ADDRESS DRIVE (VIN) S 50% VDD VSS VDD VSS A0 S1 0V VIN A1 50Ω VS1 S2 TO S7 A2 tTRANSITION tTRANSITION S8 ADG1408-EP1 90% 2.4V OUTPUT VS8 OUTPUT D EN 100Ω GND 35pF 1SIMILAR 09248-023 90% CONNECTION FOR ADG1409-EP. Figure 15. Address to Output Switching Times, tTRANSITION 3V ADDRESS DRIVE (VIN) VDD VSS VDD VSS A0 S1 VIN 0V VS A1 50Ω S2 TO S7 A2 S8 80% ADG1408-EP1 80% OUTPUT 2.4V OUTPUT D EN 100Ω GND 35pF 1SIMILAR 09248-024 tBBM CONNECTION FOR ADG1409-EP. Figure 16. Break-Before-Make Delay, tBBM 3V ENABLE DRIVE (VIN) 50% VSS VDD VSS A0 50% S1 A1 VS S2 TO S8 0V A2 ADG1408-EP1 tOFF (EN) 0.9VO OUTPUT 0.9VO D EN VIN 50Ω 1SIMILAR Figure 17. Enable Delay, tON (EN), tOFF (EN) Rev. 0 | Page 14 of 16 GND 100Ω CONNECTION FOR ADG1409-EP. 35pF 09248-025 tON (EN) OUTPUT VDD 09248-022 IS (OFF) S ADG1408-EP/ADG1409-EP 3V VDD VSS VDD VSS A0 A1 VIN A2 ADG1408-EP1 VOUT RS ΔVOUT S D VOUT EN QINJ = CL × ΔVOUT VS CL 1nF GND 09248-026 VIN 1SIMILAR CONNECTION FOR ADG1409-EP. Figure 18. Charge Injection VSS VDD 0.1µF VDD VSS 0.1µF 0.1µF NETWORK ANALYZER VSS S VDD 50Ω 50Ω NETWORK ANALYZER VSS S 50Ω VS VS D RL 50Ω GND D VOUT RL 50Ω OFF ISOLATION = 20 log VOUT VS 09248-027 GND INSERTION LOSS = 20 log Figure 19. Off Isolation VDD VOUT RL 50Ω VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 21. Insertion Loss VSS 0.1µF 0.1µF NETWORK ANALYZER VOUT 09248-029 VDD 0.1µF VDD VDD VSS VSS 0.1µF 0.1µF S1 AUDIO PRECISION D S2 VDD VSS R 50Ω RS S IN VS GND VIN RL 10kΩ GND Figure 20. Channel-to-Channel Crosstalk Figure 22. THD + Noise Rev. 0 | Page 15 of 16 VOUT 09248-030 VOUT VS 09248-028 CHANNEL-TO-CHANNEL CROSSTALK = 20 log VS V p-p D ADG1408-EP/ADG1409-EP OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 23. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model ADG1408SRU-EP ADG1408SRU-EP-RL7 ADG1409SRU-EP ADG1409SRU-EP-RL7 Temperature Range −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09248-0-3/11(0) Rev. 0 | Page 16 of 16 Package Option RU-16 RU-16 RU-16 RU-16