DICE/DWF SPECIFICATION RH101A Operational Amplifier DIE CROSS REFERENCE 5 LTC Finished Part Number 6 Order DICE CANDIDATE Part Number Below RH101A DICE RH101A DWF RH101A RH101A 7 8 4 1 3 2 80 × 59 mils Backside (substrate) is an alloyed gold layer. May be connected to V– or no connection. W DICE ELECTRICAL TEST LI ITS SYMBOL PARAMETER PAD FUNCTION 1. 2. 3. 4. 5. 6. 7. 8. BAL/COMP –IN +IN V– BAL OUT V+ COMP TA = 25°C. VS = ±20V unless otherwise noted. CONDITIONS TA = 25°C MIN MAX UNITS Pre-Irradiation (Note 1) RS ≤ 50k VOS Input Offset Voltage IOS Input Offset Current IB Input Bias Current VCM = 0V AVOL Large Signal Voltage Gain VS = ±15V, VOUT = ±10V, RL ≥ 2k 50 V/mV CMRR Common Mode Rejection Ratio RS ≤ 50k 80 dB PSRR Power Supply Rejection Ratio RS ≤ 50k 80 dB Input Voltage Range VS = ±20V ±15 V VOUT Output Voltage Swing VS = ±15V, RL ≥ 10k VS = ±15V, RL ≥ 2k ±12 ±10 V V IS Supply Current VS = ±20V Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 2 mV 10 nA 75 nA 3 mA 1 DICE/DWF SPECIFICATION RH101A W DICE ELECTRICAL TEST LI ITS SYMBOL PARAMETER TA = 25°C. VS = ±20V unless otherwise noted. CONDITIONS 10Krad(SI) MIN MAX 20Krad(SI) MIN MAX 50Krad(SI) MIN MAX 100Krad(SI) MIN MAX 200Krad(SI) MIN MAX UNITS Post-Irradiation (Note 4) RS ≤ 50k VOS Input Offset Voltage 2 2 2 2 3 mV IOS Input Offset Current 10 10 10 10 20 nA IB Input Bias Current 75 75 100 200 400 nA CMRR Common Mode Rejection Ratio VCM = ±15V, RS ≤ 50k 80 80 80 80 80 dB PSRR Power Supply Rejection Ratio VCM = ±5V to ±20V, RS ≤ 50k 80 80 80 80 80 dB AVOL Large Signal Voltage Gain RL = ±2k, VO = ±10V, VS = ±15V 50 50 50 50 25 V/mV VOUT Maximumm Output Voltage Swing VS = ±15V, RL ≥ 10k VS = ±15V, RL ≥ 2k ±12 ±10 ±12 ±10 ±12 ±10 ±12 ±10 ±12 ±10 IS Supply Current VS = ±20V 3 3 3 3 3 Note 1: Unless otherwise noted, all measurements are made with unity gain compensation (C1 = 30pF); these specifications apply for ±5V ≤ VS ≤ 20V. Note 2: For supply voltages less than ±15V, the maximum input voltage is equal to the supply voltage. V V mA Note 3: Refer to LTC standard product data sheet for all other applicable information. Note 4: The post-irradiation table is for lot qualification based on sample lot assembly and testing only. Contact LTC marketing for more detail. Wafer level testing is performed per the indicated specifications for dice. Considerable differences in performance can often be observed for dice versus packaged units due to the influences of packaging and assembly on certain devices and/or parameters. Please consult factory for more information on dice performance and lot qualifications via lot sampling test procedures. Dice data sheet subject to change. Please consult factory for current revision in production. I.D.No. 66-13-0101 2 Linear Technology Corporation LT/LT 0203 PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2003