LT1683 - Slew Rate Controlled Ultralow Noise Push-Pull DC/DC Controller

LT1683
Slew Rate Controlled
Ultralow Noise Push-Pull DC/DC Controller
DESCRIPTION
FEATURES
Greatly Reduced Conducted and Radiated EMI
n Low Switching Harmonic Content
n Independent Control of Output Switch Voltage and
Current Slew Rates
n Greatly Reduced Need for External Filters
n Dual N-Channel MOSFET Drivers
n 20kHz to 250kHz Oscillator Frequency
n Easily Synchronized to External Clock
n Regulates Positive and Negative Voltages
n Easier Layout Than with Conventional Switchers
The LT ®1683 is a switching regulator controller designed to
lower conducted and radiated electromagnetic interference
(EMI). Ultralow noise and EMI are achieved by controlling
the voltage and current slew rates of external N-channel
MOSFET switches. Current and voltage slew rates can
be independently set to optimize harmonic content of
the switching waveforms vs efficiency. The LT1683 can
reduce high frequency harmonic power by as much as
40dB with only minor losses in efficiency.
The LT1683 utilizes a dual output (push-pull) current
mode architecture optimized for low noise topologies.
The IC includes gate drivers and all necessary oscillator,
control and protection circuitry. Unique error amp circuitry
can regulate both positive and negative voltages. The oscillator may be synchronized to an external clock for more
accurate placement of switching harmonics.
n
APPLICATIONS
Power Supplies for Noise Sensitive Communication
Equipment
n EMI Compliant Offline Power Supplies
n Precision Instrumentation Systems
n Isolated Supplies for Industrial Automation
n Medical Instruments
n Data Acquisition Systems
n
Protection features include gate drive lockout for low VIN,
opposite gate lockout, soft-start, output current limit,
short-circuit current limiting, gate drive overvoltage clamp
and input supply undervoltage lockout.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
DirectSense is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
TYPICAL APPLICATION
Ultralow Noise 48V to 5V DC/DC Converter
48V
510Ω
0.5W
51k
39µF
63V
MIDCOM 31244
FZT853
10µF
20V
1N4148
23.2k
14
5
976Ω
6
1.2nF
7
16.9k
8
25k
3.3k
16
25k
3.3k
15
1.5k
12
CAP A
V5
GATE A
SYNC
CT
CAP B
LT1683
RT
GATE B
RVSL
CS
RCSL
PGND
VC
SS
13
GND
11
FB
NFB
10
22µH
150µF
OS-CON
17
3
VIN GCL
SHDN
0.22µF 22nF
MBRS340
8.2V
68µF
20V
11V
OPTIONAL
MBR0530
2N3904
2
5pF
22µH
A 5V/2A
2×100µF
POSCAP
5V Output Noise
(Bandwidth = 100MHz)
10pF
200V
MBRS340
1
18
B
200µVP-P
30pF
19
4 Si9422
A
200µV/DIV
10pF
200V
5pF
B
20mV/DIV
Si9422
0.1Ω
20
7.50k
9
5µs/DIV
1683 TA01a
30pF
2.49k
10nF
1683 TA01
1683fd
1
LT1683
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Supply Voltage (VIN)..................................................20V
Gate Drive Current...................................... Internal Limit
V5 Current................................................... Internal Limit
SHDN Pin Voltage......................................................20V
Feedback Pin Voltage (Trans. 10ms) ....................... ±10V
Feedback Pin Current .............................................10mA
Negative Feedback Pin Voltage (Trans. 10ms) .......... ±10V
CS Pin............................................................................5V
GCL Pin........................................................................16V
SS Pin............................................................................3V
Operating Junction Temperature Range
(Note 3)...................................................– 40°C to 125°C
Storage Temperature Range....................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300°C
GATE A
1
20 PGND
CAP A
2
19 GATE B
GCL
3
18 CAP B
CS
4
17 VIN
V5
5
16 RVSL
SYNC
6
15 RCSL
CT
7
14 SHDN
RT
8
13 SS
FB
9
12 VC
NFB 10
11 GND
G PACKAGE
20-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 110°C/ W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT1683EG#PBF
LT1683EG#TRPBF
1683
20-Lead Plastic SSOP
– 40°C to 125°C
LT1683IG#PBF
LT1683IG#TRPBF
1683
20-Lead Plastic SSOP
– 40°C to 125°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT1683EG
LT1683EG#TR
1683
20-Lead Plastic SSOP
– 40°C to 125°C
LT1683IG
LT1683IG#TR
1683
20-Lead Plastic SSOP
– 40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VC = 0.9V, VFB = VREF , RVSL, RCSL = 16.9k, RT = 16.9k and
other pins open unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1.235
V
Error Amplifiers
VREF
Reference Voltage
Measured at Feedback Pin
l
1.250
1.265
250
1000
nA
0.012
0.03
%/V
– 2.500
– 2.45
V
0.009
0.03
%/V
1500
2200
2500
µmho
µmho
IFB
Feedback Input Current
VFB = VREF
l
FBREG
Reference Voltage Line Regulation
2.7V ≤ VIN ≤ 20V
l
VNFR
Negative Feedback Reference Voltage
Measured at Negative Feedback Pin
with Feedback Pin Open
l
INFR
Negative Feedback Input Current
VNFB = VNFR
NFBREG
Negative Feedback Reference Voltage Line Regulation
2.7V ≤ VIN ≤ 20V
gm
Error Amplifier Transconductance
∆IC = ±50µA
– 2.56
– 37
l
l
1100
700
– 25
µA
1683fd
2
LT1683
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VC = 0.9V, VFB = VREF , RVSL, RCSL = 16.9k, RT = 16.9k and
other pins open unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IESK
Error Amp Sink Current
VFB = VREF + 150mV, VC = 0.9V
l
120
200
350
µA
IESRC
Error Amp Source Current
VFB = VREF – 150mV, VC = 0.9V
l
120
200
350
µA
VCLH
Error Amp Clamp Voltage
High Clamp, VFB = 1V
1.27
V
VCLL
Error Amp Clamp Voltage
Low Clamp, VFB = 1.5V
0.12
V
AV
Error Amplifier Voltage Gain
250
V/V
FBOV
FB Overvoltage Shutdown
Outputs Drivers Disabled
1.47
V
ISS
Soft-Start Charge Current
VSS = 1V
9.0
180
12
µA
Oscillator and Sync
fMAX
Max Switch Frequency
fSYNC
Synchronization Frequency Range
VSYNC
SYNC Pin Input Threshold
RSYNC
SYNC Pin Input Resistance
250
Oscillator Frequency = 250kHz
kHz
290
l
0.7
kHz
1.4
2.0
40
kΩ
45
46
%
10
7.6
10.4
7.9
10.7
8.1
0.2
0.35
Gate Drives (Specifications Apply to Either A or B Unless Otherwise Noted)
DCMAX
Maximum Switch Duty Cycle
RVSL = RCSL = 4.85k,
Osc Frequency = 25kHz
VGON
Gate On Voltage
VIN = 12, GCL = 12
VIN = 12, GCL = 8
VGOFF
Gate Off Voltage
VIN = 12V
IGSO
Max Gate Source Current
VIN = 12V
0.3
IGSK
Max Gate Sink Current
VIN = 12V
0.3
VINUVLO
Gate Drive Undervoltage Lockout (Note 5)
VGCL = 6.5V, Gates Enabled
l
V
V
V
A
A
7.3
7.5
V
103
120
mV
230
300
mV
Current Sense
tIBL
Switch Current Limit Blanking Time
VSENSE
Sense Voltage Shutdown Voltage
VSENSEF
Sense Voltage Fault Threshold
100
VC Pulled Low
l
86
l
ns
Slew Control (for the Following Slew Tests See Test Circuit in Figure 1b)
VSLEWR
Output Voltage Slew Rising Edge
RVSL = RCSL = 17k
26
V/µs
VSLEWF
Output Voltage Slew Falling Edge
RVSL = RCSL = 17k
19
V/µs
VISLEWR
Output Current Slew Rising Edge (CS Pin Voltage)
RVSL = RCSL = 17k
0.21
V/µs
VISLEWF
Output Current Slew Falling Edge (CS Pin Voltage)
RVSL = RCSL = 17k
0.21
V/µs
Supply and Protection
VINMIN
Minimum Input Voltage (Note 4)
VGCL = VIN
l
2.55
3.6
V
IVIN
Supply Current (Note 2)
RVSL = RCSL = 17k , VIN = 12
RVSL = RCSL = 17k , VIN = 20
l
l
25
35
45
55
mA
mA
VSHDN
Shutdown Turn-On Threshold
l
1.31
1.39
1.48
V
∆VSHDN
Shutdown Turn-On Voltage Hysteresis
l
50
110
180
mV
ISHDN
Shutdown Input Current Hysteresis
l
10
24
35
µA
V5
5V Reference Voltage
6.5V ≤ VIN ≤ 20V, IV5 = 5mA
6.5V ≤ VIN ≤ 20V, IV5 = – 5mA
4.85
4.80
5
5
5.20
5.15
V
V
IV5SC
5V Reference Short-Circuit Current
VIN = 6.5V Source
VIN = 6.5V Sink
10
–10
mA
mA
1683fd
3
LT1683
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Supply current specification includes loads on each gate as in
Figure 1a. Actual supply currents vary with operating frequency, operating
voltages, V5 load, slew rates and type of external FET.
Note 3: The LT1683E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 125°C operating range
are assured by design, characterization and correlation with statistical
process controls. The LT1683I is guaranteed and tested over the – 40° to
125° operating temperature range.
Note 4: Output gate drivers will be enabled at this voltage. The GCL voltage
will also determine drivers’ activity.
Note 5: Gate drivers are ensured to be on when VIN is greater than the
maximum value.
TYPICAL PERFORMANCE CHARACTERISTICS
Negative Feedback Voltage and
Input Current vs Temperature
2.480
3.2
1.258
700
2.485
3.0
1.256
650
1.254
600
2.490
2.8
1.252
550
2.495
2.6
1.250
500
2.500
2.4
1.248
450
2.505
2.2
1.246
400
1.244
350
2.510
2.0
1.242
300
2.515
1.8
1.240
–50 –25
0
NEGATIVE FEEDBACK VOLTAGE (V)
750
2.520
–50 –25
250
25 50 75 100 125 150
TEMPERATURE (°C)
0
1.6
25 50 75 100 125 150
TEMPERATURE (°C)
1683 G01
1683 G02
Error Amp Output Current vs
Feedback Pin Voltage from Nominal
Error Amp Transconductance
vs Temperature
2000
500
1.65
1900
400
1.60
1800
300
1700
200
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.20
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
1683 G03
CURRENT (µA)
1.70
TRANSCONDUCTANCE (µmho)
FEEDBACK VOLTAGE (V)
Feedback Overvoltage Shutdown
vs Temperature
NFB INPUT CURRENT (µA)
1.260
FB INPUT CURRENT (nA)
FEEDBACK VOLTAGE (V)
Feedback Voltage and Input
Current vs Temperature
1600
1500
1400
100
25°C
125°C
0
–100
–200
1300
1200
–300
1100
–400
1000
–50 –25
– 40°C
0
25 50 75 100 125 150
TEMPERATURE (°C)
1683 G04
–500
–400 –300 –200 –100 0 100 200 300 400
FEEDBACK PIN VOLTAGE FROM NOMINAL (mV)
1683 G05
1683fd
4
LT1683
TYPICAL PERFORMANCE CHARACTERISTICS
VC Pin Threshold and Clamp
Voltage vs Temperature
1.50
240
220
1.0
200
0.8
0.6
0.4
FAULT
180
160
140
120
0.2
80
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
25
22
23
20
VIN CURRENT (mA)
17
WITH NO EXTERNAL MOSFETs
VIN = 20 RCSL, RVSL = 17k
16
VIN = 12 RCSL, RVSL = 17k
14
0.6
0
0
25 50 75 100 125 150
TEMPERATURE (°C)
GATE DRIVE A/B PIN VOLTAGE (V)
90
80
70
60
20
30
DUTY CYCLE (%)
40
50
1683 G12
0
20
40
60
80
CS PIN VOLTAGE (mV)
100
Gate Drive A/B Low Voltage
vs Temperature
10.7
6.5
0.50
10.6
6.4
0.45
GCL = 12V
10.5
6.3
10.4
6.2
10.3
6.1
VIN = 12V
NO LOAD
10.2
6.0
10.1
5.9
10.0
5.8
GCL = 6V
9.90
5.7
9.80
5.6
9.70
–50 –25
0
120
1683 G11
Gate Drive A/B High Voltage
vs Temperature
VC PIN = 0.9V
TA = 25°C
10
0.8
1683 G10
110
0
1.0
0.2
10
–50 –25
Slope Compensation
100
1.2
0.4
12
25 50 75 100 125 150
TEMPERATURE (°C)
TA = 25°C
1.4
VIN = 12 RCSL, RVSL = 5.7k
18
1683 G09
PERCENT OF MAX CS VOLTAGE
CS Pin to VC Pin Transfer Function
1.6
5.5
25 50 75 100 125 150
TEMPERATURE (°C)
1683 G13
GATE DRIVE A/B PIN VOLTAGE (V)
SHDN PIN CURRENT (µA)
24
0
25 50 75 100 125 150
TEMPERATURE (°C)
1683 G08
VIN Current vs Temperature
27
19
0
1683 G07
SHDN Pin Hysteresis Current vs
Temperature
21
OFF
1.25
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
1683 G06
15
–50 –25
1.35
VC PIN VOLTAGE (V)
0
ON
1.40
1.30
TRIP
100
0
–50 –25
1.45
SHDN PIN VOLTAGE (V)
1.2
CS PIN VOLTAGE (mV)
VC PIN VOLTAGE (V)
1.4
50
SHDN Pin On and Off Thresholds
vs Temperature
CS Pin Trip and CS Fault Voltage
vs Temperature
0.40
VIN = 12V
NO LOAD
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
1683 G14
1683fd
5
LT1683
TYPICAL PERFORMANCE CHARACTERISTICS
Gate Drive Undervoltage Lockout
Voltage vs Temperature
Soft-Start Current vs Temperature
7.3
GCL = 6V
9.3
7.0
6.9
6.8
6.7
6.6
5.06
8.9
8.7
8.5
8.3
8.1
6.5
7.9
6.4
7.7
6.3
–50 –25
SS VOLTAGE = 0.9V
9.1
SS PIN CURRENT (µA)
VIN PIN VOLTAGE (V)
7.1
5.08
0
25 50 75 100 125 150
TEMPERATURE (°C)
V5 PIN VOLTAGE (V)
7.2
V5 Voltage vs Load Current
9.5
7.5
–50 –25
T = 125°C
5.04
5.02
T = 25°C
5.00
T = –40°C
4.98
0
25 50 75 100 125 150
TEMPERATURE (°C)
1683 G15
4.96
–15
–10
–5
0
5
LOAD CURRENT (mA)
1683 G16
10
15
1683 G17
PIN FUNCTIONS
Part Supply
V5 (Pin 5): This pin provides a 5V output that can sink or
source 10mA for use by external components. V5 source
current comes from VIN . Sink current goes to GND. VIN
must be greater than 6.5V in order for this voltage to be
in regulation. If this pin is used, a small capacitor (<1µF)
may be placed on this pin to reduce noise. This pin can
be left open if not used.
GND (Pin 11): Signal Ground. The internal error amplifier, negative feedback amplifier, oscillator, slew control
circuitry, V5 regulator, current sense and the bandgap
reference are referred to this ground. Keep the connection to this pin, the feedback divider and VC compensation
network free of large ground currents.
SHDN (Pin 14): The shutdown pin can disable the switcher.
Grounding this pin will disable all internal circuitry.
Increasing SHDN voltage will initially turn on the internal
bandgap regulator. This provides a precision threshold for
the turn on of the rest of the IC. As SHDN increases past
1.39V the internal LDO regulator turns on, enabling the
control and logic circuitry.
24µA of current is sourced out of the pin above the turn on
threshold. This can be used to provide hysteresis for the
shutdown function. The hysteresis voltage will be set by the
Thevenin resistance of the resistor divider driving this pin
times the current sourced out. Above approximately 2.1V
the hysteresis current is removed. There is approximately
0.1V of voltage hysteresis on this pin as well.
The pin can be tied high (to VIN for instance).
VIN (Pin 17): Input Supply. All supply current for the part
comes from this pin including gate drives and V5 regulator. Charge current for gate drives can produce current
pulses of hundreds of milliamperes. Bypass this pin with
a low ESR capacitor.
When VIN is below 2.55V the part will go into supply
undervoltage lockout where the gate drivers are driven low.
This, along with gate drive undervoltage lockout, prevents
unpredictable behavior during power up.
PGND (Pin 20): Power Driver Ground. This ground comes
from the MOSFET gate drivers. This pin can have several
hundred milliamperes of current on it when the external
MOSFETs are being turned off.
Oscillator
SYNC (Pin 6): The SYNC pin can be used to synchronize
the part to an external clock. The oscillator frequency
1683fd
6
LT1683
PIN FUNCTIONS
should be set close to the external clock frequency. Synchronizing the clock to an external reference is useful for
creating more stable positioning of the switcher voltage
and current harmonics. This pin can be left open or tied
to ground if not used.
gate drive will not be enabled until VIN > VGCL + 0.8V. If this
pin is tied to VIN, then undervoltage lockout is disabled.
CT (Pin 7): The oscillator capacitor pin is used in conjunction with RT to set the oscillator frequency. For RT = 16.9k:
Slew Control
COSC(nf) = 129/fOSC(kHz)
RT (Pin 8): The oscillator resistor pin is used to set the
charge and discharge currents of the oscillator capacitor.
The nominal value is 16.9k. It is possible to adjust this resistance ±25% to set oscillator frequency more accurately.
Gate Drive
GATE A, GATE B (Pins 1, 19): These pins connect to the
gates of the external N-channel MOSFETs. GATE A and
GATE B turn on with alternate clock cycles. These drivers
are capable of sinking and sourcing at least 300mA.
The GCL pin sets the upper voltage of the gate drive. The
gate pins will not be activated until VIN reaches a minimum
voltage as defined by the GCL pin (gate undervoltage
lockout).
The gate drive outputs have current limit protection to
safe guard against accidental shorts.
If the gate drive voltage is greater than about 1V the
opposite gate drive is inhibited thus preventing cross
conduction.
GCL (Pin 3): This pin sets the maximum gate voltage to
the GATE A and GATE B pins to the MOSFET gate drives.
This pin should be either tied to a Zener, a voltage source
or VIN.
If the pin is tied to a Zener or a voltage source, the
maximum gate drive voltage will be approximately
VGCL – 0.2V. If it is tied to VIN, the maximum gate voltage
is approximately VIN – 1.6.
Approximately 50µA of current can be sourced from this
pin if VGCL < VIN – 0.8V.
This pin also controls undervoltage lockout of the gate
drives. If the pin is tied to a Zener or voltage source, the
There is an internal 19V Zener tied from this pin to ground
to provide a fail-safe for maximum gate voltage.
CAP A, CAP B (Pins 2, 18): These pins are the feedback
nodes for the external voltage slewing capacitors. Normally
a small 1pf to 5pf capacitor is connected from this pin to
the drain of its respective MOSFET.
The voltage slew rate is inversely proportional to this
capacitance and proportional to the current that the part
will sink and source on this pin. That current is inversely
proportional to RVSL.
RCSL (Pin 15): A resistor to ground sets the current slew
rate for the external drive MOSFETs during switching. The
minimum resistor value is 3.3k and the maximum value
is 68k. The time to slew between on and off states of
the MOSFET current will determine how the di/dt related
harmonics are reduced. This time is proportional to RCSL
and RS (the current sense resistor) and maximum current. Longer times produce a greater reduction of higher
frequency harmonics.
RVSL (Pin 16): A resistor to ground sets the voltage slew
rate for the drains of the external drive MOSFETs. The
minimum resistor value is 3.3k and the maximum value
is 68k. The time to slew between on and off states on the
MOSFET drain voltage will determine how harmonics are
reduced from this source. This time is proportional to RVSL,
CVA/B and the input voltage. Longer times produce more
rolloff of harmonics. CVA/B is the equivalent capacitance
from CAP A or B to the drain of the MOSFET.
Switch Mode Control
CS (Pin 4): This is the input to the current sense amplifier.
It is used for both current mode control and current slewing
of the external MOSFETs. Current sense is accomplished
via a sense resistor (RS) connected from the sources of
the external MOSFETs to ground. CS is connected to the
top of RS. Current sense is referenced to the GND pin.
1683fd
7
LT1683
PIN FUNCTIONS
The switch maximum operating current will be equal to
0.1V/RS. At CS = 0.1V, the gate drivers will be immediately
turned off (no slew control).
If CS = 0.22V in addition to the drivers being turned off, VC
and SS will be discharged to ground (short-circuit protection). This will hasten turn off on subsequent cycles.
FB (Pin 9): The feedback pin is used for positive voltage
sensing. It is the inverting input to the error amplifier. The
noninverting input of this amplifier connects internally to
a 1.25V reference.
If the voltage on this pin exceeds the reference by 220mV,
then the output drivers will immediately turn off the external MOSFETs (no slew control). This provides for output
overvoltage protection
When this input is below 0.9V then the current sense
blanking will be disabled. This will assist start up.
NFB (Pin 10): The negative feedback pin is used for sensing a negative output voltage. The pin is connected to the
inverting input of the negative feedback amplifier through
a 100k source resistor. The negative feedback amplifier
provides a gain of –0.5 to the FB pin. The nominal regulation point would be –2.5V on NFB. This pin should be left
open if not used.
VC (Pin 12): The compensation pin is used for frequency
compensation and current limiting. It is the output of the
error amplifier and the input of the current comparator.
Loop frequency compensation can be performed with an
RC network connected from the VC pin to ground. The
voltage on VC is proportional to the switch peak current.
The normal range of voltage on this pin is 0.25V to 1.27V.
However, during slope compensation the upper clamp
voltage is allowed to increase with the compensation.
During a short-circuit fault the VC pin will be discharged
to ground.
SS (Pin 13): The SS pin allows for ramping of the switch
current threshold at startup. Normally a capacitor is placed
on this pin to ground. An internal 9µA current source will
charge this capacitor up. The voltage on the VC pin cannot
exceed the voltage on SS. Thus peak current will ramp
up as the SS pin ramps up. During a short circuit fault
the SS pin will be discharged to ground thus reinitializing
soft-start.
When SS is below the VC clamp voltage the VC pin will
closely track the SS pin.
This pin can be left open if not used.
If NFB is being used then overvoltage protection will occur
at 0.44V below the NFB regulation point.
At NFB < –1.8 current sense blanking will be disabled.
TEST CIRCUITS
20mA
5pF
0.9A
5pF
IN5819
CAP A/CAP B
IN5819
CAP A/CAP B
ZVN3306A
GATE A/GATE B
+
–
2
10
GATE A/GATE B
Si4450DY
CS
+
–
10
0.1
1683 F01a
Figure 1a. Typical Test Circuitry
1683 F01b
Figure 1b. Test Circuit for Slew
1683fd
8
LT1683
BLOCK DIAGRAM
VIN
CIN
RCSL
SHDN
VIN
V5
RVSL
RCSL
RVSL
TO
DRIVERS
REGULATOR
+
NEGATIVE
FEEDBACK
AMP
VREG
–
NFB
100k
GCL
50k
CAP A
GATE A
–
FB
+
ERROR
AMP
SLEW
CONTROL
+
CAP B
1.25V
CVC
CSS
GATE B
VC
–
SS
CVB
MB
CS
+
COMP
S
CT
MA
PGND
SENSE
AMP
+
RT
CVA
RSENSE
–
Q
FF
RT
R
OSCILLATOR
CT
T
Q
FF
QB
SYNC
SUB
GND
1683 BD
1683fd
9
LT1683
OPERATION
In noise sensitive applications switching regulators tend
to be ruled out as a power supply option due to their propensity for generating unwanted noise. When switching
supplies are required due to efficiency or input/output
constraints, great pains must be taken to work around
the noise generated by a typical supply. These steps may
include pre and post regulator filtering, precise synchronization of the power supply oscillator to an external clock,
synchronizing the rest of the circuit to the power supply
oscillator or halting power supply switching during noise
sensitive operations. The LT1683 greatly simplifies the task
of eliminating supply noise by enabling the design of an
inherently low noise switching regulator power supply.
The LT1683 is a fixed frequency, current mode switching
regulator with unique circuitry to control the voltage and
current slew rates of the output switches. Current mode
control provides excellent AC and DC line regulation and
simplifies loop compensation.
Slew control capability provides much greater control over
the power supply components that can create conducted
and radiated electromagnetic interference. Compliance
with EMI standards will be an easier task and will require
fewer external filtering components.
The LT1683 uses two external N-channel MOSFETs as the
power switches. This allows the user to tailor the drive
conditions to a wide range of voltages and currents.
CURRENT MODE CONTROL
Referring to the Block Diagram. A switching cycle begins
with an oscillator discharge pulse, which resets the RS
flip-flop, turning on one of the external MOSFET drivers.
The switch current is sensed across the external sense
resistor and the resulting voltage is amplified and compared to the output of the error amplifier (VC pin). The
driver is turned off once the output of the current sense
amplifier exceeds the voltage on the VC pin. In this way
pulse by pulse current limit is achieved. The toggle flip-flop
ensures that the two MOSFETs are enabled on alternate
clock cycles. Internal slope compensation is provided to
ensure stability under high duty cycle conditions.
Output regulation is obtained using the error amp to
set the switch current trip point. The error amp is a
transconductance amplifier that integrates the difference
between the feedback output voltage and an internal 1.25V
reference. The output of the error amp adjusts the switch
current trip point to provide the required load current
at the desired regulated output voltage. This method of
controlling current rather than voltage provides faster
input transient response, cycle-by-cycle current limiting
for better output switch protection and greater ease in
compensating the feedback loop. The VC pin is used for
loop compensation and current limit adjustment. During
normal operation the VC voltage will be between 0.25V
and 1.27V. An external clamp on VC or SS may be used
for lowering the current limit.
The negative voltage feedback amplifier allows for direct
regulation of negative output voltages. The voltage on the
NFB pin gets amplified by a gain of – 0.5 and driven on to
the FB input, i.e., the NFB pin regulates to –2.5V while the
amplifier output internally drives the FB pin to 1.25V as in
normal operation. The negative feedback amplifier input
impedance is 100k (typ) referred to ground.
Soft-Start
Control of the switch current during start-up can be
obtained by using the SS pin. An external capacitor from
SS to ground is charged by an internal 9µA current source.
The voltage on VC cannot exceed the voltage on SS. Thus
as the SS pin ramps up the VC voltage will be allowed to
ramp up. This will then provide for a smooth increase in
switch maximum current. SS will be discharged as a result
of the CS voltage exceeding the short-circuit threshold of
approximately 0.22V.
Slew Control
Control of output voltage and current slew rates is achieved
via two feedback loops. One loop controls the MOSFET drain
dV/dt and the other loop controls the MOSFET dI/dt.
The voltage slew rate uses an external capacitor between
CAP A or CAP B and the respective MOSFET drain. These
integrating caps close the voltage feedback loop. The
external resistor, RVSL, sets the current for the integrator.
1683fd
10
LT1683
OPERATION
The voltage slew rate is thus inversely proportional to both
the value of capacitor and RVSL.
The current slew feedback loop consists of the voltage
across the external sense resistor, which is internally amplified and differentiated. The derivative is limited to a value set
by RCSL. The current slew rate is thus inversely proportional
to both the value of sense resistor and RCSL.
The two control loops are combined internally so that a
smooth transition from current slew control to voltage
slew control is obtained. When turning on, the driver current will slew before voltage. When turning off, voltage
will slew before current. In general it is desirable to have
RVSL and RCSL of similar value.
Internal Regulator
Most of the control circuitry operates from an internal
2.4V low dropout regulator that is powered from VIN. The
internal low dropout design allows VIN to vary from 2.7V
to 20V with stable operation of the controller. When SHDN
< 1.3V the internal regulator is completely disabled.
5V Regulator
A 5V regulator is provided for powering external circuitry.
This regulator draws current from VIN and requires VIN
to be greater than 6.5V to be in regulation. It can sink or
source 10mA. The output is current limited to prevent
against destruction from accidental short circuits.
Safety and Protection Features
There are several safety and protection features on the
chip. The first is overcurrent limit. Normally the gate
drivers will go low when the output of the internal sense
amplifier exceeds the voltage on the VC pin. The VC pin is
clamped such that maximum output current is attained
when the CS pin voltage is 0.1V. At that level the outputs
will be immediately turned off (no slew). The effect of
this control is that the output voltage will foldback with
overcurrent.
In addition, if the CS voltage exceeds 0.22V, the VC and
SS pins will be discharged to ground also, resetting the
soft-start function. Thus if a short is present this will allow
for faster MOSFET turnoff and less MOSFET stress.
If the voltage on the FB pin exceeds regulation by approximately 0.22V, the outputs will immediately go low.
The implication is that there is an overvoltage fault.
The voltage on GCL determines two features. The first
is the maximum gate drive voltage. This will protect the
MOSFET gate from overvoltage.
With GCL tied to a Zener or an external voltage source
then the maximum gate driver voltage is approximately
VGCL – 0.2V. If GCL is tied to VIN , then the maximum
gate voltage is determined by VIN and is approximately
VIN – 1.6V. There is an internal 19V Zener on the GCL
pin that prevents the gate driver pin from exceeding approximately 19V.
In addition, the GCL voltage determines undervoltage
lockout of the gate drives. This feature disables the gate
drivers if VIN is too low to provide adequate voltage to
turn on the MOSFETs. This is helpful during start-up to
ensure the MOSFETs have sufficient gate drive to saturate.
If GCL is tied to a voltage source or Zener less than 6.8V,
the gate drivers will not turn on until VIN exceeds GCL
voltage by 0.8V. For VGCL above 6.5V, the gate drives are
ensured to be off for VIN < 7.3V and they will be turned
on by VGCL + 0.8V.
If GCL is tied to VIN, the gate drivers are always enabled
(undervoltage lockout is disabled).
When driving a push-pull transformer, it is important to
make sure that both drivers are not on at the same time.
Even though runaway cannot occur under such cross
conduction with this chip because current slew is regulated, increased current would be possible. This chip has
opposite gate lockout whereby when one MOSFET is on
the other MOSFET cannot be turned on until the gate of
the first drops below 1V. This ensures that cross conduction will not occur.
The gate drives have current limits for the drive currents.
If the sink or source current is greater than 300mA then
the current will be limited.
The V5 regulator also has internal current limiting that will
only guarantee ±10mA output current.
1683fd
11
LT1683
OPERATION
There is also an on-chip thermal shutdown circuit that will
turn off the outputs in the event the chip temperature rises
to dangerous levels. Thermal shutdown has hysteresis that
will cause a low frequency (<1kHz) oscillation to occur as
the chip heats up and cools down.
The chip has an undervoltage lockout feature that will
force the gate drivers low in the event that VIN drops below
2.5V. This ensures predictable behavior during start-up
and shutdown. SHDN can be used in conjuction with an
external resistor divider to completely disable the part if
the input voltage is too low. This can be used to ensure
adequate voltage to reliably run the converter. See the
section in Applications Information.
Table 1 summarizes these features.
Table 1. Safety and Protection Features
FEATURE
FUNCTION
EFFECT ON GATE DRIVERS
SLEW CONTROL
EFFECT ON VC, SS
Maximum Current Fault
Turn Off FETs at Maximum
Switch Current (VSENSE = 0.1)
Immediately Goes Low
Overridden
None
Short-Circuit Fault
Turn Off FETs and Reset VC
for Short-Circuit (VSENSE = 0.2)
Immediately Goes Low
Overridden
Discharge VC, SS
to GND
Overvoltage Fault
Turn Off Drivers If FB > VREG + 0.22V
(Output Overvoltage)
Immediately Goes Low
Overridden
None
GCL Clamp
Set Max Gate Voltage to Prevent
FET Gate Breakdown
Limits Max Voltage
None
None
Gate Drive
Undervoltage Lockout
Disable Gate Drives When VIN
Is Too Low. Set Via GCL Pin
Immediately Goes Low
Overridden
None
Thermal Shutdown
Turn Off Drivers If Chip
Temperature Is Too Hot
Immediately Goes Low
Overridden
None
Opposite Gate Lockout
Prevents Opposite Driver from
Turning on Until Driver Is Off
(Cross Conduction in Transformer)
Inhibits Turn On of
Opposite Driver
None
None
VIN Undervoltage Lockout
Disable Part When VIN ≅ 2.55V
Immediately Goes Low
Overridden
None
Gate Drive Source and Sink Current Limit Limit Gate Drive Current
Limit Drive Current
None
None
V5 Source/Sink Current Limit
Limit Current from V5
None
None
None
Shutdown
Disable Part When SHDN <1.3V
1683fd
12
LT1683
APPLICATIONS INFORMATION
Reducing EMI from switching power supplies has traditionally invoked fear in designers. Many switchers are designed
solely on efficiency and as such produce waveforms filled
with high frequency harmonics that then propagate through
the rest of the system.
The LT1683 provides control over two of the more important variables for controlling EMI with switching inductive
loads: switch voltage slew rate and switch current slew
rate. The use of this part will reduce noise and EMI over
conventional switch mode controllers. Because these
variables are under control, a supply built with this part
will exhibit far less tendency to create EMI and less chance
of encountering problems during production.
It is beyond the scope of this data sheet to get into EMI
fundamentals. Application Note 70 contains much information concerning noise in switching regulators and should
be consulted.
Oscillator Frequency
The oscillator determines the switching frequency and
therefore the fundamental positioning of all harmonics.
The use of good quality external components is important
to ensure oscillator frequency stability. The oscillator is of
a sawtooth design. A current defined by external resistor,
RT, is used to charge and discharge the capacitor, CT . The
discharge rate is approximately ten times the charge rate.
By allowing the user to have control over both components, trimming of oscillator frequency can be more easily
achieved.
The external capacitance CT is chosen by:
CT (nF) =
2180
f(kHz) •R T (kΩ)
where f is the desired oscillator frequency in kHz. For RT
equal to 16.9k, this simplifies to:
CT (nF) =
129
f(kHz)
Nominally RT should be 16.9k. Since it sets up current, its
temperature coefficient should be selected to compliment
the capacitor. Ideally, both should have low temperature
coefficients.
Oscillator frequency is important for noise reduction in
two ways. First the lower the oscillator frequency the
lower the waveform’s harmonics, making it easier to filter
them. Second the oscillator will control the placement of
the output voltage harmonics which can aid in specific
problems where you might be trying to avoid a certain
frequency bandwidth.
Oscillator Sync
If a more precise frequency is desired (e.g., to accurately
place harmonics) the oscillator can be synchronized to
an external clock. Set the RC timing components for an
oscillator frequency 10% lower than the desired sync
frequency.
Drive the SYNC pin with a square wave (with greater than
1.4V amplitude). The rising edge of the sync square wave
will initiate clock discharge. The sync pulse should have
a minimum pulse width of 0.5µs.
Be careful in sync’ing to frequencies much different
from the part since the internal oscillator charge slope
determines slope compensation. It would be possible to
get into subharmonic oscillation if the sync doesn’t allow for the charge cycle of the capacitor to initiate slope
compensation. In general, this will not be a problem until
the sync frequency is greater than 1.5 times the oscillator
free-run frequency.
Slew Rate Setting
The primary reason to use this part is to gain advantage
of lower EMI and noise due to slew control. The rolloff in
higher frequency harmonics has its theoretical basis with
two primary components. First, the clock frequency sets
the fundamental positioning of harmonics and second, the
associated normal frequency rolloff of harmonics.
e.g., CT = 1.29nF for f = 100kHz
1683fd
13
LT1683
APPLICATIONS INFORMATION
This part creates a second higher frequency rolloff of
harmonics that inversely depends on the slew time, the
time that voltage or current spends between the off state
and on state. This time is adjustable through the choice of
the slew resistors, the external resistors to ground on the
RVSL and RCSL pins and the external components used for
the external voltage feedback capacitors CAV, CBV (from
CAP A or CAP B to their respective MOSFET drains) and
the sense resistor. Lower slew rates (longer slew times,
lower frequency for harmonics rolloff) is created with
higher values of RVSL, RCSL, CAV, CBV and the current
sense resistor.
Setting the voltage and current slew rates should be done
empirically. The most practical way of determining these
components is to set CAV, CBV and the sense resistor value.
Then, start by making RVSL, RCSL each a 50k resistor pot
in series with 3.3k. Starting from the lowest resistor setting (fast slew) adjust the pots until the noise level meets
your guidelines. Note that slower slewing waveforms will
dissipate more power so that efficiency will drop. You
can monitor this as you make your slew adjustment by
measuring input and output voltage and their respective
currents. Monitor the MOSFET temperature as slew rates
are slowed. These components will heat up as efficiency
decreases.
normally set with consideration of the maximum current
in the MOSFETs.
Setting the voltage slew also involves selection of the
capacitors CAV, CBV. The voltage slew time is proportional
to the output voltage swing (basically input voltage), the
external voltage feedback capacitor and the RVSL value.
Thus at higher input voltages smaller capacitors will be
used with lower RVSL values. For a starting point use
Table 2.
Table 2
It is possible to use a single slew setting resistor. In this
case the RVSL and RCSL pins are tied together. A resistor
with a value of 1.8k to 34k (one-half the individual resistors) can then be tied from these pins to ground.
In general only the RCSL value will be available for adjustment of current slew. The current slew time does also
depend on the current sense resistor but this resistor is
<25V
5pF
50V
2.5pF
100V
1pF
The second method makes use of a capacitor divider. Care
should be taken that the voltage ratings of the capacitors
satisfy the full voltage swing (2x input voltage for pushpull configurations) thus essentially the same rating as
the MOSFETs.
MOSFET DRAIN
CAP A OR B
C2
C1
C3
1683 F02
Figure 2
The equivalent slew capacitance for Figure 2 is
(C1 • C2)/(C1 + C2 + C3).
Positive Output Voltage Setting
Sensing of a positive output voltage is usually done using a resistor divider from the output to the FB pin. The
positive input to the error amp is connected internally to
a 1.25V bandgap reference. The FB pin will regulate to
this voltage.
Referring to Figure 3, R1 is determined by:
14
CAPACITOR VALUE
Smaller value capacitors can be made in two ways. The
first is simply combining two capacitors in series. The
equivalent capacitance is then (C1 • C2)/(C1 + C2).
Measuring noise should be done carefully. It is easy to
introduce noise by poor measurement techniques. Consult
AN70 for recommended measurement techniques. Keeping
probe ground leads very short is essential.
Usually it will be desirable to keep the voltage and current slew resistors approximately the same. There are
circumstances where a better optimization can be found by
adjusting each separately, but as these values are separated
further, a loss of independence of control may occur.
INPUT VOLTAGE
V

R1= R2  OUT − 1
 1.25 
1683fd
LT1683
APPLICATIONS INFORMATION
The FB bias current represents a small error and can
usually be ignored for values of R1||R2 up to 10k.
One word of caution, sometimes a feedback zero is added
to the control loop by placing a capacitor across R1. If
the feedback capacitively pulls the FB pin above the internal regulator voltage (2.4V), output regulation may be
disrupted. A series resistance with the feedback pin can
eliminate this potential problem. There is an internal clamp
on FB that clamps at 0.7V above the regulation voltage
that should also help prevent this problem.
R1
FB PIN
VOUT
R2
1683 F03
Figure 3
Negative Output Voltage Setting
Negative output voltage can be sensed using the NFB pin.
In this case regulation will occur when the NFB pin is at
–2.5V. The nominal input bias current for the NFB is
–25µA (INFB), which needs to be accounted for in setting
up the divider.
Referring to Figure 4, R1 is chosen such that:
 VOUT − 2.5 
R1= R2 

 2.5 +R2 • 25µA 
A suggested value for R2 is 2.5k. The NFB pin is normally
left open if the FB pin is being used.
R1
NFB PIN
INFB
the LT1683 will act to prevent either output from going
beyond its set output voltage. The highest output (lightest
load) will dominate control of the regulator. This technique
would prevent either output from going unregulated high
at no load. However, this technique will also compromise
output load regulation.
Shutdown
If SHDN is pulled low, the regulator will turn off. As the
SHDN pin voltage is increased from ground the internal
bandgap regulator will be powered on. This will set a 1.39V
threshold for turn-on of the internal regulator that runs
most of the control circuitry of the regulator. Note after the
control circuitry powers on, gate driver activity will depend
on the voltage of VIN with respect to the voltage on GCL.
As the SHDN pin enables the internal regulator a 24µA
current will be sourced from the pin that can provide
hysteresis for undervoltage lockout. This hysteresis can
be used to prevent part shutdown due to input voltage
sag from an initial high current draw.
In addition to the current hysteresis, there is also approximately 100mV of voltage hysteresis on the SHDN pin.
When the SHDN pin is greater than 2.2V, the hysteretic
current from the part will be reduced to essentially zero.
If a resistor divider is used to set the turn-on threshold then
the resistors are determined by the following equations:
 RA +RB 
VON = 
•V
 RB  SHDN
R2
Figure 4
SHDN
RB
Reworking these equations yields:
Dual Polarity Output Voltage Sensing
Certain applications may benefit from sensing both positive and negative output voltages. When doing this each
output voltage resistor divider is individually set as previously described. When both FB and NFB pins are used,
RA
 ∆V

VHYST = RA •  SHDN +ISHDN 
 RA RB

–VOUT
1683 F04
VIN
RA =
(VHYST • VSHDN − VON • ∆ VSHDN )
(ISHDN • VSHDN )
RB =
(VHYST • VSHDN − VON • ∆ VSHDN )
ISHDN •(VON − VSHDN )
1683fd
15
LT1683
APPLICATIONS INFORMATION
So if we wanted to turn on at 20V with 2V of hysteresis:
2V • 1.39V − 20V • 0.1V
= 23.4k
24µA • 1.39V
2V • 1.39V − 20V • 0.1V
RB =
= 1.75k
24µA •(20V − 1.39V)
RA =
Resistor values could be altered further by adding Zeners
in the divider string. A resistor in series with SHDN pin
could further change hysteresis without changing turn-on
voltage.
Frequency Compensation
Loop frequency compensation is accomplished by way of
a series RC network on the output of the error amplifier
(VC pin).
VC PIN
RVC
2k
CVC2
4.7nF
CVC
0.01µF
1683 F06
Figure 6
Referring to Figure 6, the main pole is formed by capacitor CVC and the output impedance of the error amplifier
(approximately 400kΩ). The series resistor, RVC, creates a
“zero” which improves loop stability and transient response.
A second capacitor, CVC2, typically one-tenth the size of
the main compensation capacitor, is sometimes used to
reduce the switching frequency ripple on the VC pin. VC
pin ripple is caused by output voltage ripple attenuated
by the output divider and multiplied by the error amplifier.
Without the second capacitor, VC pin ripple is:
VCPINRIPPLE =
1.25 • VRIPPLE • gm •R VC
VOUT
where VRIPPLE = Output ripple (VP-P )
gm = Error amplifier transconductance
RVC = Series resistor on VC pin
VOUT = DC output voltage
To prevent irregular switching, VC pin ripple should be
kept below 50mVP-P . Worst-case VC pin ripple occurs at
maximum output load current and will also be increased
if poor quality (high ESR) output capacitors are used. The
addition of a 0.0047µF capacitor for CVC2 pin reduces
switching frequency ripple to only a few millivolts. A low
value for RVC will also reduce VC pin ripple, but loop phase
margin may be inadequate.
Setting Current Limit
The sense resistor sets the value for maximum operating
current. When the CS pin voltage is 0.1V the gate drivers will
immediately go low (no slew control). Therefore the sense
resistor value should be set to RS = 0.1V/ISW(PEAK), where
ISW(PEAK) is the peak current in the MOSFETs. ISW(PEAK)
will depend on the topology and component values and
tolerances. Certainly it should be set below the saturation
current value for the transformer.
If CS pin voltage is 0.22V in addition to the drivers going
low, VC and SS will be discharged to ground. This is to
provide additional protection in the event of a short circuit. By discharging VC and SS, the MOSFET will not be
stressed as hard on subsequent cycles since the current
trip will be set lower.
Turn-off of the MOSFETs will normally be inhibited for
about 100ns at the start of every turn on cycle. This is
to prevent noise from interfering with normal operation
of the controller. This current sense blanking does not
prevent the outputs from be turned off in the event of
a fault. Slewing of the gate voltage effectively provides
additional blanking.
Traces to the SENSE resistor should be kept short and
wide to minimize resistance and inductance. Large
interwinding capacitance in the transformer or high
capacitance on the drain of the MOSFETs will produce
a current pulse through the sense resistor during drain
voltage slewing. The magnitude of the pulse is C • dV/dt
where C is the capacitance and dV/dt is the voltage slew
rate which is controlled by the part. This pulse will increase
the sensed current on switch turn-on and can cause premature MOSFET turn-off. If this occurs, the transformer
may need a different winding technique (see AN39) or
alternatively, a blanking circuit can be used. Please contact
the LTC applications group for support if required.
1683fd
16
LT1683
APPLICATIONS INFORMATION
Soft-Start
Magnetics
The soft-start pin is used to provide control of switching
current during start-up. The max voltage on the VC pin is
approximately the voltage on the SS pin. A current source
will linearly charge a capacitor on the SS pin. The VC pin
voltage will thus ramp also. The approximate time for the
voltage on these pins to ramp is (1.31V/9µA) • CSS or
approximately 146ms per µF.
Design of magnetics is dependent on topology. The following details the design of the magnetics for a push-pull
converter. In this converter the transformer usually stores
little energy. The following equations should be considered
as the starting point to building a prototype.
The following definitions will be used:
VIN = Input supply voltage
The soft-start current will be initiated as soon as the part
turns on. Soft-start will be reinititated after a short-circuit
fault.
ISW = Maximum switch current
Thermal Considerations
VOUT = Desired output voltage
Most of the IC power dissipation is derived from the VIN
pin. The VIN current depends on a number of factors including: oscillator frequency; loads on V5; slew settings;
gate charge current. Additional power is dissipated if V5
sinks current and during the MOSFET gate discharge.
IOUT = Output current
The power dissipation in the IC will be the sum of:
1)The RMS VIN current times VIN
2)V5 RMS sink current times 5V
3) The gate drive’s RMS discharge current times voltage
Because of the strong VIN component it is advantageous
to operate the LT1683 at as low a VIN as possible.
It is always recommended that package temperature be
measured in each application. The part has an internal
thermal shutdown to minimize the chance of IC destruction
but this should not replace careful thermal design.
The thermal shutdown feature does not protect the external
MOSFETs. A separate analysis must be done for those
devices to ensure that they are operating within safe limits.
Once IC power dissipation, PDIS, is determined die junction
temperature is then computed as:
TJ = TAMB + PDIS • θJA
where TAMB is ambient temperature and θJA is the package
thermal resistance. For the 20-pin SSOP, θJA is 100°C/W.
RON = Switch-on resistance
f = Oscillator frequency
VF = Forward drop of the rectifier
Duty cycle is the major defining equation for this topology.
Note that the output L and C basically filter the chopped
voltage so duty cycle controls output voltage. N is the
turns ratio of the transformer. The turns ratio must be
large enough to ensure that the transformer can put out
a voltage equal to the output voltage plus the diode under
minimum input conditions. Note the transformer operates
at half the oscillator frequency (f).
N=
VOUT + VF
(2 •DCMAX )  VIN(MIN) −ISW (RON +RSENSE )
DCMAX is the maximum duty cycle of each driver with
respect to the entire cycle, which consists of two periods
(A on and B on). So the effective duty cycle is 2 • DCMAX.
The controller, in general, determines maximum duty
cycle. A 44% maximum duty cycle is a guaranteed value
for this part.
Remember to add sufficient margin in the turns ratio to
account for IR drops in the transformer windings, worstcase diode forward drops and switch-on voltage. Also at
very slow slew rates the effective DC may be reduced.
1683fd
17
LT1683
APPLICATIONS INFORMATION
There are a number of ways to choose the inductance
value for L. We suggest as a starting point that L be selected
such that the converter is continuous at IOUT(MAX)/4. If your
minimum IOUT is higher than this or your components can
handle higher peak currents then use a higher number.
1:N
D1
L
VOUT
C
ROUT
VIN
LPRI
D2
RSENSE
1683 F07
Figure 7. Push-Pull Topology
Continuous operation occurs when the current in the
inductor never goes to zero. Discontinuous operation
occurs when the inductor current drops to zero before the
start of the next cycle and can occur with small inductors
and light loads. There is nothing inherently bad about
discontinuous operation, however, converter control and
operation are somewhat different. The inductor is smaller
for discontinuous operation but the peak currents in the
switch, the transformer, the diodes, inductor and capacitor
will be higher which may produce greater losses.
For continuous operation the inductor ripple current must
be less than twice the output current. The worst case for
this is at maximum input (lowest duty cycle, DCMIN) but
in the following we will evaluate at nominal input since
the IOUT/4 is somewhat arbitrary.
Note when both inputs are off, the inductor current splits
between both secondary outputs and the diode common
goes to 0V.
Looking at the inductor current during off time, output
ripple current is:
∆IOUT = 2 •IOUT(MIN)
IOUT(MIN) = IOUT(MAX) / 4
L=
( VOUT(MIN) + VF ) • (1− 2 • DC )
The inductance of the transformer primary should be such
that L, when reflected into the primary, dominates the
input current. In other words, we want the magnetizing
current of the transformer small with respect to the current
going through the transformer to L. In general, then, the
inductance of the primary should be at least five times that
of L reflected to the input. This ensures that most of the
power will be passed through the transformer to the load.
It also increases the power capability of the converter and
reduces the peak currents that the switch will see.
5 •L
LPRI = 2
N
If the magnetizing current is small, say below 100mA, then
a smaller L can be used with a higher percentage of the
switch current generated by the magnetizing current.
With the value of L set, the ripple in the inductor is:
∆IL =
( VOUT + VF ) • (1− 2 •DC)
L•f
However, the peak inductor current is evaluated at maximum load and maximum input voltage (minimum DC).
IL(MAX) =IOUT(MAX) +
∆IL(MAX)
2
The magnetizing ripple current can be shown to be:
V
+V
∆IMAG = OUT F
N •LPRI • f
and the peak current in the switch is:
ISW(PEAK) = N • IL(MAX) + ∆IMAG
This current should be less than the current limit.
Worst-case switch ripple is:
∆ISW(PEAK) = N • ∆IL(MAX) + ∆IMAG
In the push-pull converter the maximum switch voltage
will be 2 • VIN. Because voltage is slew-controlled, the
leakage spikes are small. So, the MOSFET should have a
maximum rated switch voltage at least 20% higher than
2 • VIN.
∆IOUT • f
1683fd
18
LT1683
APPLICATIONS INFORMATION
So, given the turns ratio, primary inductance and current, the transformer can be designed. The design of the
transformer will require analyzing the power losses of the
transformer and making necessary adjustments.
The maximum inductor current is:
1.03A
IL(MAX) = 2A +
= 2.52A
2
Most transformer companies can assist you with designing
an optimal solution. For instance Midcom, Inc. (1-800643-2661). Linear Technology’s application group can
also help.
Primary inductance should be greater than:
As an example say we are designing a 48V ±20% to 5V
100kHz converter with 2A output and 500mA ripple. Then
starting with a guess for the on voltage of the MOSFET
plus sense resistor of 0.5V and VF of 0.5V:
5 + 0.5
1
N=
=
88% • ( 48 • 80% − 0.5) 6.1
For continuous operation at IOUT(MIN) = IOUT(MAX)/4,
inductor ripple (the same as output ripple):
2A
∆IL = 2 •
= 1A
4
The duty cycle for nominal input is:
VOUT + VF
DCNOM =
2 •N VIN(NOM) −ISW •RON
(
=
Then:
L=
5.5
2
• 47.5
6.1
)
1A • 100kHz
Off-the-shelf components can be used for this inductor.
Say we choose a 22µH inductor, then ripple current at
maximum input (DC = 29.1%) is:
The secondary inductance would then be:
4.1mH/6.12 = 110µH
The magnetizing ripple current is approximately:
∆IMAG =
(5 + 0.5) • (1− 2 • 29.1%) = 1.03A
22µF • 100kHz
5.5
1
• 4.1mH • 100kHz
6.1
= 81mA
Peak switch current is:
ISW(PEAK) =
1
• 2.51A + 81mA = 494mA
6.1
Note that you can discern your magnetizing ripple by
looking at the reflected inductance ripple and subtracting
it from the switch current ripple.
∆IMAG = ∆ISW – N • IL
The max ripple current on the switch is:
= 35.3%
(5 + 0.5) • (1− 2 • 35.3%) = 16µH
∆IL =
LPRI = 5 • 22µH • 6.12 = 4.1mH
∆ISW(MAX) =
1.03A
+ 81mA = 0.25A
6.1
Knowing the peak switch current we can go back and
iterate with a more accurate switch-on voltage. We
would have to know the RON of the FET. In our case our
assumptions of a 0.5V switch-on voltage is valid for
RON + RSENSE < 1Ω.
Capacitors
Correct choice of input and output capacitors is very
important to low noise switcher performance. Push-pull
topologies and other low noise topologies will in general
have continuous currents, which reduce the requirements
1683fd
19
LT1683
APPLICATIONS INFORMATION
for capacitance. However, noise depends more on the ESR
of the capacitors. In addition lower ESR can also improve
efficiency.
Input capacitors must also withstand surges that occur
during the switching of some types of loads. Some solid tantalum capacitors can fail under these surge conditions.
Design Note 95 offers more information but the following
is a brief summary of capacitor types and attributes.
Aluminum Electrolytic: Low cost and higher voltage. They
can be used in this application but in general you will
need higher capacitance to achieve low ESR. Additional
nonelectrolytic capacitors may be required to achieve
better performance.
Specialty Polymer Aluminum: Panasonic has come out
with their series CD capacitors. While they are only available for voltages below 16V, they have very low ESR and
good surge capability.
The worst component from an AC point is the gate charge
current. The actual peak current depends on gate capacitance and slew rate, being higher for larger values of each.
The total current can be estimated by gate charge and
frequency of operation. Because of the slewing with this
part, gate charge is spread out over a longer time period
than with a normal FET driver. This reduces capacitance
requirements.
Typically the current will have spikes of under 100mA
located at the gate voltage transitions. This is charge/discharge to and from the threshold voltage. Most slewing
occurs with the gate voltage near threshold.
Since the part’s VIN will typically be under 15V many options are available for choice of capacitor. Values of input
capacitor for just VIN requirement will typically be in the
50µF range with an ESR of under 0.1Ω.
Solid Tantalum: Small size and low impedance. Typically
the maximum voltage rating is 50V. With large surge currents the capacitor may need to be derated or you need a
special type such as AVX TPS line.
In addition to the part supply, decoupling of the supply to
the transformer needs to be considered. If this is the same
supply as the VIN pin then that capacitor will need to be
increased. However, often with this part the transformer
supply will be a higher voltage and as such a separate
capacitor.
OS-CON: Lower impedance than aluminum but only available for 35V or less. Form factor may be a problem.
The transformer decoupling capacitor will see the switch
current as ripple.
Ceramic: Generally used for high frequency and high
voltage bypass. They may resonate with their ESL before
ESR becomes dominant. Recent multilayer ceramic (MLC)
capacitors provide larger capacitance with low ESR.
This switch current computation can be used to estimate
the capacity for these capacitors:
1
DC
CIN =
• MIN
∆ VCAP
f
−ESR
∆ISW(MAX)
There are continuous improvements being made in capacitors so consult with manufacturers as to your specific
needs.
Input Capacitors
The input capacitor should have low ESR at high frequencies since this will be an important factor concerning how
much conducted noise is created.
There are two separate requirements for input capacitors.
The first is for supply to the part’s VIN pin. The VIN pin
will provide current for the part itself and the gate charge
current.
where ∆VCAP is the allowed sag on the input capacitor. ESR
is the equivalent series resistance for the cap. In general
allowed sag will be a few tenths of volts.
Output Filter Capacitor
The output capacitor is chosen both for capacity and ESR.
The capacity must supply the load current in the switchoff state. While slew control reduces higher frequency
components of the ripple current in the capacitor, the
capacitor ESR and the magnitude of the output ripple
1683fd
20
LT1683
APPLICATIONS INFORMATION
current controls the fundamental component. ESR should
also be low to reduce capacitor dissipation.
The capacitance value can be computed by consideration
of desired load ripple, duty cycle and ESR.
Setting the voltage on the GCL pin depends on what type
of MOSFET is used and the desired gate drive undervoltage
lockout voltage.
DCMIN
f
−ESR
MOSFET Selection
First determine the maximum gate drive that you require.
Typically you will want it to be at least 2V greater than the
maximum threshold. Higher voltages will lower the on
resistance and increase efficiency. Be certain to check the
maximum allowed gate voltage. Often this is 20V but for
some logic threshold MOSFETs it is only 8V to 10V.
There is a wide variety of MOSFETs to choose from for
this part. The part will work with either normal threshold
(3V to 4V) or logic-level threshold devices (1V to 2V).
VGCL needs to be set approximately 0.2V above the desired
max gate threshold. In addition VIN needs to be at least
1.6V above the gate voltage.
Select a voltage rating to ensure under worst-case conditions that the MOSFET will not break down. Next choose
an RON sufficiently low to meet both the power dissipation
capabilities of the MOSFET package as well as overall efficiency needs of the converter.
The GCL pin can be tied to VIN which will result in a maximum gate voltage of VIN – 1.6V.
COUT =
1
Setting GCL Voltage
∆ VOUT
∆IL(MAX)
•
The LT1683 can handle a large range of gate charges.
However at very large charge stability may be affected.
The power dissipation in the MOSFET depends on several
factors. The primary element is I2R heating when the device
is on. In addition, power is dissipated when the device is
slewing. An estimate for power dissipation is:
⎧
⎛
3 • Δ I2 ⎞ ⎤ ⎫
2 ⎡ 2
⎪
⎢ VIN − RON2 • ⎜ I2 +
2 ΔI
⎟⎥ ⎪
I +
4
⎝
⎠ ⎥⎦ ⎪
⎪
⎢
4 +⎣
P = ⎨ VIN •
• I⎬
VSR
ISR
⎪
⎪
⎪
⎪
⎭
⎩
• f + I2 • RON • DC
where I is the average current, ∆I is the ripple current in
the switch, ISR is the current slew rate, VSR is the voltage
slew rate, f is the oscillator frequency, DC is the duty cycle
and RON is the MOSFET on-resistance.
This pin also controls undervoltage lockout of the gate
drives. The undervoltage lockout will prevent the MOSFETs
from switching until there is sufficient drive present.
If GCL is tied to a voltage source or Zener less than 6.8V,
the gate drivers will not turn on until VIN exceeds the GCL
voltage by 0.8V. For VGCL above 6.5V, the gate drives are
ensured to be off for VIN < 7.3V and they will be turned
on by VGCL + 0.8V.
If GCL is tied to VIN , the gate drivers are always on
(undervoltage lockout is disabled).
Approximately 50µA of current can be sourced from this pin
if VIN > VGCL + 0.8V. This could be used to bias a Zener.
The GCL pin has an internal 19V Zener to ground that will
provide a failsafe for maximum gate voltage.
As an example say we are using a Siliconix Si4480DY
which has RDS(ON) rated at 6V. To get 6V, VGCL needs to
be set to 6.2V and VIN needs to be at least 7.6V.
1683fd
21
LT1683
APPLICATIONS INFORMATION
Gate Driver Considerations
In general, the MOSFETs should be positioned as close to
the part as possible to minimize inductance.
When the part is active the gate drives will be pulled low
to less than 0.2V. When the part is off, the gate drives
contain a 40k resistor in series with a diode to ground
that will offer passive holdoff protection. If you are using
some logic-level MOSFETs this might not be sufficient. A
resistor may be placed from gate to ground, however the
value should be reasonably high to minimize DC losses
and possible AC issues.
The gate drive source current comes from VIN . The sink
current exits through PGND. In general the decoupling
cap should be placed close to these two pins.
Switching Diodes
In general, switching diodes should be Schottky diodes.
Size and breakdown voltage depend on the specific
converter. A lower forward drop will improve converter
efficiency. No other special requirements are needed.
PCB Layout Considerations
As with any switcher careful consideration should be
given to PC board layout. Because this part reduces high
frequency EMI the board layout is less critical, however
high currents and voltages still produce the need for careful
board layout to eliminate poor and erratic performance.
the ground paths of other loops. Using singular points
of connection for the grounds is the best way to do this.
The two major points of connection are the bottom of the
input decoupling cap and the bottom of the output decoupling cap. Typically the sense resistor device PGND and
device GND will tie to the bottom of the input cap.
There are two other loops to pay attention to. The current
slew involves a high bandwidth control that goes through
the MOSFET switch, the sense resistor and into the CS
pin of the part and out the GATE pin to the MOSFET. Trace
inductance and resistance should be kept low on the GATE
drive trace. The CS trace should have low inductance. The
sense resistor should be physically close to PGND and the
MOSFETs’ sources.
Finally care should be taken with the CAP A, CAP B pins.
The part will tolerate stray capacitance to ground on these
pins (<5pF) however stray capacitance to the respective
drains should be minimized. This path would provide an
alternate capacitive path for the voltage slew.
More Help
AN70 contains information about low noise switchers and
measurement of noise and should be consulted. AN19 and
AN29 also have general knowledge concerning switching
regulators. Also, our Application Department is always
ready to lend a helping hand.
A
Basic Considerations
Keep the high current loops physically small in area. The
main loops are shown in Figure 8: the power switch loops
(A and B) and the rectifier loop (C and D). These loops can
be kept small by physically keeping the components close
to one another. In addition, connection traces should be
kept wide to lower resistance and inductances. Components
should be placed to minimize connecting paths. Careful
attention to ground connections must also be maintained.
Without getting into elaborate detail be careful that currents
from different high current loops do not get coupled into
B
CIN
A
1
3 D
2
4 C
GATE A
COUT
GATE B
CS
1683 F08
Figure 8
1683fd
22
LT1683
TYPICAL APPLICATIONS
Ultralow Noise 48V to ±12V DC/DC Converter
10k
48V
510Ω
0.5W
D1
47µF
100V
FZT853
D2
C4
22µF
50V
D3
12V
C3
10µF
25V
2N3904
5
6
7
16.9k
8
25k
3.3k
16
25k
3.3k
15
1k
12
0.22µF
6
2
8.2V
17
VIN
14
1200pF
MBR01100
10
D4
D5
23.2k
976Ω
CTX0215542
T1
1
SHDN
CAP A
V5
GATE A
SYNC
CT
CAP B
LT1683
RT
GATE B
RVSL
CS
RCSL
PGND
VC
22nF
SS
10nF
13
3,4
3
GCL
GND
11
FB
NFB
2
5pF
5pF
200V
8,9
D6
5
7
1
18
5pF
200V
5pF
25pF
19
4 Si9422
D7
L1
10µH
12V/1A
C1
33µF
16V, ×2
C2
33µF
16V, ×2
L2
10µH
–12V/1A
10.0k
2.74k
Si9422
0.068Ω
20
8.66k
9
25pF
1k
10
C1, C2:SANYO 16TPC33
C3: MURATA GRM235Y5V106Z
C4: NIPPON THCR60EIE226Z
D1, D2, D3 IN4148
D4, D5, D6, D7 MBRS1100
L1, L2: COOPER DS50224
T1: COOPER CTX02-15542
1683 TA03
1683fd
23
LT1683
PACKAGE DESCRIPTION
G Package
20-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
6.90 – 7.50*
(.272 – .295 )
20 19 18 17 16 15 14 13 12 11
1.25 0.12
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 0.03
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8 9 10
5.00 – 5.60**
(.197 – .221)
2.0
(.079)
MAX
0–8
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
0.65
(.0256)
BSC
0.22 – 0.38
(.009 – .015)
TYP
0.05
(.002)
MIN
G20 SSOP 0204
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
1683fd
24
LT1683
REVISION HISTORY
(Revision history begins at Rev D)
REV
DATE
DESCRIPTION
PAGE NUMBER
D
11/10
Updated Max Switch Frequency to 150kHz in the Electrical Characteristics section
3
1683fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
25
LT1683
TYPICAL APPLICATION
Ultralow Noise 24V to 5V DC/DC Converter
COILTRONICS
VP5-1200
24V
6.9k
39µF
2N3904
11V
8.2V
68µF
20V
17
VIN
14
5
6
1.5nF
7
16.9k
8
25k
3.3k
16
25k
3.3k
15
1k
15nF
12
SHDN
V5
GATE A
SYNC
CT
CAP B
LT1683
RT
GATE B
RVSL
CS
RCSL
PGND
VC
1nF
SS
GND
13
7
6–10
3
11
2–12
3pF
1
3
GCL
CAP A
FB
NFB
11
OPTIONAL
MBR2045CT
2
10pF
1
1µH
5V/5A
9
330µF
4
8
5
2×330µF
POSCAP
CAP A
MBR2045CT
GATE A
3pF
18
CAP B
10pF
19
4
4.7µH
IRF540
GATE B
IRF540
20
10mΩ
7.50k
9
2.49k
10
10nF
1683 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1533
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LT1534
Ultralow Noise 2A Switching Regulator
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LT1738
Ultralow Noise DC/DC Controller
High Current Output Ultralow Noise Boost Regulator;
Drives External MOSFET
LT1777
Low Noise Step-Down Switching Regulator
Programmable dI/dt; Internally Limited dV/dt
LT1425
Isolated Flyback Switching Regulator
Excellent Regulation without Transformer “Third Winding”
LT1576
1.5A, 200kHz Step-Down Switching Regulator
Constant Frequency, 1.21V Reference Voltage
LT176X Family
Low Dropout, Low Noise Linear Regulator
150mA to 3A, SOT-23 to TO-220
LTC1922-1/LTC3722
Synchronous Phase Modulated Full-Bridge Controllers
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Kilowatts, Synchronous Rectification
LT3439
Ultralow Noise Transformer Driver
1A Push-Pull DC/DC Transformer Driver
1683fd
26 Linear Technology Corporation
LT 1110 REV D • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2001