LT1738 - Slew Rate Controlled Ultralow Noise DC/DC Controller

LT1738
Slew Rate Controlled
Ultralow Noise DC/DC Controller
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DESCRIPTIO
FEATURES
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The LT ®1738 is a switching regulator controller designed
to lower conducted and radiated electromagnetic interference (EMI). Ultralow noise and EMI are achieved by
controlling the voltage and current slew rates of an external N-channel MOSFET switch. Current and voltage slew
rates can be independently set to optimize harmonic
content of the switching waveforms vs efficiency. The
LT1738 can reduce high frequency harmonic power by as
much as 40dB with only minor losses in efficiency.
The LT1738 utilizes a current mode architecture optimized for single switch topologies such as boost, flyback
and Cuk. The IC includes gate drive and all necessary
oscillator, control and protection circuitry. Unique error
amp circuitry can regulate both positive and negative
voltages. The internal oscillator may be synchronized to
an external clock for more accurate placement of switching harmonics.
Greatly Reduced Conducted and Radiated EMI
Low Switching Harmonic Content
Independent Control of Output Switch Voltage and
Current Slew Rates
Greatly Reduced Need for External Filters
Single N-Channel MOSFET Driver
20kHz to 250kHz Oscillator Frequency
Easily Synchronized to External Clock
Regulates Positive and Negative Voltages
Easier Layout Than with Conventional Switchers
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APPLICATIO S
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Power Supplies for Noise Sensitive Communication
Equipment
EMI Compliant Offline Power Supplies
Precision Instrumentation Systems
Isolated Supplies for Industrial Automation
Medical Instruments
Data Acquisition Systems
Protection features include gate drive lockout for low VIN,
soft-start, output current limit, short-circuit current limiting, gate drive overvoltage clamp and input supply
undervoltage lockout.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
Ultralow Noise 5V to 12V Converter
22µH
5V
VIN
MBRD620
P3
+
100µF
17
VIN
14
5
6
1.3nF
7
16.9k
25k
25k
3.3k
3.3k
22nF
0.22µF
8
16
15
12
B
4 × 150µF
OSCON
CAP
10µH
150µF
OSCON
A
+
12V
1A
OPTIONAL
3
GCL
SHDN
+
12V Output Noise
(Bandwidth = 100MHz)
5pF
POINT A
ON SCHEMATIC
500µV/DIV
2
V5
400µVP-P
SYNC
CT
GATE
1
Si9426
POINT B
ON SCHEMATIC
50mV/DIV
LT1738
RT
RVSL
CS
4
25mΩ
RCSL
PGND
VC
SS
1.5k
13
GND
11
FB
NFB
10
20
21.5k
9
5µs/DIV
1738 TA01a
2.5k
1738 TA01
10nF
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LT1738
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PACKAGE/ORDER I FOR ATIO
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ABSOLUTE
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AXI U RATI GS
(Note 1)
Supply Voltage (VIN) ................................................ 20V
Gate Drive Current ..................................... Internal Limit
V5 Current ................................................. Internal Limit
SHDN Pin Voltage .................................................... 20V
Feedback Pin Voltage (Trans. 10ms) ...................... ±10V
Feedback Pin Current ............................................ 10mA
Negative Feedback Pin Voltage (Trans. 10ms) ........ ±10V
CS Pin .......................................................................... 5V
GCL Pin ..................................................................... 16V
SS Pin .......................................................................... 3V
Operating Junction Temperature Range
(Note 3) ............................................ – 40°C to 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
TOP VIEW
GATE
1
20 PGND
CAP
2
19 NC
GCL
3
18 NC
CS
4
17 VIN
LT1738EG
LT1738IG
V5
5
16 RVSL
SYNC
6
15 RCSL
CT
7
14 SHDN
RT
8
13 SS
FB
9
12 VC
NFB 10
ORDER PART
NUMBER
11 GND
G PACKAGE
20-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 110°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VC = 0.9V, VFB = VREF, RVSL, RCSL = 16.9k, RT = 16.9k and
other pins open unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1.235
1.250
1.265
V
250
1000
nA
Error Amplifiers
VREF
Reference Voltage
Measured at Feedback Pin
●
IFB
Feedback Input Current
VFB = VREF
●
FBREG
Reference Voltage Line Regulation
2.7V ≤ VIN ≤ 20V
●
VNFR
Negative Feedback Reference Voltage
Measured at Negative Feedback Pin
with Feedback Pin Open
●
INFR
Negative Feedback Input Current
VNFB = VNFR
NFBREG
Negative Feedback Reference Voltage Line Regulation
2.7V ≤ VIN ≤ 20V
gm
Error Amplifier Transconductance
∆IC = ±50µA
0.012
0.03
%/V
–2.56
– 2.50
–2.45
V
–37
– 25
µA
0.009
0.03
%/V
1500
●
1100
700
2200
2500
µmho
µmho
●
IESK
Error Amp Sink Current
VFB = VREF + 150mV, VC = 0.9V
●
120
200
350
µA
IESRC
Error Amp Source Current
VFB = VREF – 150mV, VC = 0.9V
●
120
200
350
µA
VCLH
Error Amp Clamp Voltage
High Clamp, VFB = 1V
VCLL
Error Amp Clamp Voltage
Low Clamp, VFB = 1.5V
AV
Error Amplifier Voltage Gain
FBOV
FB Overvoltage Shutdown
ISS
Soft-Start Charge Current
1.27
V
0.12
V
250
V/V
Outputs Drivers Disabled
1.47
V
VSS = 1V
9.0
180
12
µA
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LT1738
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VC = 0.9V, VFB = VREF, RVSL, RCSL = 16.9k, RT = 16.9k and
other pins open unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
Oscillator Frequency = 250kHz
290
TYP
MAX
UNITS
Oscillator and Sync
fMAX
Max Switch Frequency
fSYNC
Synchronization Frequency Range
VSYNC
SYNC Pin Input Threshold
RSYNC
SYNC Pin Input Resistance
250
●
0.7
kHz
kHz
1.4
2
40
kΩ
90
93.5
%
10
7.6
10.4
7.9
10.7
8.1
V
V
0.2
0.35
V
Gate Drive
DCMAX
Maximum Switch Duty Cycle
RVSL = RCSL = 3.9k,
Osc Frequency = 25kHz
VGON
Gate On Voltage
VIN = 12, GCL = 12
VIN = 12, GCL = 8
VGOFF
Gate Off Voltage
VIN = 12V
IGSO
Max Gate Source Current
VIN = 12V
0.3
A
IGSK
Max Gate Sink Current
VIN = 12V
0.3
A
VINUVLO
Gate Drive Undervoltage Lockout (Note 5)
VGCL = 6.5V
●
7.3
7.5
V
Current Sense
tIBL
Switch Current Limit Blanking Time
VSENSE
Sense Voltage Shutdown Voltage
VSENSEF
Sense Voltage Fault Threshold
100
VC Pulled Low
●
86
ns
103
120
mV
220
300
mV
Slew Control for the Following Slew Tests See Test Circuit in Figure 1b
VSLEWR
Output Voltage Slew Rising Edge
RVSL = RCSL = 17k
26
V/µs
VSLEWF
Output Voltage Slew Falling Edge
RVSL = RCSL = 17k
19
V/µs
VISLEWR
Output Current Slew Rising Edge (CS pin V)
RVSL = RCSL = 17k
2.1
V/µs
VISLEWF
Output Current Slew Falling Edge (CS pin V)
RVSL = RCSL = 17k
2.1
V/µs
Supply and Protection
VINMIN
Minimum Input Voltage (Note 4)
VGCL = VIN
IVIN
Supply Current (Note 3)
RVSL = RCSL = 17k
RVSL = RCSL = 17k
VSHDN
Shutdown Turn-On Threshold
●
∆VSHDN
Shutdown Turn-On Voltage Hysteresis
●
VIN = 12
VIN = 20
●
2.55
3.6
V
●
12
35
40
55
mA
mA
1.31
1.39
1.48
V
50
110
180
mV
ISHDN
Shutdown Input Current Hysteresis
10
24
35
µA
V5
5V Reference Voltage
6.5V ≤ VIN ≤ 20V, IV5 = 5mA
6.5V ≤ VIN ≤ 20V, IV5 = – 5mA
4.85
4.80
5
5
5.20
5.15
V
V
IV5SC
5V Reference Short-Circuit Current
VIN = 6.5V Source
VIN = 6.5V Sink
10
–10
●
Note 1: Absolute Maximum Ratings are those values beyond which the
life of a device may be impaired.
Note 2: Supply current specification includes loads on each gate as in
Figure 1a. Actual supply currents vary with operating frequency, operating
voltages, V5 load, slew rates and type of external FET.
Note 3: The LT1738E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications from –40°C to 125°C are assured by
mA
mA
design, characterization and correlation with statistical process
controls.The LT1738I is guaranteed and tested to meet performance
specifications from – 40°C to 125°C.
Note 4: Output gate drive is enabled at this voltage. The GCL voltage will
also determine driver activity.
Note 5: Gate drive is ensured to be on when VIN is greater than max value.
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LT1738
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TYPICAL PERFOR A CE CHARACTERISTICS
Negative Feedback Voltage and
Input Current vs Temperature
2.480
3.2
1.258
700
2.485
3.0
1.256
650
2.490
2.8
1.254
600
1.252
550
2.495
2.6
1.250
500
2.500
2.4
1.248
450
2.505
2.2
1.246
400
2.510
2.0
1.244
350
1.242
300
2.515
1.8
1.240
–50 –25
0
NEGATIVE FEEDBACK VOLTAGE (V)
750
2.520
–50 –25
250
25 50 75 100 125 150
TEMPERATURE (°C)
0
1.6
25 50 75 100 125 150
TEMPERATURE (°C)
1738 G01
Feedback Overvoltage Shutdown
vs Temperature
Error Amp Transconductance vs
Temperature
Error Amp Output Current vs
Feedback Pin Voltage from Nominal
500
1900
400
1800
300
1700
200
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.20
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
CURRENT (µA)
2000
1.65
TRANSCONDUCTANCE (µmho)
FEEDBACK VOLTAGE (V)
1738 G02
1.70
1.60
1600
1500
1400
–300
1100
–400
1738 G03
SHDN Pin On and Off Thresholds
vs Temperature
1.50
240
CLAMP
220
1.0
0.8
0.6
0.4
THRESHOLD
FAULT
1.45
SHDN PIN VOLTAGE (V)
CS PIN VOLTAGE (mV)
VC PIN VOLTAGE (V)
1738 G05
CS Pin Trip Voltage and CS Fault
Voltage vs Temperature
1.4
200
180
160
140
120
ON
1.40
1.35
1.30
TRIP
0.2
0
–50 –25
–500
–400 –300 –200 –100 0 100 200 300 400
FEEDBACK PIN VOLTAGE FROM NOMINAL (mV)
1738 G04
VC Pin Threshold and Clamp
Voltage vs Temperature
1.2
125°C
–100
–200
25 50 75 100 125 150
TEMPERATURE (°C)
25°C
0
1200
0
–40°C
100
1300
1000
–50 –25
NFB INPUT CURRENT (µA)
1.260
FB INPUT CURRENT (nA)
FEEDBACK VOLTAGE (V)
Feedback Voltage and Input
Current vs Temperature
OFF
100
0
25 50 75 100 125 150
TEMPERATURE (°C)
1738 G06
80
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
1738 G07
1.25
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
1738 G08
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TYPICAL PERFOR A CE CHARACTERISTICS
SHDN Pin Hysteresis Current vs
Temperature
27
21
19
17
0
25 50 75 100 125 150
TEMPERATURE (°C)
VIN = 20 RVSL, RCSL = 17k
14
13
VIN = 12 RVSL, RCSL = 17k
0.2
GATE DRIVE A/B PIN VOLTAGE (V)
PERCENT OF MAX CS VOLTAGE
80
70
60
40
60
DUTY CYCLE (%)
80
100
10.6
GCL = 12V
10.5
6.5
0.50
6.4
0.45
6.2
10.3
6.1
VIN = 12V
NO LOAD
10.2
6.0
10.1
5.9
10.0
5.8
GCL = 6V
9.90
5.7
9.80
5.6
9.70
–50 –25
9.3
0.25
0.20
0.15
0.10
0.05
5.5
0
25 50 75 100 125 150
TEMPERATURE (°C)
0
–50 –25
V5 Voltage vs Load Current
5.08
5.06
8.7
8.5
8.3
8.1
7.9
6.4
7.7
0
25 50 75 100 125 150
TEMPERATURE (°C)
1738 G15
25 50 75 100 125 150
TEMPERATURE (°C)
SS VOLTAGE = 0.9V
8.9
6.5
6.3
–50 –25
0
1738 G14
V5 PIN VOLTAGE (V)
6.6
VIN = 12V
NO LOAD
0.30
9.1
SS PIN CURRENT (µA)
7.1
120
0.35
9.5
GCL = 6V
6.7
100
0.40
Soft-Start Current vs Temperature
7.3
6.8
40
60
80
CS PIN VOLTAGE (mV)
1738 G13
Gate Drive Undervoltage Lockout
Voltage vs Temperature
6.9
20
1738 G11
6.3
10.4
1738 G12
7.0
0
Gate Drive Low Voltage vs
Temperature
10.7
90
7.2
0
Gate Drive High Voltage vs
Temperature
VC PIN = 0.9V
TA = 25°C
20
0.6
1738 G10
110
0
0.8
11 USING LOAD OF FIGURE 1A
fOSC = 120kHz
10
–50 –25 0
25 50 75 100 125 150
TEMPERATURE (°C)
Slope Compensation
50
1.0
0.4
1738 G09
100
1.2
12
GATE DRIVE A/B PIN VOLTAGE (V)
15
–50 –25
15
VC PIN VOLTAGE (V)
16
23
TA = 25°C
1.4
VIN = 12 RVSL, RCSL = 4.85k
17
VIN CURRENT (mA)
SHDN PIN CURRENT (µA)
1.6
18
25
VIN PIN VOLTAGE (V)
CS Pin to VC Pin Transfer
Function
VIN Current vs Temperature
7.5
–50 –25
T = 125°C
5.04
5.02
T = 25°C
5.00
T = –40°C
4.98
0
25 50 75 100 125 150
TEMPERATURE (°C)
1738 G16
4.96
–15
–10
–5
0
5
LOAD CURRENT (mA)
10
15
1738 G17
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LT1738
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Part Supply
V5 (Pin 5): This pin provides a 5V output that can sink or
source 10mA for use by external components. V5 source
current comes from VIN . Sink current goes to GND. VIN
must be greater than 6.5V in order for this voltage to be in
regulation. If this pin is used, a small capacitor (<1µF) may
be placed on this pin to reduce noise. This pin can be left
open if not used.
GND (Pin 11): Signal Ground. The internal error amplifier,
negative feedback amplifier, oscillator, slew control circuitry, V5 regulator, current sense and the bandgap reference are referred to this ground. Keep the connection to
this pin, the feedback divider and VC compensation network free of large ground currents.
SHDN (Pin 14): The shutdown pin can disable the switcher.
Grounding this pin will disable all internal circuitry.
Increasing SHDN voltage will initially turn on the internal
bandgap regulator. This provides a precision threshold for
the turn on of the rest of the IC. As SHDN increases past
1.39V the internal LDO regulator turns on, enabling the
control and logic circuitry.
24µA of current is sourced out of the pin above the turn on
threshold. This can be used to provide hysteresis for the
shutdown function. The hysteresis voltage will be set by
the Thevenin resistance of the resistor divider driving this
pin times the current sourced out. Above approximately
2.1V the hysteresis current is removed. There is approximately 0.1V of voltage hysteresis on this pin as well.
The pin can be tied high (to VIN for instance).
PGND (Pin 20): Power Driver Ground. This ground comes
from the MOSFET gate driver. This pin can have several
hundred milliamperes of current on it when the external
MOSFET is being turned off.
Oscillator
SYNC (Pin 6): The SYNC pin can be used to synchronize
the part to an external clock. The oscillator frequency
should be set close to the external clock frequency.
Synchronizing the clock to an external reference is useful
for creating more stable positioning of the switcher voltage and current harmonics. This pin can be left open or
tied to ground if not used.
CT (Pin 7): The oscillator capacitor pin is used in conjunction with RT to set the oscillator frequency. For RT = 16.9k:
COSC(nf) = 129/fOSC(kHz)
RT (Pin 8): A resistor to ground sets the charge and
discharge currents of the oscillator capacitor. The nominal value is 16.9k. It is possible to adjust this resistance
±25% to set oscillator frequency more accurately.
Gate Drive
GATE (Pin 1): This pin connects to the gate of an external
N-channel MOSFET. This driver is capable of sinking and
sourcing at least 300mA.
The GCL pin sets the upper voltage of the gate drive. The
GATE pin will not be activated until VIN reaches a minimum
voltage as defined by the GCL pin (gate undervoltage
lockout).
VIN (Pin 17): Input Supply. All supply current for the part
comes from this pin including gate drive and V5 regulator.
Charge current for gate drive can produce current pulses
of hundreds of milliamperes. Bypass this pin with a low
ESR capacitor.
The gate drive output has current limit protection to safe
guard against accidental shorts.
When VIN is below 2.55V the part will go into supply
undervoltage lockout where the gate driver is driven low.
This, along with gate drive undervoltage lockout, prevents
unpredictable behavior during power up.
If the pin is tied to a zener or a voltage source, the
maximum gate drive voltage will be approximately VGCL
– 0.2V. If it is tied to VIN, the maximum gate voltage is
approximately VIN – 1.6.
GCL (Pin 3): This pin sets the maximum gate voltage to the
GATE pin to the MOSFET gate drive. This pin should be
either tied to a zener, a voltage source, or VIN.
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LT1738
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Approximately 50µA of current can be sourced from this
pin if VGCL < VIN – 0.8V.
This pin also controls undervoltage lockout of the gate
drive. If the pin is tied to a zener or voltage source, the gate
drive will not be enabled until VIN > VGCL + 0.8V. If this pin
is tied to VIN, then undervoltage lockout is disabled.
There is an internal 19V zener tied from this pin to ground
to provide a fail-safe for maximum gate voltage.
Slew Control
CAP (Pin 2): This pin is the feedback node for the external
voltage slewing capacitor. Normally a small 1pf to 5pf
capacitor is connected from this pin to the drain of the
MOSFET.
The voltage slew rate is inversely proportional to this
capacitance and proportional to the current that the part
will sink and source on this pin. That current is inversely
proportional to RVSL.
RCSL (Pin 15): A resistor to ground sets the current slew
rate for the external drive MOSFET during switching. The
minimum resistor value is 3.3k and the maximum value is
68k. The time to slew between on and off states of the
MOSFET current will determine how the di/dt related
harmonics are reduced. This time is proportional to RCSL
and RS (the current sense resistor) and maximum current.
Longer times produce a greater reduction of higher frequency harmonics.
RVSL (Pin 16): A resistor to ground sets the voltage slew
rate for the drain of the external drive MOSFET. The
minimum resistor value is 3.3k and the maximum value is
68k. The time to slew between on and off states on the
MOSFET drain voltage will determine how dv/dt related
harmonics are reduced. This time is proportional to RVSL,
CV and the input voltage. Longer times produce more
rolloff of harmonics. CV is the equivalent capacitance from
CAP to the drain of the MOSFET.
Switch Mode Control
SS (Pin 3): The SS pin allows for ramping of the switch
current threshold at startup. Normally a capacitor is placed
on this pin to ground. An internal 9µA current source will
charge this capacitor up. The voltage on the VC pin cannot
exceed the voltage on SS. Thus peak current will ramp up
as the SS pin ramps up. During a short circuit fault the SS
pin will be discharged to ground thus reinitializing softstart.
When SS is below the VC clamp voltage the VC pin will
closely track the SS pin.
This pin can be left open if not used.
CS (Pin 4): This is the input to the current sense amplifier.
It is used for both current mode control and current
slewing of the external MOSFET. Current sense is accomplished via a sense resistor (RS) connected from the
source of the external MOSFET to ground. CS is connected
to the top of RS. Current sense is referenced to the GND
pin.
The switch maximum operating current will be equal to
0.1V/RS. At CS = 0.1V, the gate driver will be immediately
turned off (no slew control).
If CS = 0.22V in addition to the drivers being turned off, VC
and SS will be discharged to ground (short-circuit protection). This will hasten turn off on subsequent cycles.
FB (Pin 9): The feedback pin is used for positive voltage
sensing. It is the inverting input to the error amplifier. The
noninverting input of this amplifier connects internally to
a 1.25V reference.
If the voltage on this pin exceeds the reference by 220mV,
then the output driver will immediately turn off the external
MOSFET (no slew control). This provides for output overvoltage protection
When this input is below 0.9V then the current sense
blanking will be disabled. This will assist start up.
NFB (Pin 10): The negative feedback pin is used for
sensing a negative output voltage. The pin is connected to
the inverting input of the negative feedback amplifier
through a 100k source resistor. The negative feedback
amplifier provides a gain of –0.5 to the FB pin. The nominal
regulation point would be –2.5V on NFB. This pin should
be left open if not used.
If NFB is being used then overvoltage protection will occur
at 0.44V below the NFB regulation point.
At NFB < –1.8 current sense blanking will be disabled.
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TEST CIRCUITS
VC (Pin 12): The compensation pin is used for frequency
compensation and current limiting. It is the output of the
error amplifier and the input of the current comparator.
Loop frequency compensation can be performed with an
RC network connected from the VC pin to ground. The
voltage on VC is proportional to the switch peak current.
The normal range of voltage on this pin is 0.25V to 1.27V.
However, during slope compensation the upper clamp
voltage is allowed to increase with the compensation.
During a short-circuit fault the VC pin will be discharged to
ground.
0.9A
20mA
5pF
5pF
IN5819
IN5819
CAP
CAP
GATE
GATE
Si4450DY
ZVN3306A
2
CS
+
–
10
0.1
10
+
–
1738 F01b
1738 F01a
Figure 1a. Typical Test Circuitry Figure 1b. Test Circuit for Slew
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BLOCK DIAGRA
SHDN
VIN
V5
RCSL
RVSL
14
17
5
15
16
TO
DRIVERS
+
REGULATOR
NEGATIVE
FEEDBACK
AMP
–
100k
3 GCL
VREG
50k
NFB 10
2 CAP
–
FB 9
+
1 GATE
ERROR
AMP
SLEW
CONTROL
+
1.25V
VC 12
20 PGND
–
+
COMP
SS 13
4 CS
SENSE
AMP
+
–
S
Q
FF
RT 8
R
OSCILLATOR
SUB
CT 7
6
11
SYNC
GND
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LT1738
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OPERATIO
In noise sensitive applications switching regulators tend
to be ruled out as a power supply option due to their
propensity for generating unwanted noise. When switching supplies are required due to efficiency or input/output
constraints, great pains must be taken to work around the
noise generated by a typical supply. These steps may
include pre and post regulator filtering, precise synchronization of the power supply oscillator to an external clock,
synchronizing the rest of the circuit to the power supply
oscillator or halting power supply switching during noise
sensitive operations. The LT1738 greatly simplifies the
task of eliminating supply noise by enabling the design of
an inherently low noise switching regulator power supply.
transconductance amplifier that integrates the difference
between the feedback output voltage and an internal
1.25V reference. The output of the error amp adjusts the
switch current trip point to provide the required load
current at the desired regulated output voltage. This
method of controlling current rather than voltage provides faster input transient response, cycle-by-cycle
current limiting for better output switch protection and
greater ease in compensating the feedback loop. The VC
pin is used for loop compensation and current limit
adjustment. During normal operation the VC voltage will
be between 0.25V and 1.27V. An external clamp on VC or
SS may be used for lowering the current limit.
The LT1738 is a fixed frequency, current mode switching
regulator with unique circuitry to control the voltage and
current slew rates of the output switch. Current mode
control provides excellent AC and DC line regulation and
simplifies loop compensation.
The negative voltage feedback amplifier allows for direct
regulation of negative output voltages. The voltage on the
NFB pin gets amplified by a gain of – 0.5 and driven on to
the FB input, i.e., the NFB pin regulates to –2.5V while the
amplifier output internally drives the FB pin to 1.25V as in
normal operation. The negative feedback amplifier input
impedance is 100k (typ) referred to ground.
Slew control capability provides much greater control
over the power supply components that can create conducted and radiated electromagnetic interference. Compliance with EMI standards will be an easier task and will
require fewer external filtering components.
The LT1738 uses an external N-channel MOSFET as the
power switch. This allows the user to tailor the drive
conditions to a wide range of voltages and currents.
CURRENT MODE CONTROL
Referring to the block diagram. A switching cycle begins
with an oscillator discharge pulse, which resets the RS
flip-flop, turning on the GATE driver and the external
MOSFET. The switch current is sensed across the external
sense resistor and the resulting voltage is amplified and
compared to the output of the error amplifier (VC pin). The
driver is turned off once the output of the current sense
amplifier exceeds the voltage on the VC pin. In this way
pulse by pulse current limit is achieved.
Internal slope compensation is provided to ensure stability under high duty cycle conditions.
Output regulation is obtained using the error amp to set
the switch current trip point. The error amp is a
Soft-Start
Control of the switch current during start up can be
obtained by using the SS pin. An external capacitor from
SS to ground is charged by an internal 9µA current source.
The voltage on VC cannot exceed the voltage on SS. Thus
as the SS pin ramps up the VC voltage will be allowed to
ramp up. This will then provide for a smooth increase in
switch maximum current. SS will be discharged as a result
of the CS voltage exceeding the short circuit threshold of
approximately 0.22V.
Slew Control
Control of output voltage and current slew rates is achieved
via two feedback loops. One loop controls the MOSFET
drain dV/dt and the other loop controls the MOSFET dI/dt.
The voltage slew rate uses an external capacitor between
CAP and the MOSFET drain. This integrating cap closes the
voltage feedback loop. The external resistor RVSL sets the
current for the integrator. The voltage slew rate is thus
inversely proportional to both the value of capacitor and
RVSL.
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The current slew feedback loop consists of the voltage
across the external sense resistor, which is internally
amplified and differentiated. The derivative is limited to a
value set by RCSL. The current slew rate is thus inversely
proportional to both the value of sense resistor and RCSL.
The two control loops are combined internally so that a
smooth transition from current slew control to voltage
slew control is obtained. When turning on, the driver
current will slew before voltage. When turning off, voltage
will slew before current. In general it is desirable to have
RVSL and RCSL of similar value.
Internal Regulator
Most of the control circuitry operates from an internal 2.4V
low dropout regulator that is powered from VIN. The
internal low dropout design allows VIN to vary from 2.7V
to 20V with stable operation of the controller. When SHDN
< 1.3V the internal regulator is completely disabled.
5V Regulator
A 5V regulator is provided for powering external circuitry.
This regulator draws current from VIN and requires VIN to
be greater than 6.5V to be in regulation. It can sink or
source 10mA. The output is current limited to prevent
against destruction from accidental short circuits.
Safety and Protection Features
There are several safety and protection features on the
chip. The first is overcurrent limit. Normally the gate driver
will go low when the output of the internal sense amplifier
exceeds the voltage on the VC pin. The VC pin is clamped
such that maximum output current is attained when the CS
pin voltage is 0.1V. At that level the outputs will be
immediately turned off (no slew). The effect of this control
is that the output voltage will foldback with overcurrent.
In addition, if the CS voltage exceeds 0.22V, the VC and SS
pins will be discharged to ground, resetting the soft-start
function. Thus if a short is present this will allow for faster
MOSFET turnoff and less MOSFET stress.
If the voltage on the FB pin exceeds regulation by approximately 0.22V, the outputs will immediately go low. The
implication is that there is an overvoltage fault.
The voltage on GCL determines two features. The first is
the maximum gate drive voltage. This will protect the
MOSFET gate from overvoltage.
With GCL tied to a zener or an external voltage source then
the maximum gate driver voltage is approximately
VGCL␣ – 0.2V. If GCL is tied to VIN, then the maximum gate
voltage is determined by VIN and is approximately
VIN – 1.6V. There is an internal 19V zener on the GCL pin
that prevents the gate driver pin from exceeding approximately 19V.
In addition, the GCL voltage determines undervoltage
lockout of the gate drive. This feature disables the gate
driver if VIN is too low to provide adequate voltage to turn
on the MOSFET. This is helpful during start up to insure the
MOSFET has sufficient gate drive to saturate.
If GCL is tied to a voltage source or zener less than 6.8V,
the gate driver will not turn on until VIN exceeds GCL
voltage by 0.8V. For VGCL above 6.5V, the gate drive is
insured to be off for VIN < 7.3V and it will be turned on by
VGCL + 0.8V.
If GCL is tied to VIN, the gate driver is always on
(undervoltage lockout is disabled).
The gate drive has current limits for the drive currents. If
the sink or source current is greater than 300mA then the
current will be limited.
The V5 regulator also has internal current limiting that will
only guarantee ±10mA output current.
There is also an on chip thermal shutdown circuit that will
turn off the output in the event the chip temperature rises
to dangerous levels. Thermal shutdown has hysteresis
that will cause a low frequency (<1kHz) oscillation to occur
as the chip heats up and cools down.
The chip has an undervoltage lockout feature that will
force the gate driver low in the event that VIN drops below
2.5V. This insures predictable behavior during start up and
shut down. SHDN can be used in conjuction with an
external resistor divider to completely disable the part if
the input voltage is too low. This can be used to insure
adequate voltage to reliably run the converter. See the
section in Applications Information.
Table 1 summarizes these features.
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Table 1. Safety and Protection Features
FEATURE
FUNCTION
EFFECT on GATE DRIVER
SLEW CONTROL EFFECT on VC, SS
Maximum Current Fault
Turn Off FET at Maximum
Switch Current (VSENSE = 0.1)
Immediately Goes Low
Overridden
None
Short-Circuit Fault
Turn Off FET and Reset VC
for Short-Circuit (VSENSE = 0.22)
Immediately Goes Low
Overridden
Discharge VC, SS
to GND
Overvoltage Fault
Turn Off Driver If FB > VREG + 0.22V
(Output Overvoltage)
Immediately Goes Low
Overridden
None
GCL Clamp
Set Max Gate Voltage to Prevent
FET Gate Breakdown
Limits Max Voltage
None
None
Gate Drive
Undervoltage Lockout
Disable Gate Drive When VIN
Is Too Low. Set Via GCL Pin
Immediately Goes Low
Overridden
None
Thermal Shutdown
Turn Off Driver If Chip
Temperature Is Too Hot
Immediately Goes Low
Overridden
None
VIN Undervoltage Lockout
Disable Part When VIN ≅ 2.55V
Immediately Goes Low
Overridden
None
Gate Drive Source and Sink Current Limit
Limit Gate Drive Current
Limit Drive Current
None
None
V5 Source/Sink Current Limit
Limit Current from V5
None
None
None
Shutdown
Disable Part When SHDN <1.3V
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Reducing EMI from switching power supplies has traditionally invoked fear in designers. Many switchers are
designed solely on efficiency and as such produce waveforms filled with high frequency harmonics that then
propagate through the rest of the system.
The LT1738 provides control over two of the more important variables for controlling EMI with switching inductive
loads: switch voltage slew rate and switch current slew
rate. The use of this part will reduce noise and EMI over
conventional switch mode controllers. Because these
variables are under control, a supply built with this part will
exhibit far less tendency to create EMI and less chance of
encountering problems during production.
It is beyond the scope of this data sheet to get into EMI
fundamentals. Application Note 70 contains much information concerning noise in switching regulators and
should be consulted.
to ensure oscillator frequency stability. The oscillator is of
a sawtooth design. A current defined by external resistor
RT is used to charge and discharge the capacitor CT . The
discharge rate is approximately ten times the charge rate.
By allowing the user to have control over both components, trimming of oscillator frequency can be more easily
achieved.
The external capacitance CT is chosen by:
C T (nF ) =
2180
f(kHz)• RT (kΩ)
where f is the desired oscillator frequency in kHz. For RT
equal to 16.9k, this simplifies to:
C T (nF ) =
129
f(kHz)
e.g., CT = 1.29nF for f = 100kHz
Oscillator Frequency
The oscillator determines the switching frequency and
therefore the fundamental positioning of all harmonics.
The use of good quality external components is important
Nominally RT should be 16.9k. Since it sets up current, its
temperature coefficient should be selected to compliment
the capacitor. Ideally, both should have low temperature
coefficients.
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Oscillator frequency is important for noise reduction in
two ways. First the lower the oscillator frequency the lower
the waveform’s harmonics, making it easier to filter them.
Second the oscillator will control the placement of the
output voltage harmonics which can aid in specific problems where you might be trying to avoid a certain frequency bandwidth.
Oscillator Sync
If a more precise frequency is desired (e.g., to accurately
place harmonics) the oscillator can be synchronized to an
external clock. Set the RC timing components for an
oscillator frequency 10% lower than the desired sync
frequency.
Drive the SYNC pin with a square wave (with greater than
2V amplitude). The rising edge of the sync square wave
will initiate clock discharge. The sync pulse should have a
minimum pulse width of 0.5µs.
Be careful in sync’ing to frequencies much different from
the part since the internal oscillator charge slope determines slope compensation. It would be possible to get into
subharmonic oscillation if the sync doesn’t allow for the
charge cycle of the capacitor to initiate slope compensation. In general, this will not be a problem until the sync
frequency is greater than 1.5 times the oscillator free-run
frequency.
Slew Rate Setting
The primary reason to use this part is to gain advantage of
lower EMI and noise due to the slew control. The rolloff in
higher frequency harmonics has its theoretical basis with
two primary components. First, the clock frequency sets
the fundamental positioning of harmonics and second, the
associated normal frequency rolloff of harmonics.
This part creates a second higher frequency rolloff of
harmonics that inversely depends on the slew time, the
time that voltage or current spends between the off state
and on state. This time is adjustable through the choice of
the slew resistors, the external resistors to ground on the
RVSL and RCSL pins and the external components used for
the external voltage feedback capacitor CV (from CAP to
the MOSFET drain) and the sense resistor. Lower slew
rates (longer slew times, lower rolloff frequency for harmonics ) are created with higher values of RVSL, RCSL, CV
and the current sense resistor.
Setting the voltage and current slew rates should be done
empirically. The most practical way of determining these
components is to set CV and the sense resistor value.
Then, start by making RVSL, RCSL each a 50k resistor pot
in series with 3.3k. Starting from the lowest resistor
setting (fast slew) adjust the pots until the noise level
meets your guidelines. Note that slower slewing waveforms will dissipate more power so that efficiency will
drop. You can monitor this as you make your slew adjustment by measuring input and output voltage and their
respective currents. Monitor the MOSFET temperature as
slew rates are slowed. The MOSFET will heat up as
efficiency decreases.
Measuring noise should be done carefully. It is easy to
introduce noise by poor measurement techniques. Consult AN70 for recommended measurement techniques.
Keeping probe ground leads very short is essential.
Usually it will be desirable to keep the voltage and current
slew resistors approximately the same. There are circumstances where a better optimization can be found by
adjusting each separately, but as these values are separated further, a loss of independence of control may occur.
It is possible to use a single slew setting resistor. In this
case the RVSL and RCSL pins are tied together. A resistor
with a value of 1.8k to 34k (one half the individual resistors) can then be tied from these pins to ground.
In general only the RCSL value will be available for adjustment of current slew. The current slew time also depends
on the current sense resistor but this resistor is normally
set with consideration of the maximum current in the
MOSFET.
Setting the voltage slew also involves selection of the
capacitor CV. The voltage slew time is proportional to the
output voltage swing (basically input voltage), the external
voltage feedback capacitor and the RVSL value. Thus at
higher input voltages smaller capacitors will be used with
lower RVSL values. For a starting point use Table␣ 2.
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R1
Table 2
VOUT
FB PIN
INPUT VOLTAGE
CAPACITOR VALUE
< 25V
R2
5pF
50V
2.5pF
100V
1pF
Smaller value capacitors can be made in two ways. The
first is simply combining two capacitors in series. The
equivalent capacitance is then (C1 • C2)/(C1 + C2).
The second method makes use of a capacitor divider. Care
should be taken that the voltage rating of the capacitor
satisfies the full voltage swing thus essentially the same
rating as the MOSFET.
The equivalent slew capacitance for Figure 2 is
(C1 • C2)/(C1 + C2 + C3).
MOSFET DRAIN
C2
1738 F03
Figure 3
Negative Output Voltage Setting
Negative output voltage can be sensed using the NFB pin.
In this case regulation will occur when the NFB pin is at
–2.5V. The nominal input bias current for the NFB is –25µA
(INFB), which needs to be accounted for in setting up the
divider.
Referring to Figure 4, R1 is chosen such that:
 VOUT − 2.5 
R1 = R2 

 2.5 + R2 • 25µA 
C1
CAP
C3
A suggested value for R2 is 2.5k. The NFB pin is normally
left open if the FB pin is being used.
1738 F02
R1
Figure 2
INFB
Positive Output Voltage Setting
Sensing of a positive output voltage is usually done using
a resistor divider from the output to the FB pin. The
positive input to the error amp is connected internally to a
1.25V bandgap reference. The FB pin will regulate to this
voltage.
Referring to Figure 3, R1 is determined by:
V

R1 = R2  OUT − 1
 1.25 
The FB bias current represents a small error and can
usually be ignored for values of R1||R2 up to 10k.
One word of caution, sometimes a feedback zero is added
to the control loop by placing a capacitor across R1. If the
feedback capacitively pulls the FB pin above the internal
regulator voltage (2.4V), output regulation may be disrupted. A series resistance with the feedback pin can
eliminate this potential problem. There is an internal clamp
on FB that clamps at 0.7V above the regulation voltage that
should also help prevent this problem.
–VOUT
NFB PIN
R2
1738 F04
Figure 4
Dual Polarity Output Voltage Sensing
Certain applications may benefit from sensing both positive and negative output voltages. When doing this each
output voltage resistor divider is individually set as previously described. When both FB and NFB pins are used, the
LT1738 will act to prevent either output from going
beyond its set output voltage. The highest output (lightest
load) will dominate control of the regulator. This technique
would prevent either output from going unregulated high
at no load. However, this technique will also compromise
output load regulation.
Shutdown
If SHDN is pulled low, the regulator will turn off. As the
SHDN pin voltage is increased from ground the internal
bandgap regulator will be powered on. This will set a 1.39V
threshold for turn on of the internal regulator that runs
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most of the control circuitry of the regulator. Note after the
control circuitry powers on, gate driver activity will depend
on the voltage of VIN with respect to the voltage on GCL.
As the SHDN pin enables the internal regulator a 24µA
current will be sourced from the pin that can provide
hysteresis for undervoltage lockout. This hysteresis can
be used to prevent part shutdown due to input voltage sag
from an initial high current draw.
Frequency Compensation
Loop frequency compensation is accomplished by way of
a series RC network on the output of the error amplifier
(VC␣ pin).
VC PIN
RVC
2k
CVC2
4.7nF
CVC
0.01µF
In addition to the current hysteresis, there is also approximately 100mV of voltage hysteresis on the SHDN pin.
When the SHDN pin is greater than 2.2V, the hysteretic
current from the part will be reduced to essentially zero.
If a resistor divider is used to set the turn on threshold then
the resistors are determined by the following equations:
 RA + RB 
VON = 
 •V
 RB  SHDN
VHYST
 ∆V

= RA •  SHDN + ISHDN
 RA RB

VIN
RA
SHDN
RB
Reworking these equations yields:
(VHYST • VSHDN − VON • ∆VSHDN)
RA =
(ISHDN • VSHDN)
(VHYST • VSHDN − VON • ∆VSHDN)
RB =
[ISHDN • (VON − VSHDN)]
So if we wanted to turn on at 20V with 2V of hysteresis:
2V • 1.39V − 20V • 0.1V
= 23.4k
24µA • 1.39V
2V • 1.39V − 20V • 0.1V
RB =
= 1.75k
24µA • (20V − 1.39V )
RA =
Resistor values could be altered further by adding zeners
in the divider string. A resistor in series with SHDN pin
could further change hysteresis without changing turn on
voltage.
1738 F05
Figure 5
Referring to Figure 5, the main pole is formed by capacitor
CVC and the output impedance of the error amplifier
(approximately 400kΩ). The series resistor RVC creates a
“zero” which improves loop stability and transient response. A second capacitor CVC2, typically one-tenth the
size of the main compensation capacitor, is sometimes
used to reduce the switching frequency ripple on the VC
pin. VC pin ripple is caused by output voltage ripple
attenuated by the output divider and multiplied by the error
amplifier. Without the second capacitor, VC pin ripple is:
VCPINRIPPLE =
1.25 • VRIPPLE • gm • RVC
VOUT
where VRIPPLE = Output ripple (VP-P )
gm = Error amplifier transconductance
RVC = Series resistor on VC pin
VOUT = DC output voltage
To prevent irregular switching, VC pin ripple should be
kept below 50mVP-P . Worst-case VC pin ripple occurs at
maximum output load current and will also be increased if
poor quality (high ESR) output capacitors are used. The
addition of a 0.0047µF capacitor for CVC2 pin reduces
switching frequency ripple to only a few millivolts. A low
value for RVC will also reduce VC pin ripple, but loop phase
margin may be inadequate.
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Setting Current Limit
The sense resistor sets the value for maximum operating
current. When the CS pin voltage is 0.1V the gate driver
will immediately go low (no slew control). Therefore the
sense resistor value should be set to RS = 0.1V/ISW(PEAK),
where ISW(PEAK) is the peak current in the MOSFET.
ISW(PEAK) will depend on the topology and component
values and tolerances. Certainly it should be set below the
saturation current value for the inductor.
If the CS pin voltage is 0.22V in addition to the driver going
low, VC and SS will be discharged to ground. This is to
provide additional protection in the event of a short circuit.
By discharging VC and SS the MOSFET will not be stressed
as hard on subsequent cycles since the current trip will be
set lower.
Turn off of the MOSFET will normally be inhibited for about
100ns at the start of every turn on cycle. This is to prevent
noise from interfering with normal operation of the controller. This current sense blanking does not prevent the outputs from being turned off in the event of a fault. Slewing
of the gate voltage effectively provides additional blanking.
Traces to the SENSE resistor should be kept short and wide
to minimize resistance and inductance. Large interwinding
capacitance in the transformer or high capacitance on the
drain of the MOSFET will produce a current pulse through
the sense resistor during drain voltage slewing. The magnitude of the pulse is C • dV/dt where C is the capacitance
and dV/dt is the voltage slew rate which is controlled by the
part. This pulse will increase the sensed current on switch
turn on and if large enough can cause premature MOSFET
turn off. If this occurs, the inductor transformer may need
a different winding technique (see AN39) or alternatively,
a blanking circuit can be used. Please contact the LTC applications group for support if required.
Soft-Start
The soft-start pin is used to provide control of switching
current during startup. The maximum voltage on the VC
pin is approximately the voltage on the SS pin. A current
source will linearly charge a capacitor on the SS pin. The
VC pin voltage will thus ramp up also. The approximate
time for the voltage on these pins to ramp up is
(1.31V/9µA) • CSS or approximately 146ms per µF.
The soft-start current will be initiated as soon as the part
turns on. Soft-start will be reinititated after a short-circuit
fault.
Thermal Considerations
Most of the IC power dissipation is derived from the VIN
pin. The VIN current depends on a number of factors
including: oscillator frequency; loads on V5; slew settings;
gate charge current. Additional power is dissipated if V5
sinks current and during the MOSFET gate discharge.
The power dissipation in the IC will be the sum of:
1) The RMS VIN current times VIN
2) V5 RMS sink current times 5V
3) The gate drive’s RMS discharge current times voltage.
Because of the strong VIN component it is advantageous
to operate the LT1738 at as low a VIN as possible.
It is always recommended that package temperature be
measured in each application. The part has an internal
thermal shutdown to minimize the chance of IC destruction but this should not replace careful thermal design.
The thermal shutdown feature does not protect the external MOSFET. A separate analysis must be done for this
device to insure that it is operating within safe limits.
Once IC power dissipation, PDIS, is determined die junction temperature is then computed as:
TJ = TAMB + PDIS • θJA
where TAMB is ambient temperature and θJA is the package
thermal resistance. For the 20-pin SSOP, θJA is 100°C/W.
Choosing The Inductor
For a boost converter, inductor selection involves tradeoffs of size, maximum output power, transient response
and filtering characteristics. Higher inductor values provide more output power and lower input ripple. However,
they are physically larger and can impede transient response. Low inductor values have high magnetizing current, which can reduce maximum power and increase
input current ripple.
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The following procedure can be used to handle these
trade-offs:
1. Assume that the average inductor current for a boost
converter is equal to load current times VOUT/VIN and
decide whether the inductor must withstand continuous overload conditions. If average inductor current at
maximum load current is 0.5A, for instance, a 0.5A
inductor may not survive a continuous 1.5A overload
condition. Also be aware that boost converters are not
short-circuit protected, and under output short conditions, only the available current of the input supply
limits inductor current.
2. Calculate peak inductor current at full load current to
ensure that the inductor will not saturate. Peak current
can be significantly higher than output current, especially with smaller inductors and lighter loads, so don’t
omit this step. Powdered iron cores are forgiving
because they saturate softly, whereas ferrite cores saturate abruptly. Other core materials fall in between. The
following formula assumes continuous mode operation but it errs only slightly on the high side for discontinuous mode, so it can be used for all conditions.
V
VIN (VOUT – VIN ) 
IPEAK = IOUT  OUT +
2 • L • f • VOUT 
 VIN
L = inductance value
VIN = supply voltage
VOUT = output voltage
I = output current
f = oscillator frequency
3. Choose a core geometry. For low EMI problems a
closed structure should be used such as a pot core, ER
core or toroid (see AN70 appendix I).
4. Select an inductor that can handle peak current,
average current (heating effects) and fault current.
5. Finally, double check output voltage ripple.
The experts in the Linear Technology Applications department have experience with a wide range of inductor types
and can assist you in making a good choice.
Capacitors
Correct choice of input and output capacitors can be very
important to low noise switcher performance. Noise depends more on the ESR of the capacitors. In addition lower
ESR can also improve efficiency.
Input capacitors must also withstand surges that occur
during the switching of some types of loads. Some solid
tantalum capacitors can fail under these surge conditions.
Design Note 95 offers more information but the following
is a brief summary of capacitor types and attributes.
Aluminum Electrolytic: Low cost and higher voltage. They
will typically only be used for higher voltage applications.
Large values will be needed for low ESR.
Specialty Polymer Aluminum: Panasonic has come out
with their series CD capacitors. While they are only available for voltages below 16V, they have very low ESR and
good surge capability.
Solid Tantalum: Small size and low impedance. Typically
the maximum voltage rating is 50V. With large surge
currents the capacitor may need to be derated or you need
a special type such as the AVX TPS line.
OS-CON: Lower impedance than aluminum but only available for 35V or less. Form factor may be a problem.
Ceramic: Generally used for high frequency and high
voltage bypass. They may resonate with their ESL before
ESR becomes dominant. Recent multilayer ceramic (MLC)
capacitors provide larger capacitance with low ESR.
There are continuous improvements being made in capacitors so consult with manufacturers as to your specific
needs.
Input Capacitors
The input capacitor should have low ESR at high frequencies since this will be an important factor concerning how
much conducted noise is generated.
There are two separate requirements for input capacitors.
The first is for the supply to the part’s VIN pin. The VIN pin
will provide current for the part itself and the gate charge
current.
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The worst component from an AC point is the gate charge
current. The actual peak current depends on gate capacitance and slew rate, being higher for larger values of each.
The total current can be estimated by gate charge and
frequency of operation. Because of the slewing with this
part gate charge is spread out over a longer time period
than with a normal FET driver. This reduces capacitance
requirements.
Typically the current will have spikes of under 100mA
located at the gate voltage transitions. This is charge/
discharge to and from the threshold voltage. Most slewing
occurs with the gate voltage near threshold.
Since the part’s VIN will typically be under 15V many
options are available for choice of capacitor. Values of
input capacitor for just the VIN requirement will typically be
in the 50µF range with an ESR of under 0.1Ω.
In addition to the part’s supply, decoupling of the supply
to the inductor needs to be considered. If this is the same
supply as the VIN pin then that capacitor will need to be
increased. However, often with this part the inductor
supply will be a higher voltage and as such will use a
separate capacitor.
The inductor’s decoupling capacitor will see the switch
current as ripple.
The above switch current computation can be used to
estimate the capacity for these capacitors.
CIN =
1
DC
• MIN
∆VCAP
f
− ESR
∆ISW(MAX)
where ∆VCAP is the allowed sag on the input capacitor.
ESR is the equivalent series resistance for the cap. In
general allowed sag will be a few tenths of a volt.
Output Filter Capacitor
The output capacitor is chosen both for capacity and ESR.
The capacity must supply the load current in the switch on
state. While slew control reduces higher frequency components of the ripple current in the capacitor, the capacitor
ESR and the magnitude of the output ripple current
controls the fundamental component. ESR should also be
low to reduce capacitor dissipation. Typically ESR should
be below 0.05Ω.
The capacitance value can be computed by consideration
of desired load ripple, duty cycle and ESR.
C OUT =
1
∆VOUT
− ESR
∆IL(MAX)
•
DC MIN
f
MOSFET Selection
There is a wide variety of MOSFETs to choose from for this
part. The part will work with either normal threshold (3V to
4V) or logic level threshold devices (1V to 2V).
Select a voltage rating to insure under worst-case conditions that the MOSFET will not break down. Next choose an
RON sufficiently low to meet both the power dissipation
capabilities of the MOSFET package as well as overall
efficiency needs of the converter.
The LT1738 can handle a large range of gate charges.
However at very large charge stability may be affected.
The power dissipation in the MOSFET depends on several
factors. The primary element is I2R heating when the
device is on. In addition, power is dissipated when the
device is slewing. An estimate for power dissipation is:

∆I2

I2 +

4 +
P = VIN •
I
SR



• f + I2 • RON • DC
 2
3 • ∆I2   
2 
 VIN − RON • I2 +
 
4   


• I
VSR



where I is the average current, ∆I is the ripple current in the
switch, ISR is the current slew rate, VSR is the voltage slew
rate, f is the oscillator frequency, DC is the duty cycle and
RON is the MOSFET on-resistance.
Setting GCL Voltage
Setting the voltage on the GCL pin depends on what type
of MOSFET is used and the desired gate drive undervoltage lockout voltage.
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LT1738
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APPLICATIO S I FOR ATIO
First determine the maximum gate drive that you require.
Typically you will want it to be at least 2V greater than the
rated threshold. Higher voltages will lower the on resistance and increase efficiency. Be certain to check the
maximum allowed gate voltage. Often this is 20V but for
some logic threshold MOSFETs it is only 8V to 10V.
VGCL needs to be set approximately 0.2V above the desired
max gate threshold. In addition VIN needs to be at least
1.6V above the gate voltage.
The GCL pin can be tied to VIN which will result in a
maximum gate voltage of VIN – 1.6V.
This pin also controls undervoltage lockout of the gate
drive. The undervoltage lockout will prevent the MOSFET
from switching until there is sufficient drive present.
If GCL is tied to a voltage source or zener less than 6.8V,
the gate drivers will not turn on until VIN exceeds the GCL
voltage by 0.8V. For VGCL above 6.5V, the gate drive is
insured to be off for VIN < 7.3V and they will be turned on
by VGCL + 0.8V.
If GCL is tied to VIN, the gate driver is always on
(undervoltage lockout is disabled).
Approximately 50µA of current can be sourced from this
pin if VIN > VGCL + 0.8V. This could be used to bias a zener.
The GCL pin has an internal 19V zener to ground that will
provide a failsafe for maximum gate voltage.
As an example say we are using a Siliconix Si4480DY
which has RDS(ON) rated at 6V. To get 6V, VGCL needs to
be set to 6.2V and VIN needs to be at least 7.6V.
Gate Driver Considerations
In general, the MOSFET should be positioned as close to
the part as possible to minimize inductance.
When the part is active the gate drive will be pulled low to
less than 0.2V. When the part is off, the gate drive contains
a 40k resistor in series with a diode to ground that will offer
passive holdoff protection. If you are using some logic
level MOSFETs this might not be sufficient. A resistor may
be placed from gate to ground, however the value should
be reasonably high to minimize DC losses and possible AC
issues.
The gate drive source current comes from VIN. The sink
current exits through PGND. In general the decoupling cap
should be placed close to these two pins.
Switching Diodes
In general, switching diodes should be Schottky diodes.
Size and breakdown voltage depend on the specific converter. A lower forward drop will improve converter efficiency. No other special requirements are needed.
PCB LAYOUT CONSIDERATIONS
As with any switcher, careful consideration should be given
to PC board layout. Because this part reduces high frequency EMI, the board layout is less critical. However, high
currents and voltages still produce the need for careful
board layout to eliminate poor and erratic performance.
Basic Considerations
Keep the high current loops physically small in area. The
main loops are shown in Figure 6: the power switch loops
(A) and the rectifier loop (B). These loops can be kept small
by physically keeping the components close to one another. In addition, connection traces should be kept wide
to lower resistance and inductances. Components should
be placed to minimize connecting paths. Careful attention
to ground connections must also be maintained. Be careful that currents from different high current loops do not
get coupled into the ground paths of other loops. Using
singular points of connection for the grounds is the best
way to do this. The two major points of connection are the
bottom of the input decoupling capacitor and the bottom
of the output decoupling capacitor. Typically, the sense
resistor device PGND and device GND will tie to the bottom
of the input capacitor.
VIN
CIN
•
A
•
B
COUT VOUT
GATE
CS
1738 F06
Figure 6
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There are two other loops to pay attention to. The current
slew involves a high bandwidth control that goes through
the MOSFET switch, the sense resistor and into the CS pin
of the part and out the GATE pin to the MOSFET. Trace
inductance and resistance should be kept low on the GATE
drive trace. The CS trace should have low inductance.
MORE HELP
AN70 contains information about low noise switchers and
measurement of noise and should be consulted. AN19 and
AN29 also have general knowledge concerning switching
regulators. Also, our Application Department is always
ready to lend a helping hand.
Finally, care should be taken with the CAP pin. The part will
tolerate stray capacitance to ground on this pin (<5pFs).
However, stray capacitance to the MOSFET drain should
be minimized. This path would provide an alternate capacitive path for the voltage slew.
U
PACKAGE DESCRIPTIO
G Package
20-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
6.90 – 7.50*
(.272 – .295 )
1.25 ±0.12
7.8 – 8.2
20 19 18 17 16 15 14 13 12 11
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8 9 10
5.00 – 5.60**
(.197 – .221)
2.0
(.079)
0° – 8°
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
0.65
(.0256)
BSC
0.22 – 0.38
(.009 – .015)
0.05
(.002)
G20 SSOP 0802
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT1738
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TYPICAL APPLICATIO
Ultralow Noise 30W Offline Power Supply
DANGER: HIGH VOLTAGE
L1
X1
+
1M
0.1µF
250VAC
“X2”
1M
90VAC
TO 264VAC
BR1
100µF
400V
P6KE200A
1
100k
2W
VBIAS
+
510k
17
56µF
35V
VIN
14
5
510k
6
1.8nF
7
165k
165k
10Ω
8
19.6k
2N2222
3.9k
3.9k
16
15
9
19
NC
D4
BA521
10
NFB
470pF
D1
A1
+VOUT
12V
2.5A
A2
MUR160
K
A
X3
12V
IN755 A
T1 11
3
6
7
12
5
8
C2
330µF
25V
+
C3
330µF
25V
+
+
C4
330µF
25V
– VOUT
5pF
600V
SHDN
V5
5pF
SYNC
CT
CAP
GATE
U3
LT1738
RT
CS
RVSL
NC
PGND
RCSL
VC
FB
GND
SS
13
11
10nF
2N2222
51k
2
1
MTP2N60E
0.1µF
4
18
20
12
0.068Ω
1/2W
6
ISO1
CNY17-3
3
VOUT
1k
0.22µF
1
2
COMP
V+
U2 REF 8
LT1431
4
COLL
RTOP
7
RMIO
G-F
G-S
6
5
3
5
2
GCL
3
1k
4
VBIAS
38.3k
1%
1k
10k
1%
1738 TA02
UNLESS OTHERWISE NOTED: ALL RESISTORS 1206, 5%
BR1: GENERAL INSTRUMENTS W06G
C2, C3, C4: SANYO MV-GX
D1: MBR20200CT
L1: HM18-10001
T1: PREMIER MAGNETICS POL-15033
NOTE: PIN 2 OF LT1738 MUST BE LAID OUT
AWAY FROM FAST SLEWING NODES
INPUT FILTER IS REQUIRED TO ATTENUATE SWITCHING FREQUENCY HARMONICS AND PASS FCC CLASS B (LT1738 DOES NOT ATTENUATE THESE LOW FREQUENCY HARMONICS)
MAIN ADVANTAGE WITH LT1738 IS IT MAKES SUPPRESSING THE HIGH FREQUENCY NOISE AND EMI EASY. THIS IS PARTICULARLY USEFUL FOR MEDICAL DEVICES BECAUSE
THE AC LINE TO EARTH GND CAPS ON THE INPUT FILTER CAN BE ELIMINATED; ALLOWING THE DEVICE TO PASS THE EARTH GND LEAKAGE CURRENT MEDICAL SPECIFICATIONS.
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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Ultralow Noise Push-Pull DC/DC Controller
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LT1425
Isolated Flyback Switching Regulator
Excellent Regulation without Transformer “Third Winding”
LT1533
Ultralow Noise 1A Switching Regulator
Push-Pull Design for Low Noise Isolated Supplies
LT1534
Ultralow Noise 2A Switching Regulator
Ultralow Noise Regulator for Boost Topologies
LT1576
1.5A, 200kHz Step-Down Switching Regulator
Constant Frequency, 1.21V Reference Voltage
LT176X Family
Low Dropout, Low Noise Linear Regulator
150mA to 3A, SOT-23 to TO-220
LT1777
Low Noise Step-Down Switching Regulator
Programmable dI/dt; Internally Limited dV/dt
LTC1922-1
Synchronous Phase Modulated Full-Bridge Controller
Adaptive DirectSenseTM Zero Voltage Switching, 50W to
Kilowatts, Synchronous Rectification
LT3439
Ultralow Noise Transformer Driver
1A Push-Pull DC/DC Transformer Driver
DirectSense is a trademark of Linear Technology Corporation.
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20
Linear Technology Corporation
LT/TP 1202 1K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2001