3.3V 256 K x 16-Bit Dynamic RAM HYB 314171BJ-50/-60/-70 3.3V Low Power 256 K x 16-Bit Dynamic RAM with Self Refresh HYB 314171BJL-50/-60/-70 Preliminary Information • • • 262 144 words by 16-bit organization 0 to 70 °C operating temperature Fast access and cycle time • RAS access time: 50 ns (-50 version) 60 ns (-60 version) 70 ns (-70 version) CAS access time: 15ns (-50,-60 version) 20 ns (-70 version) Cycle time: 95 ns (-50 version) 110 ns (-60 version) 130 ns (-70 version) Fast page mode cycle time 35 ns (-50 version) 40 ns (-60 version) 45 ns (-70 version) Single + 3.3 V (± 0.3 V) supply with a builtin VBB generator • • • • • • • • • • • • • • Low Power dissipation max. 450 mW active (-50 version) max. 378 mW active (-60 version) max. 306 mW active (-70 version) Standby power dissipation 7.2 mW standby (TTL) 3.6 mW max. standby (CMOS) 0.72 mW max. standby (CMOS) for Low Power Version Output unlatched at cycle end allows twodimensional chip selection Read, write, read-modify write, CASbefore-RAS refresh, RAS-only refresh, hidden-refresh and fast page mode capability 2 CAS / 1 WE control Self Refresh (L-Version) All inputs and outputs TTL-compatible 512 refresh cycles / 16 ms 512 refresh cycles / 128 ms Low Power Version only Plastic Packages: P-SOJ-40-1 400mil width The HYB 314171BJ/BJL is a 4 MBit dynamic RAM organized as 262 144 words by 16-bit. The HYB 314171BJ/BJL utilizes CMOS silicon gate process as well as advanced circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 314171BJ/BJL to be packed in a standard plastic 400mil wide P-SOJ-40-1 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include Self Refresh (LVersion), single + 3.3 V (± 0.3 V) power supply, direct interfacing with high performance logic device families. Semiconductor Group 1 7.96 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM Ordering Information Type Ordering Code Package Description HYB 314171BJ-50 on request P-SOJ-40-1 3.3V 50ns 256 K x 16 DRAM HYB 314171BJ-60 on request P-SOJ-40-1 3.3V 60 ns 256 K x 16 DRAM HYB 314171BJ-70 on request P-SOJ-40-1 3.3V 70 ns 256 K x 16 DRAM HYB 314171BJL-50 on request P-SOJ-40-1 3.3V 50 ns 256 K x 16 DRAM HYB 314171BJL-60 on request P-SOJ-40-1 3.3V 60 ns 256 K x 16 DRAM HYB 314171BJL-70 on request P-SOJ-40-1 3.3V 70 ns 256 K x 16 DRAM Truth Table RAS LCAS UCAS WE OE I/O1-I/O8 I/O9-I/O16 Operation H H H H H High-Z High-Z Standby L H H H H High-Z High-Z Refresh L L H H L Dout High-Z Lower byte read L H L H L High-Z Dout Upper byte read L L L H L Dout Dout Word read L L H L H Din Don't care Lower byte write L H L L H Don't care Din Upper byte write L L L L H Din Din Word write L L L H H High-Z High-Z Pin Names A0-A8 Address Inputs RAS Row Address Strobe UCAS, LCAS Column Address Strobe WE Read/Write Input OE Output Enable I/O1 – I/O16 Data Input/Output VCC Power Supply (+ 3.3 V) VSS Ground (0 V) N.C. No Connection Semiconductor Group 2 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM Pin Configuration (top view) P-SOJ-40-1 Semiconductor Group 3 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM Block Diagram Semiconductor Group 4 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM Absolute Maximum Ratings Operating temperature range ........................................................................................ 0 to + 70 °C Storage temperature range..................................................................................... – 55 to + 150 °C Input/output voltage .................................................................................... – 1 to (VCC + 0.5, 4.6) V Power supply voltage.................................................................................................. – 1 to + 4.6 V Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 5 ns Parameter Symbol Limit Values min. max. Unit Notes Input high voltage VIH 2.0 VCC + 0.5 V 1 Input low voltage VIL – 1.0 0.8 V 1 LVTTL Output high voltage (IOUT = – 2.0 mA) VOH 2.4 – V 1 LVTTL Output low voltage (IOUT = 2 mA) VOL – 0.4 V 1 LVCMOS Output high voltage (IOUT = – 100 µA) VOH 2.4 – V 1 LVCMOS Output low voltage (IOUT = 100 µA) VOL – 0.4 V 1 Input leakage current, any input (0 V < VIN < VCC + 0.3 V, all other inputs = 0 V) II(L) – 10 10 µA 1 Output leakage current (DO is disabled, 0 V < VOUT < VCC + 0.3 V ) IO(L) – 10 10 µA 1 Average VCC supply current: ICC1 – 125 105 85 mA 2, 3, 4 ICC2 – 2 mA -50 version -60 version -70 version Standby VCC supply current (RAS = LCAS = UCAS = WE = VIH) Average VCC supply current during RAS-only refresh cycles: -50 version -60 version -70 version Semiconductor Group – ICC3 5 2, 4 125 105 85 mA HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM DC Characteristics (cont’d) Parameter Symbol Limit Values min. Average VCC supply current during fast page mode operation: -50 version -60 version -70 version Standby VCC supply current (RAS = LCAS = UCAS = WE = VCC – 0.2 V) Average VCC supply current during CAS-before-RAS refresh mode: -50 version -60 version -70 version Unit Notes max. – 2, 3, 4 ICC4 ICC5 – 70 65 60 mA 1 mA – 1 2, 4 ICC6 125 105 85 mA Standby VCC current (L-version) (RAS = LCAS = UCAS = WE= VCC – 0.2 V) ICC5 – 200 µA Self Refresh Current (L-version) (RAS, LCAS, UCAS = 0.2 V A0 – A8 = VCC – 0.2 V or 0.2 V) ICCS – 250 µA Capacitance TA = 0 to 70 °C; VCC = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A8) CI1 – 6 pF Input capacitance (RAS, UCAS, LCAS, WE, OE) CI2 – 7 pF Output capacitance (l/O1 to l/O16) CIO – 7 pF Semiconductor Group 6 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM AC Characteristics 5)6) TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 5 ns Parameter Limit Values Symbol -50 Unit Note - 60 - 70 min. max. min. max. min. max. Common Parameters Random read or write cycle time tRC 95 – 110 – 130 – ns RAS precharge time tRP 35 – 40 – 50 – ns RAS pulse width tRAS 50 10k 60 10k 70 10k ns CAS pulse width tCAS 15 10k 15 10k 20 10k ns Row address setup time tASR 0 – 0 – 0 – ns Row address hold time tRAH 10 – 10 – 10 – ns Column address setup time tASC 0 – 0 – 0 – ns Column address hold time tCAH 10 – 15 – 15 – ns RAS to CAS delay time tRCD 20 35 20 45 20 50 ns RAS to column address delay time tRAD 15 25 15 30 15 35 ns RAS hold time tRSH 15 – 15 – 20 – ns CAS hold time tCSH 50 – 60 – 70 – ns CAS to RAS precharge time tCRP 5 – 5 – 5 – ns Transition time (rise and fall) tT 3 50 3 50 3 50 ns Refresh period tREF – 16 – 16 – 16 ms Refresh period (L-version) tREF – 128 – 128 – 128 ms Access time from RAS tRAC – 50 – 60 – 70 ns 8, 9 Access time from CAS tCAC – 15 – 15 – 20 ns 8, 9 – 25 – 30 – 35 ns 8,10 – 15 – 15 – 20 ns 25 – 30 – 35 – ns 7 Read Cycle Access time from column address tAA OE access time tOEA Column address to RAS lead time tRAL Read command setup time tRCS 0 – 0 – 0 – ns Read command hold time tRCH 0 – 0 – 0 – ns 11 Read command hold time ref. to RAS tRRH 0 – 0 – 0 – ns 11 CAS to output inlow-Z tCLZ 0 – 0 – 0 – ns 8 Semiconductor Group 7 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM Parameter Limit Values Symbol -50 Unit Note - 60 - 70 min. max. min. max. min. max. Output buffer turn-off delay from CAS tOFF 0 15 0 20 0 20 ns 12 Output buffer turn-off delay from OE tOEZ 0 15 0 20 0 20 ns 12 Data to OE low delay tDZO 0 – 0 – 0 – ns 13 CAS high to datadelay tCDD 15 – 20 – 20 – ns 14 OE high to data delay tODD 15 - 20 – 20 – ns 14 Write command hold time tWCH 10 – 10 – 15 – ns Write command pulse width tWP 10 – 10 – 15 – ns Write command setup time tWCS 0 – 0 – 0 – ns Write command to RAS lead time tRWL 15 – 15 – 20 – ns Write command to CAS lead time tCWL 15 – 15 – 20 – ns Write Cycle 15 Data setup time tDS 0 – 0 – 0 – ns 16 Data hold time tDH 10 – 15 – 15 – ns 16 Data to CAS lowdelay tDZC 0 – 0 – 0 – ns 13 Read-write cycle time tRWC 140 – 160 – 185 – ns RAS to WE delay time tRWD 75 – 90 – 100 – ns 15 CAS to WE delay time tCWD 40 – 45 – 50 – ns 15 Column address to WE delay time tAWD 50 – 60 – 65 – ns 15 OE command hold time tOEH 15 – 20 – 20 – ns Fast page mode cycle time tPC 35 – 40 – 45 – ns CAS precharge time tCP 10 – 10 – 10 – ns – 30 – 35 – 40 ns Read-modify-Write Cycle Fast Page Mode Cycle Access time from CAS precharge tCPA RAS pulse width tRASP 50 200k 60 200k 70 200k ns RAS hold time from CAS precharge tRHCP 30 – – – Semiconductor Group 8 35 40 ns 7 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM Parameter Limit Values Symbol -50 Unit Note - 60 - 70 min. max. min. max. min. max. Fast Page Mode Read Modify Write Cycle Fast page mode read/write cycle time tPRWC 80 – 90 – 100 – ns CAS precharge to WE delay time tCPWD 55 – 60 – 65 – ns CAS setup time tCSR 5 – 5 – 5 – ns CAS hold tim tCHR 10 – 10 – 10 – ns RAS to CAS precharge time tRPC 0 – 0 – 0 – ns Write to RAS precharge time tWRP 10 – 10 – 10 – ns Write to RAS hold time tWRH 10 – 10 – 10 – ns 25 – 30 – 40 – ns CAS before RAS refresh Cycle CAS-before RAS counter test cycle CAS precharge time tCPT Self Refresh Cycle (L-Version only) RAS pulse width tRASS 100 – 100 – 100 – µs RAS precharge time tRPS 95 – 110 – 130 – ns CAS hold time Self Refresh tCHS 35 – 40 – 50 – ns Semiconductor Group 9 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM Notes: 1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during a page mode cycle 5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with a load equivalent to 100 pF and at Voh=2.0V (Ioh=-2mA), Vol=0.8V (Iol=2mA). 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. 13) Either tDZC or tDZO must be satisfied. 43) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.), the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. Semiconductor Group 10 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM Read Cycle Semiconductor Group 11 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM Write Cycle (Early Write) Semiconductor Group 12 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM Write Cycle (OE Controlled Write) Semiconductor Group 13 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM Read-Write (Read-Modify-Write) Cycle Semiconductor Group 14 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM Fast Page Mode Read Cycle Semiconductor Group 15 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM Fast Page Mode Early Write Cycle Semiconductor Group 16 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM Fast Page Mode Read-Modify-Write Cycle Semiconductor Group 17 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM RAS-Only Refresh Cycle Semiconductor Group 18 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM CAS-Before-RAS Refresh Cycle Semiconductor Group 19 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM CAS before RAS Self Refresh Cycle Semiconductor Group 20 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM Hidden Refresh Cycle (Read) Semiconductor Group 21 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM Hidden Refresh Cycle (Early Write) Semiconductor Group 22 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM CAS/-Before-RAS Refresh Counter Test Cycle Semiconductor Group 23 HYB 314171BJ/BJL-50/-60/-70 3.3V 256 K x 16-DRAM Package Outline GPJ09018 Plastic Package, P-SOJ- 40-1 (SMD) (Plastic Small Outline J-leaded Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 24 Dimensions in mm