Supertex inc. HV3418 64-Channel Serial to Parallel Converter With High Voltage Push-Pull Outputs General Description Features The HV3418 is a low voltage serial to high voltage parallel converter with push-pull outputs. This device has been designed for use as a printer driver for inkjet applications. It can also be used in any application requiring multiple output, high voltage, low current sourcing and sinking capabilities. ►► Processed with HVCMOS® technology ►► Output voltages to 180V ►► Low power level shifting ►► Shift register speed: 6.0MHz @ VDD = 5.0V 12MHz @ VDD = 12V ►► Latched data outputs ►► Output polarity and blanking ►► CMOS compatible inputs ►► Forward and reverse shifting options The device consists of a 64-bit shift register, 64 latches, and control logic to perform the polarity select and blanking of the outputs. A DIR pin controls the direction of data shift through the device. With DIR grounded, DIOA is Data-In and DIOB is Data-Out; data is shifted from HVOUT64 to HVOUT1. When DIR is at logic high, DIOB is Data-In and DIOA is Data-Out: data is then shifted from HVOUT1 to HVOUT64. Data is shifted through the shift register on the low to high transition of the clock. Data output buffers are provided for cascading devices. Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL(polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE (latch enable) is high. The data in the latch is stored during LE transition from high to low. Functional Block Diagram POL BL LE VPP DIOA HVOUT1 CLK HVOUT2 DIR 64 bit Static Shift Register 64 Latches • • • 60 Additional Outputs • • • HVOUT63 HVOUT64 DIOB Doc.# DSFP-HV3418 C071813 Supertex inc. www.supertex.com HV3418 Pin Configuration Ordering Information Part Number Package Option Packing HV3418PG-G 80-Lead PQFP 66/Tray -G denotes a lead (Pb)-free / RoHS compliant package Absolute Maximum Ratings Parameter Value Supply voltage, VDD -0.5V to +15V Output voltage, VPP VDD to +200V Logic input levels Ground current (top view) Product Marking 1.5A High voltage supply current 1 1.3A Continuous total power dissipation 2 HV3418PG LLLLLLLLLL YYWW CCCCCCCC AAA 1200mW Operating temperature range 1 80-Lead PQFP -0.5V to VDD +0.5V 1 Storage temperature range 80 -40°C to +85°C L = Lot Number YY = Year Sealed WW = Week Sealed C = Country of Origin A = Assembler ID = “Green” Packaging 80-Lead PQFP -65°C to +150°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to GND. Notes: 1. Connection to all power and ground pads is required. Duty cycle is limited by the total power dissipated in the package. 2. For operation above 25°C ambiant derate linearly to maximum operating temperature at 20mW/°C. Package may or may not include the following marks: Si or Typical Thermal Resistance Package θja 80-Lead PQFP 37OC/W Recommended Operating Conditions Sym Parameter Min Typ Max Units VDD = 5.0V 4.5 5.0 5.5 VDD = 12V 10.8 12.0 13.2 60 - 180 V VDD Logic supply voltage VPP High voltage supply VIH High-level input voltage VDD - 0.9 - VDD V VIL Low-level input voltage 0 - 0.9 V TA Operating free-air temperature -40 - +85 °C V Power-up sequence should be the following: 1. 2. 3. 4. Connect ground Apply VDD Set all inputs (Data, CLK, Enable, etc.) to a known state Apply VPP The VPP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. Doc.# DSFP-HV3418 C071813 2 Supertex inc. www.supertex.com HV3418 DC Electrical Characteristics (Over recommended operating conditions unless otherwise noted) Sym Parameter Min Max Units Conditions IDD VDD supply current - 25 mA fCLK = 12MHz, fDATA = 12MHz, LE = low IDDQ Quiescent VDD supply current - 200 µA All VIN = 0 or VDD IPP High voltage supply current - 0.50 - 0.50 IIH High-level logic input current - 10 µA VIH = VDD IIL Low-level logic input current - -10 µA VIL = 0V 155 - VDD - 1.0V - V VPP = 180V, IHVOUT = -5.0mA, IDOUT = -100µA HVOUT - 25 DOUT - 1.0 V VPP = 180V, IHVOUT = +5.0mA, IDOUT = +100µA - VDD + 1.5 - -1.5 VOH High level output VOL Low level output VOC HVOUT clamp voltage HVOUT DOUT AC Electrical Characteristics (For V DD Sym Parameter mA V VPP = 180V. All outputs high. VPP = 180V. All outputs low. IOL = +5.0mA IOL = -5.0mA = 12V. Values in parentheses are for VDD = 5.0V, VPP = 180V, TA = 25°C) Min Max Units Conditions - 12 (6.0) MHz --- fCLK Clock frequency tW Clock width high or low 40 (83) - ns --- tSU Data set-up time before clock rises 25 (35) - ns --- tH Data hold time after clock rises 10 (30) - ns --- tWLE LE pulse width 62 (80) - ns --- tDLE Delay time clock to LE high to low 25 (35) - ns --- tSLE LE set-up time before clock rises 30 (40) - ns --- Time from LE to HVOUT - 1.0 (1.5) µs CL = 20pF tDHL Delay time clock to data high to low - 50 (110) ns CL = 20pF tDLH Delay time clock to data low to high - 75 (160) ns CL = 20pF tR, tF All logic inputs - 5.0 ns --- tON, tOFF Notes: 1. Shift register speed can be as low as DC as long as data set-up and hold time meet the spec. 2. AC characteristics are guaranteed only under VDD = 12V and VDD = 5.0V. Doc.# DSFP-HV3418 C071813 3 Supertex inc. www.supertex.com HV3418 Input and Output Equivalent Circuits VDD VDD VPP DATA OUT INPUT GND GND Logic Inputs HVOUT GND Logic Data Output High Voltage Outputs Switching Waveforms VIH DATA INPUT 50% Data Valid VIL tH tSU CLK 50% VIH 50% 50% 50% tWL 50% tWH VOH 50% VOL tDLH DIO/DIO VOH 50% VOL tDHL tWLE tDLE tOFF Doc.# DSFP-HV3418 C071813 10% tON 4 VOL tSLE 90% 10% HVOUT w/ S/R LOW HVOUT w/ S/R HIGH VOH 50% 50% LE VIL 90% VOH VOL VOH VOL Supertex inc. www.supertex.com HV3418 Function Table Inputs Function Outputs Shift Reg HV Outputs 1 2...64 1 2...64 X * *...* H H...H * H X * *...* L L...L * H L X * *...* * *...* * L H H X H or L *...* * *...* * X ↓ H H X * *...* * *...* * X X ↓ H L X * *...* * *...* * L ↑ H H H X L *...* L *...* * H ↑ H H H X H *...* H *...* * DIOA ↑ X X X L QN→ QN+1 - DIOB DIOB ↑ X X X H QN→ QN+1 - DIOA Data CLK LE BL POL DIR All on X X X L L All off X X X L Invert mode X X L Load S/R H or L ↑ Load/store data in latches X Transparent latch mode I/O relation Data Out * Notes: H = high level, L = low level = 0V, X = irrelevant, ↑ = low-to-high transition, ↓ = high-to-low transition. * = dependent on previous stage’s state before the last CLK or last LE high. Doc.# DSFP-HV3418 C071813 5 Supertex inc. www.supertex.com HV3418 Pin Description Pin # Function Pin # Function Pin # Function 1 HVOUT41/24 28 N/C 55 HVOUT15/50 2 HVOUT42/23 29 BL 56 HVOUT16/49 3 HVOUT43/22 30 POL 57 HVOUT17/48 4 HVOUT44/21 31 VDD 58 HVOUT18/47 5 HVOUT45/20 32 DIR 59 HVOUT19/46 6 HVOUT46/19 33 LGND 60 HVOUT20/45 7 HVOUT47/18 34 OGND 61 HVOUT21/44 8 HVOUT48/17 35 N/C 62 HVOUT22/43 9 HVOUT49/16 36 N/C 63 HVOUT23/42 10 HVOUT50/15 37 CLK 64 HVOUT24/41 11 HVOUT51/14 38 LE 65 HVOUT25/40 12 HVOUT52/13 39 DIOB 66 HVOUT26/39 13 HVOUT53/12 40 VPP 67 HVOUT27/38 14 HVOUT54/11 41 HVOUT1/64 68 HVOUT28/37 15 HVOUT55/10 42 HVOUT2/63 69 HVOUT29/36 16 HVOUT56/9 43 HVOUT3/62 70 HVOUT30/35 17 HVOUT57/8 44 HVOUT4/61 71 HVOUT31/34 18 HVOUT58/7 45 HVOUT5/60 72 HVOUT32/33 19 HVOUT59/6 46 HVOUT6/59 73 HVOUT33/32 20 HVOUT60/5 47 HVOUT7/58 74 HVOUT34/31 21 HVOUT61/4 48 HVOUT8/57 75 HVOUT35/30 22 HVOUT62/3 49 HVOUT9/56 76 HVOUT36/29 23 HVOUT63/2 50 HVOUT10/55 77 HVOUT37/28 24 HVOUT64/1 51 HVOUT11/54 78 HVOUT38/27 25 VPP 52 HVOUT12/53 79 HVOUT39/26 26 DIOA 53 HVOUT13/52 80 HVOUT40/25 27 N/C 54 HVOUT14/51 Notes: Pin designation for DIR = H/L Example: for DIR = H, Pin 1 is HVOUT41 for DIR = L, Pin 1 is HVOUT24 Doc.# DSFP-HV3418 C071813 6 Supertex inc. www.supertex.com HV3418 80-Lead PQFP Package Outline (PG) 20.00x14.00mm body, 3.40mm height (max), 0.80mm pitch, 3.90mm footprint D D1 E1 E Note 1 (Index Area D1/4 x E1/4) 80 1 e b Top View θ1 View B A A2 Seating Plane A1 L L1 Side View L2 Gauge Plane θ Seating Plane View B Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol Dimension (mm) A A1 MIN 2.80* 0.25 NOM - - MAX 3.40 A2 b D D1 E E1 2.55 0.30 23.65* 19.80* 17.65* 13.80* 2.80 - 23.90 20.00 17.90 14.00 0.50* 3.05 0.45 24.15* 20.20* 18.15* 14.20* e 0.80 BSC L 0.73 0.88 1.03 L1 L2 1.95 REF 0.25 BSC θ θ1 0O 5O 3.5O - 7O 16O JEDEC Registration MO-112, Variation CB-1, Issue B, Sept.1995. * This dimension is not specified in the JEDEC drawing. Drawings not to scale. Supertex Doc. #: DSPD-80PQFPPG, Version C041309. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV3418 C071813 7 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com