AN60616 PSoC 3 and PSoC 5LP Startup Procedure.pdf

PSoC® 3 and PSoC 5LP Startup Procedure
Author: Max Kingsbury
Associated Project: No
Associated Part Family: All PSoC ® 3 and PSoC 5LP Parts
Software Version: PSoC Creator ™ 2.1 SP1 or higher
Related Application Notes: AN54439, AN60631, AN73854, System Reference Guide
AN60616 describes PSoC® 3 and PSoC 5LP startup procedures, from the application of device power until the
execution of user code. It describes how to customize the startup procedure, and includes the reasons a designer
might want to change the startup procedure.
Startup Procedure
PSoC 3 and PSoC 5LP are incredibly powerful and
complicated mixed-signal microcontrollers. Through careful
configuration, they can be used to solve all kinds of
technical problems. The PSoC Creator integrated design
environment (IDE) generates the code that will configure the
parts at startup, but it requires application-specific
configuration details. Startup behavior can be manipulated
to change the amount of time startup takes, what
peripherals are configured, and much more. This application
note describes the procedure of startup and also how it can
be manipulated to best suit an application.
The PSoC 3 and PSoC 5LP startup procedure, shown in
Figure 1, configures the parts to meet the PSoC 3 and
PSoC 5LP device datasheet and PSoC Creator™ project
specifications. Startup begins after the release of a reset
source, or after the end of a power supply ramp. There are
two main portions of startup: hardware startup and firmware
startup. During hardware startup, the CPU is halted, and
other resources configure the part. During firmware startup,
the CPU runs code generated by PSoC Creator to configure
the part. When startup ends, the PSoC 3 or PSoC 5LP
device is fully configured, and its CPU begins execution of
user-authored Main.c code.
This application note describes PSoC 3 and PSoC 5LP, but
does not describe PSoC 5. For a legacy version of this
application note describing PSoC 5, see revision *C of this
application note, available on the Cypress website here.
Figure 1. PSoC 3 and PSoC 5LP Startup Procedure Overview
Hardware Startup
CPU halted
Firmware Startup
CPU Specific
Source File
Reset Released
Document No. 001-60616 Rev. *F
PSoC 3 and PSoC 5LP Startup Procedure
Hardware Startup
PSoC 3 and PSoC 5LP hardware startup configures the
parts to meet the general performance specifications given
in their datasheets. The hardware startup phase begins
after a power supply ramp or reset event. There are two
phases of hardware startup: reset and boot. After
hardware startup ends, code execution from flash begins.
Startup begins after the release of all reset sources. Reset
can be caused by the dedicated and optional reset pins, a
watchdog timer, low-voltage detection, power-on reset
(POR), or other sources. While reset is asserted, the I/O
pins are in the analog high-Z drive mode.
If the chip is experiencing power-supply ramp, startup
begins after the POR is initiated. The POR is released
when all device power supplies meet the requirements
shown in the datasheet. These requirements are listed in
the datasheet table “Power on Reset (POR) with Brown
Out DC Specifications”.
Once reset is released, the hardware-controlled portion of
startup begins. Hardware startup can be split into two
phases: reset and boot. In both phases, the CPU is halted.
In the reset phase, the device is inactive, waiting for onchip resources to stabilize enough to enter the boot phase.
In the boot phase, a dedicated hardware state machine
controls basic configuration and trim of the device using
direct memory access (DMA). Executing the boot phase
takes a fixed number of clock cycles.
Immediately after the part exits reset, the device is clocked
by the fast-start output of the internal main oscillator
(IMO). This fast-start output is generated using a fast
reference. The normal IMO output becomes valid later,
after the normal reference becomes stable. The IMO
begins to source the master clock partway through the
reset phase. Although the main IMO output is used during
part of the reset phase, it is not trimmed until the boot
Note Total hardware startup time is specified in the device
datasheet as “TSTARTUP”.
Note For more information on hardware startup behavior,
see the “Reset” section in the PSoC 3 or PSoC 5LP TRM.
Firmware Startup
Firmware startup configures the PSoC 3 or PSoC 5LP
device to behave as described in the PSoC Creator
project. It begins at the end of hardware startup. The CPU
begins executing user-authored main() code after the
completion of firmware startup.
The main task of firmware startup is to populate
configuration registers such that the part behaves as
designed in the PSoC Creator project. This includes
configuring analog and digital peripherals, as well as
system resources such as clocks and routing.
Note Some PSoC Creator components are completely
operational after firmware startup, and some require
additional code to activate. For example, pins are fully
functional, but ADCs require additional API calls. Refer to
individual component datasheets for details.
The firmware startup procedure is defined by the contents
of two source files. A CPU-specific source file for the 8051
or Cortex M3 CPU contains assembly code that executes
immediately at the beginning of firmware startup. For both
CPUs, CyFitter_cfg.c contains C code that is called from
the CPU-specific source code.
The resources configured in the CPU-specific code
include debugging, bootloaders, and DMA endpoints.
The code in CyFitter_cfg.c configures the device’s
registers so that its resources behave as designed in the
PSoC Creator project. This includes configuring the
analog and digital resources, as well as system resources
such as the clock tree and routing. The procedure is
shown in detail in Figure 2, which shows a more specific
portion of the procedure that was shown in Figure 1.
At the completion of hardware startup, the 8051 or
Cortex™-M3 CPU begins to execute code from flash,
beginning at address 0.
Figure 2. CyFitter_cfg.c Execution Steps Overview
DSI config,
Digital routing
The CyFitter_cfg.c source file contains the function
CyFitter_cfg(), which is called by the code in the CPUspecific source file. During the execution of CyFitter_cfg(),
numerous device registers are populated.
The largest batch of register population occurs first, where
the analog and digital resources are configured using
register writes. This step can be performed using either CPU
activity or DMA. If this step is performed using the CPU, the
function cfg_write_bytes_code() is called. If it is performed
using DMA, the function cfg_dma_init() is called.
Digital array,
Analog set
The second largest batch of register population is the
ClockSetup() API call. During clock setup, the part’s clock
sources and clock tree are configured to match the project’s
clock configuration. This configuration is altered in
PSoC Creator using the clocks tab of the Design Wide
Resources interface. During clock setup, the CPU’s
operating frequency changes from the initial, partially
trimmed value to the final desired value.
Note See AN60631 for more details on the clock startup
Document No. 001-60616 Rev. *F
PSoC 3 and PSoC 5LP Startup Procedure
After the completion of the firmware startup, the main() code
in main.c is executed.
P S o C 3 a n d 5 L P P i n B e h a vi o r a t S t a r t u p
PSoC 3 and 5LP have special nonvolatile latch (NVL) bits
that can be used to set pin behavior immediately after reset
is released. These I/O NVL behavior settings become
effective during hardware startup. Pins and other resources
begin to behave as desired following a set delay after reset
is de-asserted or power supply ramp meets requirements.
This delay is specified in the datasheet as “TIO_INIT”. This
value is on the order of microseconds. NVL-controlled pin
behavior is configured in the pin component customizer.
If the NVLs are not configured, the pins remain in the analog
High-Z drive mode until they are reconfigured to their runtime state.
PSoC 3-Specific Startup Details
P S o C 3 F i r mw a r e S t a r t u p
PSoC 3-specific startup code is stored in the source file
KeilStart.A51 and is written in the 8051 assembler. The
code begins at address 0 in flash with an instruction to jump
to the STARTUP1 label. The KeilStart.A51 code performs
basic part configuration, and calls CyFitter_cfg() to perform
more complex configuration. KeilStart.A51 execution is
shown in Figure 3, which shows a more specific portion of
the procedure that was introduced in Figure 1.
The “clear IDATA” step writes zeros to the portion of
program memory allocated for IDATA, usually used for
variables. The “DMAC configuration” step configures the
PSoC 3 part’s DMA resources as specified in the
PSoC Creator project.
For more details on pin behavior, see AN72382.
Bootloader Startup
In projects with both bootloader and bootloadable
application code, the two application codes run sequentially.
This means that the bootloader executes its startup and
main() code, followed by the bootloadable startup and
main() code. For more details on bootloader startup, see
Figure 3. KeilStart.A51 Execution Steps
Hardware Startup
Firmware Startup
Clear SRAM
PSoC 3 Resets
In PSoC 3, all non-software resets must be immediately
followed by a software reset. PSoC Creator fulfils this
requirement automatically. The resulting behavior is that
when a non-software reset is executed, device startup
firmware detects the reset type, and executes a software
reset. Then, the software reset completes and user code
is executed. This code for this firmware startup step is
contained in the KeilStart.A51 code, shortly after the
STARTUP1 entry point.
Compared to the time taken in firmware startup, the
additional time taken to check for and perform software
resets is minimal. In a typical application, hardware startup
takes about 30 µs with the 48-MHz fast IMO output;
therefore, performing it twice takes about 60 µs. Typical
firmware startup takes hundreds or thousands of µs. The
limited 8051 assembly code required to perform this step
takes about 0.5 µs with the 48-MHz fast IMO output.
NVL IMO Frequency Selection
In PSoC 3, the initial IMO frequency can be set to two
different values: 12 MHz and 48 MHz. This frequency
applies just after the start of the boot portion of hardware
startup, until the clock setup portion of CyFitter_cfg.c code
execution, where the configuration from the clocks tab of
the Design Wide Resources is applied. This frequency
may be configured by making a selection in the
PSoC Creator Design Wide Resources, described in the
PSoC 3 and PSoC 5LP Design Wide Resources section.
This selection is stored in the NVL bits in the device.
Document No. 001-60616 Rev. *F
PSoC 3 and PSoC 5LP Startup Procedure
PSoC 5LP-Specific Startup Details
P S o C 5 L P F i r mw a r e S t a r t u p
PSoC 5LP device-specific startup code is contained in the
Cm3Start.c source file. This file contains two reset
functions, one for each of the compilers. The source file
uses conditional compilation to determine which compiler
is being used, and this way only the applicable compiler’s
reset function is used. The comments in the functions
describe which compiler they are for.
Although they are in a .c file, each of the two reset
functions are written in in-line assembly. Each ends with a
call to the sub-main function, also stored in Cm3Start.c.
The sub-main function calls a function for PSoC
initialization, aptly titled initialize_psoc(), and then calls the
main() function in main.c. The initialize_psoc() function
performs some configuration steps but leaves the majority
of configuration to the code in cyfitter_cfg.c, which was
discussed in the Firmware Startup section.
Identifying Reset Sources
After reset and startup, it may be of use to know what
caused the device to reset. Soft resets, including the
watchdog timer and software reset result in a status bit
that can be read after the reset. Although the low-voltage
interrupt (LVI) and high-voltage interrupt (HVI) sources
may be configured to cause a reset, the status bits are
cleared after reset so that a reset cause by LVI or HVI
cannot be determined. There are also two generalpurpose bits that are stored across resets, which may be
used to track system status. These resets and generalpurpose bits may be observed by examining the
CyResetStatus variable, which is maintained by
PSoC Creator-generated startup code. More details can
be found in the PSoC Creator System Reference Guide,
under the “Preservation of Reset Status” heading.
Note “Hard” resets, such as POR, precision reset (PRES),
and reset pins (XRES), are not identifiable using this
Clock Startup
PSoC 3 and PSoC 5LP clocks are configured during
startup, as described in previous sections. The clocking
startup steps are laid out sequentially here for clarity. The
sequence is shown in Figure 4. Immediately following the
release of any reset source, the master clock is driven low.
It is not until the end of the hardware reset phase, and the
beginning of the boot phase, when the fast start IMO is
routed to the master clock bus. This is marked as “1” in
the figure. This clock is distinct from the normal IMO, and
it starts up more quickly but is less accurate.
After a certain amount of time in the boot phase, the IMO
has stabilized, and is used to source the master clock.
This is marked as “2” in the figure. In PSoC 3, if the “fast
startup” option has been selected, this IMO clock will be at
the configured frequency.
The final master clock reconfiguration is performed during
firmware startup, in the ClockStartup() function that is
contained in CyFitter_cfg.c. This is marked in the figure as
“3”. This function performs additional configuration of the
master clock and all other clock sources in the project. It is
only after the completion of ClockStartup() that the
configuration of clocks in the device will match the
configuration in the PSoC Creator project.
For more details on clock configuration in PSoC 3 and
PSoC 5LP, see AN60631.
Figure 4. PSoC 3 and PSoC 5LP Startup Clock Configuration Sequence
Firmware Startup
Hardware Startup
CPU Specific
Source File
CPU halted
Master Clock
Reset Released
(with Fast Startup if
Fast Start
No Clock
Document No. 001-60616 Rev. *F
Creator Configuration
(IMO, MHzECO, PLL etc)
PSoC 3 and PSoC 5LP Startup Procedure
Modifying Startup
The startup procedure may be altered to better fit a
specific application’s needs. You can modify the device
startup in the following ways: using the design wide
resources (DWR) interface in the PSoC Creator GUI and
modifying the PSoC 3 startup code stored in the CPUspecific source files and CyFitter_cfg.c.
Figure 5. System Tab of PSoC 3 DWR in PSoC Creator
Using the PSoC Creator GUI
The startup procedure may be modified in PSoC Creator
in the “System” tab of the design wide resources. Because
PSoC 3 and PSoC 5LP have different capabilities, they
have different options available in this interface. These
interfaces are shown in Figure 5 and Figure 6.
The only option that applies to startup for both devices is
“Device Configuration Mode”. This selection chooses how
device registers are populated. “Compressed” and
“uncompressed” modes both use the CPU to populate
configuration registers, and store the data in flash. The
“compressed” mode optimizes for flash space
consumption rather than startup time. The difference in
performance between these two modes is extremely
modest. The “DMA” mode uses DMA to populate the
registers. In “DMA” mode, the CPU’s execution is blocked
until DMA configuration is completed. In the PSoC 3, DMA
population takes much less time than 8051 CPU
population, as DMA transfers data from flash to registers
at a much higher rate. However, in PSoC 5LP, the CortexM3 can populate registers more than twice as fast as
PSoC 3 and PSoC 5LP Design Wide
The “Clear SRAM…” option determines whether or not
SRAM should be cleared upon reset. The “Enable Fast
IMO …” option selects between the two available NVLselected IMO speeds: 12 MHz and 48 MHz nominal. The
12-MHz and 48-MHz options are referred to in the device
datasheet as “slow boot mode” and “fast boot mode”,
Note The “Enable Fast IMO During Startup” option is not
available in some parts due to maximum operating
frequency ratings.
Figure 6. System Tab of PSoC 5LP DWR in PSoC
Modifying Startup Code
PSoC 3 and PSoC 5LP startup code is modified
depending upon the configuration of the PSoC Creator
project. The code is re-generated every time a change is
made to the PSoC Creator schematic or design wide
resources. This means that any changes made to the
CPU-specific source code and CyFitter_cfg.c files can
easily be lost.
Document No. 001-60616 Rev. *F
PSoC 3 and PSoC 5LP Startup Procedure
To edit the startup code, and have changes reflected in
the HEX file that is generated for device programming, the
files must only be edited when there is no need to perform
a “generate” operation. This means that the configuration
in automatically-generated source files must match the
configuration of the project’s design wide resources and
schematic. This may be ensured by first making schematic
and DWR changes, performing a “clean and build” and
only subsequently editing generated source files. At this
point, the project may be built, and the resulting firmware
reflects the edits. Every time a “clean and build” is
performed, modifications to automatically generated
source files are lost.
To attain a better understanding of the time spent
performing various tasks during startup, pin toggles may
be added in the firmware to indicate at what time certain
operations are carried out. Pin toggles may be added in C
and 8051 and Cortex-M3 assembly using the code shown
in Code 1, Code 2, Code 3, and Code 4. These may be
modified to use the desired ports and pins by changing the
constants for port drive mode and data registers, and the
constants for pin masks.
Note These pin toggles take some time to execute, and
when calculating total startup time, they should be
accounted for. Register and memory usage should also be
Code 1. PSoC 3 and PSoC 5LP Pin 0.0 Toggle in C
/* Drive pin 0.0 to logic high
/* Set port-wide drive mode to strong */
/* Set pin 0.0 data register to 0
Code 2. PSoC 3 Pin 0.0 Toggle in Assembly
; Set port 0 drive mode
; Set A to strong drive mode
A, #0CH
; Load register address (PRT0_PRT)
DPTR, #510AH
; Load register value
; Set p0.0 high
; Set A to desired register value(pin 0)
A, #01H
; Load register address (PRT0_DR)
DPTR, #5100H
; Load register value
Code 3. PSoC 5LP Pin 0.0 Toggle in GCC Assembly
/* Load register address (PRT0_PRT) */
"ldr r2, =0x4000510A\n"
/* Set drive mode
"mov r3, 0x0C\n"
/* Store drive mode in register
"str r3, [r2]\n"
/* Load register address (PRT0_DR)
"ldr r2, =0x40005100\n"
/* Set pin data
"mov r3, 0x01\n"
/* Store pin data in register
"str r3, [r2]\n"
Code 4. PSoC 5LP Pin 0.0 Toggle in MDK Assembly
/* Load register address (PRT0_PRT)
ldr r2, =0x4000510A
/* Set pin drive mode
mov r3, 0x0C
/* Store drive mode in register
str r3, [r2]
/* Load register address (PRT0_PRT)
ldr r2, =0x40005100
/* Set drive mode
mov r3, 0x01
/* Store drive mode in register
str r3, [r2]
Startup Time Optimization Tips
In some designs, a low startup time is essential. In these
designs, there are a number of steps that can be taken to
reduce startup time. It is worth noting that some of these
steps increase current consumption.
Increase Trimmed IMO Frequency
Running the fully-trimmed IMO at a higher frequency also
improves startup time. Because most startup occurs under
partially-trimmed IMO, the benefits are not as significant
as changing the partially trimmed IMO frequency. As with
increasing the partially trimmed IMO frequency, this
change increases current consumption.
Increase Fast-start IMO Frequency
Running the Fast-start IMO at 48 MHz instead of 12 MHz
speeds up most portions of startup by a factor of 4. Much
of startup is CPU or DMA limited, and these two resources
operate at the speed of the IMO. The downside to
increasing the speed of the Fast-start IMO is that device
current consumption increases. The fast-start IMO
frequency can be modified in the PSoC Creator Design
Wide Resources, as described in the PSoC 3 and PSoC
5LP Design Wide Resources section.
Faster Power Supply Ramp
While the power supply ramp is not normally considered
part of microcontroller startup, it does block the beginning
of the startup procedure. The embedded designer should
consider the possibility of increasing the speed of the VDD
ramps, if it is taking a significant amount of time compared
to device startup. Power supply ramp rates are discussed
further in AN61290 - PSoC® 3 and PSoC 5LP Hardware
Design Considerations.
Document No. 001-60616 Rev. *F
PSoC 3 and PSoC 5LP Startup Procedure
Note PSoC 3 and PSoC 5LP have maximum and
minimum power supply ramp ratings. They are listed as
“Svdd” in the device datasheet.
Use CPU for Register Population in
AN60616 has described the PSoC 3 and PSoC 5LP
startup procedure and how it can be altered to better suit a
variety of applications.
In PSoC 5LP, the Cortex-M3 CPU is much faster than
DMA at populating device registers. The CPU populates
registers over twice as fast as DMA.
About the Author
Max Kingsbury
Use DMA for Register Population in PSoC 3
Applications Engineer Senior
In PSoC 3, DMA is much faster than the 8051 CPU at
populating device registers. Gains depend heavily upon
the configuration of the part, but switching from CPU to
DMA population may save on the order of 1-20 ms.
Max holds a bachelors degree in
electrical engineering from Washington
State University. He specializes in
technical composition and debugging
embedded designs. In his spare time,
he enjoys running, photography, and
Do Not Clear SRAM in PSoC 3
Clearing SRAM takes approximately 4500 CPU clock
cycles in an 8-KB SRAM PSoC 3 part. At the slow IMO
speed of 12 MHz, this can be almost 400 µs. At 48 MHz, it
can take 100 µs. As long as variables are initialized
properly in code, not clearing SRAM has no effect upon
firmware operation.
Document No. 001-60616 Rev. *F
PSoC 3 and PSoC 5LP Startup Procedure
Document History
Document Title: AN60616 - PSoC® 3 and PSoC 5LP Startup Procedure
Document Number: 001-60616
Orig. of
Description of Change
New application note.
Updated details and readability.
Updated PSoC Creator version.
Updated abstract.
Added PSoC 5.
Added clock startup section.
Updated for PSoC Creator Version 2.1.
Updated title in Document History section to match with the spec title.
Updated for PSoC 5LP.
Fixed paragraph alignment on pages 1, 2, and 3
Minor grammatical changes.
Clarified that pin behavior is the same for both PSoC 3 and PSoC 5LP
Clarified the LVI and HVI status bits are cleared after reset.
Document No. 001-60616 Rev. *F
PSoC 3 and PSoC 5LP Startup Procedure
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find
the office closest to you, visit us at Cypress Locations.
PSoC® Solutions
Clocks & Buffers
PSoC 1 | PSoC 3 | PSoC 5LP | PSoC 4
Lighting & Power Control
Touch Sensing
USB Controllers
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
PSoC is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of
their respective owners.
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
: 408-943-2600
: 408-943-4730
© Cypress Semiconductor Corporation, 2010-2015. The information contained herein is subject to change without notice. Cypress Semiconductor
Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any
license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or
safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The
inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies
Cypress against all charges.
This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide
patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a
personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative
works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source
Code except as specified above is prohibited without the express written permission of Cypress.
right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or
use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a
malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document No. 001-60616 Rev. *F