HV2733 DATA SHEET (11/30/2011) DOWNLOAD

Supertex inc.
HV2733
16-Channel, Low Harmonic Distortion,
High Voltage Analog Switch with Bleed Resistors
Features
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Low harmonic distortion
Integrated bleed resistors on the outputs
3.3 or 5.5V CMOS input logic level
20MHz data shift clock frequency
HVCMOS technology for high performance
Very low quiescent power dissipation (-10µA)
Low parasitic capacitance
DC to 50MHz small signal frequency
response
CMOS logic circuitry for low power
Excellent noise immunity
Cascadable serial data register with latches
Flexible operating supply voltages
Applications
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General Description
The Supertex HV2733 is a low charge injection, 16-channel, low
harmonic distortion, high voltage analog switch integrated circuit
(IC) intended for use in applications requiring high voltage switching,
controlled by low voltage control signals, such as medical ultrasound
imaging, piezoelectric transducer drivers, and printers. The bleed
resistors eliminate voltage built up on capacitive loads such as
piezoelectric transducers.
The outputs are configured as single-pole double-throw analog switches.
Data are shifted into a 8-bit shift register using an external clock. The LE
latches the shift register data into the individual switch latches. A logic
high connects a switch common YX to SWX. A logic low connects YX
to SWX. A logic high in CLR resets all switches to SWX simultaneously.
To reduce any possible clock feed-through noise, the latch enable bar
(LE) should be left high until all bits are clocked in. Data are clocked in
during the rising edge of the clock. Using HVCMOS technology, this
device combines high voltage bilateral DMOS switches and low power
CMOS logic to provide efficient control of high voltage analog signals.
Medical ultrasound imaging
NDT metal flaw detection
Piezoelectric transducer drivers
Optical MEMS modules
Block Diagram
Latches
D
LE
CLR
Level
Shifters
Output
Switches
SW0
High Voltage
Level Translator
D
LE
CLR
High Voltage
Level Translator
D
LE
CLR
High Voltage
Level Translator
D
LE
CLR
High Voltage
Level Translator
D
LE
CLR
High Voltage
Level Translator
Y0
SW0
SW1
Y1
SW1
DIN
CLK
8-Bit
Shift
Register
SW2
Y2
SW2
DOUT
VDD GND
Supertex inc.
LE CLR
VNN VPP
SW6
Y6
SW6
SW7
Y7
SW7
RGND
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
HV2733
Pin Configuration
Ordering Information
Package Option
1
48-Lead LQFP
Device
48
7.00x7.00mm body
1.60mm height (max)
0.50mm pitch
HV2733
HV2733FG-G
-G indicates package is RoHS compliant (‘Green’)
48-Lead LQFP (FG)
(top view)
Product Marking
Absolute Maximum Ratings
Top Marking
Parameter
Value
VDD logic supply
-0.5V to +7.0V
VPP - VNN differential supply
220V
VPP positive supply
-0.5V to +200V
VNN negative supply
+0.5V to -200V
Logic input voltage
-0.5V to VDD +0.3V
VSIG analog signal range
VNN to VPP
Peak analog signal current/channel
Storage temperature
2.5A
YYWW
HV 2 7 3 3 FG
LLLLLLLLL
Bottom Marking
CCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
48-Lead LQFP (FG)
Packages may or may not include the following marks: Si or
-65°C to 150°C
Power dissipation, 48-Lead LQFP
1.0W
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. Continuous operation of the device at
the absolute rating level may affect device reliability. All voltages are referenced to device ground.
Recommended Operating Conditions
Sym
Parameter
Value
VDD
Logic power supply voltage
3.0V to 5.5V
VPP
Positive high voltage supply
+40V to VNN +200V
VNN
Negative high voltage supply
VIH
High level input voltage
0.9VDD to VDD
VIL
Low level input voltage
0V to 0.1VDD
VSIG
Analog signal voltage peak-to-peak
TA
Operating free air temperature
-40V to -160V
VNN+10V to VPP-10V
0°C to 70°C
Notes:
1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last.
2. VSIG must be within VNN and VPP or floating during power up/down transition.
3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec.
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
2
HV2733
DC Electrical Characteristics
(over recommended operating conditions unless otherwise noted)
Sym
0°C
Parameter
+25°C
+70°C
Units
Conditions
Min
Max
Min
Typ
Max
Min
Max
-
30
-
26
38
-
48
ISIG = 5.0mA
-
25
-
22
27
-
32
ISIG = 200mA
-
25
-
22
27
-
30
-
18
-
18
24
-
27
-
23
-
20
25
-
30
ISIG = 5.0mA
-
22
-
16
25
-
27
ISIG = 200mA
Small signal switch
ON-resistance matching
-
20
-
5.0
20
-
20
%
ISIG = 5.0mA, VPP = +100V,
VNN = -100V
RONL
Large signal switch
ON-resistance
-
-
-
15
-
-
-
Ω
VSIG= VPP -10V, ISIG = 1.0A
RINT
Value of output bleed resistor
-
-
35
50
65
-
-
KΩ
Output Switch to RGND
IRINT = 0.5mA
ISOL
Switch off leakage per switch
-
5.0
-
1.0
10
-
15
µA
VSIG = VPP -10V and VNN +10V
DC offset switch off
-
50
-
-
50
-
50
mV
DC offset switch on
-
50
-
-
50
-
50
mV
IPPQ
Quiescent VPP supply current
-
-
-
10
50
-
-
µA
All switches off
INNQ
Quiescent VNN supply current
-
-
-
-10
-50
-
-
µA
All switches off
IPPQ
Quiescent VPP supply current
-
-
-
10
50
-
-
µA
All switches on, ISW = 5.0mA
INNQ
Quiescent VNN supply current
-
-
-
-10
-50
-
-
µA
All switches on, ISW = 5.0mA
ISW
Switch output peak current
-
2.0
-
-
2.0
-
2.0
A
VSIG duty cycle < 0.1%
pulse width ≤1.0µs
fSW
Output switching frequency
-
-
-
-
50
-
-
kHz
-
5.2
-
-
5.6
-
6.4
-
3.2
-
-
4.5
-
4.5
-
3.2
-
-
4.0
-
4.5
VPP = +160V
VNN = -40V
-
5.2
-
-
5.6
-
6.4
VPP = +40V
VNN = -160V
-
3.2
-
-
4.0
-
4.5
-
3.2
-
-
4.0
-
4.5
RONS
∆RONS
VOS
IPP
INN
Small signal switch
ON-resistance
Average VPP supply current
Average VNN supply current
Ω
ISIG = 5.0mA
ISIG = 200mA
mA
VPP = +100V
VNN = -100V
VPP = +160V
VNN = -40V
No Load, RGND = 0V
Duty cycle = 50%
VPP = +40V
VNN = -160V
mA
VPP = +40V
VNN = -160V
VPP = +100V
VNN = -100V
VPP = +100V
VNN = -100V
VPP = +160V
VNN= -40V
All output
switches are
turning on
and off at
50kHz with
no load.
All output
switches are
turning on
and off at
50kHz with
no load.
IDD
Average VDD supply current
-
2.0
-
-
2.0
-
2.0
mA
fCLK = 5.0MHz, VDD = 5.0V
IDDQ
Quiescent VDD supply current
-
10
-
-
10
-
10
µA
All logic inputs are static
ISOR
Data out source current
0.45
-
0.45
0.70
-
0.40
-
mA
VOUT = VDD - 0.7V
ISINK
Data out sink current
0.45
-
0.45
0.70
-
0.40
-
mA
VOUT = 0.7V
CIN
Logic input capacitance
-
10
-
-
10
-
10
pF
---
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
3
HV2733
AC Electrical Characteristics
(over recommended operating conditions, VDD= 5.0V, tR = tF ≤ 5.0ns, 50% duty cycle, CLOAD = 20pF, unless otherwise noted)
Sym
0°C
Parameter
+25°C
+70°C
Min
Max
Min
Typ
Max
Min
Max
Units
Conditions
tSD
Set up time before LE rises
25
-
25
-
-
25
-
ns
---
tWLE
Time width of LE
12
-
-
12
-
12
-
ns
VDD = 5.0V
tDO
Clock delay time to data out
15
40
15
30
40
15
40
ns
VDD= 5.0V
Time width of CLR
55
-
55
-
-
55
-
ns
---
tSU
Set up time data to clock
7.0
-
-
7.0
-
7.0
-
ns
VDD= 5.0V
tH
Hold time data from clock
2.0
-
2.0
-
-
2.0
-
ns
---
tWCLR
fCLK
Clock frequency
-
20
-
-
20
-
20
MHz
tR,tF
Clock rise and fall times
-
50
-
-
50
-
50
ns
----
TON
Turn on time
-
5.0
-
-
5.0
-
5.0
µs
VSIG = VPP -10V, RLOAD = 10kΩ
TOFF
Turn off time
-
5.0
-
-
5.0
-
5.0
µs
VSIG = VPP -10V, RLOAD = 10kΩ
-
20
-
-
20
-
20
-
20
-
-
20
-
20
-
20
-
-
20
-
20
-30
-
-30
-33
-
-30
-
-58
-
-58
-
-
-58
-
-60
-
-60
-70
-
-60
-
dB
f = 5.0MHz, 50Ω load
-
300
-
-
300
-
300
mA
300ns pulse width,
2.0% duty cycle
dv/dt
Maximum VSIG slew rate
KO
Off isolation
KCR
Switch crosstalk
IID
Output switch isolation
diode current
50% duty cycle, fDATA = fCLK/2
VPP = +40V, VNN = -160V
v/ns
VPP = +100V, VNN = -100V
VPP = +160V, VNN = -40V
dB
f = 5.0MHz, 1.0kΩ//15pF load
f = 5.0MHz, 50Ω load
CSG(OFF)
Off capacitance SW to GND
5.0
17
5.0
12
17
5.0
17
pF
0V, f = 1.0MHz
CSG(ON)
On capacitance SW to GND
25
50
25
38
50
25
50
pF
0V, f = 1.0MHz
+VSPK
-
-
-
-
150
-
-
-VSPK
-
-
-
-
150
-
-
-
-
-
-
150
-
-
-
-
-
-
150
-
-
+VSPK
-
-
-
-
150
-
-
-VSPK
-
-
-
-
150
-
-
+VSPK
-VSPK
Output voltage spike
Supertex inc.
VPP = +40V, VNN = -160V,
RLOAD = 50Ω
mV
VPP = +100V, VNN = -100V,
RLOAD = 50Ω
VPP = +160V, VNN = -40V,
RLOAD = 50Ω
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
4
HV2733
HV2733 Test Circuits
VPP -10V
ISOL
Open
VPP -10V
Open
RL
10kΩ
VOUT
VOUT
RINT
RINT
RINT
RGND
RGND
RGND
VPP
VPP
VDD
VNN
VNN
GND
5.0V
VPP
VPP
VDD
VNN
VNN
GND
Switch OFF Leakage
VPP
VPP
VDD
VNN
VNN
GND
RINT RINT
VOUT
RLOAD
RGND
VOUT
50Ω
VIN = 10VP-P
@5.0MHz
VPP
VPP
VDD
VNN
VNN
GND
KO = 20Log
VOUT
VIN
5.0V
TON / TOFF
DC Offset ON/OFF
RINT
VIN = 10VP-P
@5.0MHz
5.0V
5.0V
RINT RINT
VPP
VPP
VDD
VNN
VNN
GND
KCR = 20Log
RGND
5.0V
VOUT
VIN
Crosstalk
Off Isolation
+VSPK
VSIG
VOUT
IID
VNN
1kΩ
RINT
RINT
50Ω
5.0V
RGND
RGND
VPP
VPP
VDD
VNN
VNN
GND
Isolation Diode Current
Supertex inc.
5.0V
VPP
VPP
VDD
VNN
VNN
GND
Output Voltage Spike
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
5
-VSPK
HV2733
Truth Table
D0
D1
D2
D3
D4
D5
D6
D7
LE
CLR
Y0
Y1
Y2
Y3
Y4
Y5
Y6
L
-
-
-
-
-
-
-
L
L
SW0
-
-
-
-
-
-
Y7
-
H
-
-
-
-
-
-
-
L
L
SW0
-
-
-
-
-
-
-
-
L
-
-
-
-
-
-
L
L
-
SW1
-
-
-
-
-
-
-
H
-
-
-
-
-
-
L
L
-
SW1
-
-
-
-
-
-
-
-
L
-
-
-
-
-
L
L
-
-
SW2
-
-
-
-
-
-
-
H
-
-
-
-
-
L
L
-
-
SW2
-
-
-
-
-
-
-
-
L
-
-
-
-
L
L
-
-
-
SW3
-
-
-
-
-
-
-
H
-
-
-
-
L
L
-
-
-
SW3
-
-
-
-
-
-
-
-
L
-
-
-
L
L
-
-
-
-
SW4
-
-
-
-
-
-
-
H
-
-
-
L
L
-
-
-
-
SW4
-
-
-
-
-
-
-
-
L
-
-
L
L
-
-
-
-
-
SW5
-
-
-
-
-
-
-
H
-
-
L
L
-
-
-
-
-
SW5
-
-
-
-
-
-
-
-
L
-
L
L
-
-
-
-
-
-
SW6
-
-
-
-
-
-
-
H
-
L
L
-
-
-
-
-
-
SW6
-
-
-
-
-
-
-
-
L
L
L
-
-
-
-
-
-
-
SW7
-
-
-
-
-
-
-
H
L
L
-
-
-
-
-
-
-
SW7
X
X
X
X
X
X
X
X
H
L
HOLD PREVIOUS STATE
X
X
X
X
X
X
X
X
X
H
SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
Notes:
1. Serial data is clocked in on the L to H transition of the CLK.
2. All switches go to a state retaining their latched condition at the rising edge of LE. When LE is low the shift registers data flow through the latch.
3. DOUT is high when data in the shift register 7 is high.
4. Shift registers clocking has no effect on the switch states if LE is high.
5. The CLR clear input overrides all other inputs.
Logic Timing Waveforms
DN+1
DN
DATA
IN
50%
LE
50%
DN-1
50%
50%
tWLE
tSD
50%
CLOCK
tSU
50%
th
tDO
DATA
OUT
50%
tON
tOFF
VOUT
(TYP)
OFF
90%
10%
ON
50%
CLR
Supertex inc.
tWCL
50%
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
6
HV2733
Pin Configuration
48-Lead LQFP (FG)
Pin #
Function
Pin #
Function
Pin #
Function
Pin #
Function
1
SW0
13
SW3
25
NC
37
RGND
2
Y0
14
Y3
26
SW5
38
GND
3
SW0
15
SW3
27
Y5
39
VDD
4
NC
16
NC
28
SW5
40
DOUT
5
SW1
17
VNN
29
NC
41
NC
6
Y1
18
NC
30
SW6
42
NC
7
SW1
19
NC
31
Y6
43
NC
8
NC
20
VPP
32
SW6
44
CLR
9
SW2
21
NC
33
NC
45
LE
10
Y2
22
SW4
34
SW7
46
CLK
11
SW2
23
Y4
35
Y7
47
DIN
12
NC
24
SW4
36
SW7
48
RGND
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
7
HV2733
48-Lead LQFP Package Outline (FG)
7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch
D
D1
E
E1
Note 1
(Index Area
D1/4 x E1/4)
48
1
e
b
Top View
L2
View B
A
A2
L
Seating
Plane
L1
Side View
A1
θ
Gauge
Plane
Seating
Plane
View B
Note:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
Symbol
MIN
Dimension
NOM
(mm)
MAX
A
A1
A2
b
D
D1
E
E1
1.40*
0.05
1.35
0.17
8.80*
6.80*
8.80*
6.80*
-
-
1.40
0.22
9.00
7.00
9.00
7.00
1.60
0.15
1.45
0.27
9.20*
7.20*
9.20*
7.20*
e
L
0.50
BSC
0.45
0.60
0.75
L1
1.00
REF
L2
0.25
BSC
θ
0O
3.5O
7O
JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001.
* This dimension is not specified in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-48LQFPFG Version, D041309.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
Supertex inc.
©2011 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Doc.# DSFP-HV2733
A113011
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
8