Supertex inc. HV6810 10-Channel, Serial-Input Latched Display Driver Features ►► High output voltage 80V ►► High speed 5MHz @5.0VDD ►► Low power IBB ≤ 0.1mA (all high) ►► Active pull down 100µA min @25OC ►► Output source current 25mA @60V VBB ►► Each device drives 10 lines ►► High-speed serially-shifted data input ►► 5.0V CMOS-compatible inputs ►► Latches on all driver outputs ►► Pin-compatible replacement for UCN5810A and TL4810A, TL4810B General Description The HV6810 is a monolithic integrated circuit designed to drive a dot matrix or segmented vacuum fluorescent display (VFD). These devices feature a serial data output to cascade additional devices for large displays. A 10-bit data word is serially loaded into the shift register on the positive-going transition of the clock. Parallel data is transferred to the output buffers through a 10-bit D-type latch while the latch enable input is high, and is latched when the latch enable is low. When the blanking input is high, all of the outputs are low. Outputs are structures formed by double-diffused MOS (DMOS) transistors with output voltage ratings of 80V and 25mA source-current capability. All inputs are compatible with CMOS levels. Applications ►► High speed dot matrix print head driver ►► VFD (vacuum fluorescent display) driver Functional Block Diagram VBB Blanking Latch Enable Data Input Clock • • • Shift Register Latches 1D C1 C2 2D LC1 Q1 1D C1 C2 2D LC2 Q2 • • • • • • • • • • • • 6 Stages (Q3 thru Q8 not shown 1D C1 C2 2D LC9 Q9 1D C1 C2 2D LC10 Q10 Serial Out Logic Diagram (positive logic) Doc.# DSFP-HV6810 E070913 Supertex inc. www.supertex.com HV6810 Pin Configuration Ordering Information Part Number Package Options Packing HV6810PJ-G 20-Lead PLCC* 48/Tube HV6810PJ-G M910 20-Lead PLCC* 1000/Reel HV6810WG-G 20-Lead SOW 1000/Reel 2 1 20 1 20 -G denotes a lead (Pb)-free / RoHS compliant package * Obsolescence notice issued for the product in the 20-Lead PLCC package. Absolute Maximum Ratings1 Parameter Logic supply voltage, VDD2 7.5V Driver supply voltage, VBB2 90V Output voltage2 90V Input voltage2 Operating temperature range (top view) (top view) Product Marking Top Marking YY = Year Sealed WW = Week Sealed L = Lot Number A = Assembler ID C = Country of Origin* = “Green” Packaging YYWW AAA -0.3V to VDD+ 0.3V Continuous total power dissipation at 25OC free-air temperature:3 20-Lead PLCC3 20-Lead SOW3 20-Lead SOW 20-Lead PLCC Value HV6810PJ LLLLLLLLLL Bottom Marking 1500mW 1500mW CCCCCCCCCCC *May be part of top marking -45°C +85°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referenced to GND. Package may or may not include the following marks: Si or 20-Lead PLCC YY = Year Sealed WW = Week Sealed A = Assembler ID L = Lot Number C = Country of Origin* = “Green” Packaging Top Marking YYWW AAA H V6810WG Notes: 1. Over operating free-air temperature 2. All voltages are referenced to VSS 3. For operation above 25OC ambient derate linearly to 85OC at 15mW/OC LLLLLLLLLL Bottom Marking CCCCCCCCCCC * May be part of top marking Typical Thermal Resistance Package θja 20-Lead PLCC 66OC/W 20-Lead SOW 66OC/W Package may or may not include the following marks: Si or 20-Lead SOW Recommended Operating Conditions Sym Parameter Min Typ Max Units VDD Supply voltage 4.5 - 5.5 V --- VBB High supply voltage 20 - 80 V --- VSS Supply voltage - 0 - V --- VIH High-level input voltage (for VDD = 5.0V) 3.5 - 5.3 V --- VIL Low-level input voltage -0.3 - 0.8 V --- IOH Continuous high-level Q output current 25 - - mA --- fCLK Clock frequency - - 5.0 MHz --- TA Operating ambient temperature -40 - +85 °C --- Doc.# DSFP-HV6810 E070913 2 Conditions Supertex inc. www.supertex.com HV6810 DC Electrical Characteristics (VDD = 5.0V, VBB = 60V, VSS = 0V, TA = 25OC unless otherwise noted) Sym Parameter VOH High level output voltage Min Typ Max Q outputs 57.5 58 - Serial output 4.0 4.5 - Q outputs - 0.15 1.0 Serial output - 0.05 0.1 60 80 - µA TA = Max, VOL = +0.7V -1.0 -15 µA VO = 0V, blanking input at VDD 1.0 µA VlN = VDD VOL Low level output voltage IOL Low level Q output current (pull-down current) IO(OFF) Off-state output current - IIH High level input current - IDD Supply current from VDD (standby) IBB Supply current from VBB - 10 50 - 10 50 - 0.05 0.1 Units V V mA 0.05 0.1 IO = +25mA VDD = +4.5V, IOL = +100µA IO = -100µA, blanking input at VDD VDD = +4.5V, IO = -100µA µA - Conditions All inputs at 0V, one Q output high All inputs at 0V, all Q outputs low All outputs low, all Q outputs open All outputs high, all Q outputs open * All typical values are at TA = 25OC except for IOL and IO(OFF). AC Electrical Characteristics (Timing requirements over recommended operating conditions) Sym Parameter Min Typ Max Units tW(CKH) Pulse duration, clock high 100 - - ns --- tW(LEH) Pulse duration, latch enable high 100 - - ns --- tSU(D) Setup time, data before clock 50 - - ns --- tH(D) Hold time, data after clock 50 - - ns --- Delay time, clock to latch enable high 50 - - ns --- - 300 - ns --- tCKH-LEH tPD * Propagation delay time, latch enable to output Conditions * Switching characteristics, VBB = 60V, TA = 25OC Power-up sequence should be the following: 1. Connect ground VSS 2. Apply VDD 3. Set all inputs (Data, CLK, Enable, etc.) to a known state 4. Apply VBB The VBB should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. Doc.# DSFP-HV6810 E070913 3 Supertex inc. www.supertex.com HV6810 Switching Waveforms tW(CKH) VIH 50% Clock tSU(D) Data 50% 50% 50% 50% 50% Input Timing 50% tPD 90% Q Output VIL VIL tW(LEH) tCKH-LEH Latch Enable VIH VIH Valid VIL tH(D) Valid Clock Input Output Switching Timing Valid VIH VIL VOH VOL Timing Diagram Clock Data In SR Contents VALID IRRELEVANT INVALID VALID Latch Enable Latch Contents PREVIOUSLY STORED DATA NEW DATA VALID Blanking Q Outputs Doc.# DSFP-HV6810 E070913 VALID 4 Supertex inc. www.supertex.com HV6810 Input and Output Equivalent Circuits VDD VBB VDD DATA OUT DATA INPUT Q GND VSS Input Equivalent Circuit VSS Logic Data Output High Voltage Output Function Table Serial Data Input Shift Register Contents I1 I2 I3 ... IN-1 IN Serial Data Output H H R1 R2 ... RN-2 RN-1 RN-1 L L R1 R2 ... RN-2 RN-1 RN-1 X R1 R2 R3 ... RN-1 RN RN X X X ... X X Clock Input --- --- LE Strobe Input Latch Contents I1 I2 I3 ... IN-1 IN --- --- X L R1 R2 R3 ... RN-1 RN P1 P2 P3 ... PN-1 PN PN H --- --- --- Blanking Input Output Contents I1 I2 I3 ... IN-1 IN --- --- P1 P2 P3 ... PN-1 PN L P1 P2 P3 ... PN-1 PN X X X ... X H L L L ... L X L Notes: L = Low logic level, H = High logic level, X = Don’t care, P = Present state, R = Previous state = Low to high transition = High to low transition Doc.# DSFP-HV6810 E070913 5 Supertex inc. www.supertex.com HV6810 Pin Description 20-Lead PLCC (PJ) Pin # Function 1 Q8 2 Q7 3 Q6 4 CLOCK 5 N/C No connection. 6 VSS Usually VSS = 0V, ground connection. 7 VDD Low voltage power supply. 8 LE (STROBE) 9 Q5 10 Q4 11 Q3 12 Q2 13 Q1 14 BLANKING 15 DATA IN 16 N/C No connection. 17 VBB High voltage power supply. 18 SERIAL DATA OUT 19 Q10 20 Q9 Doc.# DSFP-HV6810 E070913 Description High voltage output. Input data is shifted into the data shift register on the positive edge of the clock. When LE is high, the shift register output is latched to Q output. When LE stays high, the latches are in transparent mode. High voltage output. When blanking is high, all Q’s are forced to a low state, regardless of data in each channel. Input data for the input shift register. Output data from the shift register. High voltage output. 6 Supertex inc. www.supertex.com HV6810 Pin Description 20-Lead SOW (WG) Pin # Function 1 Q8 2 Q7 3 Q6 4 CLOCK 5 VSS Usually VSS = 0V, ground connection. 6 N/C No connection. 7 VDD Low voltage power supply. 8 LE (STROBE) 9 Q5 10 Q4 11 Q3 12 Q2 13 Q1 14 BLANKING 15 DATA IN 16 VBB 17 SERIAL DATA OUT 18 N/C 19 Q10 20 Q9 Doc.# DSFP-HV6810 E070913 Description High voltage output. Input data are shifted into the data shift register on the positive edge of the clock. When LE is high, the shift register output is latched to Q output. When LE stays high, the latches are in transparent mode. High voltage output. When blanking is high, all Q’s are forced to a low state, regardless of data in each channel. Input data for the input shift register. High voltage power supply. Output data from the shift register. No connection. High voltage output. 7 Supertex inc. www.supertex.com HV6810 20-Lead PLCC Package Outline (PJ) .353x.353in body, .180in height (max), .050in pitch D .048/.042 x 45O D1 1 3 .150max .056/.042 x 45O 20 Note 1 (Index Area) 18 .075max E E1 8 Note 2 e .020max (3 Places) 13 Top View Vertical Side View View B b1 A A1 Base .020min Plane A2 Seating Plane b Horizontal Side View R View B Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Actual shape of this feature may vary. Symbol Dimension (inches) A A1 A2 b b1 D D1 E E1 MIN .165 .090 .062 .013 .026 .385 .350 .385 .350 NOM .172 .105 - - - .390 .353 .390 .353 MAX .180 .120 .083 .021 .032 .395 .356 .395 .356 e .050 BSC R .025 .035 .045 JEDEC Registration MS-018, Variation AA, Issue A, June, 1993. Drawings not to scale. Supertex Doc. #: DSPD-20PLCCPJ, Version C031111 Doc.# DSFP-HV6810 E070913 8 Supertex inc. www.supertex.com HV6810 20-Lead SOW (Wide Body) Package Outline (WG) 12.80x7.50mm body, 2.65mm height (max), 1.27mm pitch D 20 θ1 Note 1 (Index Area 0.25D x 0.75E1) b Top View Gauge Plane L2 L L1 e 1 E1 E Seating Plane θ View B A View B Note 1 h h A A2 Seating Plane A1 Side View View A-A A Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol MIN Dimension NOM (mm) MAX A A1 A2 b D E E1 2.15* 0.10 2.05 0.31 12.60* 9.97* 7.40* - - - - 12.80 10.30 7.50 2.65 0.30 2.55* 0.51 13.00* 10.63* 7.60* e 1.27 BSC h L 0.25 0.40 - - 0.75 1.27 L1 L2 1.40 0.25 REF BSC θ θ1 0O 5O - - 8O 15O JEDEC Registration MS-013, Variation AC, Issue E, Sep. 2005. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-20SOWWG, Version D041309. (The package drawings in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV6810 E070913 9 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com