PRODUCT/PROCESS CHANGE NOTIFICATION Generic Copy 15-NOV-2000 SUBJECT: ON Semiconductor Change Notification 10399 TITLE: Wafer fab technology change for selected ECLinPS devices EFFECTIVE DATE: 26-Feb-2001 AFFECTED CHANGE CATEGORY(S): WAFER PROCESS SUBCONTRACTOR FAB SITE DIE SHRINK DESIGN CHANGE AFFECTED PRODUCT DIVISION(S): LOGIC PRODUCTS DIV ADDITIONAL RELIABILITY DATA: Available Contact your local ON Semiconductor Sales Office. or DAVID ERHART, <[email protected]> SAMPLES: Contact Below Contact your local ON Semiconductor Sales Office. Technical Information Center, <[email protected]> FOR ANY QUESTIONS CONCERNING THIS NOTIFICATION: Contact Sales Office or TIM GURNETT, <[email protected]> DISCLAIMER: ON Semiconductor will consider this change approved unless specific conditions of acceptance are provided in writing within 30 days of receipt of this notice. To do so, contact your local ON Semiconductor sales office. DESCRIPTION AND PURPOSE: In order to better serve our customers, ON Semiconductor will increase wafer capacity by redesigning selected ECLinPS and ECLinPSLite devices from MOSAIC3 to MOSAIC5. The devices will continue to meet the same data sheet specifications. MOSAIC5 is a more advanced wafer fabrication process technology on which all ECLinPS Plus devices are currently produced. MOSAIC5 is a trench isolated, double epi, double poly, multi-layer metal, bipolar process similar to MOSAIC3, but has a minimum photolithography feature size of 0.7 um, as compared to MOSAIC3 which has a minimum photolithography feature size of 2 um. Additionally, MOSAIC5 utilizes an industry standard inorganic interlayer dielectric layer as compared to MOSAIC3 which has an organic polyimide interlayer dielectric layer. Issue Date 15 November, 2000 Page 1 of 4 ON Semiconductor Change Notification #10399 The MOS6 wafer Fab, located in Phoenix, Arizona, has been qualified to run ECLinPS Plus devices using the same arrays on the MOSAIC5 process for approximately 2 years. The MOSAIC5 process at MOS6 has been qualified to run production wafers since 1994. The device parameters will continue to meet all data book specifications. Device reliability will continue to meet ON Semiconductor standards. These device types will be available on MOSAIC 3 during the transition period in order to provide customers an opportunity to evaluate the MOSAIC5 devices in their applications. The MOSAIC5 device types will be denoted with an additional letter, "F", as the first character of the datecode marking while MOSAIC3 devices will continue to be marked with the current marking code. Customers are invited to request samples to examine for any performance variations in their applications. The following device types have been selected: MC10EL11D, MC100EL11D, MC100LVEL11D, MC10EL16D, MC100EL16D, MC100LVEL16D, MC100EL14DW, MC100LVEL14DW, MC10E111FN, MC100E111FN, MC100LVE111FN. Samples of the MC10EL11D will be available by January 16, 2001. Samples of the MC100EL11D will be available by January 16, 2001. Samples of the MC100LVEL11D will be available by January 19, 2001. Samples of the MC10EL16D will be available by October 15, 2000. Samples of the MC100EL16D will be available by November 6, 2000. Samples of the MC100LVEL16D will be available by January 19, 2001. Samples of the MC100EL14DW will be available by November 15, 2000. Samples of the MC100LVEL14DW will be available by November 17, 2000. Samples of the MC10E111FN will be available by December 18, 2000. Samples of the MC100E111FN will be available by December 27, 2000. Samples of the MC100LVE111FN will be available by November 6, 2000. Contact the (TIC) Technical Information Center @ 1-800-282-9855 regarding sample dates for each of the device types listed above. The PCN will expire 100 days after the sample date per device type. Please contact the Technical Information Center for assistance in qualifying these device types. QUALIFICATION PLAN: The Mosaic 5 Qual reports available are: MC100EP139DW 0143 2000 MC10P01D PJJA001 1999 MC10P05D PJJA002 1999 MC10EP56DT 0178 2000 RELIABILITY DATA SUMMARY: The MOSAIC 5 arrays H26R and J58R processed in MOS 6 Fab are fully qualified. Issue Date 15 November, 2000 Page 2 of 4 ON Semiconductor Change Notification #10399 ELECTRICAL CHARACTERISTIC SUMMARY: Please see below the summary comparing the BMC control lot to the MOSAIC 5 lot. All tpd, rise and fall time variance was less than 5%. The sigma for all of the MOSAIC 5 parameters were tighter than the control lot, as shown below. MS3 to MS5 Redesign - Prelminary AC/DC Summary at Nominal (-5.2 Volts) 10EL16 - Quint Differential Line Receiver Voltage -5.2 V Temp 25 C MEASUREMENT CONTROL INFO LOT Test Name Units Mean IEE mA 15.3 VBB mV -1297 IIL D uA 35.1 IIH D uA 35.2 VOL Q mV -1725 VOH Q mV -882 DIFF TPD Ps 231 XPT (++) DIFF TPD Ps 243 XPT (- -) SE TPD Ps 255 XPT (++) SE TPD Ps 262 XPT (- -) RISE TIME Q Ps 153 RISE TIME Qbar Ps 154 FALL TIME Q Ps 147 FALL TIME Qbar Ps 143 CALC = Matrix Lot used 40 units Control Lot used 40 units UPDATED TG 10/13/00 MOSAIC 5 LIMITS LOT S Mean S Lo limit Typ Hi Limit 0.2 18.8 0.3 DNC 18 22 8 -1306 6 -1350 -1250 1.6 55.3 1 0.5 DNC 1.6 74.4 1.2 DNC 150 11 -1822 10 -1950 -1630 11 -897 3 -980 -810 6 247 4 175 250 325 VARIATION Mean 10.3% 0.3% 22.3% 35.8% 2.7% 0.8% 3.3% Sigma 20.0% 14.3% 23.1% 14.3% 4.8% 57.1% 20.0% 6 252 3 175 250 325 1.8% 33.3% 8 263 4 125 250 375 1.5% 33.3% 6 267 4 125 250 375 0.9% 20.0% 4 7 5 5 155 144 158 144 6 5 5 5 100 100 100 100 225 225 225 225 350 350 350 350 0.6% 3.4% 3.6% 0.3% 20.0% 16.7% 0.0% 0.0% ABS((X-Y)/(X+Y) Summary: The major AC issues, Prop delays and Rise & Fall times match the control lot produced from the BMC Fab. The current (IEE) is slightly higher than control lot, but match data book typical and is under the 22 mA max limit. The MOSAIC 5 process sigma was much tighter than the control lot in most cases. CHANGED PART IDENTIFICATION: The trace code will have the FAB option enabled for the new parts on the MOSAIC 5 process. Issue Date 15 November, 2000 Page 3 of 4 ON Semiconductor Change Notification #10399 AFFECTED DEVICE LIST: PART MC100E111FN MC100EL11D MC100EL14DW MC100EL16D MC100LVE111FN MC100LVEL11D MC100LVEL14DW MC100LVEL16D MC10E111FN MC10EL11D MC10EL16D Issue Date 15 November, 2000 Page 4 of 4