DK-DEV-4CGX150N Dev Kit Schematic

8
7
6
5
4
NOTES:
E
1. Project Drawing Numbers:
Raw PCB
Gerber Files
PCB Design Files
Assembly Drawing
Fab Drawing
Schematic Drawing
PCB Film
Bill of Materials
Schematic Design Files
Functional Specification
PCB Layout Guidelines
Assembly Rework
3
2
REV
DATE
PAGES
A
5/15/2010
All
1
DESCRIPTION
Initial Schematic
100-0311003-A1
110-0311003-A1
120-0311003-A1
130-0311003-A1
140-0311003-A1
150-0311003-A1
160-0311003-A1
170-0311003-A1
180-0311003-A1
210-0311003-A1
220-0311003-A1
320-0311003-A1
E
Cyclone IV GX FPGA Development Kit Board
Block Diagram
2. xx Parts, xx Library Parts, xx Nets, xx Pins
PAGE
D
C
B
DESCRIPTION
1
Title, Notes, Block Diagram, Revision History
2
C4GX FPGA Package Top
3
PCI Express Edge Connector x4
4
Cyclone IV GX Transceivers
5
Cyclone IV GX Banks 3 & 4
6
Cyclone IV GX Banks 5 & 6
7
Cyclone IV GX Banks 7 & 8
8
Cyclone IV GX Configuration
9
Cyclone IV GX Clocks
10
Clock Circuitry
11
DDR2 SDRAM x32 TOP
12
DDR2 SDRAM x32 BOTTOM
13
SSRAM & FLASH
14
MAX II
15
10/100/1000 Ethernet
16
HSM Connectors
17
User IO & Connector
18
Embedded USB Blaster
19
Power Monitor
20
Cyclone IV GX Power
21
Power 1
22
Power 2
23
Power 3
24
Decoupling
D
C
B
25
26
27
28
29
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
1
of
1
1
8
7
6
Notes:
1.
E
5
4
3
2
1
Cyclone IV GX FPGA Package Top
FPGA Schematic Symbol Breakdown:
(A) Bank 3 - DDR2 SDRAM x32
(B) Bank 4 - DDR2 SDRAM x32, FLASH, SSRAM, SHARED FSM BUS
(C) Bank 5 - HSMC PORT B
(D) Bank 6 - HSMC PORT A
(E) Bank 7 - DDR2 SDRAM x32, ETHERNET
(F) Bank 8 - DDR2 SDRAM x32, mDDR SDRAM x16, LCD
(G) TRANSCEIVERS - PCIE x4/HSMB and HSMA XCVRs
(H) TRANSCEIVER POWER
( I ) Some Clocks
( J) Configuration
( K) VCC, VCCD_PLL, VCCA, VCC_CLKIN
( L) VCCIO, VREF
(M) Ground
(N) Ground and NCs
BANK 7
BANK 8
VCCIO = 1.8V
VCCIO = 1.8V
DDR2 x32
USER DIPSWITCH, PUSH BUTTONS
ETHERNET, HSMC PORT B
DDR2 x32
GRAPHIC DISPLAY
HSMC PORT B
E
Transceiver Channels 4-7
D
D
HSMC XCVR PORT A
BANK 6
VCCIO = 2.5V/1.8V
HSMC PORT A
C
C
BANK 5
Transceiver Channels 0-3
VCCIO = 2.5V
PCIE x4 or
HSMC XCVR PORT B
HSMC PORT A
B
B
BANK 3
BANKS 4
VCCIO = 1.8V
VCCIO = 1.8V
DDR2 x32
PCIE
DDR2 x32
FLASH
SSRAM
SHARED FSM BUS
A
Title
Size
B
Date:
8
7
6
5
4
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
2
of
1
1
8
7
6
5
4
3
2
1
PCI Express Edge Connector
E
E
12V_PCIE
12V_PCIE
3.3V_PCIE
J14
PCIE_T_SMBCLK
PCIE_T_SMBDAT
R98
R99
D
DNI 3.3V_PCIE_AUX
DNI PCIE_WAKEn_R
PCIE_RX_P0
PCIE_RX_N0
B1
PCIE_PRSNT2n_x1
PCIE_RX_P1
PCIE_RX_N1
PCI BRACKET
PCIE_RX_P2
PCIE_RX_N2
PCIE_RX_P3
PCIE_RX_N3
C
PCIE_PRSNT2n_x4
SW4
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
+12V
PRSNT1_N
+12V
+12V
+12V
+12V
GND
GND
SMCLK
JTAG_TCK
SMDAT
JTAG_TDI
GND
JTAG_TDO
+3_3V
JTAG_TMS
JTAG_TRSTN
+3_3V
+3_3VAUX
+3_3V
WAKE_N
PERST_N
KEY
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B12
B13
B14
B15
B16
B17
B18
RSVD1
GND
X1
GND
REFCLK+
PET0P
REFCLKPET0N
GND
GND
PER0P
PRSNT2_N_X1
PER0N
GND
GND
A12
A13
A14
A15
A16
A17
A18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
PET1P
X4
PET1N
GND
GND
PET2P
PET2N
GND
GND
PET3P
PET3N
GND
RSVD3
PRSNT2_N_X4
GND
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
RSVD2
GND
PER1P
PER1N
GND
GND
PER2P
PER2N
GND
GND
PER3P
PER3N
GND
RSVD4
PCIE_PRSNT1n
8
8
8
8
PCIE_JTAG_TCK
PCIE_JTAG_TDI
PCIE_JTAG_TDO
PCIE_JTAG_TMS
1
2
3
4
8
7
6
5
OPEN
3.3V_PCIE
PCIE_PRSNT2n_x1
PCIE_PRSNT2n_x4
USB_DISABLEn
2.5V
R232
1.00K
TDA04H0SB1
Link Width DIP Switch
PCIE_T_PERSTn
D
9 PCIE_REFCLK_P
9 PCIE_REFCLK_N
8,18 USB_DISABLEn
4 PCIE_RX_P[3:0]
PCIE_TX_P0
PCIE_TX_N0
4 PCIE_RX_N[3:0]
4 PCIE_TX_P[3:0]
4 PCIE_TX_N[3:0]
PCIE_TX_P1
PCIE_TX_N1
PCIE_TX_P2
PCIE_TX_N2
C
PCIE_TX_P3
PCIE_TX_N3
PCIE_Slot
3.3V_PCIE
1.8V
U26
PCIE_T_PERSTn
PCIE_T_SMBCLK
PCIE_T_SMBDAT
3.3V_PCIE
B
14
13
12
11
10
9
8
VCC
IO VCC1
IO VCC2
IO VCC3
IO VCC4
NC2
/TS
R241
1.00k
12V_PCIE
C107
0.1uF
A
VL
IO VL1
IO VL2
IO VL3
IO VL4
NC1
GND
1
2
3
4
5
6
7
7 PCIE_PERSTn
7 PCIE_SMBCLK
7 PCIE_SMBDAT
B
MAX3378
3.3V_PCIE
C108
0.1uF
C109
0.1uF
C388
0.1uF
C389
0.1uF
C110
0.1uF
C390
0.1uF
C387
0.1uF
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
3
of
1
1
8
7
6
5
4
3
2
1
Cyclone IV GX Transceivers
16 HSMB_RX_P[3:0]
16 HSMB_RX_N[3:0]
16 HSMB_TX_P[3:0]
E
E
16 HSMB_TX_N[3:0]
16 HSMA_RX_P[3:0]
16 HSMA_RX_N[3:0]
16 HSMA_TX_P[3:0]
U10G
D
XCVR_RX_P0
XCVR_RX_N0
XCVR_RX_P1
XCVR_RX_N1
XCVR_RX_P2
XCVR_RX_N2
XCVR_RX_P3
XCVR_RX_N3
AC2
AC1
AA2
AA1
W2
W1
U2
U1
HSMA_RX_P0
HSMA_RX_N0
HSMA_RX_P1
HSMA_RX_N1
HSMA_RX_P2
HSMA_RX_N2
HSMA_RX_P3
HSMA_RX_N3
R2
R1
N2
N1
L2
L1
J2
J1
16 HSMA_TX_N[3:0]
U10H
Cyclone IV GX
Transceivers
GXB_TX0n
GXB_TX1p
GXB_TX1n
GXB_TX2p
GXB_TX2n
GXB_TX3p
GXB_TX3n
AB4
AB3
Y4
Y3
V4
V3
T4
T3
XCVR_TX_P0
XCVR_TX_N0
XCVR_TX_P1
XCVR_TX_N1
XCVR_TX_P2
XCVR_TX_N2
XCVR_TX_P3
XCVR_TX_N3
GXB_TX4p
GXB_TX4n
GXB_TX5p
GXB_TX5n
GXB_TX6p
GXB_TX6n
GXB_TX7p
GXB_TX7n
P4
P3
M4
M3
K4
K3
H4
H3
HSMA_TX_P0
HSMA_TX_N0
HSMA_TX_P1
HSMA_TX_N1
HSMA_TX_P2
HSMA_TX_N2
HSMA_TX_P3
HSMA_TX_N3
GXB_RX0p QL0 GXB_TX0p
GXB_RX0n
GXB_RX1p
GXB_RX1n
GXB_RX2p
GXB_RX2n
GXB_RX3p
GXB_RX3n
QL1
GXB_RX4p
GXB_RX4n
GXB_RX5p
GXB_RX5n
GXB_RX6p
GXB_RX6n
GXB_RX7p
GXB_RX7n
(1.2V)
1.2V_VCCL_GXB
AD4
N7
M5
K5
AA6
P6
T6
V5
Y5
2.00K
R221
RREF0
AE1
Cyclone IV GX
Transceiver Pwr
VCCL_GXB
VCCL_GXB
VCCL_GXB
VCCL_GXB
VCCL_GXB
VCCL_GXB
VCCL_GXB
VCCL_GXB
VCCL_GXB
3 PCIE_TX_P[3:0]
2.5V_VCCA_VCCH_GXB
VCCA_GXB
VCCA_GXB
VCCA_GXB
VCCA_GXB
VCCA_GXB
M7
R6
V7
Y6
AD3
VCCH_GXB
VCCH_GXB
VCCH_GXB
VCCH_GXB
N5
L6
U6
W7
(2.5V)
3 PCIE_TX_N[3:0]
3 PCIE_RX_P[3:0]
D
3 PCIE_RX_N[3:0]
RREF0
EP4CGX150DF896_DDR2_Swap_hsmc
Version = 0.1 Preliminary
EP4CGX150DF896_DDR2_Swap_hsmc
Version = 0.1 Preliminary
XCVR_RX_P0
R84
R86
0
DNI
PCIE_RX_P0
HSMB_RX_P0
XCVR_RX_N0
R85
R87
0
DNI
PCIE_RX_N0
HSMB_RX_N0
XCVR_RX_P1
R88
R89
0
DNI
PCIE_RX_P1
HSMB_RX_P1
XCVR_RX_N1
R90
R91
0
DNI
PCIE_RX_N1
HSMB_RX_N1
XCVR_RX_P2
R92
R94
0
DNI
PCIE_RX_P2
HSMB_RX_P2
XCVR_RX_N2
R93
R95
0
DNI
PCIE_RX_N2
HSMB_RX_N2
XCVR_RX_P3
R96
R97
0
DNI
PCIE_RX_P3
HSMB_RX_P3
XCVR_RX_N3
R100
R101
0
DNI
PCIE_RX_N3
HSMB_RX_N3
C
B
XCVR_TX_P0 0.1uF
C324
PCIE_TX_P0
C323
HSMB_TX_P0
C341
PCIE_TX_N0
C340
HSMB_TX_N0
C326
PCIE_TX_P1
C325
HSMB_TX_P1
C343
PCIE_TX_N1
C342
HSMB_TX_N1
C328
PCIE_TX_P2
C327
HSMB_TX_P2
C345
PCIE_TX_N2
C344
HSMB_TX_N2
C330
PCIE_TX_P3
C329
HSMB_TX_P3
C
DNI
XCVR_TX_N0 0.1uF
DNI
XCVR_TX_P1 0.1uF
DNI
XCVR_TX_N1 0.1uF
DNI
XCVR_TX_P2 0.1uF
DNI
XCVR_TX_N2 0.1uF
DNI
XCVR_TX_P3 0.1uF
DNI
A
B
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
XCVR_TX_N3 0.1uF
DNI
C347
PCIE_TX_N3
Title
C346
HSMB_TX_N3
Size
B
Date:
8
7
6
5
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
4
of
1
1
8
7
1.8V_B3_B4
6
5
49.9
49.9
3
FSM_D[15:0]
Cyclone IV GX Bank 4
Cyclone IV GX Bank 3
AF3
AH2
AJ3
AJ4
AG5
AK4
AH6
AK5
DDR2B_DM0
DDR2B_DQS0
FSM_A17
FSM_A5
FSM_A18
HSMB_TX_D_N15
HSMB_RX_D_N13
AH4
AH5
AK3
AK6
AD10
HSMB_TX_D_P13
DDR2B_CLK_P
DDR2B_CLK_N
HSMB_RX_D_N15
HSMB_RX_D_P14
AF10
AF4
AG4
AG3
AH3
DDR2B_BA0
DDR2B_A12
DDR2B_A9
DDR2B_A3
DDR2B_A0
DDR2B_A6
DDR2B_A1
DDR2B_CASn
FSM_A7
HSMB_RX_D_P15
AA12
AB11
AG7
AH7
AG14
AH14
AK9
AK10
AJ12
AK13
C
1.8V
DQ3B/DIFFIO_B14p
DQ3B/DIFFIO_B15p
DQ3B/DIFFIO_B16p
DQ3B/DIFFIO_B17p
DQ3B/DIFFIO_B18p
DQ3B/DIFFIO_B18n
DQ3B/DIFFIO_B19n
DQ3B/DIFFIO_B21p
DM1B/DIFFIO_B5p
DQ3B/DIFFIO_B22n
DQS1B/CQ1Bn/DPCLK0/DIFFIO_B7p
DM3B/BWSn3B/DIFFIO_B12n
DQS3B/CQ3Bn/DPCLK1/DIFFIO_B21n
DIFFIO_B9p
DIFFIO_B10n
DQ5B/DIFFIO_B25n
DIFFIO_B11p
DQ5B/DIFFIO_B27p
DIFFIO_B13n
DQ5B/DIFFIO_B28n
DIFFIO_B7n
DQ5B/DIFFIO_B30p
DQ5B/DIFFIO_B31p
DIFFIO_B3n
DQ5B/DIFFIO_B33p
DIFFIO_B4p
DQ5B/DIFFIO_B35p
DIFFIO_B4n
DQ5B/DIFFIO_B35n
DIFFIO_B6p
DQ5B/DIFFIO_B36n
DIFFIO_B6n
DM5B/BWSn5B/DIFFIO_B23n
DQS5B/CQ5Bn/DPCLK2/DIFFIO_B32p
DIFFIO_B20p
DIFFIO_B20n
DIFFIO_B14n
DIFFIO_B24p
DIFFIO_B15n
DIFFIO_B24n
DIFFIO_B16n
DIFFIO_B26p
DIFFIO_B17n
DIFFIO_B26n
DIFFIO_B19p
DIFFIO_B29p
DIFFIO_B22p
DIFFIO_B29n
DIFFIO_B34p
DIFFIO_B25p
DIFFIO_B34n
DIFFIO_B27n
DIFFIO_B28p
DIFFIO_B30n
DIFFIO_B31n
DIFFIO_B33n
DIFFIO_B36p
DIFFIO_B23p
DIFFIO_B32n
AE12
AG9
AE13
AG10
AH11
AJ10
AH12
AG13
AH8
AG25
Y20
Y21
AA21
AH27
AG28
AD24
AE24
HSMB_TX_D_N7
FSM_D7
FSM_A15
HSMB_TX_D_N6
FSM_D4
AJ27
AB22
AG27
AH28
AK28
FSM_A8
HSMB_RX_D_P13
HSMB_RX_D_N16
HSMB_RX_D_P10
HSMB_RX_D_N9
HSMB_RX_D_N14
HSMB_RX_D_P11
FSM_A11
AF16
AG16
AD16
AE16
AE17
AF18
AG17
AH17
FSM_D14
FSM_A23
HSMB_RX_D_P9
HSMB_RX_D_N11
FSM_A13
HSMB_CLK_OUT_P2
HSMB_RX_D_P8
HSMB_TX_D_P11
Y18
AA18
AJ19
AK19
AF19
AG19
AK20
AK21
DDR2B_DQ14
DDR2B_DQ9
DDR2B_DQ15
DDR2B_DQ12
DDR2B_DQ11
DDR2B_DQ8
DDR2B_DQ13
DDR2B_DQ10
DDR2B_A10
AJ6
AH13
DDR2B_DM1
DDR2B_DQS1
AB16
AJ7
AK8
AA15
AE14
AK11
AH15
AH16
AK14
DDR2B_DQ23
DDR2B_DQ22
DDR2B_DQ20
DDR2B_DQ16
DDR2B_DQ19
DDR2B_DQ17
DDR2B_DQ18
DDR2B_DQ21
FSM_D0
AB13
AF15
DDR2B_DM2
DDR2B_DQS2
AF12
AH9
AF13
AH10
AG12
AG8
FSM_A14
FSM_A19
DDR2B_ODT
DDR2B_WEn
DDR2B_RASn
DDR2B_A7
AA16
AK7
AJ9
AB14
AE15
AK12
AJ13
AA13
AG15
DDR2B_A8
DDR2B_A5
DDR2B_BA1
DDR2B_A2
DDR2B_A11
DDR2B_CSn
FSM_D15
DDR2B_CKE
DDR2B_A4
2.5V
1.8V
DQ0B
DQ0B/DIFFIO_B67p
DQ0B/DIFFIO_B67n
DQ0B/DIFFIO_B69p
DQ0B/DIFFIO_B70n
DQ0B/DIFFIO_B72p
DQ0B/RUP2
DQ0B/RDN2
HSMB_TX_D_P9
AJ22
FSM_D12
AK22
HSMB_RX_D_N12 AG20
FSM_A9
AH20
HSMB_TX_D_N10
AH21
HSMB_TX_D_N13 AJ21
HSMB_CLK_IN_P2 AG22
HSMB_TX_D_N8
AH22
FSM_A25
HSMB_TX_D_N14
AF21
AF22
EP4CGX150DF896_DDR2_Swap_hsmc
C137
1.8V
Version = 0.1 Preliminary
AE19
AD22
HSMB_RX_D_N6
HSMB_TX_D_P15
AJ15
AK15
AK17
AK18
AH18
AJ18
AE18
AH19
Y19
DDR2B_DQ30
DDR2B_DQ28
DDR2B_DQ25
DDR2B_DQ27
DDR2B_DQ24
DDR2B_DQ26
DDR2B_DQ29
DDR2B_DQ31
FSM_D10
Y17
AA17
DDR2B_DM3
DDR2B_DQS3
AE20
AK24
AK25
AH23
AK27
AJ25
AG18
HSMB_RX_D_P6
HSMB_TX_D_P14
FSM_A21
FSM_D11
FSM_A24
HSMB_RX_D_N7
HSMB_RX_D_P12
AE22
FSM_D8
AG24
AH24
AJ28
AK29
AG26
AH26
AD23
AE23
FSM_D6
FSM_D13
HSMB_TX_D_P7
FSM_A2
HSMB_TX_D_P8
HSMB_TX_D_P10
FSM_D5
HSMB_TX_D_P12
12 DDR2B_BA[1:0]
USER_LED[7:0]
12
12
12
12
12
12
12
12
12
USER_DIPSW[7:0]
DDR2B_RASn
DDR2B_CASn
DDR2B_WEn
DDR2B_CSn
DDR2B_ODT
DDR2B_ODT
DDR2B_CLK_P
DDR2B_CLK_N
DDR2B_CKE
USER_LED[7:0]
7,8,9,14,17
USER_DIPSW[7:0]
7,17,20
FLASH INTERFACE
FLASH_CLK
FLASH_CLK 13,14
FLASH_OEn
9 HSMB_TX_D_P16
FLASH_OEn 9,13,14
MAX II INTERFACE
D
MAX_OEn
MAX_OEn 9,14
HSMC PORT B
HSMB_RX_LED
HSMB_RX_LED 7,17
HSMA INTERFACE
USER_DIPSW[7:0]
USER_DIPSW[7:0]
7,17,20
3,7 PCIE_PERSTn
3,7 PCIE_SMBCLK
3,7 PCIE_SMBDAT
HSMB_RX_D_P7
HSMB_RX_D_N8
HSMB_RX_D_P8
HSMB_RX_D_P9
HSMB_RX_D_N9
HSMB_TX_D_N16
C
HSMB_RX_D_P7
HSMB_RX_D_N8
HSMB_RX_D_P8
HSMB_RX_D_P9
HSMB_RX_D_N9
HSMB_TX_D_N16
2.5V
2.5V
7 HSMB_TX_D_N15
C122
C121
C136
C135
C127
C120
HSMB_CLK_OUT_P2
HSMB_CLK_OUT_P2 9
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
HSMBT_CLK_IN_P2
HSMBT_CLK_IN_P2 16
DAP
FXLA108
2.5V
VCCB
B0
B1
B2
B3
B4
B5
B6
B7
OEn
20
19
18
17
16
15
14
13
12
11
16
16
16
16
16
16
16
16
HSMB_TX_D_N13
HSMB_TX_D_N10
HSMB_TX_D_P9
HSMB_TX_D_N14
HSMB_TX_D_P15
HSMB_TX_D_N8
HSMB_TX_D_P14
HSMB_TX_D_P16
HSMB_T_RX_D_N14
HSMB_T_RX_D_N12
HSMB_T_RX_D_P6
HSMB_T_RX_D_N6
HSMB_T_RX_D_P7
HSMB_T_RX_D_N10
HSMB_T_RX_D_N8
HSMB_T_RX_D_N7
1.8V
DAP
HSMB_RX_D_P11
HSMB_RX_D_P10
HSMB_RX_D_N9
HSMB_RX_D_P9
HSMB_RX_D_P8
HSMB_RX_D_N11
HSMB_RX_D_P12
HSMB_RX_D_N16
U37
1 VCCA
2 A0
3 A1
4 A2
5 A3
6 A4
7 A5
8 A6
9 A7
10 GND
FXLA108
2.5V
VCCB
B0
B1
B2
B3
B4
B5
B6
B7
OEn
20
19
18
17
16
15
14
13
12
11
HSMB_TX_D_P12
HSMB_TX_D_N16
HSMB_TX_D_P10
HSMB_TX_D_P8
HSMB_TX_D_N7
HSMB_TX_D_P7
HSMB_TX_D_N6
HSMB_TX_D_P6
16 HSMB_T_RX_D_P11
16 HSMB_T_RX_D_P10
16 HSMB_T_RX_D_N9
16 HSMB_T_RX_D_P9
16 HSMB_T_RX_D_P8
16 HSMB_T_RX_D_N11
16 HSMB_T_RX_D_P12
16 HSMB_T_RX_D_N16
U36
1 VCCA
2 A0
3 A1
4 A2
5 A3
6 A4
7 A5
8 A6
9 A7
10 GND
FXLA108
21
1.8V
U35
1 VCCA
2 A0
3 A1
4 A2
5 A3
6 A4
7 A5
8 A6
9 A7
10 GND
FXLA108
21
HSMB_RX_D_N14
HSMB_RX_D_N12
HSMB_RX_D_P6
HSMB_RX_D_N6
HSMB_RX_D_P7
HSMB_RX_D_N10
HSMB_RX_D_N8
HSMB_RX_D_N7
U38
1 VCCA
2 A0
3 A1
4 A2
5 A3
6 A4
7 A5
8 A6
9 A7
10 GND
DAP
1.8V
A
DIFFIO_B49p
DM4B/DIFFIO_B37p
DIFFIO_B49n DQS4B/CQ5B/DPCLK3/DIFFIO_B37n
DIFFIO_B45p
DIFFIO_B45n
DIFFIO_B55p
DIFFIO_B48p
DIFFIO_B59n
DIFFIO_B48n
DIFFIO_B60n
DIFFIO_B50p
DIFFIO_B61n
DIFFIO_B50n
DIFFIO_B62n
DIFFIO_B63n
DIFFIO_B51p
DIFFIO_B47p
DIFFIO_B51n
DIFFIO_B52p
DIFFIO_B58n
DIFFIO_B52n
DIFFIO_B53p
DIFFIO_B65p
DIFFIO_B53n
DIFFIO_B65n
DIFFIO_B56p
DIFFIO_B66p
DIFFIO_B56n
DIFFIO_B66n
DIFFIO_B68p
DIFFIO_B57p
DIFFIO_B68n
DIFFIO_B57n
DIFFIO_B71p
DIFFIO_B71n
HSMB_RX_D_N10
FSM_A22
FSM_A10
FSM_D9
HSMB_RX_D_P7
FSM_A16
HSMB_TX_D_N16
E
USER INTERFACE
0.1uF
1.8V
B
AA20
AE21
AK23
AJ24
AG23
AK26
AH25
FSM_A[25:1] 8,9,13,14,20
EP4CGX150DF896_DDR2_Swap_hsmc
Version = 0.1 Preliminary
2.5V
0.1uF
12 DDR2B_A[12:0]
DQ2B/DIFFIO_B54n
DQ2B/DIFFIO_B55n
DQ2B/DIFFIO_B59p
DQ2B/DIFFIO_B60p
DQ2B/DIFFIO_B61p
DQ2B/DIFFIO_B62p
DM0B/DIFFIO_B64p
DQ2B/DIFFIO_B63p
DQS0B/CQ1B/DPCLK5/DIFFIO_B69n
DIFFIO_B70p
DM2B/DIFFIO_B46n
DIFFIO_B72n DQS2B/CQ3B/DPCLK4/DIFFIO_B58p
DIFFIO_B64n
DQ4B/DIFFIO_B39p
DIFFIO_B38p
DQ4B/DIFFIO_B39n
DIFFIO_B38n
DQ4B/DIFFIO_B42p
DIFFIO_B40p
DQ4B/DIFFIO_B42n
DIFFIO_B40n
DQ4B/DIFFIO_B43p
DIFFIO_B41p
DQ4B/DIFFIO_B43n
DIFFIO_B41n
DQ4B/DIFFIO_B46p
DIFFIO_B44p
DQ4B/DIFFIO_B47n
DIFFIO_B44n
DQ4B/DIFFIO_B54p
DAP
C138
FSM_D[15:0] 9,13,14,20
FSM_A[25:1]
12 DDR2B_DM[3:0]
2.5V
VCCB
B0
B1
B2
B3
B4
B5
B6
B7
OEn
20
19
18
17
16
15
14
13
12
11
16
16
16
16
16
16
16
1.8V
HSMB_T_TX_D_N13
HSMB_T_TX_D_N10
HSMB_T_TX_D_P9
HSMB_T_TX_D_N14
HSMB_T_TX_D_P15
HSMB_T_TX_D_N8
HSMB_T_TX_D_P14
HSMB_T_TX_D_P16
21
1.8V
DQ1B/DIFFIO_B5n
DQ1B/DIFFIO_B8p
DQ1B/DIFFIO_B8n
DQ1B/DIFFIO_B9n
DQ1B/DIFFIO_B10p
DQ1B/DIFFIO_B11n
DQ1B/DIFFIO_B12p
DQ1B/DIFFIO_B13p
FSM_A4
HSMB_RX_D_N8
FLASH_CLK
FSM_A3
FSM_A6
HSMB_TX_D_P6
RUP2
RDN2
2.5V
VCCB
B0
B1
B2
B3
B4
B5
B6
B7
OEn
20
19
18
17
16
15
14
13
12
11
16
16
16
16
16
16
16
16
HSMB_T_TX_D_P12
HSMB_T_TX_D_N16
HSMB_T_TX_D_P10
HSMB_T_TX_D_P8
HSMB_T_TX_D_N7
HSMB_T_TX_D_P7
HSMB_T_TX_D_N6
HSMB_T_TX_D_P6
2.5V
C134
1.8V
0.1uF
HSMB_CLK_IN_P2
HSMB_T_TX_D_P16 16
U33
1
2.5V
VCCA
2
GND
3
A
Title
Size
B
7
6
5
4
DIR
5
B
4
C133
0.1uF
B
HSMBT_CLK_IN_P2
Input 7,16 HSMB_T_TX_D_P11
7,16 HSMB_T_TX_D_N11
7,16
7,16
7,16
7,16
7,16
HSMB_T_TX_D_N12
HSMB_T_TX_D_P13
HSMB_T_RX_D_P13
HSMB_T_RX_D_N13
HSMB_T_RX_D_P14
7,16 HSMB_T_RX_D_P15
7,16 HSMB_T_RX_D_N15
7,16 HSMB_T_RX_D_P16
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Date:
8
VCCB
6
output
SN74AVC1T45
7,9 HSMB_TX_D_N12
7 HSMB_TX_D_P11
7,9 HSMB_TX_D_N11
7 HSMB_RX_D_N13
7 HSMB_RX_D_P13
7 HSMB_TX_D_P13
7 HSMB_RX_D_N15
7 HSMB_RX_D_P15
7 HSMB_RX_D_P14
7,9 HSMB_RX_D_P16
21
D
AE3
AD9
SHARED BUS INTERFACE
12 DDR2B_DQS[3:0]
U10A
DDR2B_DQ6
DDR2B_DQ4
DDR2B_DQ1
DDR2B_DQ3
DDR2B_DQ0
DDR2B_DQ2
DDR2B_DQ5
DDR2B_DQ7
1
12 DDR2B_DQ[31:0]
RUP2
RDN2
U10B
E
2
Cyclone IV GX Banks 3 & 4
70 pins of translation
R166
R165
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
5
of
1
1
8
7
6
5
4
3
2
1
Cyclone IV GX Banks 5 & 6
HSMC PORT A
E
E
HSMA_TX_D_P[16:0]
HSMB_CLK_IN_P1
100, 1%
R167
HSMA_TX_D_P[16:0] 16
HSMA_TX_D_N[16:0]
HSMB_CLK_IN_N1
HSMA_TX_D_N[16:0] 16
HSMA_RX_D_P[16:0]
HSMA_RX_D_P[16:0] 16
HSMA_RX_D_N[16:0]
HSMA_RX_D_N[16:0]
HSMA_CLK_IN_P[2:1]
U10D
Cyclone IV GX Bank 5
HSMA_RX_D_P15
HSMA_RX_D_N15
D
HSMB_CLK_IN_N2
HSMA_RX_D_P14
HSMA_RX_D_N16
T23
T24
V27
V28
W25
U25
T21
Y30
AA29
W27
HSMA_RX_D_N14
HSMA_RX_D_P16
W26
T25
U21
AA30
AB29
W28
HSMA_RX_D_P13
HSMA_RX_D_N13
C
T26
T27
U27
U28
HSMB_CLK_IN_N1
W29
HSMB_CLK_IN_P1
W30
V25
V26
HSMB_RX_D_N0
AA28
HSMB_TX_D_P1
Y28
HSMB_RX_D_P5
AJ30
HSMB_CLK_OUT_N1 AH30
HSMB_RX_D_N4
HSMB_RX_D_N3
AD25
AD26
HSMA_CLK_IN_N[2:1]
Cyclone IV GX Bank 6
U10C
DQ1R/DIFFIO_R34p
DQ1R/DIFFIO_R34n
DQ1R/DIFFIO_R36p
DQ1R/DIFFIO_R36n
DQ1R/DIFFIO_R39p
DQ1R/DIFFIO_R40p
DQ1R/DIFFIO_R42n
DQ1R/DIFFIO_R43n
DQ3R/DIFFIO_R46n
DQ3R/DIFFIO_R47n
DQ3R/DIFFIO_R48n
DQ3R/DIFFIO_R49n
DQ3R/DIFFIO_R50n
DQ3R/DIFFIO_R51p
DQ3R/DIFFIO_R52p
DQ3R/DIFFIO_R53p
DM1R/DIFFIO_R44n
DQ3R/DIFFIO_R53n
DQS1R/CQ1Rn/DPCLK8/DIFFIO_R38p
DM3R/BWSn3R/DIFFIO_R54p
DIFFIO_R39nDQS3R/CQ3Rn/DPCLK7/DIFFIO_R50p
DIFFIO_R40n
DIFFIO_R42p
DQ5R
DIFFIO_R43p
DQ5R/DIFFIO_R54n
DIFFIO_R44p
DQ5R/DIFFIO_R56p
DIFFIO_R38n
DQ5R/DIFFIO_R56n
DQ5R/DIFFIO_R57p
DQ5R/DIFFIO_R57n
DIFFIO_R33p
DQ5R/DIFFIO_R59n
DIFFIO_R33n
DQ5R/DIFFIO_R60p
DIFFIO_R35p
DQ5R/DIFFIO_R60n
DIFFIO_R35n
DIFFIO_R37p
DM5R/BWSn5R/DIFFIO_R61n
DIFFIO_R37nDQS5R/CQ5Rn/DPCLK6/DIFFIO_R61p
DIFFIO_R41p
DIFFIO_R41n
DIFFIO_R46p
DIFFIO_R45p
DIFFIO_R47p
DIFFIO_R45n
DIFFIO_R48p
DIFFIO_R58p
DIFFIO_R49p
DIFFIO_R58n
DIFFIO_R51n
DIFFIO_R52n
DIFFIO_R59p
RUP3
RDN3
AB30
AD30
AB28
AC28
Y22
AD27
AE29
AE27
AE28
HSMB_RX_D_P0
HSMB_RX_D_N1
HSMB_TX_D_P0
HSMB_TX_D_P2
HSMB_RX_D_N5
HSMA_D3
HSMA_CLK_OUT0
HSMB_TX_D_N4
HSMB_RX_D_P3
AG30
AA22
HSMB_TX_D_P3
HSMB_CLK_OUT0
Y25
AF30
AA27
Y27
AH29
AG29
AE26
AB25
AA25
HSMB_CLK_OUT_N2
HSMA_D2
HSMB_RX_D_P1
HSMA_D1
HSMB_D0
HSMB_D3
HSMB_TX_D_P5
HSMB_RX_D_N2
HSMB_CLK_OUT_P1
AB26
AC25
HSMB_TX_D_N2
HSMB_RX_D_P4
AC30
AD29
AB27
AC27
AD28
AE30
AE25
HSMB_TX_D_N0
HSMB_D2
HSMB_RX_D_P2
HSMA_D0
HSMB_TX_D_N9
HSMB_D1
HSMB_TX_D_N5
HSMA_CLK_OUT_P[2:1]
HSMA_TX_D_N12
HSMA_RX_D_P6
HSMA_RX_D_P3
HSMA_RX_D_P5
HSMA_RX_D_P4
HSMA_RX_D_P10
HSMA_RX_D_N10
HSMA_RX_D_P11
M28
M29
N25
N27
R24
R27
R28
T28
DQ0R/DIFFIO_R21n
DQ0R/DIFFIO_R23p
DQ0R/DIFFIO_R24p
DQ0R/DIFFIO_R25p
DQ0R/DIFFIO_R26p
DQ0R/DIFFIO_R30p
DQ0R/DIFFIO_R30n
DQ0R/DIFFIO_R32p
HSMA_RX_D_N11
HSMA_RX_D_N9
F26
F27
E27
E28
J27
H27
H25
C29
R29
P30
DQ4R/DIFFIO_R1p
DQ4R/DIFFIO_R1n
DQ4R/DIFFIO_R3p
DQ4R/DIFFIO_R3n
DQ4R/DIFFIO_R5p
DQ4R/DIFFIO_R5n
DQ4R/DIFFIO_R6n
DQ4R/DIFFIO_R7p
DM0R/DIFFIO_R32n
DQS0R/CQ1R/DPCLK9/DIFFIO_R29n DM4R/DIFFIO_R7n
DQS4R/CQ5R/DPCLK11/DIFFIO_R2p
C30
G26
HSMA_TX_D_N0
HSMA_RX_D_P1
HSMA_RX_D_P0
HSMA_TX_D_P14
HSMA_TX_D_P13
HSMA_TX_D_N13
HSMA_TX_D_P3
HSMA_TX_D_N3
HSMA_TX_D_P11
HSMA_TX_D_P5
D29
K25
K26
K27
F30
E30
L27
H30
DQ2R/DIFFIO_R9p
DQ2R/DIFFIO_R10p
DQ2R/DIFFIO_R11p
DQ2R/DIFFIO_R11n
DQ2R/DIFFIO_R13p
DQ2R/DIFFIO_R13n
DQ2R/DIFFIO_R15p
DQ2R/DIFFIO_R19p
DIFFIO_R6p
DIFFIO_R2n
J25
G27
HSMA_TX_D_P15
HSMA_RX_D_N1
P21
J26
DM2R/DIFFIO_R16p
DQS2R/CQ3R/DPCLK10/DIFFIO_R10n
DIFFIO_R4p
DIFFIO_R4n
DIFFIO_R8p
DIFFIO_R8n
DIFFIO_R12p
DIFFIO_R12n
DIFFIO_R14p
DIFFIO_R14n
F28
F29
J28
H28
G28
G29
M21
M22
HSMA_TX_D_P4
HSMA_TX_D_N4
HSMA_TX_D_P9
HSMA_TX_D_N9
HSMA_TX_D_P6
HSMA_TX_D_N6
HSMA_TX_D_P16
HSMA_TX_D_N16
DIFFIO_R17p
DIFFIO_R17n
DIFFIO_R18p
DIFFIO_R18n
DIFFIO_R20p
DIFFIO_R20n
DIFFIO_R22p
DIFFIO_R22n
K28
K29
J29
J30
L30
K30
N24
M25
HSMA_CLK_OUT_P2
HSMA_CLK_OUT_N2
HSMA_TX_D_P7
HSMA_TX_D_N7
HSMA_TX_D_P8
HSMA_TX_D_N8
HSMA_RX_D_P2
HSMA_RX_D_N2
DIFFIO_R27p
DIFFIO_R27n
DIFFIO_R28p
DIFFIO_R28n
DIFFIO_R31p
DIFFIO_R31n
N29
N30
P27
P28
R25
R26
HSMA_CLK_OUT_P1
HSMA_TX_D_N14
HSMA_TX_D_P12
HSMA_RX_D_N6
HSMA_RX_D_N3
HSMA_RX_D_N5
HSMA_RX_D_N4
HSMA_RX_D_P9
M27
M30
M26
N28
P25
R30
DIFFIO_R21p
DIFFIO_R23n
DIFFIO_R24n
DIFFIO_R25n
DIFFIO_R26n
DIFFIO_R29p
HSMA_RX_D_N0
HSMA_TX_D_N11
HSMA_TX_D_N5
HSMA_CLK_OUT_N1
D30
L28
G30
N21
DIFFIO_R9n
DIFFIO_R15n
DIFFIO_R19n
DIFFIO_R16n
EP4CGX150DF896_DDR2_Swap_hsmc
Version = 0.1 Preliminary
HSMA_TX_D_P2
HSMA_TX_D_N2
HSMA_TX_D_P1
HSMA_TX_D_N1
HSMA_TX_D_P10
HSMA_TX_D_N10
HSMA_TX_D_N15
HSMA_TX_D_P0
HSMA_CLK_OUT_N[2:1]
16
HSMA_CLK_IN_P[2:1]
9,16
HSMA_CLK_IN_N[2:1]
9,16
HSMA_CLK_OUT_P[2:1]
16
HSMA_CLK_OUT_N[2:1]
16
D
HSMA_CLK_OUT0
HSMA_CLK_OUT0 16
HSMA_TX_D_P2
HSMA_TX_D_N2
HSMA_TX_D_P2 16
HSMA_TX_D_N2 16
HSMA_D[3:0]
HSMA_D[3:0] 16
HSMC PORT B
HSMB_CLK_OUT_P[2:1]
HSMB_CLK_OUT_N[2:1]
HSMB_CLK_IN_P1
HSMB_CLK_OUT_P[2:1]
5,9,16
HSMB_CLK_OUT_N[2:1]
16
HSMB_CLK_IN_P1
HSMB_CLK_IN_N[2:1]
16
HSMB_CLK_IN_N[2:1]
HSMB_D[3:0]
C
16
HSMB_D[3:0] 16
HSMB_CLK_OUT0
HSMB_TX_LED
HSMB_CLK_OUT0 16
HSMB_TX_LED 7,17
MAX INTERFACE
HSMA_RX_D_P7
HSMA_RX_D_N7
HSMA_RX_D_P8
HSMA_RX_D_N8
HSMA_RX_D_P12
HSMA_RX_D_N12
5,9 HSMB_TX_D_P16
5 HSMB_TX_D_N16
16 HSMB_TX_D_N9
EP4CGX150DF896_DDR2_Swap_hsmc
Version = 0.1 Preliminary
B
HSMA_RX_D_P0
HSMA_RX_D_P1
HSMA_RX_D_P2
HSMA_RX_D_P3
HSMA_RX_D_P4
HSMA_RX_D_P5
HSMA_RX_D_P6
HSMA_RX_D_P7
HSMA_RX_D_P8
HSMA_RX_D_P9
HSMA_RX_D_P10
HSMA_RX_D_P11
HSMA_RX_D_P12
HSMA_RX_D_P13
HSMA_RX_D_P14
HSMA_RX_D_P15
HSMA_RX_D_P16
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
R181
R190
R194
R189
R188
R179
R180
R178
R177
R169
R176
R175
R187
R186
R185
R191
R193
B
8,16 HSMB_TX_D_P[5:0]
HSMA_RX_D_N0
HSMA_RX_D_N1
HSMA_RX_D_N2
HSMA_RX_D_N3
HSMA_RX_D_N4
HSMA_RX_D_N5
HSMA_RX_D_N6
HSMA_RX_D_N7
HSMA_RX_D_N8
HSMA_RX_D_N9
HSMA_RX_D_N10
HSMA_RX_D_N11
HSMA_RX_D_N12
HSMA_RX_D_N13
HSMA_RX_D_N14
HSMA_RX_D_N15
HSMA_RX_D_N16
16,20 HSMB_TX_D_N[5:0]
16 HSMB_RX_D_P[5:0]
16 HSMB_RX_D_N[5:0]
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
6
of
1
1
8
7
6
5
4
3
2
Cyclone IV GX Banks 7 & 8
FSM_D1
FSM_A1
FSM_A20
1.8V_B7_B8
R170
R171
49.9
49.9
RUP4
RDN4
Cyclone IV GX Bank 8
E
D
DDR2A_DM0
DDR2A_DQS0
G22
A29
DDR2A_A2
DDR2A_ODT
DDR2A_A11
DDR2A_A4
DDR2A_RASn
DDR2A_CKE
DDR2A_BA1
DDR2A_BA0
D17
C17
G18
F18
B18
A19
B19
A20
DDR2A_CSn
DDR2A_A10
DDR2A_A5
DDR2A_A3
DDR2A_A12
DDR2A_A9
DDR2A_CLK_P
DDR2A_CLK_N
D20
C20
B21
A21
F21
F20
D23
C23
HSMA_SCL
HSMA_RX_LED
ENET_MDC
HSMB_SCL
B24
C24
K21
K22
FLASH_CEn
FLASH_ADVn
DDR2A_A8
C
E25
F24
K17
RUP4
RDN4
G25
F25
DQ2T/DIFFIO_T55n
DQ2T/DIFFIO_T56n
DQ2T/DIFFIO_T57n
DQ2T/DIFFIO_T59p
DQ2T/DIFFIO_T60p
DQ2T/DIFFIO_T61p
DQ2T/DIFFIO_T62p
DQ2T/DIFFIO_T63p
DQ0T/DIFFIO_T64n
DQ0T/DIFFIO_T65p
DQ0T/DIFFIO_T66p
DQ0T/DIFFIO_T66n
DQ0T/DIFFIO_T68p
DQ0T/DIFFIO_T68n
DQ0T/DIFFIO_T69p
DQ0T/DIFFIO_T69n
DM2T/DIFFIO_T54n
DQS2T/CQ3T/DPCLK13/DIFFIO_T47p
DM0T/DIFFIO_T64p
DQS0T/CQ1T/DPCLK12/DIFFIO_T65n
DIFFIO_T55p
DIFFIO_T56p
DIFFIO_T38p
DIFFIO_T57p
DIFFIO_T38n
DIFFIO_T59n
DIFFIO_T40p
DIFFIO_T60n
DIFFIO_T40n
DIFFIO_T61n
DIFFIO_T42p
DIFFIO_T62n
DIFFIO_T42n
DIFFIO_T63n
DIFFIO_T44p
DIFFIO_T44n
DIFFIO_T54p
DIFFIO_T47n
DIFFIO_T46p
DIFFIO_T46n
DQ4T/DIFFIO_T37n
DIFFIO_T48p
DQ4T/DIFFIO_T39n
DIFFIO_T48n
DQ4T/DIFFIO_T41n
DIFFIO_T50p
DQ4T/DIFFIO_T43p
DIFFIO_T50n
DQ4T/DIFFIO_T45p
DIFFIO_T52p
DQ4T/DIFFIO_T45n
DIFFIO_T52n
DQ4T/DIFFIO_T49p
DQ4T/DIFFIO_T51p
DIFFIO_T53n
DIFFIO_T53p
DM4T/DIFFIO_T36p
DIFFIO_T67p
DQS4T/CQ5T/DPCLK14/DIFFIO_T37p
DIFFIO_T67n
DIFFIO_T58p
IO1_B7
IO2_B7
IO3_B7
DIFFIO_T39p
DIFFIO_T41p
DIFFIO_T43n
DIFFIO_T49n
DIFFIO_T51n
RUP4
RDN4
DIFFIO_T36n
DIFFIO_T58n
F19
D21
D22
A26
D26
E24
B27
B28
DDR2A_DQ15
DDR2A_DQ13
DDR2A_DQ8
DDR2A_DQ9
DDR2A_DQ11
DDR2A_DQ10
DDR2A_DQ14
DDR2A_DQ12
A24
G17
DDR2A_DM1
DDR2A_DQS1
G20 CPU_RESETn
LCD_DATA3
E21
FSM_A1
E22
A25 HSMA_PSNTn
C26 HSMB_PSNTn
FSM_A20
D24
ENET_TX_EN
A27
A28 FLASH_RESETn
B25
F17
HSMA_TX_LED
DDR2A_A6
K18
A17
C18
D19
E19
E18
C22
A23
DDR2A_DQ23
DDR2A_DQ19
DDR2A_DQ18
DDR2A_DQ17
DDR2A_DQ16
DDR2A_DQ21
DDR2A_DQ22
DDR2A_DQ20
B16
K19
D25
DDR2A_DM2
DDR2A_DQS2
HSMB_TX_LED
A18
D18
C19
B22
A22
DDR2A_WEn
DDR2A_A0
DDR2A_A1
DDR2A_A7
A16
C25
DDR2A_CASn
HSMA_SDA
LCD_DATA1
ENET_GTX_CLK
FSM_D1
LCD_DATA6
ENET_TX_D2
HSMB_RX_D_P16
LCD_CSn
HSMB_SDA
LCD_WEn
F9
D9
C9
E10
D10
D3
C3
F10
E6
ENET_TX_D0
G10
LCD_D_Cn
ENET_RESETn
USER_LED1
CLKIN_SMA
USER_LED4
SSRAM_CLK
USER_PB1
USER_LED7
ENET_RX_D1
1.8V
DQ1T/DIFFIO_T5p
DQ1T/DIFFIO_T6p
DQ1T/DIFFIO_T6n
DQ1T/DIFFIO_T7p
DQ1T/DIFFIO_T7n
DQ1T/DIFFIO_T8p
DQ1T/DIFFIO_T8n
DQ1T/DIFFIO_T9n
DQ1T/DIFFIO_T10p
DM5T/DIFFIO_T20n
DQ5T/DIFFIO_T22n
DQ5T/DIFFIO_T24p
DQ5T/DIFFIO_T26n
DQ5T/DIFFIO_T28p
DQ5T/DIFFIO_T29n
DQ5T/DIFFIO_T32p
DQ5T/DIFFIO_T32n
DQ5T/DIFFIO_T34p
DQS1T/CQ1Tn/DPCLK17/DIFFIO_T9p
DQS5T/CQ5Tn/DPCLK15/DIFFIO_T34n
D5
D6
C7
C5
D4
F11
D11
B6
B9
USER_DIPSW0
LCD_DATA2
A5
D7
USER_DIPSW2
SSRAM_E1n
USER_DIPSW4
PCIE_SMBDAT
E9
C6
C4
E12
C11
A7
A9
A6
E7
PCIE_PERSTn
MAX_WEn
USER_DIPSW7
USER_LED5
ENET_RX_D0
USER_PB2
USER_LED0
ENET_TX_D1
DQ3T/DIFFIO_T10n
DQ3T/DIFFIO_T11p
DQ3T/DIFFIO_T11n
DQ3T/DIFFIO_T12n
DQ3T/DIFFIO_T13p
DQ3T/DIFFIO_T14p
DQ3T/DIFFIO_T17p
DQ3T/DIFFIO_T18p
DQ3T/DIFFIO_T19p
J9
F5
F4
E4
E3
DIFFIO_T20p
DIFFIO_T22p
DIFFIO_T24n
DIFFIO_T26p
DIFFIO_T28n
DIFFIO_T29p
FLASH_RDYBSYn
B7
USER_DIPSW6
G12
ENET_RX_D3
E13
PCIE_LED_X1
D14
LCD_DATA0
C15
MAX_CSn
B12
DIFFIO_T5n
DIFFIO_T12p
DIFFIO_T13n
DIFFIO_T14n
DIFFIO_T17n
DIFFIO_T18n
DIFFIO_T19n
DIFFIO_T16p
DIFFIO_T15p
DIFFIO_T25p
DIFFIO_T25n
DIFFIO_T27p
DIFFIO_T27n
D13
C13
A11
A10
SSRAM_BAn
FLASH_WEn
ENET_INTN
PCIE_LED_X4
DIFFIO_T30p
DIFFIO_T30n
DIFFIO_T31p
DIFFIO_T31n
DIFFIO_T33p
DIFFIO_T33n
DIFFIO_T35p
DIFFIO_T35n
F14
E15
F15
E16
G14
G13
G15
F16
USER_DIPSW5
ENET_RX_DV
PCIE_SMBCLK
IO1_B8
HSMB_T_SCL 16
HSMB_T_SDA 16
0.1uF
0.1uF
0.1uF
FXLA108
2.5V
VCCB
B0
B1
B2
B3
B4
B5
B6
B7
OEn
20
19
18
17
16
15
14
13
12
11
1.8V
D8
3
6
HSMB_SCL
HSMB_SDA
5
4
VCC
7
VCCIO1
VCCIO2
GND
8
1
2
VL
TRI_STATE
VL_IO1
VL_IO2
HSMB_T_RX_D_N13
HSMB_T_TX_D_P13
HSMB_T_TX_D_N12
HSMB_T_TX_D_N11
HSMB_T_TX_D_P11
HSMB_T_RX_D_P13
0.1uF
HSMB_T_SCL
HSMB_T_SDA
MAX3373
1.8V
1.8V
C319
C280
0.1uF
0.1uF
1.8V
ENET_TX_D0
ENET_RX_D3
ENET_RX_D2
ENET_RX_D1
ENET_RX_D0
ENET_RX_DV
ENET_TX_EN
ENET_GTX_CLK
U49
1 VCCA
2 A0
3 A1
4 A2
5 A3
6 A4
7 A5
8 A6
9 A7
10 GND
ENET_RESETn
ENET_MDIO
ENET_INTN
ENET_MDC
20
19
18
17
16
15
14
13
12
11
16
16
16
16
16
HSMB_T_TX_D_N15
HSMB_T_RX_D_P16
HSMB_T_RX_D_N15
HSMB_T_RX_D_P15
HSMB_T_RX_D_P14
2.5V
1.8V
C116
C115
0.1uF
0.1uF
1.8V
U31
3
6
HSMA_SCL
HSMA_SDA
5
4
VCC
VCCIO1
VCCIO2
GND
8
1
2
VL
TRI_STATE
VL_IO1
VL_IO2
2.5V
7
LCD_DATA7
LCD_DATA6
LCD_DATA5
LCD_DATA3
LCD_DATA2
ENET_TX_D3
ENET_TX_D2
ENET_TX_D1
HSMA_T_SCL 16
HSMA_T_SDA 16
U46
1 VCCA
2 A0
3 A1
4 A2
5 A3
6 A4
7 A5
8 A6
9 A7
10 GND
DAP
DAP
VCCB
B0
B1
B2
B3
B4
B5
B6
B7
OEn
21
FXLA108
2.5V
20
19
18
17
16
15
14
13
12
11
FXLA108
USER_PB[3:0]
17
USER_LED[7:0]
6
4
DDR2A_RASn
FLASH_RDYBSYn
DDR2A_WEn
DDR2A_CSn
DDR2A_ODT
DDR2A_ODT
DDR2A_CLK_P
DDR2A_CLK_N
DDR2A_CKE
DDR2A_CASn
D
ENET_MDIO
ENET_MDIO 9,15
HSMA_TX_LED 17
HSMA_RX_LED 17
8,9,14,17
ETHERNET RGMII INTERFACE
CLKIN_SMA 9
9,15 ENET_T_RX_CLK
PCIE_LED_X4 17
PCIE_LED_X1 17 15 ENET_T_RX_DV
LCD_CSn
LCD_WEn
LCD_DATA0
LCD_DATA1
LCD_CSn 17
LCD_WEn 17
LCD_DATA0 17
LCD_DATA1 17
ENET_T_TX_D0
ENET_T_RX_D3
ENET_T_RX_D2
ENET_T_RX_D1
ENET_T_RX_D0
ENET_T_RX_DV
ENET_T_TX_EN
ENET_T_GTX_CLK
C
17 LCD_D_Cn
CLKIN_SMA
PCIE_LED_X4
PCIE_LED_X1
2.5V
removed ENET_CRS
15 ENET_T_TX_D[3:0]
15 ENET_T_GTX_CLK
15 ENET_T_TX_EN
ETHERNET CONTROL INTERFACE
2.5V
C320
C281
15 ENET_RESETn
15 ENET_INTn
9,15 ENET_MDIO
0.1uF
0.1uF
17,20 USER_DIPSW[7:0]
B
3 PCIE_PERSTn
3 PCIE_SMBCLK
3 PCIE_SMBDAT
2.5V
VCCB
B0
B1
B2
B3
B4
B5
B6
B7
OEn
20
19
18
17
16
15
14
13
12
11
LCD_T_DATA7
LCD_T_DATA6
LCD_T_DATA5
LCD_T_DATA3
LCD_T_DATA2
ENET_T_TX_D3
ENET_T_TX_D2
ENET_T_TX_D1
Title
Size
3
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
B
5
DDR2A_BA[1:0]
CPU_RESETn 17 15 ENET_T_RX_D[3:0]
Date:
7
DDR2A_A[12:0]
17 LCD_T_DATA[3:2]
CPU_RESETn
MAX3373
8
DDR2A_DM[3:0]
LCD DISPLAY INTERFACE
17 LCD_T_DATA[7:5]
2.5V
U28
1 VCCA
HSMB_TX_D_N15 5 2
A0
HSMB_RX_D_P16 9
3 A1
HSMB_RX_D_N15 5
4 A2
HSMB_RX_D_P15 5
5 A3
HSMB_RX_D_P14 5
6 A4
7 A5
8 A6
9 A7
10 GND
DDR2A_DQS[3:0]
HSMA_TX_LED
ENET_RESETn 15
ENET_MDIO 9,15
14,16 HSMA_PSNTn
ENET_INTN 15
ENET_MDC 15
HSMA_RX_LED
2.5V
VCCB
B0
B1
B2
B3
B4
B5
B6
B7
OEn
E
14,16 HSMB_PSNTn
HSMB_RX_LED 17
HSMB_TX_LED 17
USER_LED[7:0]
5
5
5
5
5
5
DDR2A x32 INTERFACE
11 DDR2A_DQ[31:0]
HSMC INTERFACE
USER_PB[3:0]
U39
FXLA108
1.8V
A
16
16
16
16
16
16
FLASH_CEn
FLASH_ADVn
FLASH_WEn
21
5
5
9
9
5
5
DAP
HSMB_RX_D_N13
HSMB_TX_D_P13
HSMB_TX_D_N12
HSMB_TX_D_N11
HSMB_TX_D_P11
HSMB_RX_D_P13
U29
1 VCCA
2 A0
3 A1
4 A2
5 A3
6 A4
7 A5
8 A6
9 A7
10 GND
FLASH_RESETn
2.5V
21
1.8V
11
SSRAM_BAn 13
SSRAM_BBn 9,13 11
SSRAM_ADVn 13
SSRAM_ADSCn 13 11
SSRAM_ADSPn 13
SSRAM_E1n 13
11
SSRAM_CLK 13
SSRAM_BWn 9,13 11
SSRAM_Gn 9,13
13,14
SSRAM_GWn 13,14 11
11
11
11
11
FLASH_RESETn 13,1411
11
FLASH_CEn 13,14 11
FLASH_ADVn 13,14
FLASH_WEn 13,14
USER_PB3
DAP
C129
SSRAM_BAn
SSRAM_BBn
SSRAM_ADVn
SSRAM_ADSCn
SSRAM_ADSPn
SSRAM_E1n
SSRAM_CLK
SSRAM_BWn
SSRAM_Gn
SSRAM_GWn
21
C119
MAX_CSn 14
MAX_WEn 14
HSMB_RX_LED
HSMB_TX_LED
C130
C118
B
SHARED BUS INTERFACE
9,15
MAX_CSn
MAX_WEn
ENET_RX_D2
LCD_DATA5
USER_DIPSW1
LCD_DATA7
HSMB_RX_D_P7
HSMB_RX_D_N8
HSMB_RX_D_P8
HSMB_RX_D_P9
HSMB_RX_D_N9
HSMB_TX_D_N16
Version = 0.1 Preliminary
1.8V
DDR2A_DQS3
DIFFIO_T21n
DIFFIO_T21p
DIFFIO_T23p
DM3T/BWSn3T/DIFFIO_T16n
DIFFIO_T23n
DQS3T/CQ3Tn/DPCLK16/DIFFIO_T15n
2.5V
Version = 0.1 Preliminary
C16
USER_PB0
USER_LED6
HSMB_RX_LED
ENET_TX_D3
DIFFIO_T1p
DIFFIO_T2p
DIFFIO_T2n
DIFFIO_T3p
DIFFIO_T3n
HSMB_T_SCL
HSMB_T_SDA
A8
F12
F13
C14
D15
A12
A14
A13
D16
DDR2A_DM3
DDR2A_DQ31
DDR2A_DQ29
DDR2A_DQ25
DDR2A_DQ30
DDR2A_DQ26
DDR2A_DQ27
DDR2A_DQ24
DDR2A_DQ28
C12
D12
C10
B10
EP4CGX150DF896_DDR2_Swap_hsmc
EP4CGX150DF896_DDR2_Swap_hsmc
1.8V
9,15
9,15
9,15
HSMB_RX_D_P16
HSMB_RX_D_P16
Cyclone IV GX Bank 7
F22
B30
G23
F23
H24
G24
D28
C28
FSM_D1
FSM_A1
FSM_A20
U10F
U10E
DDR2A_DQ7
DDR2A_DQ6
DDR2A_DQ0
DDR2A_DQ5
DDR2A_DQ4
DDR2A_DQ2
DDR2A_DQ1
DDR2A_DQ3
1
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
7
of
1
1
8
7
6
5
4
3
2
Cyclone IV GX Configuration
3.3V
U10J
J16
Place at end of chain
Cyclone IV GX Configuration
2.5V
R225
10.0K
FPGA_DCLK
FPGA_CONFIGn
FPGA_DATA0
FPGA_DATA1
FPGA_DATA2
FPGA_DATA3
FPGA_DATA4
FPGA_DATA5
FPGA_DATA6
FPGA_DATA7
B3
B1
A3
G9
H9
D1
C2
AE4
AE5
AE10
AD6
USER_LED2
D
SYS_RESETn
HSMB_TX_D_P4
R230
10.0K
A4
AF27
AF28
FPGA_CEn
C1
Bank 9
Bank 3
INIT_DONE
nSTATUS
CONF_DONE
DCLK
nCONFIG
CRC_ERROR/DIFFIO_B1p
3.3V
U18
Bank 8
2.5V
MSEL0
MSEL1
MSEL2
MSEL3
AD7
AD8
AC7
AC8
nCEO/DIFFIO_B1n
AE7
Bank 3
10.0K
10.0K
10.0K
10.0K
MSEL0
MSEL1
MSEL2
MSEL3
R214
R219
R215
R220
3
4
5
6
11
12
13
14
NC01
NC02
NC03
NC04
NC05
NC06
NC07
NC08
EPCS128
Bank 8
Bank 9 nCSO
DEV_CLRn/DIFFIO_R55p
DEV_OE/DIFFIO_R55n
nCE
DNI
1
3
5
7
9
CONFIGURATION INTERFACE
2
4
6
8
10
2
4
6
8
10
14 FPGA_DATA[7:0]
FPGA_CEn
FPGA_CSOn
14
14,17
14,18
14
14,17
18
DNI
Bank 9
DATA0
DATA1/ASDO
DATA2/DIFFIO_T1n
DATA3/DIFFIO_T4p
DATA4/DM1T/BWSn1T/DIFFIO_T4n
DATA5/DIFFIO_B2p
DATA6/DIFFIO_B2n
DATA7/DIFFIO_B3p
CLKUSR
C331
GND
AE8
FPGA_STATUSn
AJ1
FPGA_CONF_DONE AB9
DNI
B4
FPGA_CSOn
FPGA_DCLK
FPGA_CONF_DONE
FPGA_STATUSn
FPGA_CONFIGn
SYS_RESETn
FPGA_CEn
E
JTAG
DATA
DCLK
nCS
ASDI
EPCS_DATA R222
FPGA_DCLK
FPGA_CSOn
EPCS_ASDI R224
8
16
7
15
14,16,18
14,16,18
14
18
24.9 FPGA_DATA0
24.9 FPGA_DATA1
JTAG_TCK
JTAG_TMS
JTAG_FPGA_TDO
JTAG_BLASTER_TDO
16 HSMA_JTAG_TDI
16 HSMB_JTAG_TDI
18 JTAG_BLASTER_TDI
2.5V
10
10.0K
100, 1%
R229
JTAG_TCK
JTAG_TMS
JTAG_FPGA_TDO
JTAG_BLASTER_TDO
1
3
5
7
9
1
2
9
R156
R228
TCK
TMS
TDO
TDI
F2
E1
F1
E2
FPGA_DCLK
FPGA_CONF_DONE
FPGA_CONFIGn
EPCS_DATA
EPCS_ASDI
VCC01
VCC02
VCC03
E
1
14 JTAG_EPM2210_TDO
16 HSMA_JTAG_TDO
16 HSMB_JTAG_TDO
Bank 5
R8
100, 1%
C2
Bank 9
0.1uF
D
3,18 USB_DISABLEn
EP4CGX150DF896_DDR2_Swap_hsmc
Version = 0.1 Preliminary
USB Blaster Programming Header
(uses JTAG mode only)
U1
USER_LED2 14,17
HSMB_TX_D_P4 16
USER_LED2
HSMB_TX_D_P4
1
2.5V
J6
USB_DISABLEn
2
4
6
8
10
JTAG_TCK
JTAG_BLASTER_TDI
JTAG_TMS
1
3
5
7
9
2.5V
R53
R50
JTAG_BLASTER_TDO
10.0K
EPM2210_JTAG_EN
10.0K
R54
1.00k
3.3V
HSMA_JTAG_EN
D37
10pF
C308
EPCS_DATA
10pF
C309
EPCS_ASDI
10pF
C310
FPGA_CSOn
1
2
3
4
CMDSH2_3
7
HSMA_JTAG_TDO
8
7
6
5
EPM2210_JTAG_EN
HSMA_JTAG_EN
HSMB_JTAG_EN
PCIE_JTAG_EN
R245
R244
R243
R242
C348
0.1uF
C
NLAS4717EPMTR2G
When Pins 4 & 8 are:
LOW --> Pins 5 & 7 = ON and Pins 2 & 10 = OFF
2.5V
HIGH --> Pins 2 &10 = ON and Pins 5 & 7 = OFF
R3
100, 1%
C1
0.1uF
B
C358
U51
JTAG_TCK
JTAG_PCIE_TDI
JTAG_PCIE_TDO
JTAG_TMS
PCIE_JTAG_EN
1
2
3
4
5
6
8
VCCA
A1
A2
A3
A4
NC1
EN
FPGA Not Installed Jumper
VCCY
Y1
Y2
Y3
Y4
NC2
GND
14
13
12
11
10
9
7
3
3
3
3
PCIE_JTAG_TCK
PCIE_JTAG_TDI
PCIE_JTAG_TDO
PCIE_JTAG_TMS
U2
1
HSMB_JTAG_TDO
5
HSMB_JTAG_EN
2
4
DNI
Logic 0 = pin 5 --> pin 3 (EPM2210 Enabled)
Logic 1 = pin 2 --> pin 3 (EPM2210 Bypass)
PCIE_JTAG_EN
3
JTAG_PCIE_TDI
7
JTAG_PCIE_TDO
10
8
9
JTAG_BLASTER_TDI
A
6
NLAS4717EPMTR2G
Title
B
Date:
7
6
5
4
3
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Size
8
MSEL0 14
MSEL2 14
MSEL3 14
NLAS4717 Switch Functions
1.00k
1.00k
1.00k
10.0K
ON = not-in-chain
OFF = in-chain
3.3V_PCIE
MSEL0
MSEL2
MSEL3
HSMB_JTAG_TDI
TDA04H0SB1
2.5V
0.1uF
HSMA_JTAG_TDI
2.5V
JTAG Chain Control
SW5
CMDSH2_3
D39
B
3
10
6
OPEN
FPGA_DCLK
JTAG_FPGA_TDO
9
CMDSH2_3
D40
C311
2
8
CMDSH2_3
D38
10pF
JTAG_EPM2210_TDO
4
70247-1051
C
5
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
8
of
1
1
100, 1%
100, 1%
R174
R168
6
HSMA_CLK_IN_N1
HSMA_CLK_IN_N2
PCIE_REFCLK_P
PCIE_REFCLK_N
5
0
0
R268
R267
CLKA_IN_P0
R208
49.9
0.1uF
2.5V
R216
1.00k
R210
1.00k
PCIE_REFCK_P
PCIE_REFCK_N
N66134802
CLKA_IN_C_P1
CLKA_IN_C_N1
R209
49.9
C384
CLKA_IN_N0
CLKA_IN_C_P1
2.5V
R212
1.00k
R207
V30
V29
R205
49.9
HSMA_CLK_IN_N1
HSMA_CLK_IN_P1
T30
T29
C386
0.1uF
C69
CLKIN_125M_P
C
CLKIN_C_125M_N
CLKIN_C_125M_P
CLKIN_C_125M_P
R197
49.9
0.1uF
2.5V
R195
1.00k
R196
1.00k
CLKA_IN_C_P0
CLKA_IN_C_N0
N66186150
CLKIN_125M_N
1.8V
CLKIO6/DIFFCLK_3n
CLKIO7/DIFFCLK_3p
HSMBT_CLK_IN0
VCCA
2
GND
3
output
VCCB
6
DIR
5
A
PLL3_CLKOUTp
PLL3_CLKOUTn
AF24
AF25
CLKOUT_SMA
HSMB_TX_D_P16
4
B
6
DIR
5
B
4
HSMB_CLK_IN_N[2:1]
1
CLKIN_SMA
HSMB_CLK_OUT_P[2:1]
SSRAM_BBn
LCD_DATA4
D27
C27
USER_LED3
K15
L15
REFCLK3n/CLKIO10/DIFFCLK_4n
REFCLK3p/CLKIO11/DIFFCLK_4p
L11
K11
M10
L10
REFCLK4p/DIFFCLK_8p/CLKIO17
REFCLK4n/DIFFCLK_8n
REFCLK5p/DIFFCLK_9p/CLKIO19
REFCLK5n/DIFFCLK_9n
Bank 8A
FSM_D3
SSRAM_BBn
LCD_DATA4
HSMB_TX_D_N11
HSMB_TX_D_N12
HSMB_TX_D_P16
SSRAM_Gn
USER_LED3
ENET_MDIO
FLASH_OEn
MAX_OEn
SSRAM_BWn
G6
F6
G7
F7
G8
F8
HSMAT_CLK_IN0
output
GND
3
A
2
HSMB_T_CLK_OUT_P2 3
1.8V
VCCB
GND
DIR
5
B
4
A
2.5V
1.8V
C125
C126
U22
1
A
VCCA
2.5V
0.1uF
0.1uF
VCCB
ENET_RX_CLK
2
GND
DIR
GND
3
A
5
output
3
A
B
4
C123
C128
0.1uF
0.1uF
7
VCCB
SN74AVC1T45
5
B
4
C132
0.1uF
0.1uF
5,6,16
HSMB_CLK_OUT_N[2:1]
6,16
HSMB_CLK_IN0 16
USER_DIPSW[7:0]
7,17,20
C
SSRAM_Gn
SSRAM_Gn 13
FLASH_OEn 13,14
MAX_OEn 14
SSRAM_BWn 13
ENET_MDIO 15
CLKIN_SMA 7
B
1.8V
2.5V
6
DIR
C117
C354
C355
0.1uF
0.1uF
1.8V
C86
C85
0.1uF
0.1uF
ENET_T_RX_CLK 15
ENET_T_RX_CLK
Input
Title
Size
B
5
4
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
CLKIN_50
6
6,16
HSMB_CLK_OUT_P[2:1]
CLKIN_SMA
Date:
8
6,16
1.8V
Input
SN74AVC1T45
HSMB_CLK_IN_P1
HSMB_CLK_IN_N[2:1]
ENET_MDIO
output
CLKIN_T_50
6,16
HSMA_TX_LED 7,17
HSMA_CLK_IN0 16
10,14 CLKIN_50
1.8V
2.5V
2.5V
VCCA
2
6
HSMA_CLK_OUT_N[2:1]
Input
U20
1
6,16
HSMB_CLK_OUT_P2
2.5V
Input
HSMA_CLK_OUT_P[2:1]
CLKA_IN_P0
CLKA_IN_N0
CLKA_IN_P1
CLKA_IN_N1
HSMB_CLK_OUT_P2 5
HSMB_T_CLK_OUT_P2 16
2.5V
HSMA_CLK_IN0
1.8V
E
10 CLKIN_125M_P
10 CLKIN_125M_N
HSMB_TX_D_N11 7
HSMB_TX_D_N12 7
HSMB_TX_D_P16 5
HSMB_CLK_OUT_P2
HSMB_T_CLK_OUT_P2
6
SN74AVC1T45
SN74AVC1T45
1.8V
10
10
10
10
FLASH_OEn
MAX_OEn
SSRAM_BWn
U34
VCCA
16
CLOCK INTERFACE
FSM_D3 13,14
SSRAM_BBn 13
LCD_DATA4 17
EP4CGX150DF896_DDR2_Swap_hsmc
HSMB_CLK_IN0
HSMA_CLK_IN_N[2:1]
3 PCIE_REFCLK_P
3 PCIE_REFCLK_N
USER_LED3 14,17
Bank 8B
1
16
USER INTERFACE
USER_DIPSW[7:0]
CLKIO8/DIFFCLK_5n
CLKIO9/DIFFCLK_5p
HSMA_TX_D_N[16:0] 6,16
HSMA_CLK_IN_P[2:1]
D
(external clock source)
output
2
HSMB_CLK_OUT_N[2:1]
R67
49.9
HSMB_CLK_IN0
A15
B15
Input
VCCB
HSMB_CLK_IN_P1
J10
Bank 7
2.5V
2.5V
VCCA
HSMB_TX_D_N11
Version = 0.1 Preliminary
U32
1
FSM_D3
HSMB_TX_D_N12
PLL2_CLKOUTn
PLL7_CLKOUTp
PLL7_CLKOUTn
PLL8_CLKOUTp
PLL8_CLKOUTn
2.5V
SN74AVC1T45
1.8V
AE6
AF6
AF7
AG6
AE9
AF9
PLL4_CLKOUTp
PLL4_CLKOUTn
HSMA_TX_D_P[16:0] 6,16
HSMC PORT B
PLL1_CLKOUTn
PLL5_CLKOUTp
PLL5_CLKOUTn
PLL6_CLKOUTp
PLL6_CLKOUTn
Bank 8 PLL2_CLKOUTp
U30
1
HSMA_TX_LED
HSMA_CLK_IN0
Bank 6
CLKIN_C_125M_N
0.1uF
HSMA_CLK_OUT_N[2:1]
CLKIO4/DIFFCLK_2n
CLKIO5/DIFFCLK_2p
R198
49.9
C70
B
CLKIO14/DIFFCLK_6p
CLKIO15/DIFFCLK_6n
CLKA_IN_C_N1
HSMAT_CLK_IN0
ENET_RX_CLK
HSMA_CLK_OUT_P[2:1]
Bank 5
HSMA_CLK_IN_N2
HSMA_CLK_IN_P2
1.00k
CLKOUT_SMA
1
Bank 4
AJ16
AK16
N66160004
CLKA_IN_N1
HSMA_CLK_IN_N[2:1]
REFCLK0p/DIFFCLK_0p/CLKIO20
REFCLK0n/DIFFCLK_0n
REFCLK1p/DIFFCLK_1p/CLKIO22
REFCLK1n/DIFFCLK_1n
C385
R206
49.9
J9
Bank 3B
0.1uF
0.1uF
HSMA_CLK_IN_P[2:1]
Bank 3 PLL1_CLKOUT9
HSMBT_CLK_IN0
CLKIN_T_50
HSMA_TX_D_N[16:0]
SMA Connector
CLKA_IN_C_N0
CLKA_IN_P1
HSMA_TX_D_P[16:0]
REFCLK2p/CLKIO12/DIFFCLK_7p
REFCLK2n/CLKIO13/DIFFCLK_7n
V11
W11
V12
W12
1
HSMC PORT A
Bank 3A
V15
W15
2
Cyclone IV GX Clocks
Cyclone IV GX Clocks
CLKA_IN_C_P0
E
3
PCIE_REFCK_P
PCIE_REFCK_N
U10I
C383
D
4
5
4
3
2
HSMA_CLK_IN_P1
HSMA_CLK_IN_P2
7
5
4
3
2
8
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
9
of
1
1
8
7
6
5
4
3
2
1
General Clock Circuitry
2.5V
Clock Enable
2.5V
C89
R109
R110
R111
R112
1.00k
1.00k
1.00k
1.00k
3.3V
CLKA_EN
2
CLKA_SDA
7
CLKA_SCL
8
3
From EPM2210
NIOS CPU Clock
2
GND
CLK-
5
SCL
CLK+
4
GND
NC
1
OE
SDA
4.7K
4.7K
U25
8
2
100M_OSC_P
R79
100, 1%
100M_OSC_N
CLKIN_SMA_CP
CLKIN_SMA_CN
100MHz
From EPM2210 and DIP SW1
X3
4.7K
CLK50_EN
1 EN
VCC
R70
VCC
6
OE
CLK_EN
C93
0.1uF
4
J11
CLKIN_50
3
OUT
ECS-3525-500-B
C106
C90
C376
0.1uF
0.1uF
2.2uF
C17
C96
2.2uF
0.1uF
To FPGA and
EPM2210
C94
0.1uF
CLKA_IN_P0
CLKA_IN_N0
Q1p
Q1n
17
16
CLKA_IN_P1
CLKA_IN_N1
9 CLKIN_125M_P
9 CLKIN_125M_N
PCLKp
PCLKn
Q2p
Q2n
15
14
CLK_SEL
Q3p
Q3n
12
11
3
ICS8543
84.5
84.5
20
19
6
7
3.3V
R74
R75
Q0p
Q0n
9
9
9
9
CLKp
CLKn
To Board Settings
DIP Switch
1 CLKIN_SMA_P
LTI-SASF546-P26-X1
100, 1%
100, 1%
CLKA_SEL
CLOCK INTERFACE
LVDS
4
5
2.5V
5
4
3
2
2.5V
R260
R259
X4
TDA04H0SB1
D
C88
0.1uF 10uF
10
18
USER_FACTORY
CLK125_EN
CLKA_EN
CLKA_SEL
VDD
VDD
1
2
3
4
GND
GND
GND
OPEN
8
7
6
5
E
3.3V
SW1
CLKA_IN_P0
CLKA_IN_N0
CLKA_IN_P1
CLKA_IN_N1
9,14 CLKIN_50
From EPM2210
D
14 CLKA_SDA
14 CLKA_SCL
14 CLKA_EN
CLK50_EN
14 CLK125_EN
1
9
13
E
R73
R72
3.3V
J12
2.5V
From EPM2210 and DIP SW1
LVPECL INPUT CLOCK
4.7K
CLK125_EN
1
EN
OUT
4
CLKIN_125M_P
2.5V
2
NC
OUTn
5
CLKIN_125M_N
6
VCC
GND
3
C76
C75
0.1uF
10uF
5
4
3
2
X2
R65
1 CLKIN_SMA_N
LTI-SASF546-P26-X1
R68
R69
C95
C101
0.1uF
0.1uF
9,14 USER_FACTORY
CLKA_SEL Settings:
125.0MHz
C
CLKIN_SMA_CP
CLKIN_SMA_CN
124
124
Setting
SWx, DIP4
High
PCLKp/n
Low
CLKp/n
C
B
B
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
10
of
1
1
8
7
6
5
4
3
DDR2 SDRAM x32 TOP
U8A
E
DDR2A_A0
DDR2A_A1
DDR2A_A2
DDR2A_A3
DDR2A_A4
DDR2A_A5
DDR2A_A6
DDR2A_A7
DDR2A_A8
DDR2A_A9
DDR2A_A10
DDR2A_A11
DDR2A_A12
U15A
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
R3
R7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RFU/A13
RFU/A14
RFU/A15
L2
L3
L1
BA0
BA1
RFU
DDR2A_BA0
DDR2A_BA1
D
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR2A_DQ0
DDR2A_DQ1
DDR2A_DQ2
DDR2A_DQ3
DDR2A_DQ4
DDR2A_DQ5
DDR2A_DQ6
DDR2A_DQ7
DDR2A_DQ8
DDR2A_DQ9
DDR2A_DQ10
DDR2A_DQ11
DDR2A_DQ12
DDR2A_DQ13
DDR2A_DQ14
DDR2A_DQ15
UDQS_P
UDQS_N
B7
A8
DDR2A_DQS1
LDQS_P
LDQS_N
F7
E8
DDR2A_DQS0
K2
J8
K8
DDR2A_CKE
DDR2A_CLK_P
DDR2A_CLK_N
DDR2A_DM0
DDR2A_DM1
F3
B3
LDM
UDM
DDR2A_RASn
DDR2A_CASn
DDR2A_WEn
DDR2A_CSn
K7
L7
K3
L8
RASn
CASn
WEn
CSn
CKE
CK_P
CK_N
DDR2A_ODT
K9
ODT
VREF
DDR2A_A0
DDR2A_A1
DDR2A_A2
DDR2A_A3
DDR2A_A4
DDR2A_A5
DDR2A_A6
DDR2A_A7
DDR2A_A8
DDR2A_A9
DDR2A_A10
DDR2A_A11
DDR2A_A12
J2
L2
L3
L1
BA0
BA1
RFU
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR2A_DQ16
DDR2A_DQ17
DDR2A_DQ18
DDR2A_DQ19
DDR2A_DQ20
DDR2A_DQ21
DDR2A_DQ22
DDR2A_DQ23
DDR2A_DQ24
DDR2A_DQ25
DDR2A_DQ26
DDR2A_DQ27
DDR2A_DQ28
DDR2A_DQ29
DDR2A_DQ30
DDR2A_DQ31
UDQS_P
UDQS_N
B7
A8
DDR2A_DQS3
LDQS_P
LDQS_N
F7
E8
DDR2A_DQS2
K2
J8
K8
DDR2A_CKE
DDR2A_CLK_P
DDR2A_CLK_N
DDR2A_DM2
DDR2A_DM3
F3
B3
LDM
UDM
DDR2A_RASn
DDR2A_CASn
DDR2A_WEn
DDR2A_CSn
K7
L7
K3
L8
RASn
CASn
WEn
CSn
CKE
CK_P
CK_N
DDR2A_ODT
K9
ODT
VREF
VREF_B7_B8
J2
MT47H16M16
C230
C260
1.8V
0.1uF
1.8V
RN4B
RN3E
RN4A
RN3H
RN3F
RN4D
RN3C
RN4C
2
5
1
8
6
4
3
3
15
12
16
9
11
13
14
14
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DDR2A_DQ8
DDR2A_DQ9
DDR2A_DQ10
DDR2A_DQ11
DDR2A_DQ12
DDR2A_DQ13
DDR2A_DQ14
DDR2A_DQ15
RN2B
RN2E
RN3B
RN2H
RN3A
RN2G
RN2F
RN2A
2
5
2
8
1
7
6
1
15
12
15
9
16
10
11
16
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DDR2A_DQ16
DDR2A_DQ17
DDR2A_DQ18
DDR2A_DQ19
DDR2A_DQ20
DDR2A_DQ21
DDR2A_DQ22
DDR2A_DQ23
RN16E
RN16A
RN17H
RN17F
RN17E
RN16C
RN17G
RN16F
5
1
8
6
5
3
7
6
12
16
9
11
12
14
10
11
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DDR2A_DQ24
DDR2A_DQ25
DDR2A_DQ26
DDR2A_DQ27
DDR2A_DQ28
DDR2A_DQ29
DDR2A_DQ30
DDR2A_DQ31
RN15E
RN15C
RN15B
RN16H
RN16G
RN15A
RN15H
RN15D
5
3
2
8
7
1
8
4
12
14
15
9
10
16
9
13
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DDR2A_DQS0
DDR2A_DQS1
RN3G
RN2C
RN5C
RN12F
RN3D
RN2D
RN12G
RN12E
7
3
3
6
4
4
7
5
10
14
14
11
13
13
10
12
DNI
DNI
56
56
DNI
DNI
56
56
0.1uF
U8B
VDD
VDD
VDD
VDD
VDD
VDDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A3
E3
J3
N1
P9
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
NC1
NC2
A2
E2
DDR2A_CLK_P
R213
100, 1%
DDR2A_CLK_N
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDD
VDD
VDD
VDD
VDD
VDDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A3
E3
J3
N1
P9
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
NC1
NC2
A2
E2
DDR2A_DM0
DDR2A_DM1
V21
V11
V20
V8
V19
V9
V18
V6
DDR2A_A0
DDR2A_A1
DDR2A_A2
DDR2A_A3
DDR2A_A4
DDR2A_A5
DDR2A_A6
DDR2A_A7
RN12A
RN6E
RN10E
RN5H
RN10G
RN6B
RN10B
RN6D
1
5
5
8
7
2
2
4
16
12
12
9
10
15
15
13
56
56
56
56
56
56
56
56
V17
V7
V10
V16
V5
DDR2A_A8
DDR2A_A9
DDR2A_A10
DDR2A_A11
DDR2A_A12
RN10F
RN6G
RN5G
RN10C
RN6C
RN10D
RN6F
RN10A
6
7
7
3
3
4
6
1
11
10
10
14
14
13
11
16
56
56
56
56
56
56
56
56
V12
V13
DDR2A_BA0
DDR2A_BA1
DDR2A_RASn
DDR2A_CASn
DDR2A_WEn
DDR2A_CSn
DDR2A_ODT
RN5F
RN6A
RN5E
RN12C
RN10H
RN6H
RN12B
RN12D
6
1
5
3
8
8
2
4
11
16
12
14
9
9
15
13
56
56
56
56
56
56
56
56
DDR2A_CKE
MT47H16M16
MT47H16M16
B
C231
C214
C229
C211
C218
C212
C219
C213
C252
C253
C254
C256
C255
C215
C244
C241
V24
V22
V15
V23
V25
0.1uF
0.1uF
0.01uF
0.1uF
4.7nF
0.1uF
0.1uF
0.01uF
0.1uF
0.1uF
0.01uF
4.7nF
0.1uF
0.1uF
0.1uF
0.1uF
V14
1.8V
PLACE CAPS NEAR U11
1.8V
PLACE CAPS NEAR U12
C263
C262
C261
C276
C264
C283
C300
C305
C282
C304
C301
C272
C302
C303
C284
C287
0.1uF
0.1uF
0.01uF
0.1uF
4.7nF
0.1uF
0.1uF
0.01uF
0.1uF
0.1uF
0.01uF
4.7nF
0.1uF
0.1uF
0.1uF
0.1uF
A
1
VTT_B7_B8
DDR2A_DQ0
DDR2A_DQ1
DDR2A_DQ2
DDR2A_DQ3
DDR2A_DQ4
DDR2A_DQ5
DDR2A_DQ6
DDR2A_DQ7
U15B
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
C
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RFU/A13
RFU/A14
RFU/A15
DDR2A_BA0
DDR2A_BA1
VREF_B7_B8
MT47H16M16
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
R3
R7
2
RN5D
4
RN5A
1
RN12H 8
13 56
16 56
9 56
RN4E
RN4F
RN4G
RN4H
5
6
7
8
12
11
10
9
RN5B
2
15 56
7 DDR2A_DQ[31:0]
7 DDR2A_DQS[3:0]
7 DDR2A_DM[3:0]
VTT_B7_B8
CN3
1
2
3
4
0.1uf x 4
8
7
6
5
CN4
1
2
3
4
0.1uf x 4
8
7
6
5
CN9
1
2
3
4
0.1uf x 4
8
7
6
5
7 DDR2A_BA[1:0]
7
7
7
7
7
7
7
7
DDR2A_RASn
DDR2A_CASn
DDR2A_WEn
DDR2A_CSn
DDR2A_ODT
DDR2A_CKE
DDR2A_CLK_P
DDR2A_CLK_N
D
CN11 0.1uf x 4
1
8
2
7
3
6
4
5
CN2
1
2
3
4
0.1uf x 4
8
7
6
5
CN1
1
2
3
4
0.1uf x 4
8
7
6
5
E
7 DDR2A_A[12:0]
VTT_B7_B8
DDR2A_DQS2
DDR2A_DQS3
DDR2A_DM2
DDR2A_DM3
RN17A
RN17B
RN16D
RN15G
RN17C
RN17D
RN16B
RN15F
16 DNI
15 DNI
13 DNI
10 DNI
14 DNI
13 DNI
15 DNI
11 DNI
1
2
4
7
3
4
2
6
C
CN15 0.1uf x 4
1
8
2
7
3
6
4
5
CN17 0.1uf x 4
1
8
2
7
3
6
4
5
CN16 0.1uf x 4
1
8
2
7
3
6
4
5
CN8
1
2
3
4
B
0.1uf x 4
8
7
6
5
DNI
DNI
DNI
DNI
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
11
of
1
1
8
7
6
5
4
3
DDR2 SDRAM x32 Bottom
U19A
E
DDR2B_A0
DDR2B_A1
DDR2B_A2
DDR2B_A3
DDR2B_A4
DDR2B_A5
DDR2B_A6
DDR2B_A7
DDR2B_A8
DDR2B_A9
DDR2B_A10
DDR2B_A11
DDR2B_A12
U17A
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
R3
R7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RFU/A13
RFU/A14
RFU/A15
L2
L3
L1
BA0
BA1
RFU
DDR2B_BA0
DDR2B_BA1
D
DDR2B_DM0
DDR2B_DM1
F3
B3
LDM
UDM
DDR2B_RASn
DDR2B_CASn
DDR2B_WEn
DDR2B_CSn
K7
L7
K3
L8
RASn
CASn
WEn
CSn
DDR2B_ODT
K9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR2B_DQ0
DDR2B_DQ1
DDR2B_DQ2
DDR2B_DQ3
DDR2B_DQ4
DDR2B_DQ5
DDR2B_DQ6
DDR2B_DQ7
DDR2B_DQ8
DDR2B_DQ9
DDR2B_DQ10
DDR2B_DQ11
DDR2B_DQ12
DDR2B_DQ13
DDR2B_DQ14
DDR2B_DQ15
UDQS_P
UDQS_N
B7
A8
DDR2B_DQS1
LDQS_P
LDQS_N
F7
E8
DDR2B_DQS0
CKE
CK_P
CK_N
K2
J8
K8
DDR2B_CKE
DDR2B_CLK_P
DDR2B_CLK_N
VREF
J2
DDR2B_A0
DDR2B_A1
DDR2B_A2
DDR2B_A3
DDR2B_A4
DDR2B_A5
DDR2B_A6
DDR2B_A7
DDR2B_A8
DDR2B_A9
DDR2B_A10
DDR2B_A11
DDR2B_A12
ODT
L2
L3
L1
BA0
BA1
RFU
DDR2B_DM2
DDR2B_DM3
F3
B3
LDM
UDM
DDR2B_RASn
DDR2B_CASn
DDR2B_WEn
DDR2B_CSn
K7
L7
K3
L8
RASn
CASn
WEn
CSn
DDR2B_ODT
K9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR2B_DQ16
DDR2B_DQ17
DDR2B_DQ18
DDR2B_DQ19
DDR2B_DQ20
DDR2B_DQ21
DDR2B_DQ22
DDR2B_DQ23
DDR2B_DQ24
DDR2B_DQ25
DDR2B_DQ26
DDR2B_DQ27
DDR2B_DQ28
DDR2B_DQ29
DDR2B_DQ30
DDR2B_DQ31
UDQS_P
UDQS_N
B7
A8
DDR2B_DQS3
LDQS_P
LDQS_N
F7
E8
DDR2B_DQS2
CKE
CK_P
CK_N
K2
J8
K8
DDR2B_CKE
DDR2B_CLK_P
DDR2B_CLK_N
VREF
J2
VREF_B3_B4
ODT
MT47H16M16
C278
C352
1.8V
0.1uF
1.8V
RN19C
RN20D
RN19B
RN20H
RN20E
RN19D
RN20B
RN20G
3
4
2
8
5
4
2
7
14
13
15
9
12
13
15
10
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DDR2B_DQ8
DDR2B_DQ9
DDR2B_DQ10
DDR2B_DQ11
DDR2B_DQ12
DDR2B_DQ13
DDR2B_DQ14
DDR2B_DQ15
RN21B
RN21E
RN20C
RN20A
RN21G
RN21C
RN21D
RN21A
2
5
3
1
7
3
4
1
15
12
14
16
10
14
13
16
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DDR2B_DQ16
DDR2B_DQ17
DDR2B_DQ18
DDR2B_DQ19
DDR2B_DQ20
DDR2B_DQ21
DDR2B_DQ22
DDR2B_DQ23
RN8E
RN7G
RN7H
RN7F
RN7E
RN8D
RN8A
RN8G
5
7
8
6
5
4
1
7
12
10
9
11
12
13
16
10
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DDR2B_DQ24
DDR2B_DQ25
DDR2B_DQ26
DDR2B_DQ27
DDR2B_DQ28
DDR2B_DQ29
DDR2B_DQ30
DDR2B_DQ31
RN9D
RN9C
RN9A
RN8H
RN8F
RN9B
RN9H
RN9E
4
3
1
8
6
2
8
5
13
14
16
9
11
15
9
12
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DDR2B_DQS0
DDR2B_DQS1
RN19A
RN21H
RN18A
RN11F
RN20F
RN21F
RN11H
RN11E
1
8
1
6
6
6
8
5
16
9
16
11
11
11
9
12
DNI
DNI
56
56
DNI
DNI
56
56
0.1uF
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDD
VDD
VDD
VDD
VDD
VDDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A3
E3
J3
N1
P9
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
NC1
NC2
A2
E2
DDR2B_CLK_P
R223
100, 1%
DDR2B_CLK_N
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDD
VDD
VDD
VDD
VDD
VDDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A3
E3
J3
N1
P9
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
NC1
NC2
A2
E2
DDR2B_DM0
DDR2B_DM1
V30
V40
V31
V43
V32
V42
V33
V45
DDR2B_A0
DDR2B_A1
DDR2B_A2
DDR2B_A3
DDR2B_A4
DDR2B_A5
DDR2B_A6
DDR2B_A7
RN11A
RN14E
RN13E
RN18H
RN13G
RN14B
RN13B
RN14D
1
5
5
8
7
2
2
4
16
12
12
9
10
15
15
13
56
56
56
56
56
56
56
56
V34
V44
V41
V35
V46
DDR2B_A8
DDR2B_A9
DDR2B_A10
DDR2B_A11
DDR2B_A12
RN13F
RN14G
RN18G
RN13C
RN14C
RN13D
RN14F
RN13A
6
7
7
3
3
4
6
1
11
10
10
14
14
13
11
16
56
56
56
56
56
56
56
56
V39
V38
DDR2B_BA0
DDR2B_BA1
DDR2B_RASn
DDR2B_CASn
DDR2B_WEn
DDR2B_CSn
DDR2B_ODT
RN18F
RN14A
RN18E
RN11C
RN13H
RN14H
RN11B
RN11D
6
1
5
3
8
8
2
4
11
16
12
14
9
9
15
13
56
56
56
56
56
56
56
56
DDR2B_CKE
RN18D
RN18B
RN11G
RN18C
4
2
7
3
13
15
10
14
56
56
56
56
RN19E
RN19F
RN19G
RN19H
5
6
7
8
12
11
10
9
DNI
DNI
DNI
DNI
MT47H16M16
MT47H16M16
B
C294
C292
C293
C295
C286
C296
C279
C318
C273
C274
C267
C269
C266
C257
C258
C268
V27
V29
V36
V28
V26
0.1uF
0.1uF
0.01uF
0.1uF
4.7nF
0.1uF
0.1uF
0.01uF
0.1uF
0.1uF
0.01uF
4.7nF
0.1uF
0.1uF
0.1uF
0.1uF
V37
1.8V
PLACE CAPS NEAR U11
1.8V
PLACE CAPS NEAR U12
C312
C313
C314
C315
C316
C317
C338
C322
C353
C351
C369
C368
C367
C339
C371
C370
0.1uF
0.1uF
0.01uF
0.1uF
4.7nF
0.1uF
0.1uF
0.01uF
0.1uF
0.1uF
0.01uF
4.7nF
0.1uF
0.1uF
0.1uF
0.1uF
1
VTT_B3_B4
DDR2B_DQ0
DDR2B_DQ1
DDR2B_DQ2
DDR2B_DQ3
DDR2B_DQ4
DDR2B_DQ5
DDR2B_DQ6
DDR2B_DQ7
U17B
U19B
C
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RFU/A13
RFU/A14
RFU/A15
DDR2B_BA0
DDR2B_BA1
VREF_B3_B4
MT47H16M16
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
R3
R7
2
A
5 DDR2B_DQ[31:0]
5 DDR2B_DQS[3:0]
5 DDR2B_DM[3:0]
VTT_B3_B4
CN7
1
2
3
4
5 DDR2B_BA[1:0]
5
5
5
5
5
5
5
5
CN10 0.1uf x 4
1
8
2
7
3
6
4
5
CN6
1
2
3
4
E
5 DDR2B_A[12:0]
0.1uf x 4
8
7
6
5
DDR2B_RASn
DDR2B_CASn
DDR2B_WEn
DDR2B_CSn
DDR2B_ODT
DDR2B_CKE
DDR2B_CLK_P
DDR2B_CLK_N
0.1uf x 4
8
7
6
5
D
CN18 0.1uf x 4
1
8
2
7
3
6
4
5
VTT_B3_B4
CN19 0.1uf x 4
1
8
2
7
3
6
4
5
CN20 0.1uf x 4
1
8
2
7
3
6
4
5
CN5
1
2
3
4
DDR2B_DQS2
DDR2B_DQS3
DDR2B_DM2
DDR2B_DM3
RN7A
RN7B
RN8C
RN9F
RN7D
RN7C
RN8B
RN9G
16 DNI
15 DNI
14 DNI
11 DNI
13 DNI
14 DNI
15 DNI
10 DNI
1
2
3
6
4
3
2
7
C
0.1uf x 4
8
7
6
5
CN13 0.1uf x 4
1
8
2
7
3
6
4
5
CN14 0.1uf x 4
1
8
2
7
3
6
4
5
B
CN12 0.1uf x 4
1
8
2
7
3
6
4
5
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
12
of
1
1
8
7
6
5
4
3
SSRAM & FLASH
1.8V
2
FLASH
SSRAM
FLASH 512Mb (32M X 16)
U6
FSM_A4
FSM_A5
FSM_A1
FSM_A9
FSM_A6
FSM_A8
FSM_A13
FSM_A7
FSM_A2
FSM_A14
FSM_A11
FSM_A12
FSM_A15
FSM_A16
FSM_A10
FSM_A3
FSM_A18
FSM_A19
FSM_A21
FSM_A20
FSM_A17
D
C
0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
SSRAM_CLK
89
CLK
SSRAM_E1n
SSRAM_E2
SSRAM_E3n
98
97
92
E1
E2
E3
SSRAM_FTn
SSRAM_LBOn
SSRAM_BAn
SSRAM_BBn
SSRAM_BWn
SSRAM_GWn
14
31
93
94
87
88
FTn
LBOn
BA
BB
BWn
GWn
SSRAM_ADSCn
SSRAM_ADSPn
SSRAM_ADVn
SSRAM_ZZ
SSRAM_Gn
85
84
83
64
86
ADSCn
ADSPn
ADVn
ZZ
Gn
5
10
90
76
71
67
60
55
40
26
21
17
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
58
59
62
63
68
69
72
73
8
9
12
13
18
19
22
23
FSM_D7
FSM_D1
FSM_D6
FSM_D3
FSM_D4
FSM_D2
FSM_D5
FSM_D0
FSM_D14
FSM_D8
FSM_D9
FSM_D13
FSM_D11
FSM_D10
FSM_D12
FSM_D15
DQPA
DQPB
74
24
SSRAM_DQP0
SSRAM_DQP1
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R30
37
36
46
47
48
49
50
43
44
45
35
34
33
32
39
42
80
81
82
99
100
1.8V
PC28FxxxP30B85
FLASH
15
41
65
91
4
11
20
27
54
61
70
77
E
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
U44
1
R21
R45
1.00K
1.00K
1.8V
1
2
3
6
7
16
25
28
29
30
38
51
52
53
56
57
66
75
78
79
95
96
R18
R22
R14
R15
R19
R31
R47
R17
1.00K
1.00K
1.00K
10K
10K
0
10K
1.00K
SSRAM_GWn
SSRAM_ADVn
SSRAM_ADSPn
SSRAM_E2
SSRAM_E3n
SSRAM_FTn
SSRAM_LBOn
SSRAM_ADSCn
SHARED BUS
VPP
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_A23
FSM_A24
FSM_A25
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
D7
D8
A7
B7
C7
C8
A8
G1
H8
B6
A1
A2
VCC
A3
VCC
A4
A5
VCCQ
A6
VCCQ
A7
VCCQ
A8
A9
D0
A10
D1
A11
D2
A12
D3
A13
D4
A14
D5
A15
D6
A16
D7
A17
A18
D8
A19
D9
A20
D10
A21
D11
A22
D12
NC(64M)/A23
D13
NC(64M,128M)/A24 D14
NC/A25(512M)
D15
FLASH_CLK
E6
CLK
FLASH_RESETn
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_ADVn
FLASH_WPn
D4
B4
F8
G8
F6
C6
RESET#
CE#
OE#
WE#
ADV#
WP#
A4
FSM_D[15:0]
A6
H3
FSM_D[15:0]
FSM_A[25:1]
5,9,14,20
E
FSM_A[25:1] 5,8,9,14,20
1.8V
D5
D6
G4
F2
E2
G3
E4
E5
G5
G6
H7
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
FSM_D7
E1
E3
F3
F4
F5
H5
G7
E7
FSM_D8
FSM_D9
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
FSM_D15
WAIT
F7
FLASH_RDYBSYn
GND
GND
GND
GND
B2
H2
H4
H6
RFU0
RFU1
RFU2
RFU3
RFU4
H1
G2
F1
E8
B8
FLASH INTERFACE
D
FLASH_RESETn
FLASH_WEn
FLASH_OEn
FLASH_RDYBSYn
FLASH_CEn
FLASH_CLK
FLASH_ADVn
FLASH_RESETn 7,14
FLASH_WEn 7,14
FLASH_OEn 9,14
FLASH_RDYBSYn 7,14
FLASH_CEn 7,14
FLASH_CLK 5,14
FLASH_ADVn 7,14
1.8V
R23
R32
R24
R26
R25
10K
10K
10K
10K
10K
FLASH_WPn
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_RDYBSYn
R44
10K
FLASH_RESETn
C
PC28F512P30BF
PLACE NEAR FLASH
GS832018GT_TQFP100
1.8V
SSRAM INTERFACE
SSRAM_BAn
SSRAM_BBn
SSRAM_BWn
SSRAM_CLK
SSRAM_E1n
SSRAM_Gn
1.8V
C16
C20
C42
C28
C35
C6
C12
C19
C27
C32
0.1uF
0.1uF
0.1uF
0.1uF
4.7nF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
SSRAM_BAn 7
SSRAM_BBn 9
SSRAM_BWn 9
SSRAM_CLK 7
SSRAM_E1n 7
SSRAM_Gn 9
1.8V
C34
C15
C13
C23
C14
C33
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
B
B
assign
assign
assign
assign
SSRAM_GWn
SSRAM_ADSPn
SSRAM_ADSCn
SSRAM_ADVn
ssram_gwn = 1'b1; // HIGH Global Write Enable—Writes all bytes; active low
ssram_advn = 1'b1; // HIGH
ssram_adscn = 1'b0; // LOW
ssram_adspn = 1'b1; // HIGH
A
SSRAM_GWn 7,14
SSRAM_ADSPn 7
SSRAM_ADSCn 7
SSRAM_ADVn 7
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
13
of
1
1
8
7
6
5
4
3
2
1
MAX II
U7A
FPGA_DATA0
FPGA_DCLK
FPGA_CONF_DONE
FPGA_STATUSn
FPGA_CONFIGn
E
MAX_EPCS
MAX_ERROR
MAX_FACTORY
MAX_USER
HSMA_PSNTn
HSMB_PSNTn
D
IOB1_1
IOB1_2
IOB1_3
IOB1_4
IOB1_5
IOB1_6
IOB1_7
IOB1_8
F3
E2
F4
E1
F5
F2
F6
F1
SENSE_SDO
SENSE_SDI
SENSE_SCK
SENSE_CSn
17 MAX_EPCS
MAX II
BANK1
D3
C2
E3
C3
E4
D2
E5
D1
CLKIN_50
CLKIN_MAX_100
IOB1_25
IOB1_26
IOB1_27
IOB1_28
IOB1_29
IOB1_30
IOB1_31
IOB1_32
IOB1_9
IOB1_10
IOB1_11
IOB1_12
IOB1_13
IOB1_14
IOB1_15
IOB1_16
G3
G2
G4
G1
G5
H2
IOB1_17
IOB1_18
IOB1_19
IOB1_20
IOB1_21
IOB1_22
H1
IOB1_24
H5
J5
SHARED BUS
U7B
IOB1_34
IOB1_35
IOB1_36
IOB1_37
IOB1_38
IOB1_39
IOB1_40
H3
J1
H4
J2
J4
K1
J3
K2
L1
K5
L2
K4
M1
K3
M2
CLKA_EN
CLKA_SDA
CLKA_SCL
CLK125_EN
D11
A13
E11
B12
C10
A12
D10
B11
MSEL0
MSEL2
MSEL3
IOB1_41
IOB1_42
IOB1_43
IOB1_44
IOB1_45
IOB1_46
IOB1_47
IOB1_48
L5
M3
L4
N1
L3
N2
M4
N3
IOB1_49
P2
FAN_CNTL
P3
L6
M5
N4
JTAG_TCK
JTAG_FPGA_TDO
JTAG_EPM2210_TDO
JTAG_TMS
IOB1/GCLK0
IOB1/GCLK1
TCK
TDI
TDO
TMS
MAX II
BANK2
C13
B16
C12
A15
D12
B14
C11
B13
FPGA_DATA1
USER_FACTORY
5,9,13,20 FSM_D[15:0]
FSM_D0
FSM_D1
FSM_D5
FSM_D9
FSM_D8
FSM_D12
FSM_D10
FSM_D3
IOB2_50
IOB2_51
IOB2_52
IOB2_53
IOB2_54
IOB2_55
IOB2_56
IOB2_57
IOB2_74
IOB2_75
IOB2_76
IOB2_77
IOB2_78
IOB2_79
IOB2_80
IOB2_81
E9
A9
A8
B8
E8
A7
D8
B7
IOB2_58
IOB2_59
IOB2_60
IOB2_61
IOB2_62
IOB2_63
IOB2_64
IOB2_65
IOB2_82
IOB2_83
C8
A6
FSM_D13
FSM_D4
IOB2_85
IOB2_86
IOB2_87
IOB2_88
IOB2_89
B6
E7
A5
D7
B5
FSM_D7
FSM_D2
FSM_D15
FSM_D11
FSM_D14
IOB2_90
IOB2_91
IOB2_92
IOB2_93
IOB2_94
IOB2_95
IOB2_96
IOB2_97
C7
A4
E6
B4
D6
C4
C6
B3
FSM_D6
IOB2_98
IOB2_99
IOB2_100
IOB2_101
IOB2_102
C5
A2
D5
B1
D4
E10
A11
IOB2_66
IOB2_67
B10
C9
A10
D9
B9
IOB2_69
IOB2_70
IOB2_71
IOB2_72
IOB2_73
2.5V
FLASH INTERFACE
R13
1.00K
Y1
C4
0.01uF
1
EN
VCC
4
2
GND
OUT
3
100MHz
USER_LED0
USER_LED1
USER_LED2
USER_LED3
USER_LED4
USER_LED5
USER_LED6
USER_LED7
IOB3_103
IOB3_104
IOB3_105
IOB3_106
IOB3_107
IOB3_108
IOB3_109
IOB3_110
N16
FLASH_ADVn
L13
FLASH_RESETn
M15
FLASH_WEn
L12
FLASH_OEn
M16
FLASH_RDYBSYn L11
FLASH_CLK
L15
FLASH_CEn
K14
B
MAX_CSn
MAX_OEn
MAX_WEn
IOB3_127
IOB3_128
IOB3_129
IOB3_130
IOB3_131
IOB3_132
IOB3_133
IOB3_134
CONFIGURATION INTERFACE
MSEL0
MSEL2
MSEL3
USER_LED[7:0]
USER_LED[7:0]
7,8,9,17
IOB4_180
IOB4_181
IOB4_182
IOB4_183
IOB4_184
IOB4_185
IOB4_187
R10
FSM_A10
FSM_A23
FSM_A16
FSM_A3
FSM_A1
FSM_A18
FSM_A17
FSM_A2
N6
T4
M6
R5
P7
T5
N7
R6
IOB4_164
IOB4_165
IOB4_166
IOB4_167
IOB4_168
IOB4_169
IOB4_170
IOB4_171
IOB4_188
IOB4_189
IOB4_190
IOB4_191
IOB4_192
IOB4_193
IOB4_194
IOB4_195
M10
T11
N10
R11
P10
T12
M11
R12
FSM_A20
FSM_A14
M7
T6
IOB4_172
IOB4_173
FSM_A9
FSM_A8
FSM_A22
FSM_A13
FSM_A24
R7
P8
T7
N8
R8
IOB4_175
IOB4_176
IOB4_177
IOB4_178
IOB4_179
IOB4_196
IOB4_197
IOB4_198
IOB4_199
IOB4_200
IOB4_201
IOB4_202
IOB4_203
N11
T13
P11
R13
M12
R14
N12
T15
FSM_A25
FSM_A6
M9
M8
IOB4_204
IOB4/DEV_CLRn IOB4_205
IOB4/DEV_OE
IOB4_206
P12
R16
P13
L16
K13
K15
K12
K16
IOB3_119
IOB3_120
IOB3_121
IOB3_122
IOB3_123
J15
J14
IOB3_125
IOB3_126
IOB3_143
IOB3_144
IOB3_145
IOB3_146
IOB3_147
IOB3_148
IOB3_149
IOB3_150
E15
F12
D16
F13
D15
F14
D14
E12
IOB3/GLCK2
IOB3/GCLK3
IOB3_151
IOB3_152
IOB3_153
IOB3_154
IOB3_155
C15
E13
C14
E14
D13
FPGA_DCLK
FPGA_CONF_DONE
FPGA_STATUSn
FPGA_CONFIGn
7,16 HSMA_PSNTn
7,16 HSMB_PSNTn
SENSE_SDO
SENSE_SDI
SENSE_SCK
SENSE_CSn
U7E
MAX II
BANK4
IOB4_156
IOB4_157
IOB4_158
IOB4_159
IOB4_160
IOB4_161
IOB4_162
IOB4_163
F16
G13
F15
G14
E16
F11
J12
H12
8
8,17
8,18
8
19
19
19
19
N9
T8
T9
R9
P9
T10
IOB3_137
IOB3_138
IOB3_139
IOB3_140
IOB3_141
IOB3_142
D
8 FPGA_DATA[7:0]
CURRENT SENSE
P4
R1
P5
T2
N5
R3
P6
R4
G15
JTAG_TCK
JTAG_TMS
JTAG_EPM2210_TDO
JTAG_FPGA_TDO
19 USER_FACTORY
FSM_A11
FSM_A19
FSM_A12
FSM_A21
FSM_A15
FSM_A5
FSM_A7
FSM_A4
IOB3_135
SYS_RESETn
MSEL0 8
MSEL2 8
MSEL3 8
USER INTERFACE
MAX_FAN
FPGA_DATA2
J16
FPGA_DATA3
J13
FPGA_DATA4
H16
FPGA_DATA5
H13
FPGA_DATA6
H15
FPGA_DATA7
H14
G16 PGM_SEL
G12 PGM_LOAD
IOB3_111
IOB3_112
IOB3_113
IOB3_114
IOB3_115
IOB3_116
IOB3_117
IOB3_118
E
FLASH_RESETn
FLASH_WEn
FLASH_OEn
FLASH_RDYBSYn
FLASH_CLK
FLASH_CEn
FLASH_ADVn
C8
4.7uF
U7D
MAX II
BANK3
P14
N13
P15
M14
N14
M13
N15
L14
CLKIN_MAX_100
C7
0.01uF
8,16,18
8,16,18
8
8
EPM2210GF256FBGA
C
7,13
7,13
9,13
7,13
5,13
7,13
7,13
L1
BLM15AG221SN1
EPM2210GF256FBGA
U7C
5,8,9,13,20 FSM_A[25:1]
2.5V
H7
H9
J8
J10
G6
F7
K11
L10
A1
A16
B2
B15
G7
G8
G9
G10
K7
K8
K9
K10
R2
R15
T1
T16
1.8V
MAX II
Power
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
H8
H10
J7
J9
K6
L7
G11
F10
VCCIO1
VCCIO1
VCCIO1
VCCIO1
C1
H6
J6
P1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
A3
A14
F8
F9
VCCIO3
VCCIO3
VCCIO3
VCCIO3
C16
H11
J11
P16
VCCIO4
VCCIO4
VCCIO4
VCCIO4
L8
L9
T3
T14
19
FAN_CNTL
C
CLOCK INTERFACE
10
10
10
10
10
9,10
2.5V
CLKA_SDA
CLKA_SCL
CLKA_EN
CLK50_EN
CLK125_EN
CLKIN_50
8 MAX_CLK
1.8V
USER I/O's
B
17 PGM_LOAD
17 PGM_SEL
17
17
17
17
MAX_ERROR
MAX_FAN
MAX_FACTORY
MAX_USER
8,17 SYS_RESETn
19 FAN_CNTL
EPM2210GF256FBGA
7 MAX_CSn
9 MAX_OEn
7 MAX_WEn
EPM2210GF256FBGA
EPM2210GF256FBGA
1.8V
2.5V
Place near MAX II
1.8V
A
C195
C206
C191
C164
C227
C165
C163
C226
C208
C217
C175
C199
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C173
C216
C196
C197
C174
C207
C198
C204
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Title
Size
B
Date:
8
7
6
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
5
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
14
of
1
1
8
7
6
5
4
3
2
1
10/100/1000 Ethernet
RGMII Mode (default)
removed ENET_TX_CLK signal, Atached to ground
2.5V
U21A
4.7K
4.7K
4.7K
4.7K
ENET_T_MDIO
ENET_T_MDC
ENET_T_INTN
ENET_T_RESETn
27
ENET_T_RESETn 28
ENET_LED_RX
ENET_LED_LINK10
2.5V
0.01uF
C67
0.01uF
C104
0.01uF
C105
0.01uF
R60
R59
R57
R58
R80
R81
R83
R82
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
J7
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
2.5V
TD0_P
TD0_N
1
2
TD1_P
TD1_N
3
6
TD2_P
TD2_N
4
5
TD3_P
TD3_N
7
8
GND
ENET_LED_LINK10
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
ENET_T_MDIO
ENET_T_MDC
ENET_T_INTN
10
HFJ11-1G02E
R76
10.0K
ENET_RSET
29
31
33
34
39
41
42
43
MDI0_P
MDI0_N
MDI1_P
MDI1_N
MDI2_P
MDI2_N
MDI3_P
MDI3_N
24
25
23
MDIO
MDC
INT_N
37
38
HSDAC_P
HSDAC_N
30
56
EN
NC1
GND
OUT
NC2
VCC
4
5
6
ENET_XTAL_25MHZ
3.3V
22
55
54
53
ENET_XTAL_25MHZ
25MHz
R66
4.99K
R71
4.7K
125CLK
XTAL1
XTAL2
VSSC
TRST_N
TCK
TDI
TDO
TMS
2.5V
JTAG
47
49
44
50
46
C
11
12
14
16
17
18
19
20
ENET_T_TX_D0
ENET_T_TX_D1
ENET_T_TX_D2
ENET_T_TX_D3
RXCLK
RX_DV
RX_ER
2
94
3
ENET_T_RX_CLK
ENET_T_RX_DV
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
95
92
93
91
90
89
87
86
ENET_T_RX_D0
ENET_T_RX_D1
ENET_T_RX_D2
ENET_T_RX_D3
CRS
COL
84
83
S_CLK_P
S_CLK_N
S_IN_P
S_IN_N
S_OUT_P
S_OUT_N
79
80
82
81
77
75
RSET
SEL_FREQ
X5
1
2
3
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
TEST
12
11
3.3V
9
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
ENET_T_GTX_CLK
MGMT
GND_TAB
GND_TAB
D
VCC
ENET_LED_TX
65
64
63
61
60
59
58
8
4
9
7
GTX_CLK
TX_CLK
TX_EN
TX_ER
MDI INTERFACE
C68
COMA
RESET_N
GMII/MII/TBI INTERFACE
R62
R61
R63
R64
SGMII INTERFACE
E
LED_TX
LED_RX
LED_DUPLEX
LED_LINK1000
LED_LINK100
LED_LINK10
68
69
70
73
74
76
E
ENET_T_TX_EN
D
ETHERNET RGMII INTERFACE
7 ENET_T_RX_D[3:0]
9 ENET_T_RX_CLK
7 ENET_T_RX_DV
removed ENET_CRS
removed ENET_RX_CRS and ENET_RX_COL signals
7 ENET_T_TX_D[3:0]
7 ENET_T_GTX_CLK
7 ENET_T_TX_EN
ETHERNET CONTROL INTERFACE
7
7
7
9
ENET_LED_TX
ENET_LED_RX
ENET_LED_DUPLEX
ENET_LED_LINK1000
ENET_LED_LINK100
ENET_LED_LINK10
ENET_RESETn
ENET_INTn
ENET_MDC
ENET_MDIO
C
2.5V
88E1111
D30
Green_LED
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
13
51
NC1
NC2
97
VSS
B
5
21
88
96
72
66
52
VDDOH
VDDOH
VDDOH
32
36
35
40
45
78
VDDO
VDDO
VDDO
VDDO
U21B
VDDOX
VDDOX
26
48
ENET_LED_TX
1.1V
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
220
2.5V
1.8V
1
6
10
15
57
62
67
71
85
ENET_INTN
ENET_RESETn
D31
Green_LED
U9
3
6
VL
TRI_STATE
5
4
VL_IO1
VL_IO2
ENET_LED_RX
VCC
7
VCCIO1
VCCIO2
GND
8
1
2
R265
220
removed ENET_LED_ACTIVITY with r445 and D6
ENET_T_INTN
ENET_T_RESETn
D27
Green_LED
MAX3373
ENET_LED_DUPLEX
R261
1.8V
ENET_MDIO
ENET_MDC
VL
TRI_STATE
5
4
VL_IO1
VL_IO2
Place near PHY
1.1V
D24
Green_LED
U14
3
6
ENET_LED_LINK1000 R264
VCC
7
VCCIO1
VCCIO2
GND
8
1
2
B
220
2.5V
88E1111
A
R266
220
D25
Green_LED
ENET_T_MDIO
ENET_T_MDC
ENET_LED_LINK100
R263
220
D26
Green_LED
MAX3373
ENET_LED_LINK10
R262
220
2.5V
C382
C360
C98
C72
C74
C97
C91
C361
C83
C73
C82
C87
C71
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Title
Size
B
Date:
8
7
6
5
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
15
of
1
1
8
7
6
5
4
3
High Speed Mezzanine (HSM) Interface
0 HSMA_TX_CP3
0 HSMA_TX_CN3
0 HSMA_TX_CP2
0 HSMA_TX_CN2
0 HSMA_TX_CP1
0 HSMA_TX_CN1
0 HSMA_TX_CP0
0 HSMA_TX_CN0
HSMA_T_SDA
JTAG_TCK
HSMA_JTAG_TDO
HSMA_CLK_OUT0
HSMA_D0
HSMA_D2
D
HSMA_TX_D_P0
HSMA_TX_D_N0
HSMA_TX_D_P1
HSMA_TX_D_N1
HSMA_TX_D_P2
HSMA_TX_D_N2
HSMA_TX_D_P3
HSMA_TX_D_N3
HSMA_TX_D_P4
HSMA_TX_D_N4
HSMA_TX_D_P5
HSMA_TX_D_N5
HSMA_TX_D_P6
HSMA_TX_D_N6
C
HSMA_TX_D_P7
HSMA_TX_D_N7
HSMA_CLK_OUT_P1
HSMA_CLK_OUT_N1
HSMA_TX_D_P8
HSMA_TX_D_N8
HSMA_TX_D_P9
HSMA_TX_D_N9
HSMA_TX_D_P10
HSMA_TX_D_N10
HSMA_TX_D_P11
HSMA_TX_D_N11
B
HSMA_TX_D_P12
HSMA_TX_D_N12
HSMA_TX_D_P13
HSMA_TX_D_N13
HSMA_TX_D_P14
HSMA_TX_D_N14
HSMA_TX_D_P15
HSMA_TX_D_N15
HSMA_TX_D_P16
HSMA_TX_D_N16
A
HSMA_CLK_OUT_P2
HSMA_CLK_OUT_N2
12V_HSMC
3.3V
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
41
43
3.3V
47
49
3.3V
53
55
3.3V
59
61
3.3V
65
67
3.3V
71
73
3.3V
77
79
3.3V
83
85
3.3V
89
91
3.3V
95
97
3.3V
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
101
103
3.3V
107
109
3.3V
113
115
3.3V
119
121
3.3V
125
127
3.3V
131
133
3.3V
137
139
3.3V
143
145
3.3V
149
151
3.3V
155
157
3.3V
3.3V
C114
10uF
C113
10uF
ASP-122953-01
BANK 1
42
44
12V
48
50
12V
54
56
12V
60
62
12V
66
68
12V
72
74
12V
78
80
12V
84
86
12V
90
92
12V
96
98
12V
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
12V
108
110
12V
114
116
12V
120
122
12V
126
128
12V
132
134
12V
138
140
12V
144
146
12V
150
152
12V
156
158
PSNTn
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
BANK 2
A
BANK 3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
HSMA_T_SCL
HSMA_T_SDA
HSMA_T_SCL 7
HSMA_T_SDA 7
HSMB_T_SCL
HSMB_T_SDA
HSMB_T_SCL 7
HSMB_T_SDA 7
12V_HSMC 3.3V
HSMA_RX_P3
HSMA_RX_N3
HSMA_RX_P2
HSMA_RX_N2
HSMA_RX_P1
HSMA_RX_N1
HSMA_RX_P0
HSMA_RX_N0
HSMA_T_SCL
JTAG_TMS
HSMA_JTAG_TDI
HSMA_CLK_IN0
C112
C111
10uF
10uF
HSMA_D1
HSMA_D3
HSMB_TX_P3
HSMB_TX_N3
HSMB_TX_P2
HSMB_TX_N2
HSMB_TX_P1
HSMB_TX_N1
HSMB_TX_P0
HSMB_TX_N0
HSMB_T_SDA
JTAG_TCK
HSMB_JTAG_TDO
HSMB_CLK_OUT0
HSMB_D0
HSMB_D2
41
43
3.3V
47
49
3.3V
53
55
3.3V
59
61
3.3V
65
67
3.3V
71
73
3.3V
77
79
3.3V
83
85
3.3V
89
91
3.3V
95
97
3.3V
101
103
105
HSMB_T_TX_D_P9 5
107
HSMB_TX_D_N9 6
109
111
HSMB_T_TX_D_P10 5
113
HSMB_T_TX_D_N10 5
115
117
HSMB_T_TX_D_P11 7
119
HSMB_T_TX_D_N11 7
121
123
HSMB_T_TX_D_P12 5
125
HSMB_T_TX_D_N12 7
127
129
HSMB_T_TX_D_P13 7
131
HSMB_T_TX_D_N13 5
133
135
HSMB_T_TX_D_P14 5
137
HSMB_T_TX_D_N14 5 139
141
HSMB_T_TX_D_P15 5
143
HSMB_T_TX_D_N15 7
145
147
HSMB_T_TX_D_P16 5
149
HSMB_T_TX_D_N16 5
151
153
HSMB_T_CLK_OUT_P2 9 155
HSMB_CLK_OUT_N2
157
159
101
103
3.3V
107
109
3.3V
113
115
3.3V
119
121
3.3V
125
127
3.3V
131
133
3.3V
137
139
3.3V
143
145
3.3V
149
151
3.3V
155
157
3.3V
HSMB_TX_D_P0
HSMB_TX_D_N0
HSMA_RX_D_P1
HSMA_RX_D_N1
HSMB_TX_D_P1
HSMB_TX_D_N1
HSMA_RX_D_P2
HSMA_RX_D_N2
HSMB_TX_D_P2
HSMB_TX_D_N2
HSMA_RX_D_P3
HSMA_RX_D_N3
HSMB_TX_D_P3
HSMB_TX_D_N3
HSMA_RX_D_P4
HSMA_RX_D_N4
HSMB_TX_D_P4
HSMB_TX_D_N4
HSMA_RX_D_P5
HSMA_RX_D_N5
HSMB_TX_D_P5
HSMB_TX_D_N5
HSMA_RX_D_P6
HSMA_RX_D_N6
HSMB_T_TX_D_P6 5
HSMB_T_TX_D_N6 5
HSMB_T_TX_D_P7 5
HSMB_T_TX_D_N7 5
HSMA_CLK_IN_P1
HSMA_CLK_IN_N1
HSMB_CLK_OUT_P1
HSMB_CLK_OUT_N1
HSMB_T_TX_D_P8 5
HSMB_T_TX_D_N8 5
HSMA_RX_D_P8
HSMA_RX_D_N8
HSMA_RX_D_P9
HSMA_RX_D_N9
HSMA_RX_D_P10
HSMA_RX_D_N10
HSMA_RX_D_P11
HSMA_RX_D_N11
HSMA_RX_D_P12
HSMA_RX_D_N12
HSMA_RX_D_P13
HSMA_RX_D_N13
HSMA_RX_D_P14
HSMA_RX_D_N14
HSMA_RX_D_P15
HSMA_RX_D_N15
HSMA_RX_D_P16
HSMA_RX_D_N16
HSMA_CLK_IN_P2
HSMA_CLK_IN_N2
HSMA_PSNTn
12V_HSMC
3.3V
D1
Green_LED
HSMA_PSNTn
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
HSMA_RX_D_P0
HSMA_RX_D_N0
HSMA_RX_D_P7
HSMA_RX_D_N7
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
R1
3.3V
ASP-122953-01
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
BANK 1
BANK 3
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
7,14 HSMA_PSNTn
9 HSMA_CLK_IN0
6 HSMA_CLK_OUT0
9 HSMA_CLK_IN_P[2:1]
9 HSMA_CLK_IN_N[2:1]
6 HSMA_CLK_OUT_P[2:1]
6 HSMA_CLK_OUT_N[2:1]
D
HSMB_RX_D_P0
HSMB_RX_D_N0
6 HSMA_TX_D_P[16:0]
HSMB_RX_D_P1
HSMB_RX_D_N1
6 HSMA_TX_D_N[16:0]
6 HSMA_RX_D_P[16:0]
HSMB_RX_D_P2
HSMB_RX_D_N2
6 HSMA_RX_D_N[16:0]
HSMB_RX_D_P3
HSMB_RX_D_N3
4 HSMA_TX_P[3:0]
4 HSMA_TX_N[3:0]
HSMB_RX_D_P4
HSMB_RX_D_N4
4 HSMA_RX_P[3:0]
HSMB_RX_D_P5
HSMB_RX_D_N5
4 HSMA_RX_N[3:0]
5 HSMB_T_RX_D_P6
5 HSMB_T_RX_D_N6
HSMC PORT B
5 HSMB_T_RX_D_P7
5 HSMB_T_RX_D_N7
9 HSMB_CLK_IN0
6 HSMB_CLK_OUT0
HSMB_CLK_IN_P1
HSMB_CLK_IN_N1
6 HSMB_CLK_IN_P1
6 HSMB_CLK_IN_N[2:1]
5 HSMB_T_RX_D_P8
5 HSMB_T_RX_D_N8
5,6,9 HSMB_CLK_OUT_P[2:1]
5 HSMB_T_RX_D_P9
5 HSMB_T_RX_D_N9
6 HSMB_CLK_OUT_N[2:1]
6 HSMB_D[3:0]
5 HSMB_T_RX_D_P10
5 HSMB_T_RX_D_N10
6,8 HSMB_TX_D_P[5:0]
5 HSMB_T_RX_D_P11
5 HSMB_T_RX_D_N11
7
6
5
4
B
6,20 HSMB_TX_D_N[5:0]
6 HSMB_RX_D_P[5:0]
5 HSMB_T_RX_D_P12
5 HSMB_T_RX_D_N12
6 HSMB_RX_D_N[5:0]
7 HSMB_T_RX_D_P13
7 HSMB_T_RX_D_N13
4 HSMB_TX_P[3:0]
4 HSMB_TX_N[3:0]
7 HSMB_T_RX_D_P14
5 HSMB_T_RX_D_N14
4 HSMB_RX_P[3:0]
7 HSMB_T_RX_D_P15
7 HSMB_T_RX_D_N15
4 HSMB_RX_N[3:0]
7 HSMB_T_RX_D_P16
5 HSMB_T_RX_D_N16
HSMBT_CLK_IN_P2
HSMB_CLK_IN_N2
HSMB_PSNTn
D2
Green_LED
56.2
HSMBT_CLK_IN_P2 5
Title
3.3V
3
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Size
B
Date:
8
C
7,14 HSMB_PSNTn
12V_HSMC
R2
E
HSMC PORT A
HSMB_D1
HSMB_D3
56.2
HSMB_PSNTn
8,14,18 JTAG_TCK
8,14,18 JTAG_TMS
HSMB_RX_P3
HSMB_RX_N3
HSMB_RX_P2
HSMB_RX_N2
HSMB_RX_P1
HSMB_RX_N1
HSMB_RX_P0
HSMB_RX_N0
HSMB_T_SCL
JTAG_TMS
HSMB_JTAG_TDI
HSMB_CLK_IN0
102
104
12V
108
110
12V
114
116
12V
120
122
12V
126
128
12V
132
134
12V
138
140
12V
144
146
12V
150
152
12V
156
158
PSNTn
B
8 HSMA_JTAG_TDO
8 HSMB_JTAG_TDO
8 HSMA_JTAG_TDI
8 HSMB_JTAG_TDI
42
44
12V
48
50
12V
54
56
12V
60
62
12V
66
68
12V
72
74
12V
78
80
12V
84
86
12V
90
92
12V
96
98
12V
BANK 2
HSMA_D[3:0] 6
5,9 HSMB_TX_D_P16
5 HSMB_TX_D_N16
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
GND_1_1
GND_1_2
GND_1_3
GND_1_4
GND_2_1
GND_2_2
GND_2_3
GND_2_4
GND_3_1
GND_3_2
GND_3_3
GND_3_4
R35
R36
R40
R41
R37
R38
R42
R43
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND_1_1
GND_1_2
GND_1_3
GND_1_4
GND_2_1
GND_2_2
GND_2_3
GND_2_4
GND_3_1
GND_3_2
GND_3_3
GND_3_4
HSMA_TX_P3
HSMA_TX_N3
HSMA_TX_P2
HSMA_TX_N2
HSMA_TX_P1
HSMA_TX_N1
HSMA_TX_P0
HSMA_TX_N0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
161
162
163
164
165
166
167
168
169
170
171
172
E
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
HSMC JTAG INTERFACE
HSMA_D[3:0]
J2
161
162
163
164
165
166
167
168
169
170
171
172
J1
2
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
16
of
1
1
8
7
6
5
4
3
2
1
User IO & Connector
2.5V
S7
1
2
S5
1
2
S8
E
1
2
S6
1
2
S4
1
2
S3
1
2
S2
1
2
S1
1
2
D
PGM_SEL
3
4
PB Switch
SYS_RESETn
3
4
PB Switch
PGM_LOAD
3
4
PB Switch
CPU_RESETn
3
4
PB Switch
USER_PB0
3
4
PB Switch
USER_PB1
3
4
PB Switch
USER_PB2
3
4
PB Switch
USER_PB3
3
4
PB Switch
R10
10.0K
R7
10.0K
USER_PB[3:0]
D15
R11
10.0K
R9
10.0K
USER_LED0
R6
10.0K
10.0K
R106
10.0K
R4
10.0K
USER_DIPSW[7:0]
RESn_LED1
R120
56.2
USER_LED[7:0]
MAX_ERROR
MAX_FAN
MAX_FACTORY
MAX_USER
FPGA_CONF_DONE
RESn_LED2
R121
56.2
RESn_LED3
R122
56.2
RESn_LED4
R113
56.2
RN1A
RN1B
RN1C
RN1D
RN1E
RN1F
RN1G
RN1H
RESn_LED5
R114
56.2
Green_LED
D9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
10K
10K
10K
10K
10K
10K
10K
10K
USER_LED5
RESn_LED6
R115
56.2
RESn_LED7
R116
56.2
E
USER_DIPSW[7:0]
USER_LED[7:0]
7,20
7,8,9,14
MAX_ERROR 14
MAX_FAN 14
MAX_FACTORY 14
MAX_USER 14
FPGA_CONF_DONE
8,14
PGM_SEL
14
SYS_RESETn 8,14
PGM_LOAD
14
CPU_RESETn 7
D
HSMA_RX_LED
HSMA_TX_LED
HSMB_RX_LED
HSMB_TX_LED
HSMA_RX_LED
HSMA_TX_LED
HSMB_RX_LED
HSMB_TX_LED
7
7
7
7
Green_LED
D7
USER_LED7
LCD DISPLAY INTERFACE
TDA08H0SB1
7 LCD_T_DATA[7:5]
Green_LED
USER DIPSWITCH
7
HSMC INTERFACE
Green_LED
D8
USER_LED6
USER_PB[3:0]
PGM_SEL
SYS_RESETn
PGM_LOAD
CPU_RESETn
Green_LED
D10
USER_LED4
USER_DIPSW0
USER_DIPSW1
USER_DIPSW2
USER_DIPSW3
USER_DIPSW4
USER_DIPSW5
USER_DIPSW6
USER_DIPSW7
1
2
3
4
5
6
7
8
56.2
Green_LED
D12
USER_LED3
2.5V
16
15
14
13
12
11
10
9
R119
Green_LED
D13
USER_LED2
R5
RESn_LED0
Green_LED
D14
USER_LED1
SW2
ON = 0
OFF = 1
USER I/O's
2.5V
2 x 16 Display Connector
7 LCD_T_DATA[3:2]
5.0V
J13
1
3
5
7
9
11
13
LCD_T_WEn
LCD_T_DATA0
LCD_T_DATA2
LCD_DATA4 9
LCD_T_DATA6
C
1.8V
1
3
5
7
9
11
13
2
4
6
8
10
12
14
2
4
6
8
10
12
14
D4
LCD_T_D_Cn
LCD_T_CSn
LCD_T_DATA1
LCD_T_DATA3
LCD_T_DATA5
LCD_T_DATA7
RESn_HSMA_RX_LED R104
HSMA_RX_LED
Green_LED
D3
HSMA_TX_LED
RESn_HSMA_TX_LED R105
56.2
RESn_HSMB_RX_LED R102
56.2
RESn_HSMB_TX_LED R103
56.2
LCD_CSn
LCD_WEn
LCD_DATA0
LCD_DATA1
LCD_CSn 7
LCD_WEn 7
LCD_DATA0 7
LCD_DATA1 7
Green_LED
D6
HDR2X7
HSMB_RX_LED
C102
7 LCD_D_Cn
56.2
C
2.5V
2.5V
0.1uF
Green_LED
D5
C103
1.8V
LCD_CSn
LCD_WEn
U24
3
6
VL
TRI_STATE
5
4
VL_IO1
VL_IO2
HSMB_TX_LED
VCC
7
VCCIO1
VCCIO2
GND
8
1
2
MAX_EPCS
MAX_EPCS 14
0.1uF
Green_LED
LCD_T_CSn
LCD_T_WEn
D19
MAX_EPCS
RES_MAX_EPCS R132
100, 1%
RES_MAX_ERRORR133
56.2
RES_MAX_FACTORYR130
56.2
RES_MAX_USER R131
56.2
RES_MAX_FAN
56.2
Green_LED
D18
MAX3373
2.5V
B
MAX_ERROR
B
2.5V
1.8V
C100
1.8V
C99
0.1uF
LCD_DATA0
LCD_DATA1
B3
Red_LED
D21
U27
3
6
VL
TRI_STATE
5
4
VL_IO1
VL_IO2
B4
VCC
7
VCCIO1
VCCIO2
GND
8
1
2
0.1uF
LCD_T_DATA0
LCD_T_DATA1
MAX_FACTORY
56.2
Green_LED
D20
MAX_USER
D29
R78 RESn_PCIEX1
MAX_FAN
PCIE_LED_X1 7
PCIE_LED_X4
PCIE_LED_X4 7
Green_LED
D28
56.2
R77
RESn_PCIEX4
Green_LED
D17
MAX3373
PCIE_LED_X1
Green_LED
R134
Red_LED
D16
2x7 HDR
LCM-S01602DSR/C
FPGA_CONF_DONE
2.5V
U23
SPACER1
A
1
MSPM-7-01
SPACER2
VCCA
1.8V
VCCB
Green_LED
6
2.5V
2
GND
DIR
5
1.8V
C377
C366
0.1uF
0.1uF
Title
MSPM-7-01
LCD_T_D_Cn
output
3
A
B
LCD_D_Cn
4
Size
Input
SN74AVC1T45
B
Date:
8
7
6
5
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
17
of
1
1
8
7
6
5
4
3
2
1
Embedded USB Blaster
MAXII USB INTERFACE
2.5V_USB
8,14,16
8,14,16
8
8
R192
56.2
3,8
8,14
8
U3A
5V_USB
E
USB
L7
J4
USB CON
BLM21PG331SN1
USB_RXFn
5V_USB
C51
10uF
1
2
3
4
6
EEDATA
C184
0.1uF
USB_EECS
R27
1.5K
SN65220DBV
USB_XTAL1
USB_XTAL2
5V_USB
R151
C154 18pF
10.0K
RSTOUT#
USB_EECS
USB_EESK
EEDATA
RESET#
32
1
2
EECS
EESK
EEDATA
2
4
31
TEST
9
17
C170 18pF
1
Y2
6.000MHz
USB_XTAL2
13
3
26
XTIN
XTOUT
USB_SI_WU
VCC-IO
5
VCC1
VCC2
USBDM
USBDP
27
28
USB_RESETn
USB_XTAL1
3V3OUT
8
7
D0
D1
D2
D3
D4
D5
D6
D7
25
24
23
22
21
20
19
18
USB_D0
USB_D1
USB_D2
USB_D3
USB_D4
USB_D5
USB_D6
USB_D7
RD#
WR
16
15
USB_RDn
USB_WR
TXE#
RXF#
14
12
USB_TXEn
USB_RXFn
SI/WU
PWREN#
11
10
USB_SI_WU
USB_PWR_ENn
2.5V_USB
CLKIN_24MHZ
R158
1.00k
C
U5
DECOUPLING CAPS
1
2
3
4
C167
C151
0.1uF
10uF
C149
0.1uF
CS
SK
DIN
DOUT
VCC
NC1
NC2
GND
B
J7
K10
K3
K4
K5
K6
K7
K9
F3
G1
G2
H1
H2
H3
J5
J6
IOB1_9
IOB1_10
IOB1_11
IOB1_12
IOB1_13
IOB1_14
IOB1_15
IOB1_16
IOB1_25
IOB1_26
IOB1_27
IOB1_28
IOB1_29
IOB1_30
IOB1_31
IOB1_32
L1
L10
L11
L2
L3
L4
L5
L6
IOB1_33
IOB1_34
L7
L9
JTAG_TCK
TCK
TDI
TDO
TMS
K1
J2
K2
J1
USB_MAX_TCK
USB_MAX_TDI
USB_MAX_TDO
USB_MAX_TMS
F2
E1
IOB1/CLK0
IOB1/CLK1
K8
L8
IOB1/DEV_CLRn
IOB1/DEV_OE
USB_DISABLEn
FPGA_STATUSn
FPGA_CEn
D22
Green_LED
USB_LED
JTAG_BLASTER_TDO
USB_DISABLEn
FPGA_CEn
FPGA_STATUSn
D
8
7
6
5
MAX II
BANK2
A1
A10
A11
A2
A3
A4
A5
A6
IOB2_35
IOB2_36
IOB2_37
IOB2_38
IOB2_39
IOB2_40
IOB2_41
IOB2_42
IOB2_51
IOB2_52
IOB2_53
IOB2_54
IOB2_55
IOB2_56
IOB2_57
IOB2_58
B5
B6
B7
B8
B9
C10
C11
C5
USB_D4
USB_D3
USB_D2
A7
A8
A9
B10
B11
B2
B3
B4
IOB2_43
IOB2_44
IOB2_45
IOB2_46
IOB2_47
IOB2_48
IOB2_49
IOB2_50
IOB2_59
IOB2_60
IOB2_61
IOB2_62
IOB2_63
IOB2_64
IOB2_65
IOB2_66
C6
C7
D10
D11
D9
E10
E11
F11
IOB2/CLK2
IOB2/CLK3
IOB2_67
IOB2_68
IOB2_69
IOB2_70
IOB2_71
IOB2_72
IOB2_73
IOB2_74
F9
G10
H10
H11
H9
J10
J11
K11
USB_RESETn
AT93C46DN-SH-B
R183
IOB1_17
IOB1_18
IOB1_19
IOB1_20
IOB1_21
IOB1_22
IOB1_23
IOB1_24
USB_TXEn
USB_D1
USB_D0
USB_WR
USB_RDn
USB_D7
USB_D6
USB_D5
R182
2.2K
USB_EEDATA
IOB1_1
IOB1_2
IOB1_3
IOB1_4
IOB1_5
IOB1_6
IOB1_7
IOB1_8
EPM240M100
5V_USB
5V_USB
B1
C1
C2
D1
D2
D3
E2
F1
E
U3B
FT245BL
29
NC1
A
NC2
B
GNDGND
27
27
6
AGND
R29
R48
6
4
5
U4
AVCC
C150
0.1uF
GND1
GND2
C185
33nF
30
USB_EESK
5
1
3
2
2.5V_USB
R149
470
U11
D
MAX II
BANK1
5V_USB
JTAG_TCK
JTAG_TMS
JTAG_BLASTER_TDI
JTAG_BLASTER_TDO
10.0K
F10
G11
C
U3C
D5
D7
E4
E8
G4
G8
H5
H7
USB_PWR_ENn
JTAG_TMS
JTAG_BLASTER_TDI
2.5V_USB
MAX II
Power
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
VCCINT
VCCINT
E9
G3
VCCIO1
VCCIO1
VCCIO1
E3
J4
J8
VCCIO2
VCCIO2
VCCIO2
C4
C8
G9
B
EPM240M100
EPM240M100
2.5V_USB
PLACE NEAR MAX II
2.5V_USB
2.5V_USB
2.5V_USB
2.5V_USB
J15
X1
C21
0.01uF
R108
1
EN
VCC
4
2
GND
OUT
3
24MHz
R107
CLKIN_24MHZ
C25
0.01uF
C3
4.7uF
1.00K USB_MAX_TCK
USB_MAX_TDO
1.00K USB_MAX_TMS
USB_MAX_TDI
1
3
5
7
9
1
3
5
7
9
2
4
6
8
10
2
4
6
8
10
0
0
C153
C169
C168
C152
C186
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
R125
R140
DNI
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
18
of
1
1
7
6
5
RSNS SNS
2
V50 SENSE_PAD
1 RSNS SNS 2
SENSE_PAD
V47
1 RSNS SNS
1.8V_FPGA
E
2.5V_B5_B6
SENSE_PAD
V51
1 RSNS SNS
SENSE_PAD
V56
1 RSNS SNS
VCC
D
2
VCCD_PLL_SNS
21
VCCD_PLL
1
VCCA_SNS 21
2.5V
VCCL_SNS 21
VCCA_VCCH_SNS
2
2
2
VCC
9
REF+
11
CH0
CH1
23
24
CH2
CH3
REF-
12
2.5V_B5_B6_N
2.5V_B5_B6_P
25
26
CH4
CH5
F0
19
1.8V_B3_B4_N
1.8V_B3_B4_P
27
28
CH6
CH7
VCC_P
1.8V_B7_B8_N
1.8V_B7_B8_P
1
2
CH8
CH9
VCC_N
VCC_N
VCC_P
17
20
18
16
3
4
SDO
SDI
SCK
CSn
CH10
CH11
VCCD_PLL_P
1.2V_VCCL_GXB_P
1.2V_VCCL_GXB_N
5
6
CH12
CH13
VCCD_PLL_N
VCCD_PLL_N
VCCD_PLL_P
7
8
CH14
CH15
2.5V_B5_B6_P
10
SENSE_PAD
RSNS SNS 2
SENSE_PAD
V54
1 RSNS SNS
1.2V
21
22
C246
0.1uF
REF=5.0V
R203
5.0V
DNI
0
R211
SENSE5_SDO
SENSE5_SDI
SENSE5_SCK
SENSE5_CSn
5.0V
2.5V
D
U12
COM
NC1
NC2
13
14
GND
15
2.5V
R202
10.0K
LTC2418
VCCA_P
E
C245
10uF
14
13
12
11
10
9
8
VCC
IO VCC1
IO VCC2
IO VCC3
IO VCC4
NC2
/TS
VL
IO VL1
IO VL2
IO VL3
IO VL4
NC1
GND
1
2
3
4
5
6
7
14 SENSE_SDO
14 SENSE_SDI
14 SENSE_SCK
14 SENSE_CSn
MAX3378
V4
1
C
VCCA_N
VCCA_P
2.5V_B5_B6_N
V55 SENSE_PAD
RSNS SNS 2
SENSE_PAD
V3
1 RSNS SNS
U13
2.5V_VCCA_VCCH_GXB_P
2.5V_VCCA_VCCH_GXB_N
2
R204
0
1.8V_B7_B8_P
1.8V_B7_B8_N
V53 SENSE_PAD
1 RSNS SNS 2
SENSE_PAD
V58
1 RSNS SNS
5V_MONITOR
A/D #0
V52 SENSE_PAD
1 RSNS SNS 2
1.2V
1
1.8V_B3_B4_P
1.8V_B3_B4_N
1.8V_B7_B8 V48 SENSE_PAD
1 RSNS SNS 2
2.5V_B5_B6_POS 23
2
R199
R201
R200
1.8V_B3_B4
1
3
Power Monitor
V49
1.8V_B3_B4_SNS 23
4
10K
10K
10K
8
VCCA_N
2
V57 SENSE_PAD
1 RSNS SNS 2
SENSE_PAD
V2
1 RSNS SNS
21
2.5V_VCCA_VCCH_GXB
U16
5
1.2V_VCCL_GXB_N
5V_MONITOR
OUT1
OUT2
ADJ/NC
2
3
1
GND
GND_TAB
6
7
VIN
C58
10uF
2
2.5V_VCCA_VCCH_GXB_P
V1
1
SENSE_PAD
RSNS SNS 2
12V
1.2V_VCCL_GXB_P
4
SHDN
C
R51
4.70M
R52
590K
C53
10uF
LT3009xDC
2.5V_VCCA_VCCH_GXB_N
SENSE_PAD
B
B
Fan Power Header
12V
J8
1
2
22_23_2021
Q2
14
B2
FAN_CNTL
FDV305N
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
FAN
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
19
of
1
25
8
7
6
5
4
3
2
1
Cyclone IV GX Power
U10K
Cyclone IV GX
Power
VCC
AA10
AA14
AB8
K13
K9
L12
L14
L16
L18
L20
M11
M13
W14
W8
Y11
W18
W20
Y15
Y13
V9
V19
W10
V17
V13
U8
U20
U18
U16
U14
U12
(1.2V)
E
D
(2.5V)
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCA
AB24
K23
AA7
AA9
T8
J6
L8
R8
C
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
W16
Y12
K16
K10
VCCD_PLL
VCCD_PLL
VCCD_PLL
VCCD_PLL
VCCD_PLL
VCCD_PLL
VCCD_PLL
VCCD_PLL
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
U10M
VCC
M15
M17
M19
M9
N10
N12
N14
R12
R14
R16
R18
R20
T11
R10
P9
P19
P17
P15
P13
P11
N8
N20
N18
N16
T13
T15
T17
T19
T9
U10
U10L
(1.2V)
Cyclone IV GX
I/O Power
1.8V_B3_B4
VREF_B3_B4
VCCD_PLL
AB23
J23
U7
Y7
Y8
M8
P7
K6
(1.2V)
FSM_A12
FSM_D2
2.5V_B5_B6
VCC_CLKIN3A
VCC_CLKIN3B
VCC_CLKIN8A
VCC_CLKIN8B
EP4CGX150DF896_DDR2_Swap_hsmc
Version = 0.1 Preliminary
HSMB_TX_D_N3
HSMB_TX_D_N1
AB12
AB15
AC9
AD11
AD12
AD13
AD14
AD15
AC10
AC12
AC13
AC15
AC16
AG11
AE11
AB18
AB19
AB20
AC18
AC19
AC21
AC22
AD17
AD18
AD19
AD20
AD21
AB21
AG21
AB17
Y24
W24
W23
W22
V23
V22
U24
AA23
AA24
U22
U30
V21
AA26
2.5V_B5_B6
VCCIO3
VCCIO6
VCCIO3
VCCIO6
VCCIO3
VCCIO6
VCCIO3
VCCIO6
VCCIO3
VCCIO6
VCCIO3
VCCIO6
VCCIO3
VCCIO6
VCCIO3
VCCIO6
VCCIO3
VCCIO6
VCCIO3
VCCIO6
VCCIO3
IO/VREFB6N0
VCCIO3
IO/VREFB6N1
IO/VREFB3N0 IO/VREFB6N2
IO/VREFB3N1
IO/VREFB3N2
VCCIO7
VCCIO7
VCCIO4
VCCIO7
VCCIO4
VCCIO7
VCCIO4
VCCIO7
VCCIO4
VCCIO7
VCCIO4
VCCIO7
VCCIO4
VCCIO7
VCCIO4
VCCIO7
VCCIO4
VCCIO7
VCCIO4
VCCIO7
VCCIO4
IO/VREFB7N0
VCCIO4
IO/VREFB7N1
VCCIO4
IO/VREFB7N2
IO/VREFB4N0
IO/VREFB4N1
VCCIO8
IO/VREFB4N2
VCCIO8
VCCIO8
VCCIO5
VCCIO8
VCCIO5
VCCIO8
VCCIO5
VCCIO8
VCCIO5
VCCIO8
VCCIO5
VCCIO8
VCCIO5
VCCIO8
VCCIO5
VCCIO8
VCCIO5
VCCIO8
VCCIO5
VCCIO8
VCCIO5
IO/VREFB8N0
IO/VREFB5N0 IO/VREFB8N1
IO/VREFB5N1 IO/VREFB8N2
IO/VREFB5N2
VCCIO9
L22
L24
M23
N23
N22
M24
P22
P24
R23
R22
K24
L25
N26
AA11
AA19
AA3
AA4
AA5
AA8
AB1
AB10
AB2
AB5
AB6
AB7
AC11
AC14
AC17
AC20
AC23
AC24
AC26
AC29
AC3
AC4
AC5
AC6
AD1
AD2
AD5
AF8
AF5
AF29
AF26
AF23
AF20
AF2
AF17
AE2
G2
G3
G4
G5
H1
H11
H14
H17
H2
H20
H23
H26
H29
H5
H6
L23
L21
1.8V_B7_B8
H22
H21
H19
H18
G19
J20
J19
J18
J17
J22
J21
G21
C21
G16
VREF_B7_B8
H12
H10
H15
H13
J11
J10
H16
J12
J13
J14
J15
J16
B13
G11
C8
USER_DIPSW3
2.5V
H7
EP4CGX150DF896_DDR2_Swap_hsmc
Version = 0.1 Preliminary
USER_DIPSW3
FSM_A12
FSM_D2
HSMB_TX_D_N1
HSMB_TX_D_N3
B
USER_DIPSW3 17
FSM_A12 13,14
FSM_D2 13,14
HSMB_TX_D_N1 16
HSMB_TX_D_N3 16
U10N
Cyclone IV GX
GND
Cyclone IV GX
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AF1
AF11
AF14
AG2
AJ11
AJ14
AJ17
AJ2
AJ20
AJ23
AJ26
AJ29
AJ5
AJ8
B11
B14
B17
B2
B20
B23
B26
B29
B5
B8
D2
E11
E14
E17
E20
E23
E26
E29
E5
E8
F3
G1
K1
J8
J7
J5
J4
J3
J24
H8
K12
K14
K2
K20
K7
K8
L13
L17
L19
E
L26
L29
L3
L4
L5
L7
L9
M1
M12
M14
M16
M18
M2
M20
M6
N11
N13
N15
N17
N19
N3
N4
N6
N9
P1
P10
P12
P14
P16
P18
P2
P20
P23
P26
P29
P5
P8
R11
R13
Y2
Y23
Y26
Y29
Y9
Y16
Y14
Y10
Y1
W9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
R15
R17
R19
R21
R3
R4
R5
R7
R9
T1
T10
T12
T14
T16
T18
T2
T20
T22
T5
T7
U11
U13
U15
U17
U19
U23
U26
U29
U3
U4
U5
U9
V1
V10
V14
V16
V18
V2
V20
V24
V6
V8
W13
W17
W19
W21
W3
W4
W5
W6
A2
AG1
NC_1
NC_2
NC_3
NC_4
AH1
AK2
EP4CGX150DF896_DDR2_Swap_hsmc
EP4CGX150DF896_DDR2_Swap_hsmc
Version = 0.1 Preliminary
Version = 0.1 Preliminary
D
C
B
PLACE NEAR FPGA
VREF_B3_B4
TP1
TP2
TP6
TP5
VREF_B7_B8
C234
C44
C235
C236
C242
C237
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C238
C239
C259
C251
C240
C210
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
TP3
TP4
TP7
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
20
of
1
25
8
7
6
5
4
3
2
1
Power 1, (2.5V, 1.2V and 12V)
14V-20V DC INPUT
FM540
Q1
12V
U48
12V
3
2
GATE VDD
IN
OUT
6
1
4
GND
NC
OPEN_EPAD
5
7
8
7
6
5
2.2uF
C202
4.7uF
2.5V
40
1
2
FDS8880
0.1uF
C161
RUN_SW
U52
3
2
GATE VDD
IN
OUT
6
1
4
GND
NC
OPEN_EPAD
5
7
RUN_SW
330pF
C144
B
5.49K
R141
ITH1
VFB1
C142
1500pF
LTC4357xDCB
TK/SS1
TK/SS2
TK/SS3
36
35
34
RUN1
RUN2
RUN3
10
9
ITH1
VFB1
2.5V
10pF
C143
Q6
D33
SI4816BDY-T1
1
0.1uF
BOOST1
TG1
SW1
BG1
CMDSH2_3
33
32
31
30
SNSP1
3
SNSN1
4
C194
BOOST1
TG1
SW1
BG1
CH2
43.2K
20.0K
C160
0.1uF
5.36K
C
10.0K
R161
C188
680pF
R12
13
12
BOOST2
TG2
SW2
BG2
1.2V
100, 1%
10pF
C157
10.0K
20.0K
D11
Blue_Led
R153
R150
330pF
43.2K
R152
12V_HSMC
10pF
140.0K
10.0K
B
C155
C156
470pF
ITH3
VFB3
15
14
100K
100K
Switching Freq = 450kHz
R155
3.24K
C190
SNSN2
6
ITH3
VFB3
R172
R173
0
BOOST2
TG2
SW2
BG2
C193
R163
37
Forced Continuous
MODE/PLLIN
R154
R162
R160
R159
39
ILIM
CH1
CH2
SNSP3
16
17
PGOOD3
PGOOD12
38
FREQ/PLLFLTR
SGND
EPAD_GND
SNSN3
7
C36
10uF
22uF
R39
5.6uH L4
1
2
R33 VCCA_SNS
L2
VCCA_VCCH_SNS0.003
BLM15AG221SN1
VCCA
L3
BLM15AG221SN1
2.5V_VCCA_VCCH_GXB
R28
1.2V
8
7
6
5
C223
C222
4.7uF
0.1uF
C159
0.1uF
1.62K
C29
10uF
22uF
SW2
1.37K
R49
1.2uH L5
1
2
+
C37
0.003
C187
330uF
4V
Tantalum
R239VCCL_SNS
L12
VCCD_PLL_SNS 0.003
BLM15AG221SN1
C
1.2V_VCCL_GXB
L11
BLM15AG221SN1
VCCD_PLL
R240
R143
VCC
0.003
R238
12V
Q4
D32
18
19
20
21
D
C39
SW1
4
3
2
INTVCC
BOOST3
TG3
SW3
BG3
0.1uF
R144
SI4816BDY-T1
1
0.1uF
SI4816BDY-T1
1
0.1uF
CMDSH2_3
INTVCC
R164
11.5K
SNSP2
5
C189
INTVCC
10.0K
DNI
25
26
27
28
4.7uF
12V
CMDSH2_3
ITH2
VFB2
C224
Q5
3.3V
ITH2
VFB2
C225
0.003
D34
C171
7
6
5
2.61K
R129
R126
220pF
8
4
3
2
INTVCC
POWER LED
CH1
1
C162
INTVCC
2
U43
0.1uF
4
C172
24
0.1uF
29
2 3
0.1uF
12V
DRVCC12
3
2
1
68.1K
R16
11.5K
150uF
C205
Q3
R20
C203
10uF
E
A
23
1
C54
INTVCC
SW3
EG2201A
12V_PCIE
D
C43
RUN_SW
VCCA_SNS
VCCA_VCCH_SNS
VCCL_SNS
VCCD_PLL_SNS
LTC4357xDCB
5 6
0
R34
INTVCC
R184
2.20
EXTVCC
4
22,23
19
19
19
19
FDS8880
VIN
RAPC712X
12V
22
2
1
3
8
7
6
5
3
2
1
4
E
DC_INPUT
D23
INTVCC
J5
C192
BOOST3
TG3
SW3
BG3
CH1
CH2
8
7
6
5
C221
C220
4.7uF
0.1uF
12V_HSMC
SW3
4
3
2
B
L6
4.32K
C158
0.1uF
1.00M
R46
8.2uH
2
1
C30
C24
10uF
220uF
R142
8
11
41
LTC3853xUJ
0.01uF
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
21
of
1
25
8
7
6
5
4
3
2
1
Power 2, (3.3V and 1.8V)
E
E
12V
INTVCC
21,23 RUN_SW
R231
2.20
C63
C62
C56
C335
10uF
10uF
150uF
2.2uF
C337
4.7uF
C321
INTVCC
0.1uF
560pF
2.15K
R251
C363
5600pF
ITH1_B
VFB1_B
C372
RUN1
RUN2
2
3
ITH1
VFB1
1.8V
DNI
19
BOOST1
TG1
SW1
BG1
21
22
23
20
SENSE_P1
27
SENSE_N1
C373
BOOST1_B
TG1_B
SW1_B
BG1_B
C334
CH2
C356
0.1uF
1000pF
C
2.15K
R258
3300pF
ITH2_B
VFB2_B
C375
5
4
BOOST2
TG2
SW2
BG2
3.3V
DNI
C374
63.4K
20.0K
R257
R253
0
Forced Continuous
R234
15
14
13
17
SENSE_P2
8
SENSE_N2
7
24
MODE/PLLIN
10
ILIM
12
PGOOD
25
FREQ/PLLFLTR
PGND
EPAD_GND
0.1uF
2.21K
D
1.8V
R56
1
2
C80
C79
10uF
10uF
R246
+
C81
330uF
4V
Tantalum
12V
Q8
CMDSH2_3
ITH2
VFB2
4.7uF
3.3uH L9
D36
C364
C289
SW1_B
2.20K
28
R256
R252
7
6
5
C288
4
3
2
INTVCC
25.5K
20.0K
8
1
26
9
CMDSH2_3
CH1
2
RUN_SW
TK/SS1
TK/SS2
SI4816BDY-T1
1
0.1uF
BOOST2_B
TG2_B
SW2_B
BG2_B
SI4816BDY-T1
1
0.1uF
C336
CH1
CH2
8
7
6
5
C291
4.7uF
0.1uF
SW2_B
1.62K
C
3.3V
4
3
2
3.3uH L8
3.90K
C357
0.1uF
C290
1
1
6
C365
Q7
D35
R55
1
2
R247
C78
C77
10uF
10uF
+
2
0.1uF
INTVCC
VIN
C362
EXTVCC
0.1uF
D
18
U50
INTVCC
11
12V
C61
330uF
4V
Tantalum
INTVCC
10.0K
DNI
R237
R248
100K
10.2K
R236
R235
B
Switching Freq = 450kHz
16
29
B
LTC3850xUF
R233
2.55K
C349
0.1uF
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
22
of
1
25
8
7
6
5
4
3
2
1
Power 3, (DDR2 (VREF/VTT), 5.0V, 1.8V FPGA VCCIO,1.1V Ethernet)
1.8V_B3_B4
5.0V
U45
E
10
TPS51100DGQ
VIN
C270
VLDOIN
VDDQSNS
2
1
VTT
VTTSNS
3
5
10uF
19 1.8V_B3_B4_SNS
0.9V VTT (3A Sink/Src)
1uF
VTT_B3_B4
10.0K
10.0K
7
9
6
VTTREF
C247 C248
C265 C350
C378 C379
10uF
10uF
10uF
10uF
10uF
10uF
12V
C275
U41
5.0V
LT3027
8
7
RUN_SW
4
8
11
VREF_B3_B4
S3
S5
PGND
GND
GND
R217
R218
IN1
SHDN1n
C148
5V_USB
0.1uF
10uF
9
3
1.8V_B7_B8
D
E
21,22 RUN_SW
C249
IN2
SHDN2n
C141
OUT1
6
C146
BYP1
ADJ1
5
4
OUT2
10
C147
0.01uF
10
TPS51100DGQ
VIN
VLDOIN
VDDQSNS
C307
10uF
C306
2
1
11
10uF
0.9V VTT (3A Sink/Src)
1uF
BYP2
ADJ2
GND
7
9
C140
0.01uF
1
2
LT3027
6
VTTREF
C277
R128
261K
R138
100K
D
10uF
R127
249K
3
5
C201 C200
C332 C333
C232 C285
10uF
10uF
10uF
10uF
10uF
10uF
4
8
11
VREF_B7_B8
VTT
VTTSNS
S3
S5
PGND
GND
GND
10.0K
10.0K
10uF
C139
VTT_B7_B8
R227
R226
R139
2.5V_USB
5.0V
U47
316K
2.5V
5.0V
U40
0.1uF
1
2
4
C
100K
6
SHDN
C124
5.0V
10uF
U42
100K
6
BST
OUT2
OUT1
SW
SHDN
GND
GND
R157
IN1
IN2
C178
3
11
10uF
ADJ
PG
R123
5.23K
C
BLM15AG221SN1
4.7K
1.8V_B7_B8
R137
.009
R118
1.50K
LTC3026
2.5V_B5_B6
2.5V_B5_B6_POS
R146
C166
.009
10uF
R147
R148
5.23K
4.7K
R136
3.0K
LTC3026
R135
1.50K
3.3V
5.0V
J3
1.1V
U53
1
1
2
2
C145
1
2
10uF
4
SW
6
SHDN
HDR2X1
R255
100K
IN1
IN2
BST
OUT2
OUT1
GND
GND
B
R117
8
7
ADJ
PG
1.8V_B3_B4
.009
1.8V_B3_B4_SNS R145
1uF
10
9
8
7
L10
C380
3
11
10uF
SHUNT INSTALLED 2.5V
SHUNT NOT INSTALLED 1.8V
ADJ
PG
5
C381
B
1uF
1.1V
10
9
8
7
R254
R250
5.11K
1
4
2.5V_B5_B6_POS 19
C180
5
1.8V_FPGA
1.8V_FPGA
4.7K
+
C359
LTC3026
R249
A
2.87K
10uF
2
1
2
3
11
3.3V
1uF
10
9
OUT2
OUT1
SW
C131
5
BST
GND
GND
R124
IN1
IN2
C92
470uF
10V
Tantalum
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
23
of
1
25
8
7
6
5
4
3
2
1
FPGA Decoupling
Place 6 vias minimum on each X2Y cap.
STANDOFF1
FPGA VCCL_GXB
FPGA VCCD_PLL
STANDOFF2
FPGA VCC
VCCD_PLL
VCC
1.2V_VCCL_GXB
STANDOFF3
C181
E
C45
C233
C271
C57
C243
C47
C22
C52
C182
C31
C59
C209
10nF
22nF
22nF
22nF
47nF
100nF
220nF
1uF
C26
330uF
330uF
+
2
C18
C297 C38
330uF
4V 4.7uF
Tantalum
100nF
470nF
1uF
1
10nF
E
STANDOFF5
1uF
10nF
STANDOFF4
C299
C10
C84
C55
330uF
4.7uF
C66
C65
330uF
2.2uF
SCREW1
2.2uF
SCREW2
SCREW3
SCREW4
FPGA 1.8V VCCIO Banks 3 and 4
D
FPGA 1.8V VCCIO Banks 7 and 8
FPGA 2.5V VCCIO Banks 5 and 6
FPGA 2.5V VCCA_GXB and VCCH_GXB
FPGA 2.5V VCCA and VCC_CLKIN
SCREW5
1.8V_B3_B4
1.8V_B7_B8
C50
C40
C250
1uF
C228
220nF
330uF
+
C41
4.7uF
2
C46
C183
330uF
4V
Tantalum
2.5V_VCCA_VCCH_GXB
C179
1uF
C60
470nF
1
220nF
2.5V_B5_B6
C298
100nF
C5
C11
330uF
4.7uF
C49
4.7uF
D
VCCA
470nF
C176
C177
1uF
C9
C64
C48
330uF
2.2uF
330uF
220nF
C
C
B
B
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone IV GX FPGA Development Kit Board
Copyright (c) 2010, Altera Corporation. All Rights Reserved.
Document Number
150-0311003-B1
Wednesday, December 08, 2010
2
Rev
01
(6XX-43286R)
Sheet
24
of
1
25
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