QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1150A BROADBAND ULTRA LOW DISTORTION 7-BIT DIGITALLY CONTROLLED VGA LT5554 DESCRIPTION Demonstration circuit 1150A 1150A is a featuring the LTC5554 IC, a 7-bit programmable gain amplifier. It incorporates a variety of passive components to support configurations for varied applications. The LT5554 is a differential input and output precision programmable gain amplifier with 16dB gain range and 0.125dB gain step. The seven LT5554 gain control inputs (PGx, x=0,2,..6) and the STROBE input can be coupled to TTL (DCcoupling type) or ECL and (low-voltage) CMOS drivers (AC-coupling type) without external components. The 3state MODE pin allows the selection of the coupling type. The LT5554 gain state can be updated asynchronously when STROBE is HIGH or synchronously using the STROBE input positive transition. In the latter STROBEDMODE, the external control logic time skew is eliminated and synchronization with the ADC clock is possible. With 0.125dB step resolution and 5ns settling time, the LT5554 may be suited in quasi-continuous gain control applications. The LT5554 power and voltage gain for Maximum Gain is 18dB when application Rout=50•. Application gain can be changed with different Rout selections. The LT5554 amplifier is unconditionally stable. Consequently, LC-filters or SAW filters can be connected to the LT5554 I/O pins without padding. Lacking global feed-back, the LT5554 has -80dB reverse isolation @ 400MHz (package limited). Design files for this circuit board are available. Call the LTC factory. PowerPath is a trademark of Linear Technology Corporation 1 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1150A BROADBAND ULTRA LOW DISTORTION 7-BIT DIGITALLY CONTROLLED VGA Table 1. Typical DEMO BOARD Performance Summary [TA = 25°C, VCC = 5V, VccO = 5V, ENB = 3V, MODE = 5v, STROBE = 2.2V, HIH = 2.2V, MAXIMUM GAIN, POUT = 4dBm/Tone (2VP-P into 50Ω Ω), ∆f = 200KHz] SYMBOL PARAMETER CONDITIONS TYPICAL PERFORMANCE UNIT VCC Supply Voltage VCCO OUT± Output Pin DC Common Mode Voltage (For more detail, Please see Note 4 of data sheet) ICC VCC Supply Current VCC = 5V 100 mA IODC OUT± Quiescent Current OUT± Voltages = 5V 96 mA RIN Input Resistance FIN=100MHz 45 Ω CIN Input Capacitance FIN=100MHz 2.8 PF RO Output Resistance FIN=100MHz 400 Ω CO Output Capacitance FIN=100MHz 1.9 PF HD2 Second Harmonic Distortion Pout=10dBm (Single Tone), FIN=100MHz, ROUT = 50Ω -76 dBc HD3 Third Harmonic Distortion Pout=10dBm (Single Tone), FIN=100MHz, ROUT = 50Ω -62 dBc 4.75 to 5.25 V 3.5 to 6 V ROUT 50Ω Ω 100Ω Ω GVMAX Maximum Voltage Gain FIN=200MHz 13.7 19.6 dB GPMAX Maximum Power Gain FIN=200MHz 13.6 16.6 dB IIP3 Input Third Order Intercept Point FIN=200MHz 27.8 27 dBm OIP3 Output Third Order Intercept Point FIN=200MHz 41.5 44 dBm IMD3 Intermodulation Product FIN=200MHz -84 -88 dBc VONOISE Output Noise Noise Spectral Density FIN=200MHz 10.7 21.4 nV/√Hz NF Noise Figure FIN=200MHz 10 10 RTI Input Referred Noise Spectral Density FIN=200MHz 1.34 1.34 nV/√Hz SFDR Spurious Free Dynamic Range FIN=200MHz 128 128 dBm/Hz dB Table 2. DC1150A Board I/O Description CONNECTOR FUNCTION COMMENTS J1 Singe-Ended Input 50Ω Signal source, no external termination necessary J3 Singe-Ended Output 50Ω matched, can drive network/spectrum analyzer input VCC LT5554 VCC pin. Connect to power supply 5V. VCCO Output bias voltage Connect to power supply 5V. VPG Bias STROBE and all PGx via 10KΩ resistors. Connect to power supply in 3 to 5V range for Maximum Gain state. Connect to GROUND for Minimum Gain state. ENABLE Enable/Shut-down Connect to 5V to enable LT5554, or connect to GND for shut-down. 2 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1150A BROADBAND ULTRA LOW DISTORTION 7-BIT DIGITALLY CONTROLLED VGA MODE Selects STROBE and PGx input type Connect to 5V for gain control inputs DC-coupled TTL levels. (consult tables 1 and 2 on page 19 of datasheet for other settings) STROBE VGA gain update mode STROBE=H : gain is asynchronously set by PGx transitions. STROBE=L : gain is not changed by PGx transitions. STROBE=signal : gain is synchronously set by the PGx state strobed by the STROBE pin positive transitions. PG0 … PG6 VGA control inputs Biased by default from VPG via 10kΩ resistors when left open. Apply the desired level to corresponding PGx Turret or J5 connector pin to change the gain state. VDEC Input common-mode voltage test point Self-biasing within LT5554, normally open. When voltage is applied, the internal bias buffer source and sink currents can be measured. Table 3. DC1150A Board I/O Optional Features CONNECTOR FUNCTION COMMENTS J5 External LT5554 state control Board Edge Connector can be used instead of board mounted turrets to control the LT5554 state. J2 PG1/PG2 Timing evaluation. 50Ω matched SMA connector J4 PG3/PG4 Timing evaluation. 50Ω matched SMA connector J6 PG5/PG6 Timing evaluation. 50Ω matched SMA connector J7 STROBE Timing and full speed up to 200MHz evaluation. 50Ω matched SMA connector Table 4. DC1150A Board I/O Optional circuits INPUT PORT OUTPUT PORT COMMENTS Single-Ended with trans- Differential outputs converted to former coupled to differ- Single-Ended with transformer ential source Single-Ended Input and Output with transformers. (Standard Demo Board is shipped with this configuration.) Simplified Input and Output circuits is shown on page 4. Differential Inputs with Differential outputs converted to Capacitively-Coupled to a Single-Ended with transformer Differential Source Differential Capacitively-Coupled input and Output with transformer. Circuit modification is shown on page 5. Single-Ended with trans- Differential wide band Decoupling Single-Ended transformer Input and differential 100 decoupling capacitors outputs. Circuit former coupled to differ- capacitors Outputs modification is shown on page 6. ential source Single-Ended with trans- Differential 50 Outputs with former coupled to differ- transformer ential source Single-Ended transformer Input and Differential 50 outputs with transformer. Circuit modification is shown on page 7. Table 5. DC1150A Board different Rout Impedance ROUT *** FUNCTION COMMENTS Rout=50• 50• Single-ended output(J3) R5 and R6 = 68.1•. T2 =TC2-1T. (Standard Demo Board installed with these components values) Rout=75• 50• Single-ended output(J3) Replace R5 and R6 from 68.1• to 124•. T2(TC2-1T) replace with TC3-1T(Mini-Circuit) Rout=100• 50• Single-ended output(J3) Replace R5 and R6 from 68.1• to 205•. T2(TC2-1T) replace with TC4-1W(Mini-Circuit) 3 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1150A BROADBAND ULTRA LOW DISTORTION 7-BIT DIGITALLY CONTROLLED VGA NOTE: *** Consult Tables 3, 4 page 23, 24 respectively of datasheet for others Rout Options. LT5554 STANDARD DEMO BOARD WITH SINGLE-ENDED INPUT AND OUTPUT TRANSFORMERS VCCO VCCO Demo Boards with simplified Input and Output Circuits IN+ 0 J1 1 T1 1:1 3 C1 C20 2.7pF 5 ETC1-1-13 1uF C2 IN- VCCO 3 1 400 25 OUT+ TC2-1T T2 OUTJ3 4 2 LT5554 Ro C5 0 C19 4.7uF R5 68.1 OUT- DEC 4 R1 0 C3 0.1uF 25 2 E1 R2 0 R6 68.1 C9 0.1uF 5 C18 0.1uF Demo Board’s Silk Screen 4 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1150A BROADBAND ULTRA LOW DISTORTION 7-BIT DIGITALLY CONTROLLED VGA MODIFICATION FOR 50 SINGLE-ENDED TRANSFORMER INPUT TO DIFFERENTIAL INPUT VCCO VCCO Demo Boards with simplified Input and Output Circuits 0 J1 1 T1 1:1 IN+ 25 DEC 2 C20 2.7pF 5 4 ETC1-1-13 0 1uF C2 IN- C19 4.7uF R5 68.1 3 VCCO Ro C5 R1 0 C3 0.1uF OUT- C1 3 E1 TC2-1T T2 J3 4 2 LT5554 1 400 5 25 OUT+ OUT- R2 0 R6 68.1 C9 0.1uF C18 0.1uF 1) Remove T1 and bypass with 0 resistors. (Connecting transformer footprint 1 to 3 and pin 5 to 4) 2) Install decoupling capacitors C1 and C2. 3) Install J11 connector. 4) Remove C20 and R1. MODIFIED INPUT CIRCUIT VCCO VCCO Differential Capacitively-Coupled Input E1 C3 0.1uF R5 68.1 J1 IN0 1 T1 1:1 3 C1 J11 IN+ 4 ETC1-1-13 OUT25 DEC 2 5 IN+ 1uF C2 IN- VCCO Ro C5 0 C19 4.7uF 3 OUTJ3 4 2 LT5554 1 400 25 OUT+ TC2-1T T2 R2 0 R6 68.1 C9 0.1uF 5 C18 0.1uF 5 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1150A BROADBAND ULTRA LOW DISTORTION 7-BIT DIGITALLY CONTROLLED VGA MODIFICATION FOR 50 SINGLE-ENDED TRANSFORMER OUTPUT TO DIFFERENTIAL 100 WIDE BAND OUTPUT VCCO VCCO Demo Boards with simplified Input and Output Circuits 0 J1 1 1:1 T1 IN+ 5 DEC 4 ETC1-1-13 0 1uF C2 IN- VCCO Ro C5 R1 0 R5 68.1 25 2 C20 2.7pF C19 4.7uF OUT- C1 3 E1 C3 0.1uF 3 OUT- TC2-1T T2 J3 4 2 LT5554 1 400 5 25 OUT+ R2 0 R6 68.1 C9 0.1uF C18 0.1uF 1) Remove R2 and T2. 2) Install decoupling capacitors C11 and C12 (using T2 footprint). 3) Install J33 connector. Modified Output circuit VCCO VCCO W ide Band Differential Output E1 C3 0.1uF 0 J1 1 T1 1:1 3 C1 5 4 ETC1-1-13 R1 0 C11 OUT25 DEC 2 C20 2.7pF IN+ R5 68.1 1uF C2 IN- OUT- J3 47nF Ro C5 0 C19 4.7uF LT5554 400 C12 25 OUT+ R6 68.1 C9 0.1uF VCCO C18 0.1uF OUT+ J33 47nF 6 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1150A BROADBAND ULTRA LOW DISTORTION 7-BIT DIGITALLY CONTROLLED VGA MODIFICATION FOR 50 SINGLE-ENDED TO 50 DIFFERENTIAL OUTPUT WITH TRANSFORMER VCCO VCCO Demo Boards with simplified Input and Output Circuits 0 J1 T1 1 1:1 3 5 4 ETC1-1-13 0 1uF C2 IN- C19 4.7uF R5 68.1 OUT3 VCCO Ro C5 R1 0 C3 0.1uF 25 DEC 2 C20 2.7pF IN+ C1 E1 OUT- TC2-1T T2 J3 4 2 LT5554 1 400 5 25 OUT+ R2 0 R6 68.1 C9 0.1uF C18 0.1uF 1) Remove R2. 2) Install J33 connector. Modified Output circuit VCCO VCCO Differential Output with Transformer 0 J1 1 T1 1:1 3 C1 5 4 ETC1-1-13 R1 0 25 C2 1uF IN- C19 4.7uF R5 68.1 VCCO Ro C5 0 C3 0.1uF OUT- J3 OUT- DEC 2 C20 2.7pF IN+ E1 3 TC2-1T T2 4 2 LT5554 1 400 5 OUT+ 25 OUT+ J33 R6 68.1 C9 0.1uF C18 0.1uF 7 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1150A BROADBAND ULTRA LOW DISTORTION 7-BIT DIGITALLY CONTROLLED VGA ADDITIONAL INFORMATION Higher OIP3 can be obtained reconfiguring the DC1150A board for ROUT > 50Ω. For DC1150A board output modifications, please refer to Table 5 above or figure 16 and table 3 on page 23 of the LT5554 datasheet. INTERMODULATION AND HARMONIC DISTORTION MEASUREMENTS The LT5554 performance is better than most signal generators and spectrum analyzers can provide. The available instrumentation performance test consists in connecting the signal source to the spectrum analyzer (bypass the DC1150A board). If the measured performance is worse than LT5554 datasheet figure, please refer to the Application Note 97 (published for the related LT5514 part) for signal source conditioning and spectrum analyzer setup. OUTPUT POWER MATCHING RELATED OIP3 AND GAIN -3DB DISCREPANCY The ROUT stands for the total output impedance as seen by the LT5554 open-collector outputs with equates to RO || (R5+R6) || R(T2). (where RO =400Ω is the LT5554 internal resistor and R(T2) is the T2 transformer secondary impedance). Then, the LT5554 power gain is: GP=10log(RIN *GM2 *ROUT) in dB The DC1150A board output power matching loss on [ RO || (R5+R6) ] accounts for a DC1150A measured BoardGain and OIP3 -3dB lower than the LT5554 datasheet performance stated for driving an on-board load, without output power matching (like in the ADC interface application case). HIGHER OIP3 AND Rout MEASUREMENTS By default, the DC1150A board has ROUT = 50Ω which provides best SFDF, not necessarily best OIP3. If the application bandwidth is greater than the T2 output transformer bandwidth, the DC1150A board can be reconfigured according to the LT5554 datasheet figure 17 and table 4. TIMING MEASUREMENTS The DC1150A timing measurements require the J2, J4, J6 (PGx), J7 (STROBE) connectors to be mounted. The function of each connector is outlined in table 2 above and the circuit is depicted in the datasheet (page 26) figure 20 to be implemented according to datasheet instructions. This setup can evaluate only three PGx at a time. The LT5554 part can be seen as a multiplier with an analog port (IN+, IN-) and a 7-bit logarithmic DAC port and opens the signal synthesizer and conditioning applications. The DC1150A board can be used to test the LT5554 in such applications if PGx 7-bit data is supplied via the J5 edge connector. DRIVING THE INPUTS DC-COUPLED It is possible to drive the LT5554 inputs differentially with DC coupling. Transformer T1 should be replaced with 0Ω resistors and connector J11 reconfigured as for differential input as illustrated on page 5. The LT5554 internal input common-mode bias reference available at DEC pin is used for the external DC level shifter circuit used to drive the LT5554 IN+, IN- inputs in DC-coupling applications. The DC current flowing into LT5554 IN+, IN- inputs can be monitored and maintained within +/- 200µA limits for best operation. The external drive circuit must have a DC 100Ω differential output 8 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1150A BROADBAND ULTRA LOW DISTORTION 7-BIT DIGITALLY CONTROLLED VGA impedance to retain the specified LT5554 gain step ac- AC-COUPLED DIFFERENTIAL OUTPUTS The LT5554 outputs can drive differentially a 3V ADC like LTC2254/5 LTC2208/9 with AC coupling. Transformer T2 should be replaced with 0Ω resistors and connector J33 reconfigured as described in Table 4 and illustrated on page 6 for differential output. Resistors R5 and R6=28.7Ω should be mounted to provide a differential 50Ω source impedance for the ADC inputs. The circuit is shown in figure 1 below. VCCO 5V VCCO E1 C3 0.1uF IN+ DEC R5 28.7 C19 4.7uF C11 OUT- J3 47nF LT5554 Ro 400 IN- OUT- C12 OUT+ C9 0.1uF R6 28.7 VCCO OUT+ J33 47nF curacy. A further refinement user may consider is to use external (high impedance) DC-current sources either open-loop or in a DC-loop controlled by the ADC VCM internal reference. This allows the setting of the LT5554 DC output common mode voltage independent of R5, R6 values. When high OP1dB are desired, the VccO can be increased but must not exceed the absolute maximum rating of 7V for OUT+ and OUT- (in shut-down full VccO voltage is applied to OUT+, OUT-). ADC INPUT OVERDRIVE PROTECTION Unlike LTC ADC parts, some ADC parts from other vendors may exhibit long recovery time when ADC inputs are driven beyond supply rail. With 5ns recovery time, the LT5554 part can provide the power limiting function when driving such ADC parts. The DC1150A board required modifications to test the power limiting function are based on one of the following two methods: Low ROUT values (current limiting) Lower the VccO supply voltage (voltage limiting) C18 0.1uF Figure 1. Differential 50 Ohm source impedance for ADC The LT5554 IODC=45mA output bias current (fairly constant throughout VGA range and temperature) will produce a 1.3V drop across (each) R5, R6 connected to VccO=5V. The DC1150A board common mode voltage at J3, J33 connectors is 3.7V. The VccO=5V specified OIP3=46dBm changes to OIP3=44.5dBm for 3.7V output common mode voltage. The ADC part will have Vcc=5V and GROUND DC level shifted with 2V and appropriately decoupled to the board ground plane. Then the common mode voltage of both parts will be fairly aligned. This is possible because LT5554 linearity close to compression is still good as depicted in the LT5554 datasheet typical characteristic section. SCHEMATIC NOTES The following schematic components may not be required in user application: • C6, the MODE decoupling capacitor • C5, the DEC decoupling capacitor. C5 improves with a few dB the input common mode performance only for frequencies below 100MHz. • C4, C8 the VCC decoupling capacitors. The LT5554 has VCC internal voltage regulators and HF decoupling. 9 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1150A BROADBAND ULTRA LOW DISTORTION 7-BIT DIGITALLY CONTROLLED VGA QUICK START PROCEDURE Table 2 shows the function of each connector and turret and figure 4 is showed a Full Schematic version of DC1150A board. Refer to figure 2 for the connection diagram and figure 3 for the standard DC1150A board schematic and follow the procedure below for evaluation with a single 5V power supply: • Connect the VCC and VCCO to the 5V power supply. • Connect the ENABLE and MODE to the 5V power supply to enable the LT5554. • Connect the VPG to the 5V power supply to set the LT5554 VGA in Maximum Gain state. Alter- natively, VPG connected to GROUND will set the Minimum Gain state. • • • The LT5554 gain can be changed from Gmax or Gmin according to a binary code by connecting any PGx (x=0,2, .. 6) to 5V respectively 0V. PG0 controls the LSB 0.125dB gain step while PG6 change the MSB 8dB gain step. Apply an input signal to J1. The input is impedance-matched to 50Ω. Observe the output via J3. The output is impedance-matched to 50Ω, suitable for the input of a network or a spectrum analyzer. 10 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1150A BROADBAND ULTRA LOW DISTORTION 7-BIT DIGITALLY CONTROLLED VGA 11 VCCO VCC +5V E6 pg1 pg4 VCC 32 31 30 29 28 27 26 25 2 C20 5 2.7pF 1 2 3 4 5 6 7 8 C2 0 4 VCC ENABLE GND OUTOUT+ GND MODE VCC GND GND DEC IN+ INDEC GND GND 33 U1 LT5554EUH pg6 R6 68.1 mode C8 0.1uF C9 0.1uF C6 47nF GND E15 E14 s trob e pg6 pg5 pg4 pg3 pg2 pg1 R2 0 GND E16 pg0 C18 0.1uF strobe pg0 enabl e 5 TC2-1T pg5 R1 0 J3 1 enable OUT- 4 2 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 GN D ETC1-1-13 MODE R27 0 R28 0 R29 0 R30 0 R31 0 R32 0 R33 0 R34 0 VCC J5 C21 0.1uF 40PINS SMT-TB 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 3 PG1 GND PG2 PG3 GND PG4 GND GND C5 1uF 3 J1 T2 VCCO C4 0.1uF PG5 GN D PG6 PG0 GN D ST R OBE GN D GN D C1 0 T1 1 IN+ R5 68.1 pg3 VDEC C19 4.7uF 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 VDEC E10 C23 0.1uF C22 0.1uF E11 E12 PG1 PG0 C25 0.1uF C24 0.1uF E13 PG2 E3 PG3 C26 0.1uF E4 PG4 0.1uF E5 PG5 STROBE VPG E8 R20 10K R21 10K R22 10K R23 10K R24 10K R25 10K R26 10K FIGURE 3. STANDARD DEMO BOARD E2 PG6 mode VCCO C28 C27 0.1uF C29 0.1uF VPG CUSTOMER NOTICE 12 LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. A CONTRACT NO. APPROVALS DRAWN A. Karpov a DATE 08/23/06 CHECKED TECHNOLOGY TITLE LT5554EUH IF AMPLIFIER APPROVED ENGINEER 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 Fax: (408)434-0507 V. Dv orkin 08/23/06 DESIGNER SIZE CAGE CODE Tuesday , April 22, 2008 SCALE: FILENAME: DWG NO REV DC1150A SHEET 3 1 OF 1 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1150A E9 E1 C3 0.1uF E7 BROADBAND ULTRA LOW DISTORTION 7-BIT DIGITALLY CONTROLLED VGA pg2 VDEC VCCO ENABLE R12 51.1 J2 VCCO J4 R14 51.1 VCC +5V E9 pg2 C12 47nF pg1 2 C20 5 2.7pF 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 C5 1uF C2 0 4 R3 TBD C4 0.1uF PG1 GN D PG2 PG3 GN D PG4 GN D GN D C1 0 3 J1 C14 47nF pg4 VCC ENABLE GND OUTOUT+ GND MODE VCC GND GND DEC IN+ INDEC GND GND 33 U1 LT5554EUH 24 23 22 21 20 19 18 17 pg6 R1 0 C15 47nF C16 47nF J6 R16 51.1 OUTJ3 5 TC2-1T R6 68.1 mode C8 0.1uF OUT+ C9 0.1uF C6 47nF C18 0.1uF R2 0 strobe pg0 C17 47nF J7 GND R17 51.1 GND E15 E14 s trobe pg6 pg5 pg4 pg3 pg2 pg1 pg0 enable 4 2 1 E16 MODE R27 0 R28 0 R29 0 R30 0 R31 0 R32 0 R33 0 R34 0 VCC J5 C21 0.1uF 40PINS SMT-TB 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 3 R4 TBD enable pg5 J11 T2 VCCO R7 OPT J33 9 10 11 12 13 14 15 16 GN D ETC1-1-13 IN- C19 4.7uF R5 68.1 VCC PG 5 GN D PG 6 PG 0 GN D ST R O BE GN D GN D 1 IN+ C13 47nF VDEC R8 0 T1 pg3 C3 0.1uF E7 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 VDEC E10 C23 0.1uF C22 0.1uF E11 PG0 E12 PG1 C25 0.1uF C24 0.1uF E13 PG2 E3 PG3 C26 0.1uF E4 PG4 0.1uF E5 PG5 STROBE VPG E8 R20 10K R21 10K R22 10K R23 10K R24 10K R25 10K R26 10K FIGURE 4. FULL SCHEMATIC VERSION E2 PG6 mode VCCO C28 C27 0.1uF 13 C29 0.1uF VPG CUSTOMER NOTICE LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. A CONTRACT NO. APPROVALS DRAWN A. Karpov a DATE 08/23/06 CHECKED TECHNOLOGY TITLE LT5554EUH IF AMPLIFIER APPROVED ENGINEER 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 Fax: (408)434-0507 V. Dv orkin 08/23/06 DESIGNER Tuesday , April 22, 2008 SIZE CAGE CODE SCALE: FILENAME: DWG NO REV DC1150A SHEET 3 1 OF 1 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1150A C11 47nF VDEC E1 BROADBAND ULTRA LOW DISTORTION 7-BIT DIGITALLY CONTROLLED VGA E6 VCCO ENABLE