HEF4521B 24-stage frequency divider and oscillator Rev. 05 — 5 November 2009 Product data sheet 1. General description The HEF4521B consists of a chain of 24 toggle flip-flops with an overriding asynchronous master reset input (MR), and an input circuit that allows three modes of operation. The single inverting stage (A2 to Y2) will function as: a crystal oscillator, an input buffer for an external oscillator or in combination with A1 as an RC oscillator. The crystal oscillator operates in Low-power mode when pins VSS1 and VDD1 are supplied via external resistors. Each flip-flop divides the frequency of the previous flip-flop by two, consequently the HEF4521B will count up to 224 = 16777216. The counting advances on the HIGH-to-LOW transition of the clock (A2). The outputs from each of the last seven stages (218 to 224) are available for additional flexibility. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the full industrial (−40 °C to +85 °C) temperature range. 2. Features n n n n n n Low power crystal oscillator operation Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the full industrial temperature range −40 °C to +85 °C Complies with JEDEC standard JESD 13-B 3. Applications n Industrial 4. Ordering information Table 1. Ordering information All types operate from −40 °C to +85 °C. Type number Package Name Description Version HEF4521BP DIP16 plastic dual in-line package; 16-leads (300 mil) SOT38-4 HEF4521BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4521B NXP Semiconductors 24-stage frequency divider and oscillator 5. Functional diagram 5 4 VDD1 6 2 Y2 A2 9 MR A1 CP STAGES 1 to 8 3 CD VSS1 Q8 CP STAGES 9 to 16 CD Q16 CP STAGES 17 to 24 CD Q24 Q18 Q19 Q20 Q21 Q22 Q23 1 10 11 12 13 14 15 Y1 7 001aae708 Fig 1. Functional diagram VDD1 VDD A2 to FFs VSS VSS1 Y2 Fig 2. to logic 001aae711 Schematic diagram of clock input circuitry HEF4521B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 5 November 2009 2 of 17 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx A2 VSS1 MR Q FF 1 T Q FF 2 T Q FF 3 T Q FF 4 T Q FF 5 T Q FF 6 T Q FF 7 T Q FF 8 T CD CD CD CD CD CD CD CD Q FF 9 T Q FF 10 T Q FF 11 T Q FF 12 T Q FF 13 T Q FF 14 T Q FF 15 T Q FF 16 T CD CD CD CD CD CD CD CD Q FF 17 T Q FF 18 T Q FF 19 T Q FF 20 T Q FF 21 T Q FF 22 T Q FF 23 T Q FF 24 T CD CD CD CD CD CD CD CD NXP Semiconductors HEF4521B_5 Product data sheet Y2 A1 VDD1 Rev. 05 — 5 November 2009 Q18 Q19 Q20 Q21 Q22 Q23 Y1 001aae710 Fig 3. Logic diagram HEF4521B 3 of 17 © NXP B.V. 2009. All rights reserved. 24-stage frequency divider and oscillator Q24 HEF4521B NXP Semiconductors 24-stage frequency divider and oscillator 6. Pinning information 6.1 Pinning HEF4521B Q24 1 16 VDD MR 2 15 Q23 VSS1 3 14 Q22 Y2 4 13 Q21 VDD1 5 12 Q20 A2 6 11 Q19 Y1 7 10 Q18 VSS 8 9 A1 001aae709 Fig 4. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description MR 2 master reset input VSS1 3 ground supply voltage 1 VDD1 5 supply voltage 1 Y1, Y2 7, 4 external oscillator connection VSS 8 ground supply voltage A1, A2 9, 6 external oscillator connection Q18 to Q24 10, 11, 12, 13, 14, 15, 1 output VDD 16 supply voltage 7. Count capacity Table 3. Count capacity Output Count capacity Q18 218 = 262144 Q19 219 = 524288 Q20 220 = 1048576 Q21 221 = 2097152 Q22 222 = 4194304 Q23 223 = 8388608 Q24 224 = 16777216 HEF4521B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 5 November 2009 4 of 17 HEF4521B NXP Semiconductors 24-stage frequency divider and oscillator 8. Functional Test A test function has been included to reduce the test time required to test all 24 counter stages. This test function divides the counter into three 8-stage sections by connecting VSS1 to VDD and VDD1 to VSS. 255 counts are loaded into each of the 8-stage sections in parallel via A2 (connected to Y2). All flip-flops are now at a HIGH level. The counter is now returned to the normal 24-stage in series configuration by connecting VSS1 to VSS and VDD1 to VDD. Entering one more pulse into input A2 will cause the counter to ripple from an all HIGH state to an all LOW state. Table 4. Functional test sequence Inputs Control terminals Outputs Remarks MR A2 Y2 VSS1 VDD1 Q18 to Q24 H L L VDD VSS L counter is in three 8-stage sections in parallel mode; A2 and Y2 are interconnected (Y2 is now input); counter is reset by MR. L see see VDD Remarks Remarks column column VSS H 255 pulses are clocked into A2, Y2. The counter advances on the LOW to HIGH transition. L L L VSS VSS H VSS1 is connected to VSS. L H L VSS VSS H the input A2 is made HIGH. L H L VSS VDD H VDD1 is connected to VDD; Y2 is now made floating and becomes an output; the device is now in the 224 mode. L ↓ VSS VDD L counter ripples from an all HIGH state to an all LOW state. [1] H = HIGH voltage level; L = LOW voltage level; ↓ = HIGH to LOW transition. 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O input/output current IDD supply current Tstg storage temperature Tamb ambient temperature total power dissipation Ptot P power dissipation Conditions −0.5 VI < −0.5 V or VI > VDD + 0.5 V −0.5 VO < −0.5 V or VO > VDD + 0.5 V to any supply terminal Max +18 ±10 VDD + 0.5 Unit V mA V - ±10 mA - ±10 mA - ±100 mA −65 +150 °C −40 +85 °C DIP16 package [1] - 750 mW SO16 package [2] - 500 mW - 100 mW per output [1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. HEF4521B_5 Product data sheet Min © NXP B.V. 2009. All rights reserved. Rev. 05 — 5 November 2009 5 of 17 HEF4521B NXP Semiconductors 24-stage frequency divider and oscillator 10. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VDD Conditions Min Typ Max Unit supply voltage 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air −40 - +85 °C ∆t/∆V input transition rise and fall rate VDD = 5 V - - 3.75 µs/V VDD = 10 V - - 0.5 µs/V VDD = 15 V - - 0.08 µs/V 11. Static characteristics Table 7. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL HIGH-level input voltage LOW-level input voltage Conditions |IO| < 1 µA |IO| < 1 µA HIGH-level output voltage |IO| < 1 µA LOW-level output voltage |IO| < 1 µA HIGH-level output current VO = 2.5 V LOW-level output current II input leakage current IDD supply current Tamb = −40 °C Tamb = 25 °C Tamb = 85 °C Min Max Min Max Min Max 5V 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V VDD 5V 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 V −1.7 - −1.4 - −1.1 - mA 5V VO = 4.6 V 5V −0.52 - −0.44 - −0.36 - mA VO = 9.5 V 10 V −1.3 - −1.1 - −0.9 - mA VO = 13.5 V 15 V −3.6 - −3.0 - −2.4 - mA VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA 15 V - ±0.3 - ±0.3 - ±1.0 µA 5V - 20 - 20 - 150 µA 10 V - 40 - 40 - 300 µA - 80 - 80 - 600 µA - - - 7.5 - - pF IO = 0 A 15 V CI input capacitance - HEF4521B_5 Product data sheet Unit © NXP B.V. 2009. All rights reserved. Rev. 05 — 5 November 2009 6 of 17 HEF4521B NXP Semiconductors 24-stage frequency divider and oscillator 12. Dynamic characteristics Table 8. Dynamic characteristics VSS = 0 V; Tamb = 25 °C; for test circuits see Figure 6; unless otherwise specified. Symbol Parameter HIGH to LOW propagation delay tPHL Conditions VDD A2 to Q18; see Figure 5 Extrapolation formula Min Typ Max Unit 923 ns + (0.55 ns/pF) CL - 950 1900 ns 10 V 339 ns + (0.23 ns/pF) CL - 350 700 ns 15 V 212 ns + (0.16 ns/pF) CL - 220 440 ns 5V 13 ns + (0.55 ns/pF) CL - 40 80 ns 10 V 4 ns + (0.23 ns/pF) CL - 15 30 ns 15 V 2 ns + (0.16 ns/pF) CL - 10 20 ns 5V 93 ns + (0.55 ns/pF) CL - 120 240 ns 10 V 44 ns + (0.23 ns/pF) CL - 55 110 ns 15 V 32 ns + (0.16 ns/pF) CL - 40 80 ns 5V 63 ns + (0.55 ns/pF) CL - 90 180 ns 10 V 24 ns + (0.23 ns/pF) CL - 35 70 ns 17 ns + (0.16 ns/pF) CL - 25 50 ns 923 ns + (0.55 ns/pF) CL - 950 1900 ns 10 V 339 ns + (0.23 ns/pF) CL - 350 700 ns 15 V 212 ns + (0.16 ns/pF) CL - 220 440 ns 5V 13 ns + (0.55 ns/pF) CL - 40 80 ns 10 V 4 ns + (0.23 ns/pF) CL - 15 30 ns 15 V 2 ns + (0.16 ns/pF) CL - 10 20 ns 5V 33 ns + (0.55 ns/pF) CL - 60 120 ns 10 V 19 ns + (0.23 ns/pF) CL - 30 60 ns 12 ns + (0.16 ns/pF) CL - 20 40 ns 5V Qn to Qn + 1; see Figure 5 MR to Qn A1 to Y1; see Figure 5 [1] 15 V LOW to HIGH propagation delay tPLH A2 to Q18; see Figure 5 5V Qn to Qn + 1; see Figure 5 A1 to Y1; see Figure 5 [1] 15 V transition time tt pulse width tW Qn; see Figure 5 A2 HIGH; minimum width; see Figure 5 MR HIGH; minimum width; see Figure 5 recovery time trec maximum frequency fmax [1] MR; see Figure 5 A1; see Figure 5 5V [1] 10 ns + (1.00 ns/pF) CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF) CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF) CL - 20 40 ns 5V 80 40 - ns 10 V 40 20 - ns 15 V 30 15 - ns 5V 70 35 - ns 10 V 40 20 - ns 15 V 30 15 - ns 5V +20 −10 - ns 10 V +15 −5 - ns 15 V 15 0 - ns 5V 6 12 - MHz 10 V 12 25 - MHz 15 V 17 35 - MHz The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). HEF4521B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 5 November 2009 7 of 17 HEF4521B NXP Semiconductors 24-stage frequency divider and oscillator Table 9. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol Parameter VDD dynamic power dissipation PD 5V Typical formula for PD (µW) where: PD = 1200 × fi + Σ(fo × CL) × fi = input frequency in MHz, VDD2 10 V PD = 5100 × fi + Σ(fo × CL) × VDD2 15 V PD = 13050 × fi + Σ(fo × CL) × VDD fo = output frequency in MHz, 2 CL = output load capacitance in pF, VDD = supply voltage in V, Σ(CL × fo) = sum of the outputs. 13. Waveforms VI VM MR input 0V tW 1/fmax VI A2 input VM 0V trec tW tPHL VOH tPLH 90 % Qn output 10 % VOL tt tt 001aae712 a. Pulse widths, maximum frequency, recovery and transition times and A2 to Qn propagation delays VI A1 input 0V VOH VM Qn output tPLH VOL tPHL VOH Y1 output VM tPLH tPHL VOH VM Qn + 1 output VOL VM VOL Y1 propagation delays Qn to Qn + 1 propagation delays 001aak015 b. A1 to Y1, MR to Qn and Qn to Qn + 1 propagation delays Measurement points are given in Table 10. The logic levels VOH and VOL are typical output voltage levels that occur with the output load. Fig 5. Waveforms showing measurement of dynamic characteristics HEF4521B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 5 November 2009 8 of 17 HEF4521B NXP Semiconductors 24-stage frequency divider and oscillator tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0V tW 001aaj781 a. Input waveforms VDD VI VO G DUT RT CL 001aag182 b. Test circuit Test data is given in Table 10. Definitions for test circuit: Device Under Test (DUT); CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 6. Test circuit for switching times Table 10. Measurement points and test data Supply voltage 5 V to 15 V Input Load VI VM tr, tf CL VDD 0.5VI ≤ 20 ns 50 pF HEF4521B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 5 November 2009 9 of 17 HEF4521B NXP Semiconductors 24-stage frequency divider and oscillator 14. Application information VDD Ro R(1) 1.8 MΩ VDD VDD1 Y1 Y2 Q18 A1 A2 HEF4521B CS CT MR VSS Q24 VSS1 R(1) 001aae713 (1) Optional for low power operation. Fig 7. Crystal oscillator circuit Table 11. Typical characteristics for crystal oscillator See Figure 7. Parameter 500 kHz circuit 50 kHz circuit Unit Resonance frequency 500 50 kHz Crystal cut S N - Equivalent resistance; RS 1 6.2 kΩ Ro 47 750 kΩ CT 82 82 pF CS 20 20 pF Crystal characteristics External resistor/capacitor values HEF4521B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 5 November 2009 10 of 17 HEF4521B NXP Semiconductors 24-stage frequency divider and oscillator RTC 001aae715 102 VDD C RS (1) fosc (kHz) VDD VDD1 Y1 Y2 Q18 A1 10 (2) A2 HEF4521B 1 MR VSS Q24 VSS1 10−1 1 10−1 001aae714 10 1 102 RTC (kΩ) 103 10 C (nF) 102 VDD = 10 V; The test circuit is shown in Figure 8. 1 f ≈ ---------------------------------- ; R S ≥ 2R TC , where: 2.3 × R TC × C (1) RTC; C = 1 nF; RS ≈ 2 RTC. (2) C; RTC = 56 kΩ; RS = 120 kΩ. f is in Hz, R is in Ω, and C is in F. V IL ( max ) R S + R TC < --------------------- , where: I LI VIL(max) = maximum input voltage LOW; and ILI = input leakage current. Fig 8. RC oscillator circuit Fig 9. Oscillator frequency as a function of RTC and C HEF4521B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 5 November 2009 11 of 17 HEF4521B NXP Semiconductors 24-stage frequency divider and oscillator 001aae658 12.5 gfs (mA/V) 10 (1) 7.5 (2) Rbias 560 kΩ (3) 5 VDD 0.47 µF Vi (f = 1 kHz) A2 Y2 input output 100 µF 2.5 A io 0 VSS 0 5 10 15 VDD (V) 001aae820 gfs = dio/dvi with vo constant (see Figure 11). (1) Average + 2 s. (2) Average. (3) Average − 2 s, where ‘s’ is the observed standard deviation. Fig 10. Test setup for measuring forward transconductance Fig 11. Typical forward transconductance gfs as a function of the supply voltage at Tamb = 25 °C 001aae716 75 001aae717 20 IDD (mA) gain (VO/VI) 15 50 typ typ 10 25 5 0 0 0 5 10 15 0 VDD (V) 5 10 15 VDD (V) Fig 12. Voltage gain VO/VI as a function of supply voltage Fig 13. Supply current as a function of supply voltage 330 kΩ A2 Y2 001aae718 Fig 14. Test setup for measuring the Figure 12 and Figure 13 graphs HEF4521B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 5 November 2009 12 of 17 HEF4521B NXP Semiconductors 24-stage frequency divider and oscillator 15. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 15. Package outline SOT38-4 (DIP16) HEF4521B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 5 November 2009 13 of 17 HEF4521B NXP Semiconductors 24-stage frequency divider and oscillator SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 16. Package outline SOT109-1 (SO16) HEF4521B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 5 November 2009 14 of 17 HEF4521B NXP Semiconductors 24-stage frequency divider and oscillator 16. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4521B_5 20091105 Product data sheet - HEF4521B_4 Modifications: • • • Section 2 “Features” ESD values removed. Section 10 “Recommended operating conditions” ∆t/∆V values updated. Abbreviations section removed. HEF4521B_4 20090421 Product data sheet - HEF4521B_CNV_3 HEF4521B_CNV_3 19950101 Product specification - HEF4521B_CNV_2 HEF4521B_CNV_2 19950101 Product specification - - HEF4521B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 5 November 2009 15 of 17 HEF4521B NXP Semiconductors 24-stage frequency divider and oscillator 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] HEF4521B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 5 November 2009 16 of 17 HEF4521B NXP Semiconductors 24-stage frequency divider and oscillator 19. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Count capacity . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional Test. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application information. . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 5 November 2009 Document identifier: HEF4521B_5