INTEGRATED CIRCUITS 74ALS273 Octal D–type flip–flop Product specification IC05 Data Handbook 1991 Feb 08 Philips Semiconductors Product specification Octal D-type flip-flop 74ALS273 FEATURES PIN CONFIGURATION • Eight edge-triggered D-type flip-flops • Buffered common clock • Buffered asynchronous master reset • See 74ALS377 for clock enable version • See 74ALS373 for transparent latch version • See 74ALS374 for 3-State version MR 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 11 CP DESCRIPTION The 74ALS273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. GND 10 SF00346 The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output. ORDERING INFORMATION ORDER CODE All outputs will be forced Low independently of clock or data inputs by a Low voltage level on the MR input. The device is useful for applications where the true output only is required and the CP and MR are common to all flip-flops. TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 95MHz 16mA 74ALS273 DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C DRAWING NUMBER 20-pin plastic DIP 74ALS273N SOT146-1 20-pin plastic SO 74ALS273D SOT163-1 20-pin plastic SSOP Type II 74ALS273DB SOT339-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION D0 – D7 74ALS (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Data inputs 1.0/2.0 20µA/0.2mA CP Clock pulse input (active rising edge) 1.0/1.0 20µA/0.1mA MR Master Reset input (active-Low) 1.0/1.0 20µA/0.1mA 3-State outputs 130/240 2.6mA/24mA Q0 – Q7 NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL 3 4 7 8 13 14 17 18 1 11 D0 D1 D2 D3 D4 D5 D6 CP 1 MR Q0 2 VCC = Pin 20 GND = Pin 10 1991 Feb 08 Q1 5 Q2 6 Q3 9 Q4 12 Q5 15 Q6 16 C1 D7 3 11 R Q7 19 1D 2 4 5 7 6 8 9 13 12 14 15 17 16 18 19 SF00348 SF00347 2 853–1398 01670 Philips Semiconductors Product specification Octal D-type flip-flop 74ALS273 LOGIC DIAGRAM D0 D1 3 CP D2 4 D4 8 D5 13 D7 D6 14 17 18 11 D Q D CP RD MR D3 7 Q D CP RD Q D CP RD Q D CP RD Q D CP RD Q D Q D CP RD CP RD Q CP RD 1 2 Q0 5 6 Q1 9 Q2 Q3 12 Q4 16 15 Q5 19 Q6 Q7 VCC = Pin 20 GND = Pin 10 SF00349 FUNCTION TABLE INPUTS H h L l X ↑ = = = = = = OUTPUTS MR CP Dn OPERATING MODE Qn L X X L Reset (clear) H ↑ h H Load “1” H ↑ l L Load “0” High-voltage level High state must be present one setup time before the Low-to-High clock transition Low-voltage level Low state must be present one setup time before the Low-to-High clock transition Don’t care Low-to-High clock transition ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) PARAMETER SYMBOL RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current VOUT Voltage applied to output in High output state IOUT Current applied to output in Low output state Tamb Operating free-air temperature range Tstg Storage temperature range –30 to +5 mA –0.5 to VCC V 48 mA 0 to +70 °C –65 to +150 °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage UNIT V V 0.8 V IIK Input clamp current –18 mA IOH High-level output current –2.6 mA IOL Low-level output current 24 mA +70 °C Tamb 1991 Feb 08 Operating free-air temperature range 0 3 Philips Semiconductors Product specification Octal D-type flip-flop 74ALS273 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL VOH O TEST CONDITIONS1 PARAMETER High level output voltage High-level LIMITS MIN VCC±10%,, VIL = MAX,, VIH = MIN IOH = –0.4mA VCC – 2 IOH = MAX 2.4 IOL = 12mA VOL O Low level output voltage Low-level VCC = MIN,, VIL = MAX,, VIH = MIN VIK Input clamp voltage VCC = MIN, II = IIK IOL = 24mA TYP2 MAX UNIT V 3.2 V 0.25 0.40 V 0.35 0.50 V –0.73 –1.5 V II Input current at maximum input voltage VCC = MAX, VI = 7.0V 0.1 mA IIH High-level input current VCC = MAX, VI = 2.7V 20 µA –0.1 mA IIL Low level input current Low-level IO Output current3 ICC Supply current (total) MR, CP Dn VCC = MAX, MAX VI = 0 0.4V 4V VCC = MAX, VO = 2.25V ICCH ICCL –0.2 mA –112 mA 12 18 mA 21 29 mA –30 VCC = MAX NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX fMAX Maximum clock frequency Waveform 1 65 tPLH tPHL Propagation delay CP to Qn Waveform 1 2.0 3.0 8.0 11.0 MHz ns tPHL Propagation delay MR to Qn Waveform 2 4.0 12.0 ns AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN tsu(H) tsu(L) Setup time, High or Low Dn to CP th(H) th(L) UNIT MAX Waveform 3 5.0 5.0 ns Hold time, High or Low Dn to CP Waveform 3 0.0 0.0 ns tw(H) tw(L) CP pulse width, High or Low Waveform 1 6.0 8.0 ns tw(L) MR pulse width, Low Waveform 2 7.0 ns tREC Recovery time, MR to CP Waveform 2 12.0 ns 1991 Feb 08 4 Philips Semiconductors Product specification Octal D-type flip-flop 74ALS273 AC WAVEFORMS For all waveforms, VM = 1.3V. 1/fmax CP VM VM Dn VM VM VM VM VM tsu(H) th(H) tsu(L) th(L) tw(H) tPHL tw(L) tPLH VM Qn CP VM VM VM SF00294 SC00064 Waveform 3. Data Setup and Hold Times Waveform 1. Propagation Delay for Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency MR VM VM tw(L) tREC VM CP tPHL Qn VM SC00065 Waveform 2. Master Reset Pulse Width, Master Reset to Output Delay, and Master Reset to Clock Recovery Time TEST CIRCUIT AND WAVEFORMS VCC VIN CL RL AMP (V) VM 10% D.U.T. RT 90% VM VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE 10% tTHL (tff) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0.3V AMP (V) 90% Test Circuit for Totem-pole Outputs POSITIVE PULSE 90% VM VM 10% 10% tw 0.3V Input Pulse Definition DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS Family Amplitude VM 74ALS 3.5V 1.3V Rep.Rate tw tTLH tTHL 1MHz 500ns 2.0ns 2.0ns SC00005 1991 Feb 08 5 Philips Semiconductors Product specification Octal D–type flip–flop 74ALS273 DIP20: plastic dual in-line package; 20 leads (300 mil) 1991 Feb 08 6 SOT146-1 Philips Semiconductors Product specification Octal D–type flip–flop 74ALS273 SO20: plastic small outline package; 20 leads; body width 7.5 mm 1991 Feb 08 7 SOT163-1 Philips Semiconductors Product specification Octal D–type flip–flop 74ALS273 SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm 1991 Feb 08 8 SOT339-1 Philips Semiconductors Product specification Octal D–type flip–flop 74ALS273 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1991 Feb 08 9