PHILIPS 74LVC3G14DP

74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
Rev. 07 — 12 June 2008
Product data sheet
1. General description
The 74LVC3G14 provides three inverting buffers with Schmitt trigger action.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment. Schmitt trigger action at the inputs
makes the circuit tolerant of slower input rise and fall time. This device is fully specified for
partial power-down applications using IOFF. The IOFF circuitry disables the output,
preventing the damaging backflow current through the device when it is powered down.
2. Features
n
n
n
n
n
n
n
n
n
n
n
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
ESD protection:
u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Unlimited rise and fall times
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C.
3. Applications
n Wave and pulse shaper for highly noisy environment
n Astable multivibrator
n Monostable multivibrator.
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC3G14DP
−40 °C to +125 °C
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74LVC3G14DC
−40 °C to +125 °C
VSSOP8
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74LVC3G14GT
−40 °C to +125 °C
XSON8
plastic extremely thin small outline package; no leads;
8 terminals; body 1 × 1.95 × 0.5 mm
SOT833-1
74LVC3G14GD
−40 °C to +125 °C
XSON8U
plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
SOT996-2
74LVC3G14GM −40 °C to +125 °C
XQFN8U
plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm
SOT902-1
5. Marking
Table 2.
Marking codes
Type number
Marking code
74LVC3G14DP
V14
74LVC3G14DC
V14
74LVC3G14GT
V14
74LVC3G14GD
V14
74LVC3G14GM
V14
6. Functional diagram
1A
1Y
3Y
3A
2A
2Y
A
001aah728
Fig 1.
Logic symbol
IEC logic symbol
74LVC3G14_7
Product data sheet
mna025
001aah729
Fig 2.
Y
Fig 3.
Logic diagram
(one Schmitt trigger)
© NXP B.V. 2008. All rights reserved.
Rev. 07 — 12 June 2008
2 of 18
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
7. Pinning information
7.1 Pinning
74LVC3G14
1A
1
8
VCC
3Y
2
7
1Y
2A
3
6
3A
GND
4
5
2Y
74LVC3G14
1A
1
8
VCC
3Y
2
7
1Y
2A
3
6
3A
GND
4
5
2Y
001aab834
Transparent top view
001aag081
Fig 4.
Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 5.
Pin configuration SOT833-1 (XSON8)
74LVC3G14
74LVC3G14
1
8
VCC
3Y
2
7
1Y
2A
3
6
3A
GND
4
5
2Y
1
3A
2Y
8
1Y
7
1A
2
6
3Y
3
5
2A
GND
4
1A
VCC
terminal 1
index area
001aai242
Transparent top view
Transparent top view
Fig 6.
001aag082
Pin configuration SOT996-2 (XSON8U)
Fig 7.
Pin configuration SOT902-1 (XQFN8U)
7.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
SOT505-2, SOT765-1,
SOT833-1 and SOT996-2
SOT902-1
1A, 2A, 3A
1, 3, 6
7, 5, 2
data input
1Y, 2Y, 3Y
7, 5, 2
1, 3, 6
data output
GND
4
4
ground (0 V)
VCC
8
8
supply voltage
74LVC3G14_7
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 07 — 12 June 2008
3 of 18
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
8. Functional description
Table 4.
Function table [1]
Input nA
Output nY
L
H
H
L
[1]
H = HIGH voltage level; L = LOW voltage level
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
Conditions
Min
Max
Unit
−0.5
+6.5
V
−50
-
mA
[1]
−0.5
+6.5
V
VI < 0 V
VI
input voltage
IOK
output clamping current
VO > VCC or VO < 0 V
-
±50
mA
VO
output voltage
Active mode
[1][2]
−0.5
VCC + 0.5
V
Power-down mode
[1][2]
−0.5
+6.5
V
-
±50
mA
IO
output current
ICC
supply current
-
100
mA
IGND
ground current
−100
-
mA
-
250
mW
−65
+150
°C
Max
Unit
Ptot
total power dissipation
Tstg
storage temperature
VO = 0 V to VCC
Tamb = −40 °C to +125 °C
[3]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3]
For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
10. Recommended operating conditions
Table 6.
Operating conditions
Symbol
Parameter
VCC
supply voltage
1.65
5.5
V
VI
input voltage
0
5.5
V
VO
output voltage
Active mode
0
VCC
V
Power-down mode; VCC = 0 V
0
5.5
V
−40
+125
°C
Tamb
Conditions
ambient temperature
74LVC3G14_7
Product data sheet
Min
© NXP B.V. 2008. All rights reserved.
Rev. 07 — 12 June 2008
4 of 18
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
11. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
Tamb = −40 °C to +85 °C
VOH
VOL
HIGH-level output voltage
LOW-level output voltage
VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 5.5 V
VCC − 0.1 -
-
V
IO = −4 mA; VCC = 1.65 V
1.2
-
-
V
IO = −8 mA; VCC = 2.3 V
1.9
-
-
V
IO = −12 mA; VCC = 2.7 V
2.2
-
-
V
IO = −24 mA; VCC = 3.0 V
2.3
-
-
V
IO = −32 mA; VCC = 4.5 V
3.8
-
-
V
VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 5.5 V
-
-
0.1
V
IO = 4 mA; VCC = 1.65 V
-
-
0.45
V
IO = 8 mA; VCC = 2.3 V
-
-
0.3
V
IO = 12 mA; VCC = 2.7 V
-
-
0.4
V
IO = 24 mA; VCC = 3.0 V
-
-
0.55
V
IO = 32 mA; VCC = 4.5 V
-
-
0.55
V
II
input leakage current
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
-
±0.1
±5
µA
IOFF
power-off leakage current
VI or VO = 5.5 V; VCC = 0 V
-
±0.1
±10
µA
ICC
supply current
VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V
-
0.1
10
µA
∆ICC
additional supply current
VI = VCC − 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V
-
5
500
µA
CI
input capacitance
VCC = 3.3 V; VI = GND to VCC
-
3.5
-
pF
-
V
Tamb = −40 °C to +125 °C
VOH
VOL
II
HIGH-level output voltage
LOW-level output voltage
input leakage current
VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 5.5 V
VCC − 0.1 -
IO = −4 mA; VCC = 1.65 V
0.95
-
-
V
IO = −8 mA; VCC = 2.3 V
1.7
-
-
V
IO = −12 mA; VCC = 2.7 V
1.9
-
-
V
IO = −24 mA; VCC = 3.0 V
2.0
-
-
V
IO = −32 mA; VCC = 4.5 V
3.4
-
-
V
IO = 100 µA; VCC = 1.65 V to 5.5 V
-
-
0.1
V
IO = 4 mA; VCC = 1.65 V
-
-
0.7
V
IO = 8 mA; VCC = 2.3 V
-
-
0.45
V
IO = 12 mA; VCC = 2.7 V
-
-
0.6
V
IO = 24 mA; VCC = 3.0 V
-
-
0.8
V
IO = 32 mA; VCC = 4.5 V
-
-
0.8
V
-
-
±20
µA
VI = VIH or VIL
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
74LVC3G14_7
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 07 — 12 June 2008
5 of 18
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
IOFF
power-off leakage current
VI or VO = 5.5 V; VCC = 0 V
-
-
±20
µA
ICC
supply current
VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V
-
-
40
µA
∆ICC
additional supply current
VI = VCC − 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V
-
-
5000
µA
All typical values are measured at maximum VCC and Tamb = 25 °C.
[1]
Table 8.
Transfer characteristics
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 9
Symbol Parameter
positive-going
threshold voltage
VT+
negative-going
threshold voltage
VT−
VH
[2]
−40 °C to +85 °C
Conditions
−40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
VCC = 1.8 V
0.70
1.10
1.50
0.70
1.70
V
VCC = 2.3 V
1.00
1.40
1.80
1.00
2.00
V
VCC = 3.0 V
1.30
1.76
2.20
1.30
2.40
V
VCC = 4.5 V
1.90
2.47
3.10
1.90
3.30
V
VCC = 5.5 V
2.20
2.91
3.60
2.20
3.80
V
VCC = 1.8 V
0.25
0.61
0.90
0.25
1.10
V
VCC = 2.3 V
0.40
0.80
1.15
0.40
1.35
V
VCC = 3.0 V
0.60
1.04
1.50
0.60
1.70
V
VCC = 4.5 V
1.00
1.55
2.00
1.00
2.20
V
VCC = 5.5 V
1.20
1.86
2.30
1.20
2.50
V
VCC = 1.8 V
0.15
0.49
1.00
0.15
1.20
V
VCC = 2.3 V
0.25
0.60
1.10
0.25
1.30
V
VCC = 3.0 V
0.40
0.73
1.20
0.40
1.40
V
VCC = 4.5 V
0.60
0.92
1.50
0.60
1.70
V
VCC = 5.5 V
0.70
1.02
1.70
0.70
1.90
V
see Figure 10 and
Figure 11
see Figure 10 and
Figure 11
hysteresis voltage see Figure 10, Figure 11
and Figure 12
[1]
All typical values are measured at Tamb = 25 °C
[2]
VH = VT+ − VT−
74LVC3G14_7
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 07 — 12 June 2008
6 of 18
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
12. Dynamic characteristics
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter
−40 °C to +85 °C
Conditions
power dissipation
capacitance
CPD
Unit
Min
Max
Min
Max
VCC = 1.65 V to 1.95 V
1.0
4.2
11.0
1.0
12.0
ns
VCC = 2.3 V to 2.7 V
0.5
3.0
6.5
0.5
7.2
ns
VCC = 2.7 V
0.5
3.8
7.0
0.5
7.7
ns
VCC = 3.0 V to 3.6 V
0.5
3.2
6.0
0.5
6.7
ns
VCC = 4.5 V to 5.5 V
0.5
2.4
4.3
0.5
4.7
ns
-
18.1
-
-
-
pF
[2]
propagation delay nA to nY; see Figure 8
tpd
−40 °C to +125 °C
Typ[1]
[3]
VI = GND to VCC; VCC = 3.3 V
[1]
Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2]
tpd is the same as tPLH and tPHL.
[3]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
13. Waveforms
VI
VM
nA input
VM
GND
t PHL
t PLH
VOH
VM
nY output
VOL
VM
mna344
Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8.
The data input (nA) to output (nY) propagation delays
74LVC3G14_7
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 07 — 12 June 2008
7 of 18
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
Table 10.
Measurement points
VCC
Input VM
Output VM
1.65 V to 1.95 V
0.5 × VCC
0.5 × VCC
2.3 V to 2.7 V
0.5 × VCC
0.5 × VCC
2.7 V
1.5 V
1.5 V
3.0 V to 3.6 V
1.5 V
1.5 V
4.5 V to 5.5 V
0.5 × VCC
0.5 × VCC
VEXT
VCC
VI
RL
VO
G
DUT
RT
CL
RL
mna616
Test data is given in Table 11. Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 9.
Table 11.
Load circuitry for switching times
Test data
Supply voltage
Input
Load
VEXT
VCC
VI
tr = t f
CL
RL
tPLH, tPHL
1.65 V to 1.95 V
VCC
≤ 2.0 ns
30 pF
1 kΩ
open
2.3 V to 2.7 V
VCC
≤ 2.0 ns
30 pF
500 Ω
open
2.7 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
3.0 V to 3.6 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
4.5 V to 5.5 V
VCC
≤ 2.5 ns
50 pF
500 Ω
open
14. Waveforms transfer characteristics
VT+
VO
VI
VH
VT−
VO
VI
VH
VT−
VT+
Fig 10. Transfer characteristic
mna207
mna208
VT+ and VT− limits at 70 % and 20 %.
Fig 11. Definition of VT+, VT− and VH
74LVC3G14_7
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 07 — 12 June 2008
8 of 18
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
ICC
(mA)
mdb627
14
12
10
8
6
4
2
0
0
0.5
1
1.5
VI (V)
2
VCC = 3.0 V
Fig 12. Typical transfer characteristics
15. Application information
The slow input rise and fall times cause additional power dissipation, this can be
calculated using the following formula:
Padd = fi × (tr × ∆ICC(AV) + tf × ∆ICC(AV)) × VCC where:
Padd = additional power dissipation (µW);
fi = input frequency (MHz);
tr = input rise time (ns); 10 % to 90 %;
tf = input fall time (ns); 90 % to 10 %;
∆ICC(AV) = average additional supply current (µA).
∆ICC(AV) differs with positive or negative input transitions, as shown in Figure 13.
An example of a relaxation circuit using the 74LVC3G14 is shown in Figure 14.
74LVC3G14_7
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 07 — 12 June 2008
9 of 18
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
mnb086
50
∆ICC(AV)
(mA)
(1)
40
30
20
(2)
10
0
2
3
4
5
VCC (V)
6
Linear change of VI between 0.8 V to 2.0 V. All values given are typical unless otherwise specified.
(1) Positive-going edge.
(2) Negative-going edge.
Fig 13. ∆ICC(AV) as a function of VCC
R
C
mna035
1
1
f = --- ≈ ---------------------T 0.8 × RC
Fig 14. Relaxation oscillator
74LVC3G14_7
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 07 — 12 June 2008
10 of 18
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
16. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
D
E
A
SOT505-2
X
c
HE
y
v M A
Z
5
8
A
A2
(A3)
A1
pin 1 index
θ
Lp
L
1
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(1)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
4.1
3.9
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT505-2
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
---
Fig 15. Package outline SOT505-2 (TSSOP8)
74LVC3G14_7
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 07 — 12 June 2008
11 of 18
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
D
E
SOT765-1
A
X
c
y
HE
v M A
Z
5
8
Q
A
A2
A1
pin 1 index
(A3)
θ
Lp
1
4
e
L
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
Q
v
w
y
Z(1)
θ
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.40
0.15
0.21
0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT765-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
MO-187
Fig 16. Package outline SOT765-1 (VSSOP8)
74LVC3G14_7
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 07 — 12 June 2008
12 of 18
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
1
2
SOT833-1
b
4
3
4×
(2)
L
L1
e
8
7
6
e1
5
e1
e1
8×
A
(2)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.25
0.17
2.0
1.9
1.05
0.95
0.6
0.5
0.35
0.27
0.40
0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT833-1
---
MO-252
---
EUROPEAN
PROJECTION
ISSUE DATE
07-11-14
07-12-07
Fig 17. Package outline SOT833-1 (XSON8)
74LVC3G14_7
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 07 — 12 June 2008
13 of 18
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
B
D
SOT996-2
A
A
E
A1
detail X
terminal 1
index area
e1
v
w
b
e
L1
1
4
8
5
C
C A B
C
M
M
y
y1 C
L2
L
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
b
D
E
e
e1
L
L1
L2
v
w
y
y1
mm
0.5
0.05
0.00
0.35
0.15
2.1
1.9
3.1
2.9
0.5
1.5
0.5
0.3
0.15
0.05
0.6
0.4
0.1
0.05
0.05
0.1
REFERENCES
OUTLINE
VERSION
IEC
SOT996-2
---
JEDEC
JEITA
---
EUROPEAN
PROJECTION
ISSUE DATE
07-12-18
07-12-21
Fig 18. Package outline SOT996-2 (XSON8U)
74LVC3G14_7
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 07 — 12 June 2008
14 of 18
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
XQFN8U: plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
B
D
SOT902-1
A
terminal 1
index area
E
A
A1
detail X
L1
e
e
C
∅v M C A B
∅w M C
L
4
y1 C
y
5
3
metal area
not for soldering
e1
b
2
6
e1
7
1
terminal 1
index area
8
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
b
D
E
e
e1
L
L1
v
w
y
y1
mm
0.5
0.05
0.00
0.25
0.15
1.65
1.55
1.65
1.55
0.55
0.5
0.35
0.25
0.15
0.05
0.1
0.05
0.05
0.05
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT902-1
---
MO-255
---
EUROPEAN
PROJECTION
ISSUE DATE
05-11-25
07-11-14
Fig 19. Package outline SOT902-1 (XQFN8U)
74LVC3G14_7
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 07 — 12 June 2008
15 of 18
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
17. Abbreviations
Table 12.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
UTLP
Ultra-Thin Leadless Package
18. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC3G14_7
20080612
Product data sheet
-
74LVC3G14_6
Modifications:
•
•
Section 9: derating factor for TSSOP8 package corrected.
Added type number 74LVC3G14GD (XSON8U package).
74LVC3G14_6
20080207
Product data sheet
-
74LVC3G14_5
74LVC3G14_5
20071005
Product data sheet
-
74LVC3G14_4
74LVC3G14_4
20070314
Product data sheet
-
74LVC3G14_3
74LVC3G14_3
20050131
Product data sheet
-
74LVC3G14_2
74LVC3G14_2
20041027
Product data sheet
-
74LVC3G14_1
74LVC3G14_1
20040510
Product data sheet
-
-
74LVC3G14_7
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 07 — 12 June 2008
16 of 18
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
19.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74LVC3G14_7
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 07 — 12 June 2008
17 of 18
74LVC3G14
NXP Semiconductors
Triple inverting Schmitt trigger with 5 V tolerant input
21. Contents
1
2
3
4
5
6
7
7.1
7.2
8
9
10
11
12
13
14
15
16
17
18
19
19.1
19.2
19.3
19.4
20
21
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Waveforms transfer characteristics . . . . . . . . . 8
Application information. . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 12 June 2008
Document identifier: 74LVC3G14_7