INTEGRATED CIRCUITS PTN3500 Maintenance and control device Product specification Supersedes data of 2000 Nov 22 2001 Jan 17 Philips Semiconductors Product specification Maintenance and control device PTN3500 FEATURES PIN CONFIGURATION • I2C to parallel port expander • Internal 256x8 E2PROM • Self timed write cycle (5 ms typ.) • Four byte page write operation • Controlled pull-up on address lines • Low voltage VCC range of +2.5 V to +3.6 V • 5 V – tolerant I/Os • Low standby current (< 60 µA ) • Power on Reset • Supports Live Insertion • Compatible with SMBus specification version 1.1 • High E2PROM endurance and data retention • Available in SO16 and TSSOP16 package options VDD A0 1 16 A1 2 15 SDA A2 3 14 SCL P0 4 13 WC PTN3500 P1 5 12 P7 P2 6 11 P6 P3 7 10 P5 8 9 P4 VSS SW00541 Figure 1. DESCRIPTION PIN DESCRIPTION The PTN3500 is a general purpose maintenance and control device. It features an on-board E2PROM that can be used to store error codes or board manufacturing data for read–back by application software for diagnostic purposes. PIN NUMBER The eight quasi bidirectional data pins can be independently assigned as inputs or outputs to monitor board level status or activate indicator devices such as LEDs. The PTN3500 has three address pins allowing up to 8 devices to share the common two wire I2C software protocol serial data bus. The PTN3500 supports live insertion to facilitate usage in removable cards on backplane systems. SYMBOL NAME AND FUNCTION 1,2,3 A0:2 Address Lines 4,5,6,7 P0:3 Quasi–bidirectional i/o pins 8 VSS Supply Ground 9,10,11,12 P4:7 Quasi–bidirectional i/o pins 13 WC Write Control Pin. Should be tied LOW. 14 SCL I2C Serial Clock 15 SDA I2C Serial Data 16 VDD Supply Voltage ORDERING INFORMATION Type number n mber Package Name Description Version PTN3500D SO16 Plastic small-outline package; 16 leads; body width 7.5 mm SOT162-1 PTN3500DH TSSOP16 Plastic thin shrink small-outline package; 16 leads; body width 4.4 mm SOT403-1 FUNCTIONAL DIAGRAM SCL SDA A2:0 I2C Control WC E2PROM 256 x 8 8-Bit I/O Port P7:0 SW00562 Figure 2. 2001 Jan 17 2 853-2226 25435 Philips Semiconductors Product specification Maintenance and control device PTN3500 CHARACTERISTICS OF THE I2C-BUS The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 4). Bit transfer One data bit is transferred during each clock phase. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (See Figure 3). System configuration A device generating a message is a “transmitter”, a device receiving is the “receiver”. The device that controls the message is the “master” and the devices which are controlled by the master are the “slaves” (see Figure 5). SDA SCL DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED SW00542 Figure 3. Bit transfer SDA SDA SCL SCL S P START CONDITION STOP CONDITION SW00543 Figure 4. Definition of start and stop conditions SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER SW00544 Figure 5. System configuration 2001 Jan 17 3 Philips Semiconductors Product specification Maintenance and control device PTN3500 out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set–up and hold times must be taken into account. Acknowledge (see Figure 6) The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked DATA OUTPUT BY TRANSMITTER NOT ACKNOWLEDGE DATA OUTPUT BY RECEIVER ACKNOWLEDGE SCL FROM MASTER 1 2 8 9 S CLOCK PULSE FOR ACKNOWLEDGEMENT START CONDITION SW00545 Figure 6. Acknowledgment on the I2C-bus FUNCTIONAL DESCRIPTION VDD WRITE PULSE 100 µA DATA FROM SHIFT REGISTER D Q FF P0 TO P7 CI S POWER-ON RESET VSS D Q FF READ PULSE CI S DATA TO SHIFT REGISTER SW00546 Figure 7. Simplified schematic diagram of each I/O 2001 Jan 17 4 Philips Semiconductors Product specification Maintenance and control device PTN3500 Addressing For addressing, see Figure 8. SLAVE ADDRESS S 0 1 0 0 A2 SLAVE ADDRESS A1 A0 0 A S 1 0 1 0 a. (a) I/O EXPANDER A2 A1 A0 0 A b. SW00547 (b) MEMORY Figure 8. PTN3500 slave addresses Asynchronous Start Following any Start condition on the bus, a minimum of 9 SCL clock cycles must be completed before a Stop condition can be issued. The device does not support a Stop or a repeated Start condition during this time period. I/O OPERATIONS (see also Figure 7) Each of the PTN3500’s eight I/Os can be independently used as an input or output. Input I/O data is transferred from the port to the microcontroller by the READ mode (See Figure 10). Output data is transmitted to the port by the I/O WRITE mode (see Figure 9). SCL 1 2 3 4 5 6 7 8 SLAVE ADDRESS (I/O EXPANDER) SDA S 0 1 0 0 A2 A1 A0 START CONDITION DATA TO PORT DATA TO PORT 0 A R/W DATA 1 A ACKNOWLEDGE FROM SLAVE DATA 2 A ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE WRITE TO PORT DATA OUT FROM PORT DATA 1 VALID t pv DATA 2 VALID t pv SW00548 Figure 9. I/O WRITE mode (output) SLAVE ADDRESS (I/O EXPANDER) SDA S 0 1 0 0 START CONDITION A2 A1 A0 DATA FROM PORT 1 R/W A DATA FROM PORT DATA 1 A ACKNOWLEDGE FROM SLAVE DATA 4 ACKNOWLEDGE FROM MASTER 1 P STOP CONDITION READ FROM PORT DATA INTO PORT DATA 2 DATA 1 DATA 3 t ph DATA 4 t ps SW00549 Figure 10. I/O READ mode (input) 2001 Jan 17 5 Philips Semiconductors Product specification Maintenance and control device PTN3500 Quasi-bidirectional I/Os (see Figure 11) A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH. In this mode, only a current source to VDD is active. An additional strong pull-up to VDD allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs. SLAVE ADDRESS (PTN3500) SDA S 0 1 0 0 A2 A1 A0 START CONDITION SCL 1 2 0 R/W 3 4 5 6 DATA TO PORT DATA TO PORT 7 A A 1 ACKNOWLEDGE FROM SLAVE P3 ACKNOWLEDGE FROM SLAVE A 0 P P3 8 P3 OUTPUT VOLTAGE P3 PULL-UP OUTPUT CURRENT IOHt IOH SW00757 Figure 11. Transient pull-up current IOHt while P3 changes from LOW-to-HIGH and back to LOW SYMBOL PARAMETER tpv Output data valid; CL ≤ 100 pF tps Input data setup time; CL ≤ 100 pF 0 µs tph Input data hold time; CL ≤ 100 pF 4 µs 2001 Jan 17 MIN TYP 6 MAX UNIT 4 µs Philips Semiconductors Product specification Maintenance and control device PTN3500 the master issues the stop condition, initiating the internal write cycle to the non-volatile memory. Only write and read operations to the Quasi-bidirectional I/O are allowed during the internal write cycle. MEMORY OPERATIONS Write operations Write operations require an additional address field to indicate the memory address location to be written. The address field is eight bits long, providing access to any one of the 256 words of memory. There are two types of write operations, byte write and page write. Page Write (see Figure 13) A page write is initiated in the same way as the byte write. If after sending the first word of data, the stop condition is not received the PTN3500 considers subsequent words as data. After each data word the PTN3500 responds with an acknowledge and the two least significant bits of the memory address field are incremented. Should the master not send a stop condition after four data words the address counter will return to its initial value and overwrite the data previously written. After the receipt of the stop condition the inputs will behave as with the byte write during the internal write cycle. Byte Write (see Figure 12) To perform a byte write the start condition is followed by the memory slave address and the R/W bit set to 0. The PTN3500 will respond with an acknowledge and then consider the next eight bits sent as the word address and the eight bits after the word address as the data. The PTN3500 will issue an acknowledge after the receipt of both the word address and the data. To terminate the data transfer SLAVE ADDRESS (MEMORY) SDA WORD ADDRESS S 1 0 1 0 A2A1A0 0 A START CONDITION A P A ACKNOWLEDGE FROM SLAVE R/W DATA ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE STOP CONDITION SW00553 Figure 12. Byte write SLAVE ADDRESS (MEMORY) SDA WORD ADDRESS S 1 0 1 0 A2 A1 A0 0 A START CONDITION R/W ACKNOWLEDGE FROM SLAVE DATA TO MEMORY A DATA n ACKNOWLEDGE FROM SLAVE Figure 13. Page Write 2001 Jan 17 7 DATA TO MEMORY A DATA +3n ACKNOWLEDGE FROM SLAVE A P STOP CONDITION SW00554 Philips Semiconductors Product specification Maintenance and control device PTN3500 The master must perform a byte write to the address location to be read, but instead of transmitting the data after receiving the acknowledge from the PTN3500 the master reissues the start condition and memory slave address with the R/W bit set to one. The PTN3500 will then transmit an acknowledge and use the next eight clock cycles to transmit the data contained in the addressed location. The master ceases the transmission by issuing the stop condition after the eighth bit, omitting the ninth clock cycle acknowledge. Read operations PTN3500 read operations are initiated in an identical manner to write operations with the exception that the memory slave address’ R/W bit is set to a one. There are three types of read operations; current address, random and sequential. Current Address Read (see Figure 14) The PTN3500 contains an internal address counter that increments after each read or write access, as a result if the last word accessed was at address n then the address counter contains the address n+1. Sequential Read (see Figure 16) The PTN3500 sequential read is an extension of either the current address read or random read. If the master doesn’t issue a stop condition after it has received the eighth data bit, but instead issues an acknowledge, the PTN3500 will increment the address counter and use the next eight cycles to transmit the data from that location. The master can continue this process to read the contents of the entire memory. Upon reaching address 255 the counter will return to address 0 and continue transmitting data until a stop condition is received. The master ceases the transmission by issuing the stop condition after the eighth bit, omitting the ninth clock cycle acknowledge. When the PTN3500 receives its memory slave address with the R/W bit set to one it issues an acknowledge and uses the next eight clocks to transmit the data contained at the address stored in the address counter. The master ceases the transmission by issuing the stop condition after the eighth bit. There is no ninth clock cycle for the acknowledge. Random Read (see Figure 15) The PTN3500’s random read mode allows the address to be read from to be specified by the master. This is done by performing a dummy write to set the address counter to the location to be read. SLAVE ADDRESS (MEMORY) SDA DATA FROM MEMORY S 1 0 1 0 A2A1A0 1 A P START CONDITION STOP CONDITION R/W ACKNOWLEDGE FROM SLAVE SW00556 Figure 14. Current Address Read SLAVE ADDRESS (MEMORY) SDA S 1 0 1 0 A2 A1 A0 0 A START CONDITION SLAVE ADDRESS (MEMORY) WORD ADDRESS P A S 1 0 1 0 A2 A1 A0 1 A ACKNOWLEDGE FROM SLAVE R/W DATA FROM MEMORY ACKNOWLEDGE FROM SLAVE R/W START CONDITION ACKNOWLEDGE FROM SLAVE STOP CONDITION SW00557 Figure 15. Random Read SLAVE ADDRESS (MEMORY) SDA DATA FROM MEMORY S 1 0 1 0 A2 A1 A0 1 A START CONDITION R/W DATA n ACKNOWLEDGE FROM SLAVE DATA FROM MEMORY DATA FROM MEMORY A DATA n+1 ACKNOWLEDGE FROM MASTER A DATA N+X ACKNOWLEDGE FROM MASTER P STOP CONDITION SW00558 Figure 16. Sequential Read 2001 Jan 17 8 Philips Semiconductors Product specification Maintenance and control device PTN3500 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. PARAMETER SYMBOL MIN MAX UNIT VCC Supply Voltage –0.5 4.0 V VI Input Voltage VSS – 0.5 5.5 V II DC Input Current –20 20 mA IO DC Output Current –25 25 mA IDD Supply Current –100 100 mA ISS Supply Current –100 100 mA Ptot Total Power Dissipation 400 mW PO Total Power Dissipation per Output 100 mW TSTG Storage Temperature –65 +150 _C TAMB Operating Temperature –40 +85 _C VESD Electrostatic Discharge: Human Body Model, 1.5 kΩ, 100 pF – >2000 V Machine Model, 0 Ω, 200 pF – >200 V DC ELECTRICAL CHARACTERISTICS Tamb = –40_C to +85_C unless otherwise specified; VCC = 3.3 V SYMBOL PARAMETER MIN TYP MAX UNIT Supply VDD Supply Voltage IDDQ IDD1 2.5 3.3 3.6 V Standby Current; A0, A1, A2, WC = HIGH 60 µA Supply Current Read 1 mA IDD2 Supply Current Write 2 mA VPOR Power on Reset Voltage 2.4 V Input SCL; input, output SDA VIL Input LOW voltage –0.5 0.3 VDD V VIH Input HIGH voltage 0.7 VDD 5.5 V IOL Output LOW current @ VOL = 0.4 V 3 IL Input leakage current @ VI = VDD or VSS –1 CI Input capacitance @ VI = VSS mA 1 µA 7 pF I/O Expander Port VIL Input LOW voltage –0.5 0.3 VDD V VIH Input HIGH voltage 0.7 VDD 5.5 V IIHL(max) Input current through protection diodes –400 400 µA IOL Output LOW current @ VOL = 1 V 10 25 IOH Output HIGH current @ VOH = Vss 30 100 IOHt Transient pull-up current CI Input Capacitance 10 pF CO Output Capacitance 10 pF mA 300 2 µA mA Address Inputs (A0, A1, A2), WC input VIL Input LOW voltage –0.5 0.3 VDD V VIH Input HIGH voltage 0.7 VDD 5.5 V IL Input leakage current @ VI = VDD –1 1 µA Input leakage (pull-up) current @ VI = VSS 10 100 µA 2001 Jan 17 9 25 Philips Semiconductors Product specification Maintenance and control device PTN3500 I2C-BUS TIMING CHARACTERISTICS SYMBOL I2C-bus PARAMETER MIN. TYP. MAX. UNIT timing (see Figure 17; Note 1) fSCL SCL clock frequency – – 400 kHz tSW tolerable spike width on bus – – 50 ns tBUF bus free time 1.3 – – µs tSU;STA START condition set–up time 0.6 – – µs tHD;STA START condition hold time 0.6 – – µs tr SCL and SDA rise time – – 0.3 µs tf SCL and SDA fall time – – 0.3 µs tSU;DAT data set–up time 250 – – ns tHD;DAT data hold time 0 – – ns tVD;DAT SCL LOW to data out valid – – 1.0 µs tSU;STO STOP condition set–up time 0.6 – – µs NOTE: 1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing of VSS to VDD. handbook, full pagewidth PROTOCOL t START CONDITION (S) BIT 7 MSB (A7) BIT 6 (A6) SU;STA BIT 0 LSB (R/W) ACKNOWLEDGE (A) STOP CONDITION (P) 1 / f SCL SCL t t t r BUF f SDA t HD;STA t t SU;DAT HD;DAT t VD;DAT MBD820 t SU;STO SW00561 Figure 17. 2001 Jan 17 10 Philips Semiconductors Product specification Maintenance and control device PTN3500 POWER-UP TIMING SYMBOL PARAMETER MAX. UNIT 1 Power-up to Read Operation 1 ms tPUW1 Power-up to Write Operation 5 ms tPUR NOTE: 1. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are guaranteed by design. WRITE CYCLE LIMITS SYMBOL PARAMETER MIN. TYP. (5) MAX. UNIT tWR1 Write Cycle Time – 5 10 ms NOTE: 1. tWR is the maximum time that the device requires to perform the internal write operation. Write Cycle Timing SCL SDA 8th Bit ACK Word n MEMORY ADDRESS tWR Stop Condition Start Condition SW00560 Figure 18. 2001 Jan 17 11 Philips Semiconductors Product specification Maintenance and control device PTN3500 SOLDERING seconds depending on heating method. Typical reflow temperatures range from 215 to 250°C. Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45°C. Wave soldering Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our IC Package Databook (order code 9398 652 90011). If wave soldering cannot be avoided, the following conditions must be observed: DIP • A double-wave (a turbulent wave with high upward pressure Soldering by dipping or by wave The maximum permissible temperature of the solder is 260°C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369–1) or SSOP20 (SOT266–1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300°C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400°C, contact may be up to 5 seconds. Maximum permissible solder temperature is 260°C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150°C within 6 seconds. Typical dwell time is 4 seconds at 250°C. SO and SSOP A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Reflow soldering Reflow soldering techniques are suitable for all SO and SSOP packages. Repairing soldered joints Fix the component by first soldering two diagonally opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320°C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. 2001 Jan 17 12 Philips Semiconductors Product specification Maintenance and control device PTN3500 SO16: plastic small outline package; 16 leads; body width 7.5 mm 2001 Jan 17 13 SOT162-1 Philips Semiconductors Product specification Maintenance and control device PTN3500 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm 2001 Jan 17 14 SOT403-1 Philips Semiconductors Product specification Maintenance and control device PTN3500 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 01-01 Document order number: 2001 Jan 17 15 9397 750 07932