PHILIPS PDI1394L41BE

INTEGRATED CIRCUITS
PDI1394L41
1394 content protection AV link layer
controller
Preliminary specification
Supersedes data of 1999 Sep 30
2000 Apr 15
NOTICE: DTLA SENSITIVE INFORMATION HAS BEEN WITHHELD FROM THIS DATA SHEET. SEE SECTION 2.1 FOR DETAILS.
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
1.0 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.0 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.0 QUICK REFERENCE DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.0 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.0 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.0 FUNCTIONAL DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.0 INTERNAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.0 APPLICATION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.0 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2 AV Interface 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3 AV Interface 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4 Phy Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5 Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.0 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.0 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.0 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 AV interface and AV layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.1 IEC 61883 International Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.2 CIP Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.3 The AV Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.4 Content Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.5 mLAN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.6 SY – Sync Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.7 Programmable Buffer Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3 Bushold and Link/PHY single capacitor galvanic isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.1 Bushold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.2 Single capacitor isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5 The host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5.1 Read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5.2 Write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5.3 Big and little endianness, data invariance, and data bus width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5.4 Accessing the asynchronous packet queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5.5 The CPU bus interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6 The Asynchronous Packet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6.1 Reading an Asynchronous Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6.2 Link Packet Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.0 REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1 Link Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1.1 ID Register (IDREG) – Base Address: 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1.2 General Link Control (LNKCTL) – Base Address: 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1.3 Link /Phy Interrupt Acknowledge (LNKPHYINTACK) – Base Address: 0x008 . . . . . . . . . . . . . . . . . . . . . . . . .
13.1.4 Link / Phy Interrupt Enable (LNKPHYINTE) – Base Address: 0x00C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1.5 Cycle Timer Register (CYCTM) – Base Address: 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1.6 Phy Register Access (PHYACS) – Base Address: 0x014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1.7 Global Interrupt Status and TX Control (GLOBCSR) – Base Address: 0x018 . . . . . . . . . . . . . . . . . . . . . . . . .
13.1.8 Timer (TIMER) – Base Address: 0x01C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2 AV (Isochronous) Transmitter and Receiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.1 Isochronous Transmit Packing Control and Status (ITXPKCTL) – Base Address: 0x020 . . . . . . . . . . . . . . .
13.2.2 Common Isochronous Transmit Packet Header Quadlet 1 (ITXHQ1) – Base Address: 0x024 . . . . . . . . . . .
13.2.3 Common Isochronous Transmit Packet Header Quadlet 2 (ITXHQ2) – Base Address: 0x028 . . . . . . . . . . .
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Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
13.2.4 Isochronous Transmitter Interrupt Acknowledge (ITXINTACK) – Base Address: 0x02C . . . . . . . . . . . . . . . .
13.2.5 Isochronous Transmitter Interrupt Enable (ITXINTE) – Base Address: 0x030 . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.6 Isochronous Transmitter Control Register (ITXCTL) – Base Address: 0x34 . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.7 Isochronous Transmitter Memory Status (ITXMEM) – Base Address: 0x038 . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.8 Isochronous Receiver Unpacking Control (IRXPKCTL) – Base Address: 0x040 . . . . . . . . . . . . . . . . . . . . . .
13.2.9 Common Isochronous Receiver Packet Header Quadlet 1 (IRXHQ1) – Base Address: 0x044 . . . . . . . . . .
13.2.10 Common Isochronous Receiver Packet Header Quadlet 2 (IRXHQ2) – Base Address: 0x048 . . . . . . . . .
13.2.11 Isochronous Receiver Interrupt Acknowledge (IRXINTACK) – Base Address: 0x04C . . . . . . . . . . . . . . . . .
13.2.12 Isochronous Receiver Interrupt Enable (IRXINTE) – Base Address: 0x050 . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.13 Isochronous Receiver Control Register (IRXCTL) – Base Address: 0x054 . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.14 Isochronous Receiver Memory Status (IRXMEM) – Base Address: 0x058 . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3 Asynchronous Control and Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.1 Asynchronous RX/TX Control (ASYCTL) – Base Address: 0x080 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.2 Asynchronous RX/TX Memory Status (ASYMEM) – Base Address: 0x084 . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.3 Asynchronous Transmit Request Next (TX_RQ_NEXT) – Base Address: 0x088 . . . . . . . . . . . . . . . . . . . . . .
13.3.4 Asynchronous Transmit Request Last (TX_RQ_LAST) – Base Address: 0x08C . . . . . . . . . . . . . . . . . . . . . .
13.3.5 Asynchronous Transmit Response Next (TX_RP_NEXT) – Base Address: 0x090 . . . . . . . . . . . . . . . . . . . . .
13.3.6 Asynchronous Transmit Response Last (TX_RP_LAST) – Base Address: 0x094 . . . . . . . . . . . . . . . . . . . . .
13.3.7 Asynchronous Receive Request (RREQ) – Base Address: 0x098 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.8 Asynchronous Receive Response (RRSP) – Base Address: 0x09C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.9 Asynchronous RX/TX Interrupt Acknowledge (ASYINTACK) – Base Address: 0x0A0 . . . . . . . . . . . . . . . . . .
13.3.10 Asynchronous RX/TX Interrupt Enable (ASYINTE) – Base Address: 0x0A4 . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.11 RDI Register – Base Address: 0x0B0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.12 Shadow Register (SHADOW_REG) – Base Address: 0x0F4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4 Indirect Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.1
...........................................................................................
13.4.2 Indirect Address Register (INDADDR) – Base Address: 0x0F8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3 Indirect Data Register (INDDATA) – Base Address: 0x0FC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.5 Indirect Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.5.1 Registers for FIFO Size Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.0 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.1 Pin Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.0 AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.0 TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.1 AV Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.2 AV Interface Critical Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.3 PHY-Link Interface Critical Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4 Host Interface Critical Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5 CYCLEIN/CYCLEOUT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.6 RESET Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
1.0 FEATURES
PDI1394L41
2.0 DESCRIPTION
• IEEE1394.a and IEEE1394–1995 Standard Link Layer Controller
• Hardware Support for the IEC61883 International Standard of
The PDI1394L41, Philips Semiconductors Full Duplex 1394
Audio/Video (AV) Link Layer Controller, is an IEEE 1394–1995
compliant link layer controller featuring 2 embedded AV layer
interfaces. The AV layers are designed to encrypt and pack, or
unpack and decrypt application data packets for transmission over
the IEEE1394 bus using isochronous data transfers and the “5C”
content protection method.
Digital Interface for Consumer Electronics
• Interface to any IEEE 1394–1995 or 1394.a Physical Layer
Interface
• 5V Tolerant I/Os
• Single 3.3V supply voltage
• Full-duplex isochronous operation
• Operates with 400/200/100 Mbps physical layer devices
• 12K byte fully programmable FIFO pool for isochronous and
The application data is packetized according to the IEC 61883
International Standard of Interface for Consumer Electronic
Audio/Video Equipment. Both AV layer interfaces are byte-wide
ports capable of accommodating various MPEG–2 and DVC
codecs. A flexible host interface is provided for internal register
configuration as well as performing asynchronous data transfers.
Both 8 bit and 16 bit wide data paths, as well as
multiplexed/non-multiplexed access modes are supported.
asynchronous data
• Supports single capacitor isolation mode and IEEE 1394–1995,
The PDI1394L41 is powered by a single 3.3V power supply and the
inputs and outputs are 5V tolerant. It is available in the LQFP144
package.
Annex J. isolation
• 6-field deep SYT buffer added to enhance real-time isochronous
2.1 Use restrictions
synchronization using the AVFSYNC pin
Due to rules set forth by the Digital Transmission Licensing
Administrator (DTLA) information concerning some features of the
L41 is the subject of a license issued by the DTLA. That information
has been omitted from this data sheet and is available only to DTLA
licensees on a restricted distribution basis. In order to obtain a copy
of the information, licensed parties should contact Philips
Semiconductors at [email protected] and request data sheet
addendum AL41-1. Upon verification of the requestor’s DTLA
license status, a paper copy of the addendum will be sent to the
DTLA listed responsible person within the requesting company.
Distribution of samples and sales of the L41 chip are likewise
restricted to DTLA licensees. For information pertaining to the
procurement of a DTLA license please consult the DTLA website at
DTCP.com.
• Generates its own AV port clocks under software control. Select
one of three frequencies: 24.576, 12.288, or 6.144 MHz
• Hardware support for the “5C” content protection method
• On chip timer resources
• Flexible 8/16 bit multiplexed/non-multiplexed host interface
• Parallel AV interface
• Fast 56-bit M6 cipher/decipher blocks capable of operating at over
80 Mbps
• Hardware authentication acceleration to reduce software
processor loading
• Highly configurable 12 K byte FIFO
3.0 QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C
PARAMETER
SYMBOL
VDD
Functional supply voltage range
IDD
Supply current @ VDD = 3.3V
SCLK
Device clock
CONDITIONS
MIN
3.0
Operating
49.147
TYP
MAX
UNIT
3.3
3.6
V
110
150
mA
49.152
49.157
MHz
4.0 ORDERING INFORMATION
PACKAGES
144-pin LQFP144
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
0°C to +70°C
PDI1394L41BE
PDI1394L41BE
SOT486–1
NOTE:
This datasheet is subject to change.
Please visit out internet website www.semiconductors.philips.com/1394 for latest changes.
2000 Apr 15
1
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
5.0 PIN CONFIGURATION
144
109
1
108
LQFP
36
73
37
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
*
Function
HIF D15
HIF D14
HIF D13
HIF D12
GND
VDD
HIF D11
HIF D10
HIF D9
HIF D8
GND
VDD
HIF AD7
HIF AD6
HIF AD5
HIF AD4
GND
VDD
HIF AD3
HIF AD2
HIF AD1
HIF AD0
GND
VDD
HIF A8
HIF A7
HIF A6
HIF A5
HIF A4
HIF A3
HIF A2
HIF A1
HIF A0
GND
VDD
HIF CSN
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
72
Function
HIF WRN
HIF INTN
HIF ALE
HIF RDN
HIF WAIT
RESETN
GND
VDD
HIF 16BIT
HIF MUX
1394 MODE
PD
RESERVED
RESERVED
RESERVED
RESERVED
GND
VDD
CLK50
CYCLEIN
CYCLEOUT
RESERVED
RESERVED
GND
VDD
TESTPIN
TESTPIN
TESTPIN
RESERVED
RESERVED
RESERVED
RESERVED
GND
VDD
RESERVED
RESERVED
Pin
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
Function
PHY D7*
PHY D6*
PHY D5*
PHY D4*
GND
VDD
PHY D3*
PHY D2*
PHY D1*
PHY D0*
GND
VDD
PHY CTL1*
PHY CTL0*
LREQ
SCLK*
GND
VDD
LPS*
LINKON
ISON
GND
VDD
AV1ERR0
AV1ERR1
AV1ENDPCK
AV1CLK
AV1FSYNC
AV1 SY
AV1VALID
AV1SYNC
AV1EMIO
AV1EMI1
GND
VDD
AV1D0
Pin
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Function
AV1D1
AV1D2
AV1D3
GND
VDD
AV1D4
AV1D5
AV1D6
AV1D7
AV1READY
GND
VDD
AV2ERR0/LTLEND
AV2ERR1/DATINV
AV2ENDPCK
AV2CLK
AV2FSYNC
AV2 SY
AV2VALID
AV2SYNC
AV2EMI0
AV2EMI1
GND
VDD
AV2D0
AV2D1
AV2D2
AV2D3
GND
VDD
AV2D4
AV2D5
AV2D6
AV2D7
AV2READY
RESERVED
Indicates pin equipped with internal bus hold circuit activated by the state of the ISON pin.
SV01020
2000 Apr 15
2
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
6.0 FUNCTIONAL DIAGRAM
HIF A[8:0]
HIF D[15:8]
PD
CYCLEIN
CYCLEOUT
CLK50
PHY CTL[0:1]
LPS
LREQ
ISON
LinkOn
SCLK
1394MODE
PDI1394L41
IEEE 1394
CONTENT PROTECTION
AV LINK LAYER CONTROLLER
VDD
GND
AV1 D[7:0]
AV1CLK
AV1VALID
AV2D[7:0]
AV2CLK
AV2VALID
AV1SYNC
AV2SYNC
AV2FSYNC
AV2 SY
AV2READY
AV2EMI[1:0]
AV2ENDPCK
AV2ERR0/LTLEND
AV2ERR1/DATAINV
AV1FSYNC
AV1 SY
AV1READY
AV1EMI[1:0]
AV1ENDPCK
AV1ERR0
AV1ERR1
AV LAYER 2
AV LAYER 1
PHY D[0:7]
HIF WRN
HIF RDN
HIF CSN
HIF 16BIT
HIF MUX
RESETN
HIF ALE
HIF WAIT
HIF INTN
PHY
HOST
HIF AD[7:0]
SV01021
AV1 D[7:0]
AV1READY
AV1EMI[1:0]
AV1CLK
AV1SYNC
AV1VALID
AV1FSYNC
AV1ENDPCK
AV1ERR0
AV1ERR1
AV1SY
AV2 D[7:0]
AV2READY
AV2EMI[1:0]
AV2CLK
AV2SYNC
AV2VALID
AV2FSYNC
AV2ENDPCK
AV2ERR0/LTLEND
AV2ERR1/DATAINV
AV2SY
HOST
AV LAYER2
AV LAYER1
7.0 INTERNAL BLOCK DIAGRAM
HIF A[8:0]
HIF D[15:8]
HIF AD[7:0]
HIF 16BIT
HIF WRN
HIF ALE
HIF RDN
HIF MUX
HIF CSN
AV1 LAYER
ISOCHRONOUS
TRANSMITTER/
RECEIVER
CYCLEOUT
LPS
CYCLEIN
PHY D[0:7]
12KB BUFFER
MEMORY
(ISOCH & ASYNC
PACKETS)
LINK CORE
PHY CTL[0:1]
LREQ
LinkOn
ISON
PD
SCLK
1394MODE
AV2 LAYER
ISOCHRONOUS
TRANSMITTER/
RECEIVER
NOTE: THERE IS ONE
ISOCHRONOUS RECEIVER
AND ONE ISOCHRONOUS
TRANSMITTER—THEREFORE,
WHEN EITHER AVPORT IS SET
TO TRANSMIT, THE OTHER
AVPORT IS AUTOMATICALLY
SET TO RECEIVE
ASYNC
TRANSMITTER
AND
RECEIVER
8-BIT
INTERFACE
CONTROL
AND
STATUS
REGISTERS
RESETN
HIF WAIT
HIF INTN
SV01022
2000 Apr 15
3
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
8.0 APPLICATION DIAGRAM
MPEG OR DVC
DECODER
AV
INTERFACE
PDI1394L41
AV LINK
MPEG OR DVC
DECODER
AV
INTERFACE
PHY–LINK
INTERFACE
PDI1394Pxx
PHY
1394 CABLE
INTERFACE
DATA 16/
ADDRESS 9/
INTERRUPT & CONTROL
HOST CONTROLLER
SV01023
9.0 PIN DESCRIPTION
9.1 Host Interface
PIN No.
PIN SYMBOL
I/O
NAME AND FUNCTION
13, 14, 15, 16, 19,
20, 21, 22
HIF AD[7:0]
I/O
Host Interface Data 7 (MSB) through 0. Byte wide data path to internal registers.
1, 2, 3, 4, 7, 8, 9,
10
HIF D[15:8]
I/O
Host Interface Data 15 (MSB) through 8. Only used in 16 bit access mode (HIF
16BIT = HIGH).
26, 27, 28, 29, 30,
31, 32, 33
HIF A[7:0]
I/O
Host Interface Address 0 through 8. Provides the host with a byte wide interface to internal
registers. See description of Host Interface for addressing rules (Section 12.5).
25
HIF A8
I
Control bit used to indicate the first byte/word of a read function or the last byte/word of a write
function so that the data quadlet is fetched or stored. See Section 12.5 for more information
regarding the host interface.
36
HIF CSN
I
Chip Select (active LOW). Host bus control signal to enable access to the FIFO and control
and status registers.
37
HIF WRN
I
Write enable. When asserted (LOW) in conjunction with HIF CSN, a write to the PDI1394L41
internal registers is requested. (NOTE: HIF WRN and HIF RDN : if these are both LOW in
conjunction with HIF CSN, then a write cycle takes place. This can be used to connect CPUs
that use R/W_N line rather than separate RD_N and WR_N lines. In that case, connect the
R/W_N line to the HIF WRN and tie HIF RDN LOW.)
38
HIF INTN
O
Interrupt (active LOW). Indicates a interrupt internal to the PDI1394L41. Read the General
Interrupt Register for more information. This pin is open drain and requires a 1KW pull-up
resistor.
39
HIF ALE
I
Address latch enable. Used in multiplex mode only.
40
HIF RDN
I
Read enable. When asserted (LOW) in conjunction with HIF CSN, a read of the PDI1394L41
internal registers is requested.
41
HIF WAIT
O
Wait signal. Signals Host interface in WAIT condition when HI. See Section 12.5.
42
RESETN
I
Reset (active LOW). The asynchronous master reset to the PDI1394L41.
45
HIF 16BIT
I
Host interface mode pin. When LOW HIF operates in 8 bit mode. When HIGH HIF operates in
16 bit mode.
46
HIF MUX
I
Host interface mode pin. When LOW HIF operates in non-multiplex mode, when HIGH HIF
operates in multiplex mode. When HIGH, the low-order eight address bits are multiplexed with
data on HIF AD[7:0], otherwise they are non-multiplexed and supplied on A[7:0].
2000 Apr 15
4
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
9.2 AV Interface 1
NOTE: This AV interface may be configured to transmit or receive according to the condition of “DIRAV1” bit in GLOBCSR register
(0X018)—default is transmit.
PIN No.
PIN SYMBOL
I/O
NAME AND FUNCTION
96
AV1ERR0
O
CRC error. Indicates bus packet delivered on AV1 D[7:0] had a CRC error; the current AV
packet is unreliable.
97
AV1ERR1
O
Sequence Error. Indicates at least one source packet was lost before the current AV1 D [7:0] data.
98
AV1ENDPCK
I
End of application packet indication from data source. Required only if input packet is not
multiple of 4 bytes. It can be tied LOW for data packets that are 4*N in size.
99
AV1CLK
I/O
External application clock. Rising edge active. This pin can be programmed to be an output
and the application clock. Depending on the configuration of AV Port 1 as transmitter or receiver,
the output enable is located in the ITXPKCTL register (address 0x020) or IRXPKCTL register
(address 0x040).
100
AV1FSYNC
I/O
Programmable frame sync, is set to input when AV interface 1 is a transmitter and to output
when the interface is configured as a receiver. When the pin is an input, it is used to designate
a frame of data for Digital Video (DV). The signal is time stamped and transmitted in the SYT
field of ITXHQ2. When set to an output, the signal is derived from SYT field of IRXHQ2.
101
AV1 SY
I/O
SY Value. When port AV1 is configured as a transmitter, this pin is an input. When the AV port
is configured to as a receiver, the pin is an output. See the description for bit 0 of the
ITXCTL (0x034) and IRXCTL (0x054) registers.
102
AV1VALID
I/O
Indicates data on AV1 D [7:0] is valid.
103
AV1SYNC
I/O
Indicates that the data currently being clocked by the source under the condition of AV1VALID
is the start of an application packet. If the AV interface is configured as a receiver, then it will
assert AV1SYNC when an application packet becomes available and persist until the first data
of the packet is clocked out. Thus, AV1VALID may last for more than one cycle, but for exactly
one cycle in which AV1VALID is asserted.
105, 104
AV1EMI[1:0]
O
Encryption Mode Indication pins. Outputs encryption mode when this AV port is in receive state
with decipher enabled.
117, 116, 115, 114,
111, 110, 109, 108
AV1 D[7:0]
I/O
Audio/Video Data 7 (MSB) through 1. Part of byte-wide interface to the AV layer 1.
I
When the AV port is configured as a receiver, this pin is an input. This is a flow control signal
that allows the destination to indicate whether it is able to accept data flowing across
AV Interface 1. The AV interface responds to an inactive AV1READY by not asserting
AV1VALID, and thereby withholding data.
The AV1READY signal is processed through one level of pipelining, which means that the
AV Link will accept data on the cycle in which AV1READY is de-asserted and will not accept
data on the cycle in which AV1READY is asserted.
118
AV1READY
O
2000 Apr 15
When the AV port is configured to transmit, this pin is an output. This is a flow control signal
that allows the destination to indicate whether it is able to accept data flowing across
AV Interface 1. The source of data, an external entity, responds to an inactive AV1READY by
not asserting AV1VALID, and thereby withholding data.
The AV1READY signal should be processed by the sink through one level of pipelining, which
means that the receiver must be able to accept data on the cycle in which AV1READY is
de-asserted. The receiving interface does not have to accept data on the cycle in which
AV1READY is asserted.
5
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
9.3 AV Interface 2
NOTE: This AV interface may be configured to transmit or receive according to the condition of “DIRAV1” bit in GLOBCSR register—default is
receive.
PIN No.
121
PIN SYMBOL
AV2ERR0/
LTLEND
I/O
NAME AND FUNCTION
I/O
CRC error, indicates bus packet containing AV2 D [7:0] had a CRC error, the current AV packet
is unreliable. This pin is also used to input the mode of LTLEND (Little Endian) bit after a chip
reset. An appropriate pull-up or pull-down resistor (22 kΩ recommended) should be connected
to place the pin in the desired state during reset. Please see details related to use of the
LTLEND bit in the “Host Interface” section (of the datasheet (Section 12.5).
Sequence Error. Indicates at least one source packet was lost before the current AV2 D [7:0]
data. This pin is also used to input the mode of DATINV (Data Invariant) bit after a chip reset.
An appropriate pull-up or pull-down resistor (22 kΩ recommended) should be connected to
place the pin in the desired state during reset. Please see details related to use of the DATINV
bit in the “Host Interface” section (of the datasheet (Section 12.5).
122
AV2ERR1/
DATINV
I/O
123
AV2ENDPCK
I
124
AV2CLK
I/O
External application clock. Rising edge active. This pin can be programmed to be an output
and the application clock. Depending on the configuration of AV Port 2 as transmitter or
receiver, the output enable is located in the ITXPKCTL register (address 0x020) or IRXPKCTL
register (address 0x040).
125
AV2FSYNC
I/O
Programmable frame sync, is set to input when AV interface 2 is a transmitter, and to output
when the interface is configures as a receiver. When the pin is an input, it is used to designate
a frame of data for Digital Video (DV). The signal is time stamped and transmitted in the SYT
field of ITXHQ2. When set to an output, the signal is derived from SYT field of IRXHQ2.
126
AV2 SY
I/O
SY Value: When port AV2 is configured as a transmitter, this pin is an input. When the AV port
is configured to as a receiver, the pin is an output. See the description for bit 0 of the
ITXCTL (0x034) and IRXCTL (0x054) registers.
127
AV2VALID
I/O
Indicates data on AV2 D [7:0] is valid.
End of application packet indication from data source. Required only if input packet is not
multiple of 4 bytes. It can be tied LOW for data packets that are 4*N in size.
128
AV2SYNC
I/O
Indicates that the data currently being clocked by the source under the condition of AV2VALID
is the start of an application packet. If the AV interface is configured as a receiver, then it will
assert AV2SYNC when an application packet becomes available and persist until the first data
of the packet is clocked out. Thus, AV2VALID may last for more than one cycle, but for exactly
one cycle in which AV2VALID is asserted.
130, 129
AV2EMI[1:0]
O
Encryption Mode Indication pins. Outputs encryption mode when this AV port is in receive state
with decipher enabled.
142, 141, 140,
139, 136, 135,
134, 133
AV2 D[7:0]
I/O
Audio/Video Data 7 (MSB) through 0. Part of byte-wide interface to the AV layer 2.
I
When the AV port is configured as a receiver, this pin is an input. This is a flow control signal
that allows the destination to indicate whether it is able to accept data flowing across
AV Interface 2. The AV interface responds to an inactive AV2READY by not asserting
AV2VALID, and thereby withholding data.
The AV2READY signal is processed through one level of pipelining, which means that the
AV Link will accept data on the cycle in which AV2READY is de-asserted and will not accept
data on the cycle in which AV2READY is asserted.
143
AV2READY
O
2000 Apr 15
When the AV port is configured to transmit, this pin is an output. This is a flow control signal
that allows the destination to indicate whether it is able to accept data flowing across
AV Interface 2. The source of data, and external entity, responds to an inactive AV2READY by
not asserting AV2VALID, and thereby withholding data.
The AV2READY signal should be processed by the sink through one level of pipelining, which
means that the receiver must be able to accept data on the cycle in which AV2READY is
de-asserted. The receiving interface does not have to accept data on the cycle in which
AV2READY is asserted.
6
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
9.4 Phy Interface
PIN No.
PIN SYMBOL
I/O
NAME AND FUNCTION
82, 81, 80, 79,
76, 75, 74, 73
PHY D[0:7]
I/O
Data 0 (MSB) through 7 (NOTE: To preserve compatibility to the specified Link-Phy interface of
the IEEE 1394–1995 standard, Annex J, bit 0 is the most significant bit). Data is expected on
AV D[0:1] for 100Mb/s, AV D[0:3] for 200Mb/s, and AV D[0:7] for 400Mb/s. See IEEE 1394–1995
standard, Annex J for more information.
86, 85
PHY CTL[0:1]
I/O
Control Lines between Link and Phy. See 1394 Specification for more information.
47
1394 MODE
I
1394–1995 Annex J PHY (HIGH), or 1394.a PHY (LOW)
87
LREQ
O
Link Request. Bus request to access the PHY. See IEEE 1394–1995 standard, Annex J for more
information. (Used to request arbitration or read/write PHY registers).
88
SCLK
I
System clock. 49.152MHz input from the PHY (the PHY-LINK interface operates at this frequency).
91
LPS
O
Link power status.
92
LINKON
I
L41 generates a host interrupt when this pin receives a link on signal from the PHY. Interrupt is a
request from another node for the L41 to be powered up (see PD pin).
ISON
I
Isolation mode. This pin is asserted (LOW) when an Annex J type isolation barrier is used.
See IEEE 1394–1995 Annex J. for more information. When tied HIGH, this pin enables internal
bushold circuitry on the affected PHY interface pins (see below). Active bushold circuits allow
either the direct connection to PHY pins or the use of the single capacitor isolation mode.
PIN No.
PIN SYMBOL
I/O
5, 11, 17, 23,
34, 43, 53, 60,
69, 77, 83, 89,
94, 106, 112,
119, 131, 137
GND
Ground reference
6, 12, 18, 24,
35, 44, 54, 61,
70, 78, 84, 90,
95, 107, 113,
120, 132, 138
VDD
3.3V ± 0.3V power supply
48
PD1,2,3,4
I
49, 50, 51, 52,
58, 59, 65, 66,
67, 68, 71, 72
144
RESERVED
NA
55
CLK50
O
Auxiliary clock, value is SCLK (usually 49.152 MHz)
56
CYCLEIN
I
Provides the capability to supply an external cycle timer signal for the beginning of 1394 bus
cycles.
57
CYCLEOUT
O
Reproduces the 8kHz cycle clock of the cycle master.
62, 63, 64
TESTPIN
93
9.5 Other Pins
NAME AND FUNCTION
Power Down. When asserted (high), the AV Link goes into a low power mode and de-asserts the
LPS pin. When in this state, reads and writes to the registers are not allowed. The AV Link will
resume operation when PD is de-asserted (low), all register settings and configurations are
restored to their pre power down values.
These pins are reserved for factory testing. For normal operation they should be connected to
ground.
Test pins. These signals must be connected to ground.
NOTES:
Before asserting the RPL bit, SWPD or setting the PD pin high, the user should assure that the link chip is in the following state of operation:
1. The isochronous transmit FIFO is not receiving data for transmission
2. The isochronous transmitter is disabled
3. No asynchronous packets are being generated for transmission
4. Both the ASYNC request and response queues are empty
2000 Apr 15
7
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
10.0 RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
VCC
PARAMETER
CONDITIONS
DC supply voltage
VI
Input voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
IOL
UNIT
MIN.
MAX.
3.0
3.6
V
0
5
V
2.0
V
0.8
V
High-level output current
4
mA
Low-level output current
–4
mA
dT/dV
Input transition rise or fall time
0
20
ns/V
Tamb
Operating ambient temperature range
0
+70
°C
SCLK
System clock
49.147
49.157
MHz
AVCLK
AV interface clock
0
24
MHz
tr
Input rise time
10
ns
tf
input fall time
10
ns
11.0 ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V).
LIMITS
SYMBOL
VDD
PARAMETER
CONDITIONS
DC supply voltage
UNIT
MIN
MAX
–0.5
+4.6
V
–
–50
mA
–0.5
+5.5
V
–
±50
mA
–0.5
VDD +0.5
V
IIK
DC input diode current
VI
DC input voltage
IOK
DC output diode current
VO
DC output voltage
IO
DC output source or sink current
–
±50
mA
DC VCC or GND current
–
±150
mA
–60
150
°C
0
70
°C
0.6
W
IGND, ICC
Tstg
Storage temperature range
Tamb
Operating ambient temperature
Ptot
Power dissipation per package
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
2000 Apr 15
8
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
12.0 FUNCTIONAL DESCRIPTION
12.1 Overview
The PDI1394L41 is an IEEE1394–1995 and IEEE1394.a compliant link layer controller. It provides a direct interface between a 1394 bus and
various MPEG–2 and DVC codecs. The AV Link maps and unmaps AV data streams and similar data onto 1394 isochronous packets. Data can
be ciphered or deciphered according to the ‘5C’ standard method of content protection. The AV Link also provides an 8 bit or 16 bit wide host
interface for an attached microcontroller. Through the host interface port, the host controller can configure the AV layer for transmission or
reception of AV datastreams. The host interface port also allows the host controller to transmit and receive 1394 asynchronous data packets.
12.2 AV interface and AV layer
The AV interface and AV layer format “application packets” according to the IEC 61883 specification for isochronous transport over the 1394
network. The AV transmitter and receiver within the AV layer perform all the functions required to pack and unpack AV packet data for transfer
over a 1394 network. Once the AV layer is properly configured for operation, no further host controller service should be required. The operation
of the AV layer is full-duplex, i.e., the AV layer can receive and transmit AV packets on the same bus cycle.
12.2.1 IEC 61883 International Standard
The PDI1394L41 is specifically designed to support the IEC61883 International Standard of Digital Interface for Consumer Electronic
Audio/Video Equipment. The IEC specification defines a scheme for mapping various types of AV datastreams onto 1394 isochronous data
packets. The standard also defines a software protocol for managing isochronous connections in a 1394 bus called Connection Management
Protocol (CMP). It also provides a framework for transfer of functional commands, called Function Control Protocol (FCP).
12.2.2 CIP Headers
A feature of the IEC61883 International Standard is the definition of Common Isochronous Packet (CIP) headers. These CIP headers contain
information about the source and type of datastream mapped onto the isochronous packets.
The AV Layer supports the use of CIP headers. CIP headers are added to transmitted isochronous data packets at the AV data source. When
receiving isochronous data packets, the AV layer automatically analyzes their CIP headers. The analysis of the CIP headers determines the
method the AV layer uses to unpack the AV data from the isochronous data packets.
The information contained in the CIP headers is accessible via registers in the host interface.
(See IEC61883 International Standard of Digital Interface for Consumer Electronic Audio/Video Equipment for more details on CIP headers).
12.2.3 The AV Interface
The AV link’s 8-bit parallel interface is synchronous with AVxCLK, and was designed to interface with various MPEG-2 and DVC codecs. The
AV interface port buffer, if so programmed, can time stamp incoming AV packets. The AV packet data is stored in the embedded memory buffer,
along with its time stamp information. After the AV packet has been written into the AV layer, the AV layer creates an isochronous bus packet
with the appropriate CIP header. The bus packet along with the CIP header is transferred over the appropriate isochronous channel/packet.
The size and configuration of isochronous data packet payload transmitted is determined by the AV layer’s configuration registers accessible
through the host interface.
The AV interface port waits for the assertion for AVxVALID and AVxSYNC. AVxSYNC is aligned with the rising edge of AVxCLK and the first
byte of data on AVxDATA[7:0]. The duration of AVxSYNC is one AVxCLK cycle. AVxSYNC signals the AV layer that the transfer of an AV packet
has begun. At the time the AVxSYNC is asserted, the AV layer creates a new time stamp in the buffer memory. (This only happens if so
configured. The DVC format does not require these time stamps). The time stamp is then transmitted as part of the source packet header. This
allows the AV receiver to provide the AV packet for output at the appropriate time. Only one AVSYNC pulse is allowed per application packet; if
additional sync pulses are presented before the full packet is inputted, a new packet will be started and the previously inputted packet data will
be discarded (and not transmitted) in conjunction with the input error interrupt bit (INPERR, bit 3 of register 0x02C) being set to flag the error.
An additional synchronization mechanism is defined by the IEC 61883 specification, called frame sync. The frame synchronization signal
AVxFSYNC is time stamped and placed in the SYT field of the CIP header. The default delay value for the frame sync is 3 bus cycle times
(duration of 125 µs each) in the future, and is transmitted on the very next isochronous cycle regardless of available data. The PDI1394L41
allows this value to be programmable from 2 to 4 cycle times (see section 13.2.1). Additionally, for some audio applications, the SYT value can
be programmed to be appended only to isochronous cycles that have application data attached to them. This mode is enabled via the ‘mLAN’
bit (again, see section 13.2.1). When the mLAN mode is enabled, two additional cycle delays are automatically added to the SYT_DELAY value
(bits 6 and 5 of the ITXPKCLT register). On the receiver side, when the SYT stamp matches the cycle timer register, a pulse is generated on the
AVxFSYNC output. The timing for AVxFSYNC is independent of AVxCLK.
Some applications would like to create their own transmit timestamps independent of the AV Layer. On receive, these applications would like to
process the embedded time stamps instead of allowing the AV Layer to process these time stamps. This can be accommodated via the
ENXTMSTMP bit in the ITXPKCTL register for transmit and DIS_TSC bit in the IRXPKCTL register for receive. In conjunction with this mode,
additional means of flow control are enabled via the AVxREADY signal.
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Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
Port Dir
AVxREADY
Description
Transmit
Out
The L41 is prepared to receive a byte. The attached device will not assert AVVALID for any cycle in which
AVxRDY is false.
Receive
In
The attached device is prepared to receive a byte. The L41 will not assert AVxVALID for any cycle in which
AVxREADY is false.
When the AV port is configured as a receiver, the AVxSYNC signal will be asserted as soon as the PDI1394L41 AVx port has an application
packet available for delivery (independent of AVxREADY) and will remain asserted until the first byte of the application packet is clocked from
the AV port.
12.2.4 Content Protection
The AV Layer incorporates features to implement the Digital Transmission Copy Protection (DTCP) scheme that is specified by the Digital
Transmission Licensing Authority (DTLA). The DTCP specification consists of two primary functions: stream ciphering and authentication. Refer
to “5C Digital Transmission Content Protection Specification – Volume 1” for more details about the DTCP scheme.
On the AV Link stream ciphering is accomplished by internal 56 bit M6 content cipher and decipher blocks. To ease software development effort
and reduce the loading on the controlling processor, the link chip also includes a cryptographic accelerator capable of doing elliptic curve
multiplications and Sign and Verify operations.
Due to the size and number of operands for the M6 and cryptographic accelerator blocks, the host interface register set has been extended to
provide additional control and data registers. These extensions have been implemented via an indirect addressing mechanism. This mechanism
allows software written for previous versions of the AV Link (PDI1394L21 and PDI1394L11) to operate on the PDI1394L41. Note, however, that
some extensions to the interrupt registers were made to accommodate interrupts originating from the content protection block.
For a full description of the use of the L41’s content protection features please see data sheet addendum AL41–1. AL41–1 addendum can be
requested from Philips by DTLA licensees by e-mailing [email protected]. One paper copy of this addendum is available to each DTLA
licensee after verification of license status. Please see Section 2.1 of this data sheet for further information. DTLA license information is
available at DTCP.com.
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Preliminary specification
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PDI1394L41
12.2.5 mLAN Support
The AV transmitter has some additional features to support mLAN (IEC 61883-6). These are enabled by setting bit 30 of ITXPKCTL (0x020) to
logic 1. At the rising edge of AVxFSYNC, a SYT time stamp will be generated and written into the SYT queue of the isochronous transmitter.
This stamp will point to a time in the future dictated by the following formula:
SYT[15:12] = CYCTM[15:12] + programmed SYT_DELAY value + 2
SYT[11:0] = CYCTM[11:0]
The additional delay of two cycles is specific to this mLAN mode. The oldest SYT time stamp in the SYT queue will be sent first, but only when
accompanied by a data payload. Any pending SYT time stamp will be held until the next non-empty bus packet is sent. At the moment of
transmission, the SYT time stamp should at least point one cycle in the future. If it points to a time that is less than one cycle in the future, it will
be discarded.
The SYT queue in the isochronous transmitter can store 4 entries, the SYT queue in the isochronous receiver can store six entries. This
supports the case where an 8 kHz signal is applied to AVxFSYNC, and mLAN = 1, and SYT_Delay = 2. Assuming there is data on every cycle,
the receiver will receive an SYT time stamp each cycle with the first SYT time stamp pointing just less than six cycles in the future. When the
SYT queue in the isochronous receiver is full, then the most recently received SYT time stamp is overwritten with the next arriving SYT time
stamp.
12.2.6 SY – Sync Support
This feature supports the 1394 digital camera specification. The state of this pin will be reflected in the SY bit (ITXCTL register 0x034) and will
be transmitted along with the isochronous data block that was entered with it. The intended use of this pin is to signal the start of a new frame of
video in the isochronous header section of the data payload. Similarly, the isochronous receiver will assert the AVxSY pin simultaneously with
the first byte of the isochronous bus packet in which the SY value was received. NOTE: The SY functionality is only intended to be used when
the M6 cipher and de-cipher are not enabled.
AV DATA
AV SYNC
AV SY
SV01787
Figure 1. Behavior of sysncr
12.2.7 Programmable Buffer Memory
The PDI1394L41 maintains six distinct buffers that are highly configurable to optimize bandwidth capabilities. Buffers can be increased or
decreased from the default value by accessing the indirect address range of 0x100 through 0x1FC (INDADDR, 0x0F8). If the AV Layer is
configured to transmit or receive DVB compliant MPEG-2 type data, the default Isochronous (AV) buffer sizes are recommended. FIFO sizes
cannot be changed dynamically; after a FIFO size change, transmitters and receivers must be reset.
Buffers can be programmed with 64 quadlet (256 Byte) granularity. Minimum buffer size is 64 quadlets, maximum buffer size is limited to 11 kB.
The sum of all buffers cannot exceed 12K Bytes, or 3K Quadlets.
DEFAULT BUFFER SIZE
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BUFFER MEMORY
SIZE
(Quadlets)
Asynchronous Receive Response FIFO
256
Asynchronous Receive Request FIFO
256
Asynchronous Transmit Response FIFO
256
Asynchronous Transmit Request FIFO
256
Isochronous (AV) Transmit Buffer
1024
Isochronous (AV) Receive Buffer
1024
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Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
12.3 Bushold and Link/PHY single capacitor galvanic isolation
12.3.1 Bushold
The PDI1394L41 uses an internal bushold circuit on each of the indicated pins to keep these CMOS inputs from “floating” while being driven by
a 3-Stated device or input coupling capacitor. Unterminated high impedance inputs react to ambient electrical noise which cause internal
oscillation and excess power supply current draw.
The following pins have bushold circuitry enabled when the ISON pin is in the logic “1” state:
Name
PHY CTL0
PHY CTL1
PHY D0
PHY D1
PHY D2
PHY D3
PHY D4
PHY D5
PHY D6
PHY D7
Function
PHY control line 0
PHY control line 1
PHY data bus bit 0
PHY data bus bit 1
PHY data bus bit 2
PHY data bus bit 3
PHY data bus bit 4
PHY data bus bit 5
PHY data bus bit 6
PHY data bus bit 7
Philips bushold circuitry is designed to provide a high resistance pull-up or pull-down on the input pin. This high resistance is easily overcome
by the driving device when its state is switched. Figure 2 shows a typical bushold circuit applied to a CMOS input stage. Two weak MOS
transistors are connected to the input. An inverter is also connected to the input pin and supplies gate drive to both transistors. When the input
is LOW, the inverter output drives the lower MOS transistor and turns it on. This re-enforces the LOW on the input pin. If the logic device which
normally drives the input pin were to be 3-Stated, the input pin would remain “pulled-down” by the weak MOS transistor. If the driving logic
device drives the input pin HIGH, the inverter will turn the upper MOS transistor on, re-enforcing the HIGH on the input pin. If the driving logic
device is then 3-Stated, the upper MOS transistor will weakly hold the input pin HIGH.
The PHY’s outputs can be 3-Stated and single capacitor isolation can be used with the Link; both situations will allow the Link inputs to float.
With bushold circuitry enabled, these pins are provided with dc paths to ground, and power by means of the bushold transistors; this
arrangement keeps the inputs in known logical states.
INTERNAL
CIRCUITS
INPUT PIN
SV00911
Figure 2. Bushold circuit
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PDI1394L41
12.3.2 Single capacitor isolation
The circuit example (Figure 3) shows the connections required to implement basic single capacitor Link/PHY isolation.
NOTE: The isolation enablement pins on both devices are in their “1” states, activating the bushold circuits on each part. The bushold circuits
provide local dc ground references to each side of the isolating/coupling capacitors. Also note that ground isolation/signal-coupling must be
provided in the form of a parallel combination of resistance and capacitance as indicated in the IEEE 1394 standard.
APPLICATION/LINK
+3.3V
LINK
PDI1394L41
ISOLATED/PHY
+3.3V
ISON
SCLK
PHY D0
PHY D1
PHY D2
PHY D3
PHY D4
PHY D5
PHY D6
PHY D7
PHYCTL0
PHYCTL1
LREQ
LPS
Cc
Cc
Cc
Cc
Cc
Cc
Cc
Cc
Cc
Cc
Cc
Cc
CL
LINKON
APPLICATION AND LINK GROUND
ISO–
SYSCLK
PHY
D0
PDI1394P2x
D1
D2
D3
D4
D5
D6
D7
PHYCTL0
PHYCTL1
LREQ
LPS
LINKON
LINK
3.3V
PHY
3.3V
CL
13K
ISOLATED PHY GROUND
VALUES OF THESE RESISTORS DEPEND
ON PHY USED. SEE PHY DATASHEET.
9.1K
ALSO SEE APPLICATION NOTE AN2452
FOR MORE DETAILS
Cc
1MEG Ω
Cr
CC = 1 nF; Cr = 100 nF; CL = 3.3nF
SV01816
Figure 3. Single capacitor Link/PHY isolation
12.4 Power Management
The PDI1394L41 implements several features for power management as noted in the P1394a draft 5.0. These features include:
1. Reset of the Phy/Link interface by setting the RPL bit in the LNKCTL register.
2. Disable of the Phy/Link interface caused by either setting the SWPD bit in the RDI register –OR– asserting (high) the PD pin.
3. Initialization of the Phy/Link interface after it was disabled or reset.
The application can power up the Phy/Link interface by deasserting the PD pin –OR– clearing (low) the SWPD in the RDI register. This will
cause the L41 to produce a pulsing signal on the LPS pin. When the L41 is in power down mode, reads and writes to the host interface will be
restricted to those addressing only the RDI register (0x0B0). Please see Section 13.3.11 for further details.
There are 3 ways to power up the L41. (1) When the application wants the 1394 node to resume operation, it simply needs to de–assert the PD
pin, or (2) clear the SWPD bit in the RDI register. The link can also be awakened by another bus node sending a link–on packet to the PHY of
the application’s node. (3) The attached PHY will activate its LinkOn line and the L41 will see the signal and set the LOA bit of the RDI register
(assuming that the ELOA bit is in its enabled, ”1”, state). The L41 will generate an interrupt of the host processor. It will then be up to the host
processor to decide whether to honor the link–on request of the other node. Then the host processor will de–assert the PD pin –OR– clear the
SWPD bit in the RDI register. This activity will power up the L41 causing it to send the pulsing signal out on the LPS pin which notifies the
PHYchip of link activity and allows the PHY to discontinue directing the link on signal to the L41. Subsequently, the host processor must
acknowledge the LOA interrupt by writing a ”1” to the LOA bit position in the RDI register after the link on signal from the PHY has stopped.
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PDI1394L41
12.5 The host interface
The host interface allows an 8 bit or 16 bit CPU to access all registers and the asynchronous packet queues. It is designed to be easy to use
with a wide range of processors, including 8051, MIPS1900, ST20, PowerPC etc. The host interface can work with 8 bit or 16 bit wide data
paths, and offers multiplexed or non-multiplexed access. There are 64 register addresses (for quadlet wide registers). To access bytes rather
than quadlets the address space is 256 bytes, requiring 8 address lines.
The use of an 8 bit or 16 bit interface introduces an inherent problem that must be solved: register fields can be more than 8 bits wide and be
used (control) or changed (status) at every internal clock tick. If such a field is accessed through an 8 bit or 16 bit interface it requires more than
one read or write cycle, and the value should not change in between to maintain consistency. To overcome this problem accesses to the chip’s
internal register space are always 32 bits, and the host interface must act as a converter between the internal 32 bit accesses and external 8 bit
or 16 bit accesses. This is where the shadow register (0x0F4) is used.
12.5.1 Read accesses
To read an internal register the host interface can make a snapshot (copy) of that specific register which is then made available to the CPU 8 or
16 bits at a time. The register that holds the snapshot copy of the real register value inside the host interface is called the shadow register.
During an 8-bit read cycle address lines HIF A0 and HIF A1 are used to select which of the 4 bytes currently stored in the shadow register is
output onto the CPU data bus. This selection is done by combinatorial logic only, enabling external hardware to toggle these lines through
values 0 to 3 while keeping the chip in a read access mode to get all 4 bytes out very fast (in a single extended read cycle), for example into an
external quadlet register. During a 16 bit read cycle address line HIF A1 is used to select which pair of 4 bytes currently stored in the shadow
register is output to the CPU bus. Again the selection is by combinatorial logic, enabling external hardware to toggle HIF A1 while keeping the
chip in read access mode to get both words very quickly.
This solution requires a control line to direct the host interface to make a snapshot of an internal register when needed, as well as the internal
address of the target register. The register address is connected to input address lines HIF A2..HIF A7, and the update control line to input
address line HIF A8. To let the host interface take a new snapshot the target address must be presented on HIF A2..HIF A7 and HIF A8 must be
raised while executing a read access. The new value will be stored in the shadow register and the selected byte (HIF A0, HIF A1, 8 bit mode)
or word (HIF A1, 16 bit mode) appears on the output.
Not all registers can be accessed in Direct Address Space. Some of the registers are in an indirect address space, these registers control the
FIFO size and content protection system. The correct internal register space has to be selected through the host interface, using directly
addressable registers INDADDR (0x0F8) and INDDATA (0x0FC).
TR
8/16
CPU
MUX
32
SHADOW REGISTER
MUX
Q
32
Q
REGISTERS
HIF A0..1 (8 BIT MODE)
HIF A1 (16 BIT MODE)
32
HIF A2..7
HIF A8
UPDATE/COPY CONTROL
SV01034
NOTES:
1. It is not required to read all 4 bytes of a register before reading another register. For example, in 8 bit mode, if only byte 2 of register 0x54 is
required a read of byte address 0x100 + (0×54) + 2 = 0x156 is sufficient.
2. The update control line does not necessarily have to be connected to the CPU address line HIF A8. This input could also be controlled by
other means, for example a combinatorial circuit that activates the update control line whenever a read access is done for byte 0. This
makes the internal updating automatic for quadlet reading.
3. Reading the bytes of the shadow register can be done in any order and as often as needed.
4. It is possible to read/modify/write a register using the shadow register (0x0F4) without rewriting all 4 bytes. For example, to modify an enable
bit in the fourth byte of the Asynchronous Interrupt Enable (0x0A4), a read of location 0x100+0x0A0+3=0x1A3, followed by a write of the
modified byte to the same location 0x100+0x0A0+3=0x1A3 is sufficient. The other bytes remain unchanged.
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1394 content protection AV link layer controller
PDI1394L41
12.5.2 Write accesses
To write to an internal register the host interface must collect the 4 byte values (8 bit mode) or 2 word values (16 bit mode) into a 32 bit value
and then write the result to the target register in a single clock tick. This requires a register to hold the 32 bit value being compiled until it is
ready to be written to the actual target register. This temporary register inside the host interface is called the shadow register. In 8 bit mode,
address lines HIF A0 and HIF A1 are used to select which of the 4 bytes of the shadow register is to be written with the value on the CPU data
bus. In 16 bit mode, HIF A1 is used to select which half of the shadow register is to be written with the value on the CPU data bus. Only one
byte (8 bit mode) or one word (16 bit mode) can be written in a single write access cycle.
Not all registers can be accessed in Direct Address Space. Some of the registers are in an indirect address space, these registers control the
FIFO size and content protection system. The correct internal register space has to be selected through the host interface, using directly
addressable registers INDADDR (0x0F8) and INDDATA (0x0FC).
TR
MUX
8/16
CPU
SHADOW REGISTER
MUX
Q
32
Q
REGISTERS
HIF A0..1 (8 BIT MODE)
HIF A1 (16 BIT MODE)
32
HIF A2..7
HIF A8
UPDATE/COPY CONTROL
SV01035
NOTES:
1. It is not required to write all 4 bytes, or both words of a register: those bytes that are either reserved (undefined) or don’t care do not have
to be written in which case they will be assigned the value that was left in the corresponding byte of the shadow register from a previous
write access. For example, to acknowledge an interrupt for the isochronous receiver in 8 bit mode, a single byte write to location
0x100+(0x4C)+3 = 0x14F is sufficient. The value 256 represents setting HIF A8=1. The host interface cannot directly access the FIFOs, but
instead reads from/writes into a transfer register (shown as TR in the Figures above). Data is moved between FIFO and TR by internal logic
as soon as possible without CPU intervention.
2. The update control line does not necessarily have to be connected to the CPU address line HIF A8. This input could also be controlled by
other means, for example a combinatorial circuit that activates the update control line whenever a write access is done for byte 3 or the
upper 16 bits. This makes the internal updating automatic for quadlet writing.
3. Writing the bytes or words of the shadow register can be done in any order and as often as needed (new writes simply overwrite the old
value).
4. It is now possible to read/modify/write a register using the shadow register (0x0F4) without rewriting all 4 bytes. For example, to modify an
enable bit in the fourth byte of the Asynchronous Interrupt Enable (0x0A4), a read of location 0x100+0x0A0+3=0x1A3, followed by a write of
the modified byte to the same location 0x100+0x0A0+3=0x1A3 is sufficient. The other bytes remain unchanged.
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Preliminary specification
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PDI1394L41
12.5.3 Big and little endianness, data invariance, and data bus width
The host interface offers programmable endianness, data invariance, and selectable 8 and 16 bit data widths. LTLEND (pin 121) and DATINV
(pin 122) are multiplexed configuration pins that will be sampled on the trailing edge of RESET; the states of these pins are established by
connecting each pin to the proper logic state, ground or VDD, through a resistor, 22 kΩ is recommended. To verify the configuration, the shadow
register (0x0F4) will be preset to a value of 0x0F0A0500 after a power reset. Table 1 describes the configurations.
Table 1. Configuration possible combinations
LTLEND (Little Endian)
DATINV (Data Invariant)
HIF 16BIT
1
1
See Table 2
Result
1
0
1
Bytes are swapped within the word
0
X
1
16-bit data bus, address as in PDI1394L21
0
X
0
8-bit data bus, address as in PDI1394L21
Byte/Word address is reversed
Table 2. Explanation of the mode LittleEnd = 1, DataInvariant = 1
HIF16 = 0
Outside Address (A1, A0)
HIF16 = 1
Inside Address (A1, A0)
Outside Address (A1, A0)
Inside Address (A1, A0)
00
11
0X
1X
01
10
0X
1X
10
01
1X
0X
11
00
1X
0X
It is important to note that some operands in the indirect address space consist of more than one quadlet. For these operands, the lowest
address always contains the most significant quadlet.
In Bit Endian mode and DATAINV = 0, the bytes in each quadlet are numbered 0..3 from left (most significant) to right (least significant) as
shwon in Figure 4.
To access a register in 8 bit HIF mode, at address N the CPU should use addresses E:
E = N ; to access the upper 8 bits of the register.
E = N + 1 ; to access the upper middle 8 bits of the register.
E = N + 2 ; to access the lower middle 8 bits of the register.
E = N + 3 ; to access the lower 8 bits of the register.
To access a register in 16 bit HIF mode, at internal address N, the CPU should use addresses E:
E = N ;to access the upper 16 bits of the register
E = N + 2 ;to access the lower 16 bits of the register
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYTE 0
BYTE 1
BYTE 2
BYTE 3
SV00656
Figure 4. Byte order in quadlets as implemented in the host interface, HIF LTLEND = LOW
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PDI1394L41
In Little Endian mode and DATAINV = 0, the bytes in each quadlet are numbered 3. .0 from the left (most significant) to right (least significant)
as shown in Figure 5. To access a register in 8 bit HIF mode, at address N the CPU should use addresses E:
E = N + 3 ;to access the upper 8 bits of the register
E = N + 2 ;to access the upper middle 8 bits of the register
E = N + 1 ;to access the lower middle 8 bits of the register
E = N ;to access the lower 8 bits of the register
To access a register in 16 bit HIF mode, at internal address N, the CPU should used addresses E:
E = N ;to access the lower 16 bits of the register
E = N + 2 ;to access the upper 16 bits of the register
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYTE 3
BYTE 2
BYTE 1
BYTE 0
SV01079
Figure 5. Byte order in quadlets as implemented in the host interface, HIF LTLEND = HIGH
12.5.4 Accessing the asynchronous packet queues
Although entire incoming packets are stored in the receiver buffer memory they are not randomly accessible. These buffers act like FIFOs and
only the frontmost (oldest) data quadlet entry is accessible for reading. Therefore only one location (register address) is allocated to each of the
two receiver queues. Reading this location returns the head entry of the queue, and at the same time removes it from the queue, making the
next stored data quadlet accessible.
With the current host interface such a read is in fact a move operation of the data quadlet from the queue to the shadow register. Once the data
is copied into the shadow register it is no longer available in the queue itself so the CPU should always read all 4 bytes, or both words, before
attempting any other read access (be careful with interrupt handlers for the PDI1394L41!).
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PDI1394L41
12.5.5 The CPU bus interface signals
The CPU interface is directly compatible with a wide range of microcontrollers, and supports both multiplexed and non-multiplex access. It uses
separate HIF RDN, HIF WRN, HIF ALE, and HIF CSN chip select lines. There are 9 address inputs (HIF A0..HIF A8) and 8 or 16 data in/out
lines HIF D[7:0] or HIF D [15:0]. The upper 8 bits of the data in/out lines are only used when the 8/16 bit mode pin (HIF16BIT) is held HIGH.
The CPU is not required to run a clock that is synchronous to the 1394 base clock. The control signals will be resampled by the host interface
before being used internally.
In non-multiplex mode (HIF MUX = LOW), an access through the host interface starts when HIF CSN = 0 and either HIF WRN = 0 or HIF RDN = 0.
Typically the chip select signal is derived from the upper address lines of the CPU (address decode stage), but it could also be connected to a
port pin of the CPU to avoid the need for an external address decoder in very simple CPU systems. When both HIF CSN = 0 and HIF RDN = 0
the host interface will start a read access cycle, so the cycle is triggered at the falling edge of either HIF CSN or HIF RDN, whichever is later.
In multiplex mode (HIF MUX = HIGH), an access through the host interface starts when HIF CSN = 0 and either HIF WRN = 0 or HIF RD_N = 0.
The address must now be presented on the HIF AD [7:0] lines, and will be latched on the falling edge of ALE. If HIF RDN = 0, data will be
offered after the falling edge of ALE. If HIF WRN = 0, data has to be presented by the microcontroller.
In both multiplexed and non-multiplexed mode, HIF WAIT can be used to signal to the controlling CPU that an extension of the current access
cycle is needed. This allows the PDI1394L41 to work in the same address space as peripherals with a shorter access time. HIF WAIT will
remain HIGH for the minimum duration of the access cycle. If HIF A[8] is HIGH, HIF WAIT will extend the access cycle to 120ns to allow for the
shadow register transfer to take place. Subsequent access to the same register which does not required A[8] to be raised, can be executed
much faster. By connecting HIF WAIT to the appropriate input on the controlling processor, the PDI1394L41 can be mapped in memory space
with faster devices. The PDI1394L41 should not be mapped in memory space with devices that require access faster than 15 ns.
HIF A[7:0] can be used as a simple demultiplexer. In multiplex mode, the address on AD[7:0] will appear on A[7:0] immediately, and will remain
there until the next rising edge of HIF ALE.
HIF CS_N
HIF RD_N
HIF WR_N
HIF A8
HIFA7–A0
HIFD15–D8
HIFAD7–AD0
HIF_WAIT
HIF_MUX
HIF16BIT
NOTE: ALE line is held LOW.
An extended read cycle may be implemented by holding CS_N and RD_N low (active)
and changing only the A7–A0 address. After each new address stabilizes, wait at least
tACC and read the data. The extended read cycle can be used only following a read of
the first byte of the shadow register using the A8 transfer mechanism. See the section
on Read Accesses (12.5.1).
SV01088
Figure 6. 16 Bit Read Cycle Non-multiplexed
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HIF CS_N
HIF RD_N
HIF WR_N
HIFA7–A0
HIFD15–D8
HIFAD7–AD0
A8
HIF_WAIT
HIF_MUX
HIF16BIT
NOTE: ALE line is held LOW.
SV01089
Figure 7. 16 Bit Write Cycle Non-multiplexed
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HIF CS_N
HIF ALE
AD7–AD0
ADDR
DATA
ADDR
LATCHED
A7–A0
HIFD15–D8
DATA
LATCHED
DATA
DATA
A8
HIF RD_N
HIF WR_N
HIF_WAIT
HIF_MUX
HIF16BIT
Note: Second write cycle elongated by WAIT signal.
SV01090
Figure 8. 16 Bit Write Cycle Multiplexed
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HIF CS_N
HIF ALE
HIF AD7–AD0
HIF A7–A0
ADDR
DA
TA
ADDR
LATCHED
TA
LATCHED
DATA
HIFD15–D8
DA
DATA
A8
HIF RD_N
HIF WR_N
HIF_WAIT
HIF_MUX
HIF16BIT
SV01091
Figure 9. 16 Bit Read Cycle Multiplexed
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HIF CS_N
HIF ALE
AD7–AD0
A7–A0
ADDR
DATA
ADDR
LATCHED
DATA
LATCHED
A8
HIF RD_N
HIF WR_N
HIF_WAIT
HIF_MUX
HIF16BIT
SV01772
Figure 10. 8 Bit Write Cycle Multiplexed
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HIF CS_N
HIF ALE
HIF AD7–AD0
HIF A7–A0
ADDR
DA
TA
ADDR
LATCHED
DA
TA
LATCHED
A8
HIF RD_N
HIF WR_N
HIF_WAIT
HIF_MUX
HIF16BIT
SV01773
Figure 11. 8 Bit Read Cycle Multiplexed
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HIF CS_N
HIF RD_N
HIF WR_N
HIFA7–A0
HIFAD7–AD0
A8
HIF_WAIT
HIF_MUX
HIF16BIT
NOTE: ALE line is held LOW.
SV01774
Figure 12. 8 Bit Write Cycle Non-multiplexed
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HIF CS_N
HIF RD_N
HIF WR_N
HIF A8
HIFA7–A0
HIFAD7–AD0
HIF_WAIT
HIF_MUX
HIF16BIT
NOTE: ALE line is held LOW.
SV01775
Figure 13. 8 Bit Read Cycle Non-multiplexed
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12.6 The Asynchronous Packet Interface
The PDI1394L41 provides an interface to asynchronous data packets through the registers in the host interface. The format of the
asynchronous packets is specified in the following sections.
12.6.1 Reading an Asynchronous Packet
Upon reception of a packet, the packet data is stored in the appropriate receive FIFO, either the Request or Response FIFO. The location of the
packet is indicated by either the RREQQQAV or RRSPQAV status bit being set in the Asynchronous Interrupt Acknowledge (ASYINTACK)
register. The packet is transferred out of the FIFO by successive reads of the Asynchronous Receive Request (RREQ) or Asynchronous
Receive Response (RRSP) register. The end of the packet (the last quadlet) is indicated by either the RREQQLASTQ or RRSPQLASTQ bit set
in ASYINTACK. Attempting to read the FIFO when either RREQQQAV bit or RRSPQQAV bit is set to 0 (in the Asynchronous RX/TX interrupt
acknowledge, ASYINTACK, register) will result in a queue read error.
12.6.2 Link Packet Data Formats
The data formats for transmission and reception of data are shown below. The transmit format describes the expected organization for data
presented to the link at the asynchronous transmit, physical response, or isochronous transmit FIFO interfaces.
12.6.2.1 Asynchronous Transmit Packet Formats
These sections describe the formats in which packets need to be delivered to the queues (FIFOs) for transmission. There are four basic formats
as follows:
ITEM
FORMAT
1
No packet data
No-packet
2
Quadlet packet
3
4
Block Packet
Unformatted transmit
USAGE
TRANSACTION CODE
(tCode)
Quadlet read requests
4
Quadlet/block write responses
2
Quadlet write requests
0
Quadlet read responses
6
Block read requests
5
Block write requests
1
Block read responses
7
Lock requests
9
Lock responses
Bhex
Asynchronous streams
Ahex
Concatenated self-ID / PHY packets
Ehex
Each packet format uses several fields (see names and descriptions below). More information about these fields (not the format) can be found
in the 1394 specification. Grey fields are reserved and should be set to zero values.
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Table 1. Asynchronous Transmit Fields
Field Name
Description
spd
This field indicates the speed at which this packet is to be sent. 00=100 Mbs, 01=200 Mbs, and 10=400 Mbs.
11 = undefined
tLabel
This field is the transaction label, which is used to pair up a response packet with its corresponding request packet.
tLabels are also used as identifiers to associate a Link data confirmation (see 12.6.2.13) with the corresponding
request, response, or asynchronous stream packet.
rt
Only value 01 = retryX is supported.
tCode
The transaction code for this packet.
DestinationID
Contains a node ID value.
DestinationOffsetHigh
DestinationOffsetLow
The concatenation of these two field addresses a quadlet in the destination node’s address space.
rCode
Response code for write response packet.
rCode
Meaning
0
Node successfully completed requested operation.
1–3
Reserved
4
Resource conflict detected by responding agent. Request may be retried.
5
Hardware error. Data not available.
6
Field within request packet header contains unsupported or invalid value.
7
Address location within specified node not accessible.
8–Fh
Reserved
channel
A channel allocated from the isochronous manager register CHANNELS_AVAILABLE.
tag
sy
Used only for Asynchronous stream transmit fields.
fields Values supplied,
supplied as appropriate
appropriate, by the user
user.
priority
For responses, priority is set to 0000 if fair arbitration is to be used and to 0001 if priority arbitration is to be used, as
allowed by the 1394a supplement to Std IEEE 1394–1995.
Quadlet data
For quadlet write requests and quadlet read responses, this field holds the data to be transferred.
Data length
The number of bytes requested in a block read request.
dataLength
The number of bytes of data to be transmitted in this packet
extendedTcode
The tCode indicates a lock transaction, this specifies the actual lock action to be performed with the data in this
packet.
block data
The data to be sent. If dataLength=0, no data should be written into the FIFO for this field. Regardless of the
destination or source alignment of the data, the first byte of the block must appear in the high order byte of the first
quadlet.
padding
If the dataLength mod 4 is not zero, then zero-value bytes are added onto the end of the packet to guarantee that a
whole number of quadlets is sent.
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12.6.2.2 No-data Transmit
The no-data transmit formats are shown in Figures 14 and 15. The first quadlet contains packet control information. The second and third
quadlets contain 16-bit destination ID and either the 48-bit, quadlet aligned destination offset (for requests) or the response code (for
responses).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 spd
tLabel
destinationID
rt
tCode
priority
destinationOffsetHigh
destinationOffsetLow
SV01080
Figure 14. Quadlet Read Request Transmit Format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 spd
destinationID
tLabel
rt
tCode
priority
rCode
SV01081
Figure 15. Quadlet/Block Write Response Packet Transmit Format
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12.6.2.3 Quadlet Transmit
Three quadlet transmit formats are shown below. In these figures: The first quadlet contains packet control information. The second and third
quadlets contain 16-bit destination ID and either the 48-bit quadlet-aligned destination offset (for requests) or the response code (for responses).
The fourth quadlet contains the quadlet data for read response and write quadlet request formats, or the upper 16 bits contain the data length
for the block read request format.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 spd
tLabel
destinationID
rt
tCode
priority
destinationOffsetHigh
destinationOffsetLow
quadlet data
SV01082
Figure 16. Quadlet Write Request Transmit Format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 spd
destinationID
tLabel
rt
tCode
priority
rCode
quadlet data
SV01083
Figure 17. Quadlet Read Response Transmit Format
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 spd
tLabel
destinationID
rt
tCode
priority
destinationOffsetHigh
destinationOffsetLow
data length
SV01084
Figure 18. Block Read Request Transmit Format
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12.6.2.4 Block Transmit
The block transmit format is shown below, this is the generic format for reads and writes. The first quadlet contains packet control information.
The second and third quadlets contain the 16-bit destination node ID and either the 48-bit destination offset (for requests) or the response code
and reserved data (for responses). The fourth quadlet contains the length of the data field and the extended transaction code (all zeros except
for lock transaction). The block data, if any, follows the extended transaction code.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 spd
tLabel
destinationID
rt
tCode
priority
destinationOffsetHigh
destinationOffsetLow
dataLength
extendedTcode
Block data
padding (if needed)
SV01085
Figure 19. Block Packet Transmit Format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 spd
destinationID
tLabel
rt
tCode
priority
rCode
dataLength
extendedTcode
Block data
padding (if needed)
SV01086
Figure 20. Block Read or Lock Response Transmit Format
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12.6.2.5 Unformatted Transmit
The unformatted transmit format is shown in Figure 21. The first quadlet contains packet control information. The remaining quadlets contain
data that is transmitted without any formatting on the bus. No CRC is appended on the packet, nor is any data in the first quadlet sent. This is
used to send PHY configuration and Link-on packets. Note that the bit-inverted check quadlet must be included in the FIFO since the AV Link
core will not generate it.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
spd
tLabel
00
1110
priority
unformatted packet data
SV01087
Figure 21. Unformatted Transmit Format
12.6.2.6 Asynchronous Stream Transmit
The PDI1394L41 supports asynchronous stream as specified in IEEE1394.a. The asynchronous stream packet format is shown below. The first
quadlet contains packet control information. The second quadlet contains datalength, tag, channel number, and synchronization code. The third
quadlet contains the datalength in quadlets. The datalength can be zero for empty asynchronous stream packets.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
spd
dataLength
tLabel
tag
channel
1
1110
priority
1010
sy
Block data
padding (if needed)
SV01050
Figure 22. Asynchronous Stream Packet Transmit Format
When a packet conforming to this format is written to either asynchronous transmit FIFO, an asynchronous stream packet (identical on the
cable to an isochronous packet) will be transmitted during the asynchronous phase of a bus cycle.
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12.6.2.7 Asynchronous Receive Packet Formats
This section describes the asynchronous receive packet formats. Four basic asynchronous data packet formats and one confirmation format exist:
Table 2. Asynchronous Data Packet Formats
ITEM
FORMAT
1
No packet data
No-packet
2
Quadlet packet
3
Block Packet
USAGE
TRANSACTION CODE
Quadlet read requests
4
Quadlet/block write responses
2
Quadlet write requests
0
Quadlet read responses
6
Block read requests
5
Block write requests
1
Block read responses
7
Lock requests
9
Lock responses
Bhex
4
Self-ID / PHY packet
Concatenated self-ID / PHY packets
Ehex
5
Confirmation packet
Confirmation of packet transmission
8
Each packet format uses several fields. More information about most of these fields can be found in the 1394 specification.
Table 3. Asynchronous Receive Fields
Field Name
Description
destinationID
This field is the concatenation of busNumbers (or all ones for “local bus”) and nodeNumbers (or all ones for
broadcast) for this node.
tLabel
This field is the transaction label, which is used to pair up a response packet with its corresponding request packet.
tLables are also used as identifiers to associate a Link data confirmation (see 12.6.2.13) with the corresponding
request, response, or asynchronous stream packet.
rt
The retry code of the received packet; see the 1394 specification.
tCode
The transaction code for this packet.
priority
The priority level for this packet (0000 for cable environment).
sourceID
This is the node ID of the sender of this packet.
destinationOffsetHigh,
destinationOffsetLow
The concatenation of these two field addresses a quadlet in this node’s address space.
rCode
Response code for the received packet; see the 1394 specification.
quadlet data
For quadlet write requests and quadlet read responses, this field holds the data received.
dataLength
The number of bytes of data to be received in a block packet.
extendedTcode
If the tCode indicates a lock transaction, this specifies the actual lock action to be performed with the data in this
packet.
block data
The data received. If dataLength=0, no data will be written into the FIFO for this field. Regardless of the destination
or source alignment of the data, the first byte of the block will appear in the high order byte of the first quadlet.
padding
If the dataLength mod 4 is not zero, then zero-value bytes are added onto the end of the packet to guarantee that a
whole number of quadlets is sent.
u
Unsolicited response tag bit. This bit is set to one (1) if the received response was unsolicited.
ackSent
This field contains the acknowledge code that the link layer returned to the sender of the received packet. For
packets that do not need to be acknowledged (such as broadcasts) the field contains the acknowledge value that
would have been sent if an acknowledge had been required. The values for this field are listed in Table 4 (they also
can be found in the IEEE 1394 standard).
status
This field is used for asynchronous streams.
0000
Reserved.
0001
packet OK.
0010–1100
Reserved.
1101
Data CRC error and/or block size mismatch have been detected.
1110–1111
Reserved.
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Table 4. Acknowledge codes
Code
Name
Description
0001
ack_complete
The node has successfully accepted the packet. If the packet was a request subaction, the
destination node has successfully completed the transaction and no response subaction shall follow.
0010
ack_pending
The node has successfully accepted the packet. If the packet was a request subaction, a response
subaction will follow at a later time. This code shall not be returned for a response subaction.
0100
ack_busy_X
The packet could not be accepted. The destination transaction layer may accept the packet on a
retry of the subaction.
0101
ack_busy_A
The packet could not be accepted. The destination transaction layer will accept the packet when the
node is not busy during the next occurrence of retry phase A.
0110
ack_busy_B
The packet could not be accepted. The destination transaction layer will accept the packet when the
node is not busy during the next occurrence of retry phase B.
1101
ack_data_error
The node could not accept the block packet because the data field failed the CRC check, or because
the length of the data block payload did not match the length contained in the dataLength field. This
code shall not be returned for any packet that does not have a data block payload.
1110
ack_type_error
A field in the request packet header was set to an unsupported or incorrect value, or an invalid
transaction was attempted (e.g., a write to a read-only address).
reserved
This revision of the AV Link will not generate other acknowledge codes, but may receive them from
newer (1394 A) links. In that case, these new values will show up here.
0000, 0011,
0111 – 1100,
and 1111
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12.6.2.8 No-data Receive
The no-data receive formats are shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second
and third quadlet contain 16-bit source ID and either the 48-bit, quadlet-aligned destination offset (for requests) or the response code (for
responses). The last quadlet contains packet reception status.
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
destinationID
tLabel
rt
tCode
priority
destinationOffsetHigh
sourceID
destinationOffsetLow
spd
ackSent
SV00257
Figure 23. Quadlet Read Request Receive Format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
destinationID
tLabel
sourceID
rt
tCode
priority
rCode
spd
u
ackSent
SV00258
Figure 24. Write Response Receive Format
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12.6.2.9 Quadlet Receive
The quadlet receive formats are shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second
and third quadlets contain 16-bit source ID and either the 48-bit, quadlet-aligned destination offset (for requests) or the response code (for
responses). The fourth quadlet is the quadlet data for read responses and write quadlet requests, and is the data length and reserved for block
read requests. The last quadlet contains packet reception status.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
destinationID
tLabel
sourceID
rt
tCode
priority
destinationOffsetHigh
destinationOffsetLow
quadlet data
spd
ackSent
SV00259
Figure 25. Quadlet Write Request Receive Format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
destinationID
tLabel
sourceID
rt
tCode
priority
rCode
quadlet data
spd
u
ackSent
SV00260
Figure 26. Quadlet Read Response Receive Format
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
destinationID
tLabel
sourceID
rt
tCode
priority
destinationOffsetHigh
destinationOffsetLow
data length
spd
ackSent
SV00261
Figure 27. Block Read Request Receive Format
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12.6.2.10 Block receive
The block receive format is shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second and
third quadlets contain 16-bit sourceID and either the 48-bit destination offset (for requests) or the response code and reserved data (for
responses). The fourth quadlet contains the length of the data field and the extended transaction code (all zeros except for lock transactions).
The block data, if any, follows the extended code. The last quadlet contains packet reception status.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
destinationID
tLabel
rt
tCode
priority
destinationOffsetHigh
sourceID
destinationOffsetLow
dataLength
extendedTcode
Block data
padding (if needed)
spd
ackSent
SV00262
Figure 28. Block Write or Lock Request Receive Format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
destinationID
tLabel
sourceID
rt
tCode
priority
rCode
dataLength
extendedTcode
Block data
padding (if needed)
spd
u
ackSent
SV00263
Figure 29. Block Read or Lock Response Receive Format
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12.6.2.11 Asynchronous Stream Receive
The Asynchronous streaming receive packet format is shown below. The first quadlet contains dataLength, tag, and Channel number for source
identification, and synchronization information. The following quadlets contain (possibly zero) quadlets of block information. The last quadlet
contains transmission speed and status information. Asynchronous stream packets are placed in the Receive Response FIFO.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
dataLength
tag
chanNum
10102
sy
Block data (possibly zero)
spd
status
SV01052
12.6.2.12 Self-ID and PHY packets receive
The self-ID and PHY packet receive formats are shown below. The first quadlet contains a synthesized packet header with a tCode of 0xE
(hex). For self-ID information, the remaining quadlets contain data that is received from the time a bus reset ends to the first subaction gap. This
is the concatenation of all the self-ID packets received. Note that the bit-inverted check quadlet is included in the Read Request FIFO and the
application must check it.
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11102
00002
self ID packet data
00
ackSent
SV00264
Figure 30. Self-ID Receive Format
The “ackSent” field will either be “ACK_DATA_ERROR” if a non-quadlet-aligned packet is received or there was a data overrun, or
“ACK_COMPLETE” if the entire string of self-ID packets was received.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11102
00002
PHY packet first quadlet
SV00265
Figure 31. PHY Packet Receive Format
For PHY packets, there is a single following quadlet which is the first quadlet of the PHY packet. The check quadlet has already been verified
and is not included.
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12.6.2.13 Link data confirmation formats
After a request, response, or asynchronous stream packet is transmitted, the asynchronous transmitter assembles a Link data confirmation (see
Figure 32) which is used to confirm the transmission to the higher layers. Packets transmitted from the Transmit Request FIFO are confirmed by
a confirmation written into the Receive Request FIFO and packets transmitted from the Transmit Response FIFO are confirmed by a
confirmation written into the Receive Response FIFO.
Outgoing packets and their confirmations are associated by their tLabels. It is the user’s responsibility to assure the uniqueness of active
tLabels.
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
tLabel
01
1000
conf
SV01051
Figure 32. Request and response confirmation format
Table 5. Confirmation codes
CODE1
DESCRIPTION
0
Non-broadcast packet transmitted; addressed node returned no acknowledge (transaction complete).
1
Broadcast packet transmitted or non-broadcast packet transmitted; addressed node returned an acknowledge complete
(transaction complete).
2
Non-broadcast packet transmitted; addressed node returned an acknowledge pending.
4
Retry limit exceeded; destination node hasn’t accepted the non-broadcast packet within the maximum number of retries
(transaction complete).
D16
Acknowledge data error received (transaction complete).
E16
Acknowledge type error received (transaction complete).
NOTE:
1. All other codes are reserved.
12.7 Interrupts
The PDI1394L41 provides a single interrupt line (HIF INTN) for connection to a host controller. Status indications from four major areas of the
device are collected and ORed together to activate HIF INTN. Status from four major areas of the device are collected in four status registers;
LNKPHYINTACK, ITXINTACK, IRXINTACK, and ASYINTACK. At this level, each individual status can be enabled to generate a chip-level
interrupt by activating HIF INTN. To aid in determining the source of a chip-level interrupt, the major area of the device generating an interrupt is
indicated in the lower 4 bits of the GLOBCSR register. These bits are non-latching Read-Only status bits and do not need to be acknowledged.
To acknowledge and clear a standing interrupt, the bit in LNKPHYINTACK, ITXINTACK, IRXINTACK, or ASYINTACK causing the interrupt
status has to be written to a logic ‘1’; Note: Writing a value of ‘0’ to the bit has no effect.
12.7.1 Determining and Clearing Interrupts
When responding to an interrupt event generated by the PDI1394L41, or operating in polled mode, the first register examined is the GLOBCSR
register. The least significant nibble contains interrupt status bits from general sections of the device; the link layer controller, the AV transmitter,
the AV receiver, and the asynchronous transceiver. The bits in GLOBCSR[3:0] are self clearing status bits. They represent the logical OR of all
the enabled interrupt status bits in their section of the AV Link Layer Controller.
Once an interrupt, or status is detected in GLOBCSR, the appropriate interrupt status register needs to be read, see the Interrupt Hierarchy
diagram for more detail. After all the interrupt indications are dealt with in the appropriate interrupt status register, the interrupt status indication
will automatically clear in the GLOBCSR.
All interrupt status bits in the various interrupt status registers are latching unless otherwise noted.
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12.7.1.1 Interrupt Hierarchy
3
2 1
0
ASYTX/RX
ITXINT
IRXINT
LNKPHYINT
HIF INT_N
GLOBCSR (0x018)
CYDONE
CYPEND
CYLOST
CYSEC
CYSTART
TCERR
CYTMOUT
PHYRST
ITBADFMT
ATBADFMT
SNT_REJ
HDRERR
PHYINT
PHYRRX
TIMER
CMDRST
FAIRGAP
ARBGAP
AUTH DN
21 20 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 0
LNKPHYINTACK (0x008)
CRCERR
CIPTAGFLT
RCVBP
SQOV
IRO/E
IREMI
IR100LFT
IR256LFT
IR512LFT
IRXFULL
IRXEMPTY
FSYNC
SEQERR
13 12 10 9 8 7 6 5 4 3 2 1 0
IRXINTACK (0x04C)
ITXFULL
ITXEMPTY
TRMBP
DBCERR
INPERR
DISCARD
ITEMI
IT100LFT
IT256LFT
IT512LFT
TRMSYT
M6 ERROR
ITO/E
14 13 12 9 8 7 6 5 4 3 2 1 0
ITXINTACK (0x02C)
TREQQWR
RREQQFULL
SIDQAV
RRSPQLASTQ
RREQQLASTQ
RRSPQRDERR
RREQQRDERR
RRSPQQAV
RREQQQAV
TIMEOUT
RCVDRSP
TRSPQFULL
TREQQFULL
TRSPQWRERR
TREQQWRERR
TRSPQWR
RRSPQFULL
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYINTACK (0x0A0)
SV00913
Figure 33. Interrupt Hierarchy
13.0 REGISTER MAP
Registers are 32 bits (quadlet) wide and all accesses are always done on a quadlet basis. This means that it is not possible to write just the
lower 8 bits, and leave the other bits unaffected (see Section 12.5.2 for more information). The values written to undefined fields/bits are ignored
and thus DON’T CARE.
A full bitmap of all registers is listed in Table 6. The meaning of shading and bit cell values is as follows:
A bit/field with no name written in it and dark shading is reserved and not used.
A bit/field with a name in it and light shading is a READ ONLY (status) bit/field.
A one bit value (0 or 1) written at the bottom of a writable (control) bit is the default value after power-on-reset.
Table 6. Full Bitmap of all Registers (consists of four tables shown on the following pages)
2000 Apr 15
41
2000 Apr 15
FMT
0
0
0
0
0
0
0
0
0
ITXINTACK
0x02C
ITXINTE
0x030
42
0
0
0
0
0
0
1
0
0
0
0
0
0
DBS
0
0
0
0
0
0
FN
0
PHYRGDATA
PRELOAD
0
0
TRDEL
0
0
0
0
0
0
0
ELNKPHYINT
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
CYCLE_NUMBER
0
QPC
0
0
0
0
0
0
0
FDF
0
MAXBL
0
0
PHYRXAD
0
0
0
0
0 0
0
0
0
0
0
0
0
0
0
0
ITXINT
0
IRXINT
ECYLOST
0
0
LNKIPHYINT
PHYRXDATA
ECYPEND
0
ECYDONE
CYCLE_OFFSET
ECYSTART
0x010
ECYSEC
CYCTM
0
ASYTX/RX
TxRDY
CYPEND
0
CYLOST
0
CYDONE
0
BUSYFLAG
ETCERR
0
CYSTART
0 0
CYSEC
TCERR
0
ESNT_REJ
0
ROOT
SNT_REJ
HDRERR
0
EHDRERR
CYSOURCE
CYTMREN
0
CYTMOUT
ATBADFMT
0
EATBADFMT
RPL
CYMASTER
RST Rx
STRICTISOCH
RST Tx
0
ECYTMOUT
ITBADFMT
0
EITBADFMT
0
PHYRST
PHYINT
PHYRRX
EPHYRRX
0
0
EPHYRST
ARBGAP
EPHYINT
0
0
ITXHQ2
0x028
SYT
0
0
0
0 0
0
0
0
0
RST_ITX
0
0
EIRXINT
0
ITXEMPTY
0
0
0
0
0
0
0
0
0
0
0 0
0
0
0
0
0
EITXEMPTY
ITXHQ1
0
0
EARBGAP
CMDRST
FAIRGAP
ECMDRST
LTLEND
1394 content protection AV link layer controller
EN_FS
0x018
0
ITXFULL
GLOBCSR
0
DISCARD
0
0
0
0
PART CODE
EN_ITX
0
0
0
EITXFULL
0
0
0
EDISCARD
0 0
0
INPERR
0
0
0
DBCERR
0
0
EINPERR
0
0
EFAIRGAP
DATAINV
1
SYT_DELAY
0
0
0
0
EITXINT
PHYRGAD
0
EDBCERR
0
0
0
0
0
TRMSYT
0
0
0
0
8
0
0
0
0
0
0
0 0
0
0
0
0
0
TRMBP
0
0
0
0
ETRMSYT
0
0
0
0
ENXTMSTP
0
NODE ID
EASYTX/RX
0
DIRAV1
CYCLE_SECONDS
ENOUTAV1
0x00C
ENOUTAV2
LNKPHYINTE
TIMER
0x008
ETIMER
LNKPHYINTACK
15
ETRMBP
0
0
IT512LFT
0
0
0
IT256LFT
0
0
0
EIT512LFT
0
P
EIT256LFT
0
P
IT100LFT
0
1
EIT100LFT
0x024
SPH
0
0
1
ITEMI
0
0
RxENABLE
BUS ID
ITO/E
0
0
0
16
EITEMI
0
0
23
EITO/E
0
0
AUTH DN
1
BSYCTRL
TxENABLE
IDREG
EAUTH DN
IDVALID
RCVSELFID
24
M6 ERROR
0x020
31
EM6 ERROR
ITXPKCTL
TMBRE
0x01C
TMCONT
TIMER
0
TXAP_CLK
0x014
0
WRPHY
PHYACS
0
RDPHY
LNKCTL
0x004
TMGOSTOP
REGISTER
ADDRESS
mLAN
Philips Semiconductors
Preliminary specification
PDI1394L41
7
0
0x000
VERSION CODE
0
1
0
0
0
0
0
ATACK
0
0
0
PM
0
0
0
1
0
SV01030
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
0
0
0
0
ITXMEM
0x038
0
0
0
0
ODD/EVEN
SY
0
BPAD
0
0
0
0
1
ITXME
0
RST_IRX
0
ITXM5AV
0
EMI
ITXMAF
SPD
CHANNEL
ITXM100LFT
0
0
EN_FS
TAG
7
ITXMF
0x034
8
ITXM512LFT
ITXCTL
15
ITXM256LFT
16
EN_IRX
23
SPAV
24
CPHR_EN
31
REGISTER
ADDRESS
PDI1394L41
<RESERVED>
0
0
F0
SID
DBS
FN
0
0
1
SPH
E0
F1
0x044
E1
IRXHQ1
DIS_TSC
0x040
RMVUAP
IRXPKCTL
SNDIMM
RXAP_CLK
0x03C
QPC
IRXHQ2
SEQERR
CRCERR
0
0
EIR256LFT
EIR512LFT
EIRXEMPTY
ECRCERR
ECIPTAGFLT
0
0
EFSYNC
ESEQERR
0
EIRXFULL
SQOV
FSYNC
0
EIR100LFT
ESQOV
IRXEMPTY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EMI
0
0
0
<RESERVED>
0x05C
.
.
.
<RESERVED>
0x07C
SV01031
2000 Apr 15
43
IRXME
0
ERR
IRXM5AV
0
CHANNEL
SY
IRXFULL
0
IRXMAF
0x058
RCVBP
IR512LFT
0
IRXMF
IRXMEM
ERCVBP
IR256LFT
0
ODD/EVEN
IR100LFT
0
TAG
0
0
0
IRXM512LFT
SPD
0
0
IRXM256LFT
0x054
0
0
IRXM100LFT
IRXCTL
DECPHR_EN
0x050
0
IREMI
IRXINTE
0
IRO/E
0x04C
EIREMI
IRXINTACK
CIPTAGFLT
SYT
SYTOVF
FDF
ESYTOVF
FMT
EIRO/E
0x048
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
TREQQE
0
TREQQWR
0
TREQQAF
0
TREQQ5AV
0
TRSPQWR
0
TREQQWRERR
0 1
TRSPQE
0
TREQQF
1
TRSPQWRERR
1
TREQQFULL
0
TRSPQAF
0
0
0
0
0
0
0
TRSPQ5AV
0
ETRSPQFULL
0
RREQQE
0
0
TRSPQF
0
RREQQAF
0x084
0
RREQQ5AV
ASYMEM
0
RRSPQE
0
RREQQF
0
7
TOF
RRSPQ5AV
1
RRSPQF
1
RRSPQAF
0
8
TOS
TRSPQIDLE
0
MAXRC
TREQQIDLE
ATXRST
0x080
ARXALL
ASYCTL
16 15
ARXRST
24 23
DIS_BCAST
31
REGISTER
ADDRESS
PDI1394L41
FIRST/MIDDLE QUADLET OF PACKET FOR TRANSMITTER REQUEST QUEUE
(WRITE ONLY)
TX_RQ_NEXT
0x088
LAST QUADLET OF PACKET FOR TRANSMITTER REQUEST QUEUE
(WRITE ONLY)
TX_RQ_LAST
0x08C
FIRST/MIDDLE QUADLET OF PACKET FOR TRANSMITTER RESPONSE QUEUE
(WRITE ONLY)
TX_RP_NEXT
0x090
LAST QUADLET OF PACKET FOR TRANSMITTER RESPONSE QUEUE
(WRITE ONLY)
TX_RP_LAST
0x094
RREQ
QUADLET OF PACKET FROM RECEIVER REQUEST QUEUE (TRANSFER REGISTER)
0x098
RRSP
QUADLET OF PACKET FROM RECEIVER RESPONSE QUEUE (TRANSFER REGISTER)
ETIMEOUT
ERCVDRSP
0
0
0
0
0
ETREQQWR
ERREQQQAV
0
ETRSPQWR
RCVDRSP
0 0
ETREQQWRERR
TIMEOUT
0
ETRSPQWRERR
RREQQQAV
0
ETREQQFULL
RRSPQQAV
0
TRSPQFULL
RREQQRDERR
0
0
ERRSPQQAV
0
0
ERREQQRDERR
0
RRSPQRDERR
0
ERRSPQRDERR
RRSPQLASTQ
RREQQLASTQ
0
ERRSPQLASTQ
0
0
ERREQQLASTQ
0
SIDQAV
RREQQFULL
0x0A4
0
ESIDQAV
ASYINTE
0
ERREQQFULL
0x0A0
RRSPQFULL
ASYINTACK
ERRSPQFULL
0x09C
0
0
0
0
0
<RESERVED>
2000 Apr 15
LPSTAT
EPLI
ELOA
ESCA
ESCI
PLI
LOA
SCA
SCI
RDI
0x0B0
SWPD
0x0A8
0x0AC
0
0
0
0
0
0
0
0
0
0
44
SV01032
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
REGISTER
ADDRESS
31
24 23
PDI1394L41
16 15
8
7
0
<RESERVED>
0x0B4
.
.
.
.
0x0F0
SHADOW_REG
byte 0
byte 1
byte 2
byte 3
0x0F4
0
INDADDR
0
0
0
1
1
1
1
0
0
0
0
1
0
RESERVED
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
INDADDR
0x0F8
INDDATA
WINDOW TO THE INDIRECT QUADLET POINTED TO BY INDADDR
0x0FC
SV01033
2000 Apr 15
45
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
13.1 Link Control Registers
13.1.1 ID Register (IDREG) – Base Address: 0x000
The ID register is automatically updated by the attached PHY with the proper Node ID after completion of the bus reset.
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUS ID
NODE ID
PART CODE
VERSION CODE
SV00915
Reset Value 0xFFFF1001
Bit 31..22:
R/W
BUS ID: The 10-bit bus number that is used with the Node ID in the source address for outgoing packets and used to
accept or reject incoming packets. This field reverts to all ‘1’s (0x3FF) upon bus reset.
Bit 21..16:
R/W
NODE ID: Used in conjunction with Bus ID in the source address for outgoing packets and used to accept or reject
incoming packets. This register auto-updates with the node ID assigned after the 1394 bus Tree-ID sequence.
Bit 15..8:
R
PART CODE: “02” designates PDI1394L41.
Bit 7..0:
R
VERSION CODE: “01” shows this is revision level 1 of this part.
13.1.2 General Link Control (LNKCTL) – Base Address: 0x004
The General Link control register is used to program the Link Layer isochronous transceiver, as well as the overall link transceiver. It also
provides general link status.
BUSYFLAG
TxRDY
ROOT
CYMASTER
CYSOURCE
CYTMREN
STRICTISOCH
RPL
RST Tx
RST Rx
DATAINV
LTLEND
RxENABLE
BSYCTRL
TxENABLE
RCVSELFID
IDVALID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATACK
SV00892
Reset Value 0x46000002
Bit 31:
R/W
IDValid (IDVALID): When equal to one, the PDI1394L41 accepts the packets addressed to this node. This bit is
automatically set after selfID complete and node ID is updated.
Bit 30:
R/W
Receive Self ID (RCVSELFID): When asserted, the self-identification packets, generated by each PHY device on the
bus, during bus initialization are received and placed into the asynchronous request queue as a single packet. Bit 30
also enables the reception of PHY configuration packets in the asynchronous request queue.
Bit 29..27:
R/W
Busy Control (BSYCTRL): These bits control what busy status the chip returns to incoming packets. The field is
defined below:
000 = use protocol requested by received packet (either dual phase or single phase)
001 = RESERVED
010 = RESERVED
011 = use single phase retry protocol
100 = use protocol requested in packet, always send a busy ack (for all packets)
101 = RESERVED
110 = RESERVED
111 = use single phase retry protocol, always send a busy ack
Bit 26:
R/W
Transmitter Enable (TxENABLE): When this bit is set, the link layer transmitter will arbitrate and send packets.
Bit 25:
R/W
Receiver Enable (RxENABLE): When this bit is set, the link layer receiver will receive and respond to bus packets.
Bit 23:
R
Data Invariant (DATAINV) refers to the byte ordering of data being presented to the Link through the host interface
(HIF) port and the handling of the address and data lines by the link chip. When DATAINV = 0, the Link is in address
invariant mode. When DATAINV = 1, the Link is in data invariant mode. This bit is only important if the LTLEND
(Little Endian) bit is set (1), otherwise it is ignored. Interpretation of address and data information varies with the
settings of these bits and with the data format being presented. See the section on Big and Little Endian Modes for
more information (Section 12.5.3).
2000 Apr 15
46
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
Bit 22:
R
Bit 21:
Bit 20:
Bit 18:
R/W
R/W
R/W
Bit 12:
R/W
Bit 11:
R/W
Bit 10:
R/W
Bit 9:
R/W
Bit 6:
Bit 5:
Bit 4:
R
R
R
Bit 3..0:
R
2000 Apr 15
PDI1394L41
Little Endian (LTLEND): Refers to the state of the endianess of the data and address lines connected to the ’L41.
This bit reflects the state of the AV2ERR0/LTLEND pin during power reset. The state of this pin is read during reset
and that state is latched into this bit position. When LTLEND = 0, the chip is set to receive BIG ENDIAN address and
data on its host interface (HIF). When LTLEND = 1, the Link chip will receive LITTLE ENDIAN oriented data
and address information. If this bit is set (1), the state of the DATAINV pin will also become important for
determination of data positions in the internal link registers. See the section on Big and Little Endian Modes for more
information (Section 12.5.3).
Reset Transmitter (RSTTx): When set to one, this synchronously resets the transmitter within the link layer.
Reset Receiver (RSTRx): When set to one, this synchronously resets the receiver within the link layer.
Reset PHY-Link interface (RPL): Resets the PHY–Link interface in accordance with 1394a requirements.
Note: This bit automatically resets to “0” when the interface reset operation has been completed. The PHY–Link
reset operation occurs very quickly, reading this bit accurately is not usually possible.
Before asserting the RPL bit, SWPD or setting the PD pin high, the user should assure that the link chip is in the
following state of operation:
1) The isochronous transmit FIFO is not receiving data for transmission
2) The isochronous transmitter is disabled
3) No asynchronous packets are being generated for transmission
4) Both the ASYNC request and response queues are empty
Strict Isochronous (STRICTISOCH): Used to accept or reject isochronous packets sent outside of specified
isochronous cycles (between a Cycle Start and subaction gap). A ‘1’ rejects packets sent outside the specified
cycles, a “0” accepts isochronous packets sent outside the specified cycle.
Cycle Master (CYMASTER): When asserted and the PDI1394L41 is attached to the root PHY (ROOT bit = 1), and
the cycle_count field of the cycle timer register increments, the transmitter sends a cycle-start packet. Cycle Master
function will be disabled if a cycle timeout is detected (CYTMOUT bit 5 in LNKPHYINTACK). To restart the Cycle
Master function in such a case, first reset CYMASTER, then set it again.
Cycle Source (CYSOURCE): When asserted, the cycle_count field increments and the cycle_offset field resets for each
positive transition of CYCLEIN. When deasserted, the cycle count field increments when the cycle_offset field rolls over.
Cycle Timer Enable (CYTIMREN): When asserted, the cycle offset field increments. When deasserted, the Cycle
Timer Register (0x010, CYCTM) can be used as a general read write register for Host Interface Firmware testing.
Transmitter Ready (TxRDY): The transmitter is idle and ready.
Root (ROOT): Indicates this device is the root on the bus. This automatically updates after the self_ID phase.
Busy Flag (BUSYFLAG): The type of busy acknowledge which will be sent next time an acknowledge is required.
0 = Busy A, 1 = Busy B (only meaningful during a dual-phase busy/retry operation).
AT acknowledge received (ATACK): The last acknowledge received by the transmitter in response to a packet sent
from the transmit-FIFO interface while the ATF is selected (diagnostic purposes).
47
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
13.1.3 Link /Phy Interrupt Acknowledge (LNKPHYINTACK) – Base Address: 0x008
The Link/Phy Interrupt Acknowledge register indicates various status and error conditions in the Link and Phy which can be programmed to
generate an interrupt. The interrupt enable register (LNKPHYINTE) is a mirror of this register. Acknowledgment of an interrupt is accomplished
by writing a ‘1’ to a bit in this register that is set. This action reset the bit indication to a ‘0’. Writing a ‘1’ to a bit that is already “0” will have no
effect on the register.
ITBADFMT
ATBADFMT
SNT_REJ
HDRERR
TCERR
CYTMOUT
CYSEC
CYSTART
CYDONE
CYPEND
CYLOST
CMDRST
FAIRGAP
ARBGAP
PHYINT
PHYRRX
PHYRST
AUTH DN
TIMER
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV01040
Reset Value 0x00000000
Bit 21:
R/W
Authentication Acceleration Done (AUTH DN). The authentication accelerator has finished an operation. Check the
status of ‘Valid’ in the Authentication Accelerator indirect register.
Bit 20:
R/W
Timer (TIMER): When TIMER = 1, this bit indicates that the timer has counted down to zero. This interrupt may occur
only once or may occur repeatedly, according to the setting of the TMCONT bit in the TIMER register. Acknowledge
this interrupt by writing a “1” back into this bit position.
Bit 18:
R/W
Command Reset Received (CMDRST): A write request to RESET-START has been received.
Bit 17:
R/W
Fair Gap (FAIRGAP): The serial bus has been idle for a fair-gap time (called subaction gap in the IEEE 1394
specification).
Bit 16:
R/W
Arbitration Reset Gap (ARBGAP): The serial bus has been idle for an arbitration reset gap.
Bit 15:
R/W
Phy Chip Int (PHYINT): The Phy chip has signaled an interrupt through the Phy interface after a bus reset or PHY
reset. This bit becomes active for any of the following reasons (1) PHY has detected a loop on the bus, (2) cable
power has fallen below the minimum voltage, (3) the PHY arbitration state machine has timed-out usually indicative
of a bus loop, (4) a bus cable has been disconnected. Typically, recognition and notification of any of the above
events by the PHY requires between 166 and 500 microseconds; therefore, this bit is not instantaneously set.
Bit 14:
R/W
Phy Register Information Received (PHYRRX): A register has been transferred by the Physical Layer device into the
Link.
Bit 13:
R/W
Phy Reset Started (PHYRST): A Phy-layer reconfiguration has started. This interrupt clears the ID valid bit. (Called
Bus Reset in the IEEE 1394 specification). The Async queues will be flushed during a bus reset.
Bit 10:
R/W
Isochronous Transmitter is Stuck (ITBADFMT): The transmitter has detected invalid data at the transmit-FIFO
interface when the ITF is selected. Reset the isochronous transmitter to clear.
Bit 9:
R/W
Asynchronous Transmitter is Stuck (ATBADFMT): The transmitter expected start of new async packet in queue, but
found other data (out of sync with user). Reset the asynchronous transmitter to clear.
Bit 8:
R/W
Busy Acknowledge Sent by Receiver (SNT_REJ): The receiver was forced to send a busy acknowledge to a packet
addressed to this node because the receiver response/request FIFO overflowed.
Bit 7:
R/W
Header Error (HDRERR): The receiver detected a header CRC error on an incoming packet that may have been
addressed to this node.
Bit 6:
R/W
Transaction Code Error (TCERR): The transmitter detected an invalid transaction code in the data at the transmit
FIFO interface.
Bit 5:
R/W
Cycle Timed Out (CYTMOUT): ISOCH cycle lasted more than 125µs from Cycle-Start to Fair Gap: Disables cycle
master function
Bit 4:
R/W
Cycle Second incremented (CYSEC): The cycle second field in the cycle-timer register incremented. This occurs
approximately every second when the cycle timer is enabled.
Bit 3:
R/W
Cycle Started (CYSTART): The transmitter has sent or the receiver has received a cycle start packet.
Bit 2:
R/W
Cycle Done (CYDONE): A fair gap has been detected on the bus after the transmission or reception of a cycle start
packet. This indicates that the isochronous cycle is over; Note: Writing a value of ‘0’ to the bit has no effect.
Bit 1:
R/W
Cycle Pending (CYPEND): Cycle pending is asserted when cycle timer offset is set to zero (rolled over or reset) and
stays asserted until the isochronous cycle has ended.
Bit 0:
R/W
Cycle Lost (CYLOST): The cycle timer has rolled over twice without the reception of a cycle start packet. This only
occurs when cycle master is not asserted.
2000 Apr 15
48
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
13.1.4 Link / Phy Interrupt Enable (LNKPHYINTE) – Base Address: 0x00C
This register is a mirror of the Link/Phy Interrupt Acknowledge (LNKPHYINTACK) register. Enabling an interrupt is accomplished by writing a ‘1’
to the bit corresponding to the interrupt desired.
This register enables the interrupts described in the Link /Phy Interrupt Acknowledge register (LNKPHYINTACK) description. A one in any of the
bits enables that function to create an interrupt. A zero disables the interrupt, however the status is readable in the Link /Phy Interrupt
Acknowledge register.
EHDRERR
ETCERR
ECYTMOUT
ECYSEC
ECYSTART
ECYDONE
ECYPEND
ECYLOST
EITBADFMT
EATBADFMT
ESNT_REJ
ECMDRST
EFAIRGAP
EARBGAP
EPHYINT
EPHYRRX
EPHYRST
ETIMER
EAUTH DN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV00894
Reset Value 0x00000000
Bits 21..0 are interrupt enable bits for the Link/Phy Interrupt Acknowledge (LNKPHYINTACK).
13.1.5 Cycle Timer Register (CYCTM) – Base Address: 0x010
Cycle Timer Register operation is controlled by the Cycle Timer Enable (CYTMREN) bit in the Link Control Register (LNKCTL, 0x004). If the
Cycle Timer Register is disabled, it can be used as a general read write register for Host Interface Firmware testing.
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CYCLE_SECONDS
CYCLE_NUMBER
CYCLE_OFFSET
SV00276
Reset Value 0x00000000
Bit 31..25:
R/W
Seconds count: 1-Hz cycle timer counter.
Bit 24..12:
R/W
Cycle Number: 8kHz cycle timer counter.
Bit 11..0:
R/W
Cycle Offset: 24.576MHz cycle timer counter.
2000 Apr 15
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Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
13.1.6 Phy Register Access (PHYACS) – Base Address: 0x014
This register provides access to the internal registers on the Phy. There are special considerations when reading or writing to this register. When
reading a PHY register, the address of the register is written to the PHYRGAD field with the RDPHY bit set. The PHY data will be valid when the
PHYRRX bit (LNKPHYINTACK register bit 14) is set. Once this happens the register data is available in the PHYRXDATA, the address of the
register just read is also available in the PHYRXAD fields. When writing a Phy register, the address of the register to be written is set in the
PHYRGAD field and the data to be written to the register is set in PHYRGDATA, along with the WRPHY bit being set. Once the write is
complete, the WRPHY bit will be cleared. Do not write a new Read/Write command until the previous one has been completed. After the Self-ID
phase, PHY register 0 will be read automatically.
RDPHY
WRPHY
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYRGAD
PHYRGDATA
PHYRXAD
PHYRXDATA
SV00277
Reset Value 0x00000000
Bit 31:
R/W
Read Phy Chip Register (RDPHY): When asserted, the PDI1394L41 sends a read register request with address
equal to Phy Rg Ad to the Phy interface. This bit is cleared when the request is sent.
Bit 30:
R/W
Write Phy Chip Register (WRPHY): When asserted, the PDI1394L41 sends a write register request with address
equal to Phy Rg Ad to the Phy interface. This bit is cleared when the request is sent.
Bit 27..24:
R/W
Phy Chip Register Address (PHYRGAD): This is the address of the Phy-chip register that is to be accessed.
Bit 23..16:
R/W
Phy Chip Register Data (PHYRGDATA): This is the data to be written to the Phy-chip register indicated in Phy Rg Ad.
Bit 11..8:
R
Phy Chip Register Received Address (PHYRXAD): Address of register from which Phy Rx Data came.
Bit 7..0:
R
Phy Chip Register Received Data (PHYRXDATA): Data from register addressed by Phy Rx Ad.
13.1.7 Global Interrupt Status and TX Control (GLOBCSR) – Base Address: 0x018
This register is the top level interrupt status register. If the external interrupt line is set, this register will indicate which major portion of the AV
Link generated the interrupt. There is no interrupt acknowledge required at this level. These bits auto clear when the interrupts in the
appropriate section of the device are cleared or disabled. Control of the AV transceiver is also provided by this register.
Bits 0 to 3 are used to identify which internal modules are currently generating an interrupt. After identifying the module, the appropriate register
in that module must be read to determine the exact cause of the interrupt.
5
4
3
2
1
0
LNKPHYINT
6
IRXINT
7
ASYTX/RX
8
ITXINT
9
ELNKPHYINT
EITXINT
EASYTX/RX
DIRAV1
ENOUTAV2
ENOUTAV1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
EIRXINT
A timer is available to aid the implementation of higher level protocols such as AV/C and HAVi. The timer can be started and stopped, and
automatically reloads with 1s (TIMLOAD = 1) or 100ms (TIMLOAD = 0). When the set time has expired, an interrupt will be generated through
TIMER (Bit 20, LNKPHYINTACK 0x008). In normal timer mode (TIMMODE = 0), the timer will generate an interrupt, reload and restart every
time it expires, until TIMRNSTP is cleared. In bus reset timer mode (TIMMODE = 1), even when already running the timer will reload with 1s
and restart automatically after a bus reset. If another bus reset occurs before the timer expires, the timer will again reload and restart. No
interrupt will be generated until the timer expires.
SV01024
NOTES
1. There can be more than one interrupt source active at the same time.
2. The HIF INT_N signal (pin 28) remains active as long as there is at least one more enabled active interrupt status bit.
Reset Value 0x00010000
Bit 18:
R/W
Enable output AVPORT2: A ‘1’ enables AVPORT2 as an output. A ‘0’ sets the 3-State condition on the port. In
3-State condition the port may be used as an input or unused output according to the state of DIRAV1 (bit 16).
Bit 17:
R/W
Enable output AVPORT1: A ‘1’ enables AVPORT1 as an output. A ‘0’ sets the 3-State condition on the port. In
3-State condition the port may be used as an input or unused output according to the state of DIRAV1 (bit 16).
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Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
Bit 16:
R/W
Bit 11:
R/W
Bit 10:
R/W
Bit 9:
R/W
Bit 8:
R/W
Bit 3:
R
Bit 2:
Bit 1:
Bit 0:
R
R
R
PDI1394L41
Direction of AVPORT1 (DIRAV1): A ‘1’ enables AVPORT1 as a transmitter, thus AVPORT1 pins are inputs. A ‘0’
configures AVPORT1 as a receiver, AVPORT1 pins are outputs in this configuration. The configuration of AVPORT2
pins is opposite of AVPORT1 pins. When AVPORT1 is set to transmit, AVPORT2 receives and vice versa.
Enables generation of external interrupt by asynchronous transmitter and receiver module (ASYTX/RX, bit 3) when
set (1). Disables such interrupts when clear (0) (regardless of ASYINTE contents).
Enables generation of external interrupt by the isochronous transmitter module (ITXINT, bit 2) when set (1).
Disables such interrupts when clear (0) (regardless of ITXINTE contents).
Enables generation of external interrupt by the isochronous receiver module (IRXINT, bit 1) when set (1).
Disables such interrupts when clear (0) (regardless of IRXINTE contents).
Enables generation of external interrupt by general link/phy module (LKPHYINT, bit 0) when set (1). Disables such
interrupts when clear (0) (regardless of LNKPHYINTE contents).
Asynchronous Transmitter/Receiver Interrupt (ASYITX/RX): Interrupt source is in the Asynchronous Transmitter/
Receiver Interrupt Acknowledge/Source register.
AV Transmitter Interrupt (ITXINT): Interrupt source is in the AV Transmitter Interrupt Acknowledge/Source register.
AV Receiver Interrupt (IRXINT): Interrupt source is in the AV Receiver Interrupt Acknowledge/Source register.
Link-Phy Interrupt (LNKPHYINT): Interrupt source is in the Link Phy Interrupt Acknowledge register.
13.1.8 Timer (TIMER) – Base Address: 0x01C
TMGOSTOP
TMCONT
TMBRE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRELOAD
SV01096
Reset Value
Bit 31:
Bit 30:
R/W
R/W
Bit 29:
R/W
Bit 23..0:
R/W
2000 Apr 15
TMGOSTOP: Timer Go/Stop, when = 1 start timer; when = 0 stop timer.
TMCONT: Timer Continuous, when = 1 continuously operate timer; when = 0 operate timer for one timing cycle,
then stop.
TMBRE: Timer Bus Reset Enable, when = 1, start the timer at the beginning of a bus reset; when = 0 start the timer
from the TMGOSTOP bit setting.
Timer preload bits. Load a number into the timer preload bits with the most significant bit in the higher numbered bit
position; the least significant bit in the timer preload register is bit 0. The basic timing unit is 1/(2*CLK25) or 80.14
nanoseconds. The maximum timer time-out is about 1.34 seconds ((2^24)–1 units). The timer uses the preload
value inputted by the host into bits 0 through 23 of this register. The preload value is placed in the actual
timer/counter (invisible to outside world) and this value is decremented by 1 for each unit of time. The timer
eventually counts down to zero and then it sets the TIMER interrupt flag bit in register 0x008, LINKPHYINTACK
(assuming the interrupt was enabled by the ETIMER bit). Depending on the setting of the TMCONT bit in this
register, the timer preload value may be automatically reloaded into the timer/counter (when TMCONT = 1) with the
timing cycle automatically re-starting, or the timer will simply interrupt and stop (when TMCONT bit = 0). TMBRE
adds a mode to the timer operation which starts the timing automatically at the start of a 1394 bus reset. When
TMBRE is set (1), the TMGOSTOP bit function is disabled; the TMCONT bit function is still available.
NOTE: When TMCONT = 1, failing to acknowledge a TIMER interrupt has no effect on the starting/restarting of the
timer; if an interrupt is not acknowledged (bit reset), the timer will continue to time out and restart.
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Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
13.2 AV (Isochronous) Transmitter and Receiver Registers
13.2.1 Isochronous Transmit Packing Control and Status (ITXPKCTL) – Base Address: 0x020
This register allows the user to set up the appropriate AV packets from data entered into the AV interface. The packing and control parameters
(TRDEL, MAXBL, DBS, FN, QPC, and SPH) should never be changed while the transmitter is operating. The only exception to this is the
MAXBL parameter when in MPEG-2 packing mode.
NOTE: When reset of isochronous transmitter is necessary, first disable the transmitter (place bit 4, EN_ITX, LOW), wait for FIFO to empty, then
reset the transmitter (place RST_ITX, bit 0, HIGH). This procedure will ensure that data in the FIFO is transmitted before reset.
PM
EN_FS
RST_ITX
EN_ITX
MAXBL
SYT_DELAY
TRDEL
ENXTMSTP
mLAN
TXAP_CLK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV00886
Reset Value 0x00000001
Bit 30:
R/W
mLAN mode bit: When = 1, SYT system is in mLAN mode. When mLAN = 0 normal SYT time stamping operation is
assumed. With mLAN = 1, the SYT time stamp for an FSYNC pulse will NOT be appended to an empty bus packet.
Any pending SYT stamp will be held until the next non-empty bus packet is sent. As an FSYNC pulse is input to the
transmitting node’s link chip, an SYT stamp will be made. This SYT stamp will point to a time in the future dictated by
the SYT DELAY value (in register 0x020) added to the current least significant nibble (lsn) of the cycle number, plus
the current cycle offset value. This mode automatically increases SYT_DELAY value by two additional cycles beyond
the value programmed in the SYT_DELAY bits.
Bit 29..28:
R/W
TXAP_CLK: Application Clock, default mode, ‘00’ the AVxCLK pin is an input. This pin can become an application
clock for the isochronous Transmitter (and output) by programming it to ‘01’, ‘10’, or ‘11’.
The programming values are:
00
Input
01
24.576MHz
10
12.288MHz
11
6.144MHz
Note that when enabled as ‘01’, ‘10’, or ‘11’, the AV port that is configured as transmitter and enabled will output this
clock signal on its AVxCLK pin.
Bit 27..16:
R/W
TRDEL: Transport delay. Value added to cycle timer to produce time stamps. Lower 4 bits add to upper 4 bits of
cycle_offset, (Cycle Timer Register, CYCTM). Remainder adds to cycle_count field.
Bit 15..8:
R/W
MAXBL: The (maximum) number of data blocks to be put in a payload.
Bit 7:
R/W
ENXTMSTP: Enable External time stamp control. Allows an external time stamp (generated by the application) to be
inserted in place of the link-generated time stamp. Defaults to link generated time stamp. The application must present
the first byte of a quadlet-wide time stamp accompanied by the AVSYNC pulse (and AVVALID) to the AVPORT. The
external time stamp quadlet is inputted first, followed by the application data packet. The transmitted packet size is
now one quadlet larger than the original isochronous data packet—Set up the isochronous transmitter accordingly with
SPH = 1. CAUTION: Unless valid IEC 61883 time stamp format (based on the link cycle timer) is used, the receiving
node link chip must be equipped with a time stamp check disabling function similar to the DIS_TSC bit (register
0X040, Bit 7). Please see section 13.2.8 for details.
Bit 6..5:
R/W
SYT_DELAY: Programmable delay of AV1FSYNC and AV2FSYNC. Each cycle is 1 bus cycle, 125 ms.
Reset value is “00”, a 3 cycle delay.
01 = 2 cycles
00 = 3 cycles
10 = 4 cycles
11 = Reserved
Bit 4:
R/W
EN_ITX: Enable receipt of new application packets and generation of isochronous bus packets in every cycle. This bit
also enables the Link Layer to arbitrate for the transmitter in each subsequent bus cycle. When this bit is disabled (0),
the current packet will be transmitted and then the transmitter will shut down.
Bit 3..2:
R/W
PM: packing mode:
00 = variable sized bus packets, most generic mode.
01 = fixed size bus packets.
10 = MPEG–2 packing mode.
11 = No data, just CIP headers are transmitted.
Bit 1:
R/W
EN_FS:enable generation/insertion of SYT stamps (Time Stamps) in CIP header.
Bit 0:
R/W
Reset Isochronous Transmitter (RST_ITX): causes transmitter to be reset when ‘1’. In order for synchronous reset of
ITX to work properly, an AVxCLK (from either the internal or external source) must be present and ensure that the
reset bit is kept (programmed) HIGH for at least the duration of one AVxCLK period. Failure to do so may cause the
application interface of this module to be improperly reset (or not reset at all). When reset is enabled, all bytes will
be flushed from the FIFO and transmission will cease immediately.
2000 Apr 15
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Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
13.2.2 Common Isochronous Transmit Packet Header Quadlet 1 (ITXHQ1) – Base Address: 0x024
The AV Transmit Packing Control register holds the specification for the packing scheme used on the AV data stream. This information is
included in Common Isochronous Packet (CIP) header quadlet 1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FN
QPC
SPH
DBS
SV01747
Reset Value 0x00000000
Bit 16..23:
R/W
DBS: Size of the data blocks from which AV payload is constructed. The value 0 represents a length of 256 quadlets.
Bit 14..15:
R/W
FN: (Fraction Number) The encoding for the number of data blocks into which each source packet shall be divided
(00 = 1, 01 = 2, 10 = 4, 11 = 8).
Bit 11..13:
R/W
QPC: Number of dummy quadlets to append to each source packet before it is divided into data blocks of the
specified size. The value QPC must be less than DBS and less than 2FN.
Bit 10:
R/W
SPH: Indicates that a 25-bit CYCTM based time stamp has to be inserted before each application packet.
13.2.3 Common Isochronous Transmit Packet Header Quadlet 2 (ITXHQ2) – Base Address: 0x028
The contents of this register are copied to the second quadlet of the CIP header and transmitted with each isochronous packet.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMT
FDF
SYT
SV00281
Reset Value 0x00000000
Bit 29..24:
R/W
FMT: Value to be inserted in the FMT field in the AV header.
Bit 23..0:
R/W
FDF/SYT: Value to be inserted in the FDF field. When the EN_FS bit in the Transmit Control and Status Register
(ITXPKCTL) is set (=1), the lower 16 bits of this register are replaced by an SYT stamp if a rising edge on
AVFSYNCIN has been detected or all ‘1’s if no such edge was detected since the previous packet. The upper 8 bits
of the register are sent as they appear in the FDF register. When the EN_FS bit in the Transmit Control and Status
Register is unset (=0), the full 24 bits can be set to any application specified value.
2000 Apr 15
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Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
13.2.4 Isochronous Transmitter Interrupt Acknowledge (ITXINTACK) – Base Address: 0x02C
The AV Transmitter Interrupt Control and Status register is the interrupt register for the AV transmitter.
Bits 2, 3, and 4 “auto repair” themselves, i.e. AVLINK will detect the situation and attempt to recover on its own. The host controller still needs to
clear these interrupts to be alerted the next time.
IT100LFT
IT256LFT
IT512LFT
TRMSYT
TRMBP
DBCERR
INPERR
DISCARD
ITXFULL
ITXEMPTY
M6 ERROR
ITO/E
ITEMI
SYTTI
EOTI
DBCEI
IDDSCI
PLDSCI
ITXMFI
ITXMEI
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV01054
Reset Value 0x00000000
Bit 14:
R/W
M6 ERROR: Either the M6 cipher block has encountered an unrecoverable error. Proper operation will be resumed
by disabling and resetting the ITX.
Bit 13:
R/W
ITO/E: An odd/even key change has occurred in the cipher, it is now OK to write in the new key set.
Bit 12:
R/W
ITEMI: This bit indicates that the EMI bit value used to cipher outgoing transmission has changed.
Bits 9 .. 0 are interrupt acknowledge bits; and are defined as:
Bit 9:
R/W
IT100LFT: Interrupt when transmitter queue reaches 100 quadlets from full.
Bit 8:
R/W
IT256LFT: Interrupt when transmitter queue reaches 256 quadlets from full.
Bit 7:
R/W
IT512LFT: Interrupt when transmitter queue reaches 512 quadlets from full. This bit is disabled if 0.5K Byte buffer
size is set.
Bit 6:
R/W
TRMSYT: Interrupt on transmission of a SYT in CIP header quadlet 2
Bit 5:
R/W
TRMBP: Interrupt on payload transmission/discard complete.
Bit 4:
R/W
DBCERR: Acknowledge interrupt on Data Block Count (DBC) synchronization loss.
Bit 3:
R/W
INPERR: Acknowledge interrupt on input error (input data discarded).
Bit 2:
R/W
DISCARD: Interrupt on lost cycle (payload discarded).
Bit 1:
R/W
ITXFULL: Interrupt on isochronous memory bank full. This is a fatal error. The ITX transmitter will reset itself
automatically when this occurs.
Bit 0:
R/W
ITXEMPTY: Interrupt on isochronous memory bank empty.
Other bits will always read ‘0’.
13.2.5 Isochronous Transmitter Interrupt Enable (ITXINTE) – Base Address: 0x030
These are the enabled bits for the AV Transmitter Control.
0
EITXEMPTY
EITXFULL
2 1
EINPERR
EDISCARD
5 4 3
ETRMBP
EDBCERR
6
EIT512LFT
ETRMSYT
EIT256LFT
EIT100LFT
EITEMI
EITO/E
EM6 ERROR
ITXMEI
ITXMFI
IDDSCI
PLDSCI
SYTTI
EOTI
DBCEI
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
SV01055
Reset Value 0x00000000
Bits 13..0 are interrupt enable bits for the Isochronous Transmitter Interrupt Acknowledge register (ITXINTACK).
2000 Apr 15
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Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
13.2.6 Isochronous Transmitter Control Register (ITXCTL) – Base Address: 0x34
TAG
CHANNEL
SPD EMI
ODD/EVEN
SY
CPHR_EN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV01016
Reset Value 0x00000000
Bit 20:
R/W
Cipher Enable: When set, the internal M6 cipher will encrypt the application packets with the associated key in the
M6 indirect address space for the given EMI value assigned. When the EMI value changes the cipher will
automatically change the key on the next application packet. Writes to the ODD/EVEN bit (bit 1 will automatically
swap the odd/even key in the cipher. Note: the maximum average data rate for the M6 cipher is 60 Mbps.
Bit 15..14:
R/W
Tag: Tag code to insert in isochronous bus packet header. Should be ‘01’ for IEC 61883 International Standard data.
Bit 13..8:
R/W
Channel: Isochronous channel number.
Bit 5..4:
R/W
Speed: Cable transmission speed (S100, S200, S400).
00 = 100Mbs
01 = 200Mbs
10 = 400Mbs
11 = reserved
Bit 3..2
R/W
Encryption Mode Indication: This bit pattern specifies the level of copy control information for the data stream. The
field only has significance when the internal cipher is enabled (CPHR_EN = 1). The bits are read only and follow the
value of the AVxEMI pins when EMI_PE = 1 (bit 19). The bits are read/write when EMI_PE = 0. See the “5C Digital
Transmission Content Protections Specification, Volume 1” for more details about EMI values.
Bit 1
R/W
Odd even bit used for encryption key (0 = even, 1 = odd). When the internal M6 cipher is enabled (CPHR_EN = 1), a
write that changes this bit field will cause the cipher to swap its odd/even key. The key will be changed on the very
next application packet and an interrupt (ODDEVN) will be generated. See the “5C Digital Transmission Content
Protection Specification, Volume 1” for more details about odd/even values. When the internal cipher is not enabled
(CPHR_EN = 0) the bit value is R/W and the current bit value will be transmitted in the isochronous header.
Bit 0
R
SY: Sync code to insert in SY field of isochronous bus packet header. This bit reflects the value of the AVx SY pin
and is synchronized with the data payload that was associated with it.
13.2.7 Isochronous Transmitter Memory Status (ITXMEM) – Base Address: 0x038
The AV Transmitter Memory Status register reports on the condition of the internal memory buffer used to store incoming AV data streams
before transmission over the 1394 bus. This register is used primarily for diagnostics; several memory status flags are also available in the
ITXINTACK register.
ITXM100LFT
ITXM256LFT
ITXM512LFT
ITXMF
ITXMAF
ITXM5AV
ITXME
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV01056
Reset Value 0x00000003
BIT 6:
R
Bit 5:
R
Bit 4:
R
Bit 3:
R
Bit 2:
R
Bit 1:
R
Bit 0:
R
2000 Apr 15
ITXM100LFT: 100 or less quadlets of storage available.
ITXM256LFT: Memory has 256 quadlets of space remaining before becoming full.
ITXM512LFT: Memory has 512 quadlets of space remaining before becoming full.
ITXMF: memory is completely full, no storage available.
ITXMAF: almost full, exactly one quadlet of storage available.
ITXM5AV: at least 5 more quadlets of storage available.
ITXME: memory bank is empty (zero quadlets stored).
55
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
13.2.8 Isochronous Receiver Unpacking Control (IRXPKCTL) – Base Address: 0x040
NOTE: When receiver reset is required, first disable receiver (EN_IRX = 0), then wait until Rx FIFO is emptied, then perform the reset. This will
allow previously received packets to go to the application instead of being lost.
BPAD
EN_FS
RST_IRX
SNDIMM
DIS_TSC
RMVUAP
SPAV
EN_IRX
RXAP_CLK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV00887
Reset Value 0x00000041
AV Receiver Control Bits.
Bit 29..28:
R/W
RXAP_CLK: Receiver Application Clock, default mode, ‘00’ the AVxCLK pin is an input. This pin can become an
application clock and output for the isochronous Receiver by programming it to ‘01’, ‘10’, or ‘11’.
The programming values are:
00
Input
01
24.576MHz
10
12.288MHz
11
6.144MHz
Note that when enabled as ‘01’, ‘10’, or ‘11’, the AV port that is configured as receiver and enabled will output this
clock signal on its AVxCLK pin.
Bit 8:
R/W
SNDIMM: Send immediately; when set to “1”, this bit will allow a received isochronous packet containing a CRC
error to be output immediately (without regard to the time stamp value). This bit defaults to “0”. In default (reset)
mode, the packet will be output with respect to the time stamp value, even if there is a CRC error.
CAUTION: If there is an error in the time stamp, the packet may be held far into the future. This will affect
subsequently received packets.
Bit 7:
R/W
DIS_TSC: Disable Time Stamp Checking. Defaults to “0”, time stamp checking is enabled. When time stamp
checking is disabled, the time stamp accompanying a packet is output before the packet to the application for use
by the application. This adds an extra quadlet of data to the received data stream; the application must be capable
of handling this extra 4 bytes.
Bit 6:
R/W
RMVUAP: Remove unreliable packets from memory, do not attempt delivery
Bit 5:
R
SPAV: Source packet available for delivery in buffer memory.
Bit 4:
R/W
EN_IRX: Enable receiver operation. Value is only checked whenever a new bus packet arrives, so enable/disable
while running is ‘graceful’, meaning any transfers in process will be completed before this bit is asserted.
Bit 2..3:
R/W
BPAD: Value indicating the amount of byte padding to be removed from the last data quadlet of each source packet,
from 0 to 3 bytes. This is in addition to quadlet padding as defined in IEC 61883 International Standard.
Bit 1:
Bit 0:
2000 Apr 15
R/W
R/W
EN_FS: Enable processing of SYT stamps.
RST_IRX: causes the receiver to be reset when ‘1’. In order for synchronous reset of IRX to work properly, the
application must supply an AVCLK and ensure that the reset bit is kept (programmed) HIGH for at least the duration
of one AVCLK period. Failure to do so may cause the application interface of this module to be improperly reset (or
not reset at all).
56
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
13.2.9 Common Isochronous Receiver Packet Header Quadlet 1 (IRXHQ1) – Base Address: 0x044
This quadlet represents the last received header value when AV receiver is operating.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
FN
QPC
E0
F0
SPH
DBS
SV00286
Reset Value 0x00000000
Bit 31..30:
R
Bit 29..24
R
Bit 23.16:
R
Bit 15..14:
R
Bit 13..11:
R
Bit 10:
R
E0: End of Header, F0: Format: Always set to 00 for first AV header quadlet.
SID: Source ID, contains the node address of the sender of the isochronous data.
DBS: Size of the data blocks from which AV payload is constructed. The value 0 represents a length of 256 quadlets.
FN (Fraction Number): The encoding for the number of data blocks into which each source packet has been divided
(00 = 1, 01 = 2, 10 = 4, 11 = 8) by the transmitter of the packet.
QPC: Number of dummy quadlets appended to each source packet before it was divided into data blocks of the
specified size.
SPH: Indicates that a CYCTM based time stamp is inserted before each application packet (25 bits specified in the
IEC 61883 International Standard).
13.2.10 Common Isochronous Receiver Packet Header Quadlet 2 (IRXHQ2) – Base Address: 0x048
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDF
SYT
E1
F1
FMT
SV00287
Reset Value 0x0000FFFF
Bit 31..30:
R
E1: End of Header, F1: Format: Should be set to 10 for second AV header quadlet.
Bit 29..24:
R
FMT: Value inserted in the Format field.
Bit 23..0:
R
FDF/SYT: If ‘‘EN FS” in Register IRXPKCTL (0x040) is set to ‘1’, then lower 16-bits are interpreted as SYT.
2000 Apr 15
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Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
13.2.11 Isochronous Receiver Interrupt Acknowledge (IRXINTACK) – Base Address: 0x04C
IR100LFT
IR256LFT
IR512LFT
IRXFULL
IRXEMPTY
FSYNC
SEQERR
CRCERR
CIPTAGFLT
RCVBP
SQOV
SYTOVF
IRO/E
IREMI
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV01025
Reset Value 0x00000000
Bit 14:
R/W
SYTOVF: SYT FIFO overflow. The isochronous receiver’s SYT field FIFO has overflowed and has been
automatically reset and cleared. This interrupt alerts the host controller that up to 7 AVFSYNC pulses may be
missing due to an SYT field reception error.
Bit 13:
R/W
IRO/E: Odd/even key change. Software should write in the new set of keys to the cipher.
Bit 12:
R/W
IREMI: This bit indicates when there has been a change in the received EMI bit values (bits 2 and 3 of register
0x054). This interrupt, when = 1, indicates that a changed EMI field has been received.
Bit 10:
R/W
IR100LFT: Interrupt when receiver queue reaches 100 quadlets from full.
Bit 9:
R/W
IR256LFT: Interrupt when receiver queue reaches 256 quadlets from full.
Bit 8:
R/W
IR512LFT: Interrupt when receiver queue reaches 512 quadlets from full. This bit is disabled if 0.5K Byte buffer size
is set.
Bit 7:
R/W
IRXFULL: Isochronous data memory bank has become full. this is a fatal error, the recommended action is to reset
and re-initialize the receiver.
Bit 6:
R/W
IRXEMPTY: Isochronous data memory bank has become empty.
Bit 5:
R/W
FSYNC: Pulse at fsync output.
Bit 4:
R/W
SEQERR: Sequence error of data blocks.
Bit 3:
R/W
CRCERR: CRC error in bus packet.
Bit 2:
R/W
CIPTAGFLT: Faulty CIP header tag (E,F bits). i.e.: The CIP header did not meet the standard and the whole packet
is ignored.
Bit 1:
R/W
RCVBP: Bus packet processing complete.
Bit 0:
R/W
SQOV: Status queue overflow. This is a fatal error, the recommended action is to reset and re-initialize the receiver.
13.2.12 Isochronous Receiver Interrupt Enable (IRXINTE) – Base Address: 0x050
Interrupt enable bits for AV Receiver.
ECIPTAGFLT
ERCVBP
ESQOV
EIR100LFT
EIR256LFT
EIR512LFT
EIRXFULL
EIRXEMPTY
EFSYNC
ESEQERR
ECRCERR
ESYTOVF
EIRO/E
EIREMI
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV01026
Reset Value 0x00000000
Bit 13..0 are interrupt enable bits for the Isochronous Receiver Interrupt Acknowledge (IRXINTACK).
2000 Apr 15
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Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
13.2.13 Isochronous Receiver Control Register (IRXCTL) – Base Address: 0x054
CHANNEL
ERR
ODD/EVEN
SY
SPD TAG
EMI
DECPHR_EN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV01041
Reset Value 0x00000000
Bit 20:
R/W
De-cipher Enable: When set the internal M6 cipher will decrypt the application packets with the associated key in the
M6 indirect address space for the given EMI value assigned. When the EMI value changes, the cipher will
automatically change the key on the next application packet. Changes to the ODD/EVEN bit (bit 1) will automatically
swap the odd/even key in the cipher. Note: the maximum average data rate for the M6 cipher is 60 Mbps.
Bit 17..16:
R
SPD: Speed of last received isochronous packet (S100 .. S400).
00 = 100 Mbps
01 = 200 Mbps
10 = 400 Mbps
11 = Reserved
Bit 15..14:
R/W
TAG: Isochronous tag value (must match) for AV format, ‘01’ for IEC 61883 International Standard data.
Bit 13..8:
R/W
CHAN: Channel number to receive isochronous data.
Bit 7..4:
R
ERR: Error code for last received isochronous AV packet.
Bit 3..2:
R
Encryption Mode Indication: This bit pattern specifies the level of copy control information for the data stream. The
field only has significance when the internal cipher is enabled (DECPHR_EN = 1). The value of these bits is stored
and accompanies the received packet through the IRx FIFO. At a later time, when the first byte of the accompanied
packet is presented at the receiving AV port, that EMI value is also presented. Note: The EMI value in this register
is indicative only of the EMI value of the packet which is being received from the bus. The EMI value at the AV port
may differ due to aging as it progresses through the IRx FIFO. See the “5C Digital Transmission Content Protection
Specification, Volume 1” for more details about EMI values.
Bit 1:
R
ODD/EVEN: Used for encryption key (0= even, 1 = odd). When the internal M6 decipher is enabled
(DECPHR_EN = 1), changes to this bit field will cause the cipher to swap its odd/even key. An interrupt will be
generated, ‘Odd/even’ in the IRXINTACK register to allow firmware to update key sets. See the “5C Digital
Transmission Content Protection Specification, Volume 1” for more details about odd/even values.
Bit 0:
R
SY: Sync code to insert in SY field of isochronous bus packet header. This bit reflects the value of the SY bit
received from the isochronous header and is synchronized in the receiver FIFO with the data payload that was
associated with it. Note: The SY value in this register is indicative only of the EMI packet which is being received
from the bus. The SY value at the AV port may differ due to aging as it progresses through the IRx FIFO.
Table 7. Error Codes
Code
Name
0000
reserved
0001
ack_complete
0010
through
1100
reserved
1101
ack_data_error
1110
and
1111
reserved
2000 Apr 15
Meaning
The node has successfully accepted the packet. If the packet was a request subaction, the destination node has
successfully completed the transaction and no response subaction shall follow.
The node could not accept the block packet because the data field failed the CRC check, or because the length
of the data block payload did not match the length contained in the dataLength field. this code shall not be
returned for any packet that does not have a data block payload.
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Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
13.2.14 Isochronous Receiver Memory Status (IRXMEM) – Base Address: 0x058
The AV Receiver Memory Status register reports on the condition of the internal memory buffer used to store outgoing AV data streams after
reception from the 1394 bus. This register is used primarily for diagnostics; several memory flags are also available in the IRXINTACK register.
IRXM100LFT
IRXM256LFT
IRXM512LFT
IRXMF
IRXMAF
IRXM5AV
IRXME
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV01057
Reset Value 0x00000003
Bit 6:
R
Bit 5:
R
Bit 4:
R
Bit 3:
R
Bit 2:
R
Bit 1:
R
Bit 0:
R
2000 Apr 15
IRXM100LFT: FIFO is 100 quadlets from full.
IRXM256LFT: FIFO is 256 quadlets from full.
IRXM512LFT: FIFO is 512 quadlets from full.
IRXMF: Full: no space available.
IRXMAF: Almost full: exactly one quadlet of storage available.
IRXM5AV: At least 5 more quadlets of storage available.
RXME: Memory bank is empty (no data committed).
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Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
13.3 Asynchronous Control and Status Interface
13.3.1 Asynchronous RX/TX Control (ASYCTL) – Base Address: 0x080
DIS_BCAST
ARXRST
ATXRST
ARXALL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAXRC
TOS
TOF
SV00889
Reset Value 0x00300320
Bit 23:
R/W
DIS_BCAST: Disable the reception of broadcast packets (async packets address to 0x3F).
Bit 22:
R/W
ARXRST: Asynchronous receiver reset. This bit will auto clear when the link layer state machine is idle.
Bit 21:
R/W
ATXRST: Asynchronous transmitter reset. the power-up reset value of this bit is “0”, however, after every bus reset
this bit is set (1). this effectively disables the asynchronous transmitter; re-enable the async transmitter by clearing
this bit after each bus reset, especially if asynchronous transmission is to be used.
Bit 20:
R/W
ARXALL: Receive and filter only RESPONSE packets. When set (1), all responses are stored. When clear (0), only
solicited responses are stored.
Bit 19..16:
R/W
MAXRC: Maximum number of asynchronous transmitter single phase retries
Bit 15..13:
R/W
TOS: Time out seconds, integer of 1 second
Bit 12..0:
R/W
TOF: Time out fractions, integer of 1/8000 second. Resets to 0320h, which is 100 milliseconds.
13.3.2 Asynchronous RX/TX Memory Status (ASYMEM) – Base Address: 0x084
TRSPQIDLE
TREQQIDLE
RRSPQF
RRSPQAF
RRSPQ5AV
RRSPQE
RREQQF
RREQQAF
RREQQ5AV
RREQQE
TRSPQF
TRSPQAF
TRSPQ5AV
TRSPQE
TREQQF
TREQQAF
TREQQ5AV
TREQQE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV00918
Reset Value 0x00033333
Bit 17:
Bit 16:
Bit 15:
Bit 14:
Bit 13:
Bit 12:
Bit 11:
Bit 10:
Bit 9:
Bit 8:
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
2000 Apr 15
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Unused bits read ‘0’. The information in this register is primarily used for diagnostics.
TRSPQIDLE: Transmitter response queue is idle. Indicates that the transfer register for this queue is empty.
TREQQIDLE: Transmitter request queue is idle. Indicates that the transfer register for this queue is empty.
RRSPQF: Receiver response queue full.
RRSPQAF: Receiver response queue almost full (precisely 1 more quadlet available).
RRSPQ5AV: Receiver response queue at least 5 quadlets available.
RRSPQE: Receiver response queue empty.
RREQQF: Receiver request queue full.
RREQQAF: Receiver request queue almost full (precisely 1 more quadlet available).
RREQQ5AV: Receiver request queue at least 5 quadlets available.
RREQQE: Receiver request queue empty.
TRSPQF: Transmitter response queue full.
TRSPQAF: Transmitter response queue almost full (precisely 1 more quadlet available).
TRSPQ5AV: Transmitter response queue at least 5 quadlets available.
TRSPQE: Transmitter response queue empty.
TREQQF: Transmitter request queue full.
TREQQAF: Transmitter request queue almost full (precisely 1 more quadlet available).
TREQQ5AV: Transmitter request queue at least 5 quadlets available.
TREQQE: Transmitter request queue empty.
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1394 content protection AV link layer controller
PDI1394L41
13.3.3 Asynchronous Transmit Request Next (TX_RQ_NEXT) – Base Address: 0x088
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_RQ_NEXT
SV00293
Bit 31..0:
W
TX_RQ_NEXT: First/middle quadlet of packet for transmitter request queue (write only).
Writing this register will clear the TREQQWR flag until the quadlet has been written to its queue.
13.3.4 Asynchronous Transmit Request Last (TX_RQ_LAST) – Base Address: 0x08C
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_RQ_LAST
SV00294
Bit 31..0:
W
TX_RQ_LAST: Last quadlet of packet for transmitter request queue (write only).
Writing this register will clear the TREQQWR flag until the quadlet has been written to its queue.
13.3.5 Asynchronous Transmit Response Next (TX_RP_NEXT) – Base Address: 0x090
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_RP_NEXT
SV00295
Bit 31..0:
W
TX_RP_NEXT: First/middle quadlet of packet for transmitter response queue (write only).
Writing this register will clear the TRSPQWR flag until the quadlet has been written to its queue.
13.3.6 Asynchronous Transmit Response Last (TX_RP_LAST) – Base Address: 0x094
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_RP_LAST
SV00296
Bit 31..0:
2000 Apr 15
W
TX_RP_LAST: Last quadlet of packet for transmitter response queue (write only).
Writing this register will clear the TRSPQWR flag until the quadlet has been written to its queue.
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Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
13.3.7 Asynchronous Receive Request (RREQ) – Base Address: 0x098
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RREQ
SV00297
Reset Value 0x00000000
Bit 31..0:
R
RREQ:Quadlet of packet from receiver request queue (transfer register).
Reading this register will clear the RREQQQAV flag until the next received quadlet is available for reading.
13.3.8 Asynchronous Receive Response (RRSP) – Base Address: 0x09C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RRSP
SV00298
Reset Value 0x00000000
Bit 31..0:
R
RRSP:Quadlet of packet from receiver response queue (transfer register).
Reading this register will clear the RRSPQQAV flag until the next received quadlet is available for reading.
13.3.9 Asynchronous RX/TX Interrupt Acknowledge (ASYINTACK) – Base Address: 0x0A0
1
TRSPQWR
2
0
TREQQWR
3
TREQQWRERR
4
TREQQFULL
5
TRSPQWRERR
6
RCVDRSP
7
TRSPQFULL
8
TIMEOUT
RRSPQQAV
9
RREQQQAV
RRSPQRDERR
RREQQRDERR
RRSPQLASTQ
RREQQLASTQ
SIDQAV
RRSPQFULL
22 21 20 19 18 17 16 15 14 13 12 11 10
RREQQFULL
31 30 29 28 27 26 25 24 23
SV00796
Reset Value 0x00000C00
Bit 31..17:
R/W
Bit 16:
R/W
Bit 15:
R/W
Bit 14:
R/W
Bit 13:
R/W
Bit 12:
R/W
Bit 11:
R/W
Bit 10:
R/W
Bit 9:
R/W
Bit 8:
R/W
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2000 Apr 15
Unused bits read ‘0’
RRSPQFULL: Receiver response queue did become full. Write a “1” to this bit to reset the interrupt.
RREQQFULL: Receiver request queue did become full. Write a “1” to this bit to reset the interrupt.
SIDQAV: Current quadlet in RREQ is selfID data. This bit is set only after a bus reset, not after reception of PHY
packets other than self IDs. This interrupt automatically resets when the quadlet is read.
RRSPQLASTQ: Current quadlet in RRSP is last quadlet of packet. This interrupt automatically resets when the
quadlet is read.
RREQQLASTQ: Current quadlet in RREQ is last quadlet of packet. This interrupt automatically resets when the
quadlet is read.
RRSPQRDERR: Receiver response queue read error (transfer error) or bus reset occurred.
When set (1), this queue is blocked for read access. Write a “1” to this bit to reset the interrupt.
RREQQRDERR: Receiver request queue read error (transfer error) or bus reset occurred.
When set (1), this queue is blocked for read access. Write a “1” to this bit to reset the interrupt.
RRSPQQAV: Receiver response queue quadlet available (in RRSP). This interrupt automatically resets when the
quadlet is read.
RREQQQAV: Receiver request queue quadlet available (in RREQ). This interrupt automatically resets when the
quadlet is read.
TIMEOUT: Split transaction response timeout. Write a “1” to this bit to reset the interrupt.
RCVDRSP: Solicited response received (within timeout interval). Write a “1” to this bit to reset the interrupt.
TRSPQFULL: Transmitter response queue did become full. Write a “1” to this bit to reset the interrupt.
TREQQFULL: Transmitter request queue did become full. Write a “1” to this bit to reset the interrupt.
TRSPQWRERR: Transmitter response queue write error (transfer error). Write a “1” to this bit to reset the interrupt.
TREQQWRERR: Transmitter request queue write error (transfer error). Write a “1” to this bit to reset the interrupt.
TRSPQWR: Transmitter response queue written (transfer register emptied). Write a “1” to this bit to reset the interrupt.
TREQQWR: Transmitter request queue written (transfer register emptied). Write a “1” to this bit to reset the interrupt.
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Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
13.3.10 Asynchronous RX/TX Interrupt Enable (ASYINTE) – Base Address: 0x0A4
1
0
ETREQQWR
2
ETRSPQWR
3
ETREQQWRERR
4
ETREQQFULL
5
ETRSPQWRERR
6
ETRSPQFULL
7
ETIMEOUT
8
ERCVDRSP
ERRSPQQAV
9
ERREQQQAV
ERREQQRDERR
ERREQQLASTQ
ERRSPQRDERR
ERRSPQLASTQ
ESIDQAV
ERRSPQFULL
22 21 20 19 18 17 16 15 14 13 12 11 10
ERREQQFULL
31 30 29 28 27 26 25 24 23
SV00797
Reset Value 0x00000000
Bits16..0 are interrupt enable bits for the Asynchronous RX/TX Interrupt Acknowledge (ASYINTACK).
7
6
5
4
3
2
1
0
SCI
8
SCA
9
LOA
ESCI
ESCA
ELOA
EPLI
LPSTAT
SWPD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PLI
13.3.11 RDI Register – Base Address: 0x0B0
SV01779
Reset Value 0x00000000
Bit 31:
R/W
Bit 30:
R
Bit 19:
R/W
Bit 18:
R/W
Bit 17:
R/W
Bit 16:
R/W
2000 Apr 15
Note: Before asserting the RPL bit, SWPD or setting the PD pin high, the user should assure that the link chip is in
the following state of operation:
1) The isochronous transmit FIFO is not receiving data for transmission
2) The isochronous transmitter is disabled
3) No asynchronous packets are being generated for transmission
4) Both the ASYNC request and response queues are empty
SWPD: Software power–down. Writing a 1 to this register bit will cause the link to de–activate its LPS pin causing the
PHY to turn off the SCLK to the link. This, in turn, causes the link chip to go into a low power mode in which only the
RDI register is accessible. The function of this bit is identical to that of the hardware pin ”PD”. When PD is set (1),
SWPD will be set automatically by the pin state and will cause entry into the power down mode as stated above. DO
NOT USE BOTH (HARDWARE AND SOFTWARE) MODES OF OPERATION TO CAUSE THE POWER DOWN
FUNCTION. Use either hardware mode (the PD pin) OR the software method (setting / resetting the SWPD bit), not
both. The PD pin will take precedence over the software method... the link will not come out of PD mode unless the
PD pin is de–asserted (0). An unused PD pin should be connected to the link chip ground.
LPSTAT: Link – PHY interface status. This bit reflects the status of the LPS signal. When the LPS signal is active
(pulsing) the PHY interprets it as indicating that the link power is on and the link is requesting to be activated. The
PHY, in turn, supplies the SCLK to the link, thus giving it the means to become active. The SCLK is used by the link
to operate most of its internal circuitry. If LPS was active and then de–activated, it is a signal to the PHY chip that the
link desires entry into the power down mode. The LPSTAT bit continually indicates the status of the LPS pin and thus
the overall status of the link – PHY interface. It should also be noted here that a momentary de–activation of the LPS
signal by the setting of the RPL bit (bit 18 of register 0x004, LNKCTL) to cause a link – PHY interface reset will also
be indicated by the LPSTAT bit. It is suggested that this momentary status change be ignored when the host
controller causes a link – PHY reset through the use of the RPL bit.
EPLI: Enable the PHY – link initialized interrupt. Leaving this bit in the reset (0) state allows the PLI bit to be read as
a status bit.
ELOA: Enable link–on active interrupt. Leaving this bit in the reset (0) state allows the LOA bit to be read as a status
bit.
ESCA: Enable SCLK active interrupt. Leaving this bit in the reset (0) state allows the SCA bit to be read as a status
bit.
ESCI: Enable SCLK inactive interrupt. Leaving this bit in the reset (0) state allows the SCI bit to be read as a status
bit.
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Preliminary specification
1394 content protection AV link layer controller
Bit 3:
R/W
Bit 2:
R/W
Bit 1:
R/W
Bit 0:
R/W
PDI1394L41
PLI: PHY – link interface initialized interrupt. This interrupt indicates when the PHY – link initialization routine has
been accomplished. This bit will be set upon completion of the initialization; if enabled, it will cause a host interface
interrupt in order to inform the host controller of the completed action. Reset of this interrupt requires the writing of a
(1) to this bit position.
LOA: Link–on active interrupt. This interrupt will become active when a link–on signal is received by the link from the
PHY. This bit will remain active as long as the link–on signal is active. When enabled, this bit will set and cause a
host interface interrupt when the link detects the presence of a link–on signal from the PHY. In practice, the link will
be in the power down state when this interrupt occurs (a link–on packet was sent by another node on the bus which
desires to communicate with this powered down node). Proper servicing of this interrupt will contain a scenario
similar to: this node is in power down mode and the host controller has set the ELOA bit to enable the interrupt and
the PHY of this node received a link–on packet from another node requesting this node to power up; (1) the host
controller gets the interrupt and makes a decision to power up, (2) the host de–asserts SWPD (by hardware or
software means... see SWPD above), (3) the host monitors SCA for a ”1” state, (4) when SCA is true, the host writes
a 0 to the ELOA bit and then writes a 1 to the LOA interrupt bit to cancel the interrupt. The link is now powered up.
SCA: SCLK active interrupt. When the SCLK signal from the PHY to the link is present, this bit is set. If this interrupt
has been enabled, the host will receive an interrupt when the SCLK becomes active (an example of such use might
be during the recovery from a link power down situation).
SCI: SCLK inactive interrupt. When the SCLK signal is NOT active, this bit sets. If this interrupt is enabled, when the
SCLK ceases to be active, the interrupt will occur. SCLK could become inactive due to the PHY connected to this
link going into power down mode.
13.3.12 Shadow Register (SHADOW_REG) – Base Address: 0x0F4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BYTE 0
BYTE 1
BYTE 2
9
8
7
6
5
4
3
2
1
0
BYTE 3
SV01817
Reset Value 0x0F0A0500
Bit 31..0:
R/W
The shadow register is a mechanism that allows a byte (8-bit) or word (16-bit) host interface write quadlets (32-bit)
into the AV Link. Bytes or words can be written into the shadow register in any order and then written to the AV Link
by asserting address line A8 with the desired address. For example, if you want to write to Transmit Request Next
register (TX_RQ_NEXT), and you were using an 8-bit host, then you would write the first three bytes to the shadow
register and the fourth byte to the address 0x188 (or 0x189, or 0x18A, or 0x18B). In practice, any write or read with
address line A8 not asserted will be directed to the shadow register. To verify the settings of LTLEND and DATAINV,
this register is initialized to 0x0F0A0500 on power up. Note, unlike the other registers in this device, access to this
register should not be addressed with address line A8 = 1.
2000 Apr 15
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Philips Semiconductors
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1394 content protection AV link layer controller
PDI1394L41
13.4 Indirect Address Registers
13.4.1
The host interface register set has been extended to provide additional control and data registers for FIFO size control and copy protection
control registers. These extensions have been implemented via an indirect addressing mechanism. This mechanism allows software written for
previous versions of the AV Link (PDI1394L21 and PDI1394L11) to operate on the PDI1394L41 with minimal changes.
To read or write from the indirect memory, you first write the appropriate address into the indirect address register (A8 = 1), then read or write
from (or to) the indirect data increment the indirect address by one quadlet. Therefore, if you are writing several quadlets to continuous
addresses, you will not need to increment the indirect address register.
13.4.2 Indirect Address Register (INDADDR) – Base Address: 0x0F8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
INDADDR
RESERVED
SV01027
Bit 15..0:
R/W
Indirect Address: To read or write from the indirect memory, you first write the appropriate address into the indirect
address register (A8 = 1), then read or write from (or to) the indirect data register (INDDATA, 0x0FC). Each write or
read (A8 = 1) to the indirect data register (INDDATA) will automatically increment the indirect address by one
quadlet. The following addresses are defined in the indirect address space:
Table 8. INDADDR address and function
INDADDR
FUNCTION
0–0x0FC
Reserved
0x100–0x1FC
FIFO Size Registers
0x200–0x3FC
See datasheet addendum
0x400–0x4FC
See datasheet addendum
0x500–0xFFFF
Reserved
13.4.3 Indirect Data Register (INDDATA) – Base Address: 0x0FC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
WINDOW TO THE INDIRECT QUADLET POINTED TO BY INDADDR
SV01764
Bit 31..0:
2000 Apr 15
R/W
Quadlet of data pointed to by the indirect address n the INDADDR register (0x0F8). Note that the Indirect address
autoincrements on each read or write of the INDDATA register.
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PDI1394L41
13.5 Indirect Address Registers
The following registers are defined in the indirect address space. Access to these registers must be made through the Indirect Address
(INDADDR) and Indirect Data (INDDATA) registers.
13.5.1 Registers for FIFO Size Programming
Each FIFO can be programmed to a certain size with a granularity of 64 quadlets. The size is determined by the values of the base_fifo and
end_fifo fields of the FIFO Size registers. The following formula applies:
fifo_size = (end_fifo – base_fifo + 1) × 64 quadlets
The FIFO’s have been implemented on a single memory. The base_fifo and end_fifo fields are sued to determine the physical start and end
address of each FIFO inside the memory.
The start address of a FIFO is {fifo_addr[11:6] = base_fifo, fifo_addr[5:0] = 000000}.
The end address of a FIFO is {fifo_addr[11:6] = end_fifo, fifo_addr[5:0] = 111111}.
Note: The end_fifo must be larger than base_fifo and the hardware does not check for invalid values.
RRSPSIZE: base_fifo
000000
RRSP
000011
RRSPSIZE: end_fifo
RREQSIZE: base_fifo
000100
RREQ
000111
RREQSIZE: end_fifo
TRSPSIZE: base_fifo
001000
TRSP
001011
TRSPSIZE: end_fifo
TREQSIZE: base_fifo
TREQSIZE: end_fifo
001100
TRSP
001111 & 111111
IRXSIZE: base_fifo
IRXSIZE: end_fifo
010000
ITXSIZE: base_fifo
ITXSIZE: end_fifo
IRX
Fields in FIFO Size registers
011111
100000 & 000000
ITX
101111
fifo_bank
SV01765
Figure 34. Reset situation of size programmable FIFOs
13.5.1.1 Asynchronous Receive Response FIFO Size (RRSPSIZE) – Indirect Address: 0x100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
0
0
0
2
1
0
1
1
end_fifo
base_fifo
0
3
0
0
0
0
0
0
SV01766
Reset Value 0x00000003
Bit 31..14
R/W
Bit 13..8
R/W
Bit 7, 6
R/W
Bit 5..0
R/W
2000 Apr 15
Unused bits read ‘0’
base_fifo: Base address of the FIFO
Unused bits read ‘0’
end_fifo: End address of the FIFO
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PDI1394L41
13.5.1.2 Asynchronous Receive Request FIFO Size (RREQSIZE) – Indirect Address: 0x104
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
0
0
1
2
1
0
1
1
end_fifo
base_fifo
0
3
0
0
0
0
0
1
SV01767
Reset Value 0x00000407
Bit 31..14
R/W
Bit 13..8
R/W
Bit 7, 6
R/W
Bit 5..0
R/W
Unused bits read ‘0’
base_fifo: Base address of the FIFO
Unused bits read ‘0’
end_fifo: End address of the FIFO
13.5.1.3 Asynchronous Transmit Response FIFO Size (TRSPSIZE) – Indirect Address: 0x110
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
0
1
0
2
1
0
1
1
end_fifo
base_fifo
0
3
0
0
0
0
1
0
SV01768
Reset Value 0x0000080B
Bit 31..14
R/W
Bit 13..8
R/W
Bit 7, 6
R/W
Bit 5..0
R/W
Unused bits read ‘0’
base_fifo: Base address of the FIFO
Unused bits read ‘0’
end_fifo: End address of the FIFO
13.5.1.4 Asynchronous Transmit Request FIFO Size (TREQSIZE) – Indirect Address: 0x114
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
0
1
1
2
1
0
1
1
end_fifo
base_fifo
0
3
0
0
0
0
1
1
SV01769
Reset Value 0x00000C0F
Bit 31..14
R/W
Bit 13..8
R/W
Bit 7, 6
R/W
Bit 5..0
R/W
2000 Apr 15
Unused bits read ‘0’
base_fifo: Base address of the FIFO
Unused bits read ‘0’
end_fifo: End address of the FIFO
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Preliminary specification
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PDI1394L41
13.5.1.5 Isochronous Receiver FIFO Size (IRXSIZE) – Indirect Address: 0x120
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
1
0
0
2
1
0
1
1
end_fifo
base_fifo
0
3
0
0
0
1
1
1
SV01770
Reset Value 0x0000101F
Bit 31..14
R/W
Bit 13..8
R/W
Bit 7, 6
R/W
Bit 5..0
R/W
Unused bits read ‘0’
base_fifo: Base address of the FIFO
Unused bits read ‘0’
end_fifo: End address of the FIFO
13.5.1.6 Isochronous Transmitter FIFO Size (ITXSIZE) – Indirect Address: 0x130
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
0
0
0
2
1
0
1
1
end_fifo
base_fifo
1
3
0
0
1
0
1
1
SV01771
Reset Value 0x0000202F
Bit 31..14
R/W
Bit 13..8
R/W
Bit 7, 6
R/W
Bit 5..0
R/W
2000 Apr 15
Unused bits read ‘0’
base_fifo: Base address of the FIFO
Unused bits read ‘0’
end_fifo: End address of the FIFO
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PDI1394L41
14.0 DC ELECTRICAL CHARACTERISTICS
Table 9. DC Electrical Characteristics
SYMBOL
PARAMETER
VIL
LOW input voltage
VIH
HIGH input voltage
VIT1+
VIT1–
VIT2+
VIT2–
Input threshold, falling edge
LOW output voltage
VOH2
HIGH output voltage
VOL2
LOW output voltage
IOZ
IDD
NOTE
V
Pin categories 1, 2, 3
V
Pin categories 1, 2, 3
VDD/2 + 0.9
V
Pin categories 6, 8
LOW to HIGH transition
VDD/2 – 0.9
VDD/2 – 0.3
V
Pin categories 6, 8
HIGH to LOW transition
.42 VDD + 0.9
V
Pin category 9
LOW to HIGH transition
.42 VDD + 0.3
V
Pin category 9
HIGH to LOW transition
2.4
V
Pin category 1
IOH = 4mA
IOL = 4mA
V
Pin category 1
IOH = 4mA
IOL = 4mA
V
Pin categories 4, 6, 7
IOH = 4mA
0.4
V
Pin categories 4, 5, 6, 7
IOL = 4mA
±1
mA
Pin categories 2, 3
VI = 5.5V or 0V
200
mA
Pin category 8
VI = 5.5V or 0V
±5
mA
Pin categories 1, 7
VI = 5.5V or 0V
200
mA
Pin category 6
VI = 5.5V or 0V
150
mA
Under idle conditions, the
maximum value is 10 mA
Input threshold, rising edge
VOL1
UNIT
0.8
VDD/2 + 0.3
Input threshold, falling edge
HIGH output voltage
MAX
2.0
Input threshold, rising edge
VOH1
IL
MIN
0.4
2.4
Input
In
ut leakage current
3-State output
out ut current
Supply current
14.1 Pin Categories
Table 10. Pin Categories
Category 1:
Input/Output
Category 2:
Input
Category 3:
Input
Category 4:
Output
Category 5:
Output
Category 6:
Input/Output
Category 7:
Category 8:
Category 9:
HIF AD[7:0]
HIF A[8]
RESETN
CYCLEOUT
HIF INTN
PHY D[0:7]
LREQ
SCLK
LNKON
AVxSYNC
HIF CSN
CYCLEIN
CLK50
AV2ERR0
HIF WRN
AV2ERR1
PHY
CTL[0:1]
HIF WAIT
HIF MUX
LPS
AVxVALID
AVxENDPCK
HIF16BIT
AVxEMI
AV xD[7:0]
HIF ALE
1394MODE
AV1ERR0
AVxCLK
HIF RDN
AV1ERR1
AVxFSYNC
HIF D[15:8]
HIF A[7:0]
AVxSYSYNC
AVxSY
AVxREADY
2000 Apr 15
70
ISON
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
15.0 AC CHARACTERISTICS
GND = 0V, CL = 50pF
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
WAVEFORMS
Tamb = 0°C to +70°C
MIN
tPERIOD
(parallel
mode)
TYP
UNIT
MAX
AV clock period
Figure 36
41.67
ns
tSU
AV clock setup time
Figure 36
20
ns
tIH
AV clock input hold time
Figure 36
3
ns
tOD
AV clock output delay time
Figure 36
3
tWHIGH
AV clock pulse width HIGH
Figure 36
10
tWLOW
AV clock pulse width LOW
Figure 36
10
tPWFS
AVxFSYNC pulse width HIGH
Figure 37
200
tSUP
PHY-link setup time
Figure 38
6.0
ns
tHP
PHY-link hold time
Figure 38
0
ns
SCLK period
Figure 38
20.343
tSCLKPER
Note: CL = 20pF
20.345
24
ns
300
ns
20.347
ns
10.0
ns
tDP
PHY-link output delay
Figure 39
2.0
tAS
Host address setup time
Figure 40
0
ns
tAH
Host address hold time
Figure 40
0
ns
tCL
Host chip select pulse width LOW
Figure 40
115
ns
tCH
Host chip select pulse width HIGH
Figure 40
42
ns
tRP
Host read pulse width
Figure 40
115
ns
tACC
Host access time
Figure 40
tDH
Host data hold time
Figure 40
0
tDS
Host data setup time
Figure 40
0
tDZ
Host data bus release (Hi-Z)
Figure 40
115
ns
ns
ns
15
tWRP
Host write pulse width
Figure 40
tWAIT
WAIT output delay
Figure 40
tWWAIT
WAIT pulse width
Figure 40
20
ns
tCWH
CYCLEIN HIGH pulse width
Figure 41
200
ns
tCWL
CYCLEIN LOW pulse width
Figure 41
200
ns
tCP
CYCLEIN cycle period
Figure 41
125
tCD
CYCLEOUT cycle delay
Figure 42
tRESET
RESET_N pulse width LOW
tPWALE
ALE pulse width
2000 Apr 15
71
115
ns
ns
10
ns
µs
20
ns
Figure 43
10
µs
Figures 7, 8, 9, 10
20
ns
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
16.0 TIMING DIAGRAMS
16.1 AV Interface Operation
AVCLK
MESSAGE
AV D[7:0]
INVALID DATA
MESSAGE
INVALID DATA
MESSAGE
AVSYNC
AVVALID
AVERR[0]
ASSERTED IN THE EVENT OF A BUS PACKET CRC ERROR
AVERR[1]
ASSERTED IN THE EVENT OF A DATA BLOCK SEQUENCE ERROR
SV00240
Figure 35. AV Parallel Interface Operation Diagram
16.2 AV Interface Critical Timings
AVCLK
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
tWHIGH
AV D [7:0], AVVALID,
AVSYNC, AVENDPCK
SY, FSYNC, READY
VALID
tSU
tIH
tWLOW
tPERIOD
AV D [7:0], AVERR[1:0],
AVSYNC, AVVALID
VALID
tOD
SV00688
Figure 36. AV Interface Timing Diagram
AVxFSYNC
tPWFS
SV00890
Figure 37. AVxFSYNC Timing Diagram
2000 Apr 15
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PDI1394L41
16.3 PHY-Link Interface Critical Timings
tSCLKPER
SCLK
50%
tSUP
PHY D[0:7], PHY CTL[0:1]
50%
tHP
50%
50%
SV00919
Figure 38. PHY D[0:7], PHY CTL[0:1] Input Setup and Hold Timing Waveforms
SCLK
50%
tDP
PHY D[0:7], PHY CTL[0:1], LREQ
50%
SV00694
Figure 39. PHY D[0:7], PHY CTL[0:1], and LREQ Output-Delay Timing Waveforms
2000 Apr 15
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Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
16.4 Host Interface Critical Timings
READ
tAS
tAH
tAS
tAH
HIF A[7:0]
VALID
tCL
tCH
HIF CS_N
tRP
HIF RD_N
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
HIF D[7:0]
tAS
VALID
tACC
tDZ
A8
tPWWAIT
tWAIT
WAIT
WRITE
tWRP
HIF WR_N
HIF D[7:0]
VALID
tDS
tDH
A8
WAIT
tWAIT
Note: Wait line asserts only during Read and Write cycles in which A8 is asserted.
SV01776
Figure 40. Host Interface Timing Waveforms
16.5 CYCLEIN/CYCLEOUT Timings
CYCLEIN
50%
50%
tCWH
50%
tCWL
tCP
SV00696
Figure 41. CYCLEIN Waveform
2000 Apr 15
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1394 content protection AV link layer controller
SCLK
PDI1394L41
50%
50%
tCD
tCD
CYCLEIN
CYCLEOUT
50%
50%
SV00697
Figure 42. CYCLEOUT Waveforms
16.6 RESET Timings
RESET_N
50%
50%
tRESET
SV00698
Figure 43. RESET_N Waveform
2000 Apr 15
75
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Preliminary specification
1394 content protection AV link layer controller
LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm
2000 Apr 15
76
PDI1394L41
SOT486-1
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
NOTES
2000 Apr 15
77
PDI1394L41
Philips Semiconductors
Preliminary specification
1394 content protection AV link layer controller
PDI1394L41
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 04-00
Document order number:
2000 Apr 15
78
9397 750 07108