74AHC2G241; 74AHCT2G241 Dual buffer/line driver; 3-state Rev. 02 — 13 January 2009 Product data sheet 1. General description The 74AHC2G241; 74AHCT2G241 is a high-speed Si-gate CMOS device. The 74AHC2G241; 74AHCT2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state. A LOW level at pin 2OE causes output 2Y to assume a high-impedance OFF-state. Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise and fall times. 2. Features n Symmetrical output impedance n High noise immunity n ESD protection: u HBM JESD22-A114E: exceeds 2000 V u MM JESD22-A115-A: exceeds 200 V u CDM JESD22-C101C: exceeds 1000 V n Low power dissipation n Balanced propagation delays n Multiple package options n Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number 74AHC2G241DP Package Temperature range Name Description Version −40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm −40 °C to +125 °C XSON8U plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; UTLP based; body 3 × 2 × 0.5 mm 74AHCT2G241DP 74AHC2G241DC 74AHCT2G241DC 74AHC2G241GD 74AHCT2G241GD 74AHC2G241; 74AHCT2G241 NXP Semiconductors Dual buffer/line driver; 3-state 4. Marking Table 2. Marking Type number Marking code 74AHC2G241DP A241 74AHCT2G241DP C241 74AHC2G241DC A41 74AHCT2G241DC C41 74AHC2G241GD A41 74AHCT2G241GD C41 5. Functional diagram 1 1OE 2 1A 2 1Y 6 1 2OE 7 1 6 EN1 5 2A 5 2Y 3 7 2 001aaa409 Fig 1. 3 EN2 001aaa408 Logic symbol Fig 2. IEC logic symbol 6. Pinning information 6.1 Pinning 74AHC2G241 74AHCT2G241 74AHC2G241 74AHCT2G241 1OE 1 8 VCC 1A 2 7 2OE 2Y 3 6 1Y GND 4 5 2A 1OE 1 8 VCC 1A 2 7 2OE 2Y 3 6 1Y GND 4 5 2A 001aaj392 Transparent top view 001aaj391 Fig 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 4. Pin configuration SOT996-2 (XSON8U) 74AHC_AHCT2G241_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 January 2009 2 of 16 74AHC2G241; 74AHCT2G241 NXP Semiconductors Dual buffer/line driver; 3-state 6.2 Pin description Table 3. Pin description Symbol Pin Description 1OE 1 output enable input (active LOW) 1A 2 data input 2Y 3 data output GND 4 ground (0 V) 2A 5 data input 1Y 6 data output 2OE 7 output enable input (active HIGH) VCC 8 supply voltage 7. Functional description Table 4. Function table[1] Input Output Input Output 1OE 1A 1Y 2OE 2A 2Y L L L H L L L H H H H H H X Z L X Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage VI input voltage IIK input clamping current VI < −0.5 V [1] IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] IO output current −0.5 V < VO < VCC + 0.5 V Min Max Unit −0.5 +7.0 V −0.5 +7.0 V −20 - mA - ±20 mA - ±25 mA ICC supply current - 75 mA IGND ground current −75 - mA Tstg storage temperature −65 +150 °C - 250 mW Ptot total power dissipation Tamb = −40 °C to +125 °C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. For XSON8U package: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 74AHC_AHCT2G241_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 January 2009 3 of 16 74AHC2G241; 74AHCT2G241 NXP Semiconductors Dual buffer/line driver; 3-state 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74AHC2G241 Min Typ 74AHCT2G241 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V VI input voltage 0 - 5.5 0 - 5.5 V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C ∆t/∆V input transition rise and fall rate VCC = 3.3 V ± 0.3 V - - 100 - - - ns/V VCC = 5.0 V ± 0.5 V - - 20 - - 20 ns/V 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V 74AHC2G241 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = −50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = −50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = −4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V IO = −8.0 mA; VCC = 4.5 V 3.94 - - 3.8 - 3.70 - V LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V IOZ OFF-state VI = VCC or GND; output current VCC = 5.5 V - - 0.25 - 2.5 - 10 µA II input leakage current - - 0.1 - 1.0 - 2.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 1.0 - 10 - 40 µA VI = 5.5 V or GND; VCC = 0 V to 5.5 V 74AHC_AHCT2G241_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 January 2009 4 of 16 74AHC2G241; 74AHCT2G241 NXP Semiconductors Dual buffer/line driver; 3-state Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter CI 25 °C Conditions input capacitance −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 1.5 10 - 10 - 10 pF 74AHCT2G241 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −50 µA 4.4 4.5 - 4.4 - 4.4 - V 3.94 - - 3.8 - 3.70 - V - 0 0.1 - 0.1 - 0.1 V - - 0.36 - 0.44 - 0.55 V IO = −8.0 mA VOL LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 µA IO = 8.0 mA IOZ OFF-state VI = VCC or GND; output current VCC = 5.5 V - - 0.25 - 2.5 - 10 µA II input leakage current - - 0.1 - 1.0 - 2.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 1.0 - 10 - 40 µA ∆ICC additional per input pin; VI = 3.4 V; supply current other inputs at VCC or GND; IO = 0 A; VCC = 5.5 V - - 1.35 - 1.5 - 1.5 mA CI input capacitance - 1.5 10 - 10 - 10 pF VI = 5.5 V or GND; VCC = 0 V to 5.5 V 11. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure 8. Symbol Parameter 25 °C Conditions Min Typ CL = 15 pF - CL = 50 pF - CL = 15 pF CL = 50 pF −40 °C to +85 °C −40 °C to +125 °C Unit Max Min Max Min Max 4.7 8.0 6.6 11.5 1.0 9.5 1.0 11.5 ns 1.0 13.0 1.0 14.5 ns - 3.4 5.5 1.0 6.5 1.0 7.0 ns - 4.7 7.5 1.0 8.5 1.0 9.5 ns 74AHC2G241 tpd propagation delay nA to nY; see Figure 5 [1] VCC = 3.0 V to 3.6 V [2] VCC = 4.5 V to 5.5 V [3] 74AHC_AHCT2G241_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 January 2009 5 of 16 NXP Semiconductors 74AHC2G241; 74AHCT2G241 Dual buffer/line driver; 3-state Table 8. Dynamic characteristics …continued GND = 0 V; for test circuit see Figure 8. Symbol Parameter ten enable time 25 °C Conditions Min Typ Max Min Max Min Max - 5.0 8.0 1.0 9.5 1.0 11.5 ns - 6.9 11.5 1.0 13.0 1.0 14.5 ns CL = 15 pF - 3.6 5.1 1.0 6.0 1.0 6.5 ns CL = 50 pF - 4.9 7.5 1.0 8.5 1.0 9.5 ns CL = 15 pF - 4.9 8.0 1.0 9.5 1.0 10.0 ns CL = 50 pF - 7.0 11.5 1.0 13.0 1.0 14.5 ns - 3.6 5.6 1.0 6.3 1.0 7.0 ns - 5.4 8.0 1.0 9.0 1.0 9.5 ns - 6.0 9.7 1.0 11.5 1.0 12.5 ns - 8.3 13.2 1.0 15.0 1.0 16.5 ns - 4.1 6.8 1.0 8.0 1.0 8.5 ns - 5.7 8.8 1.0 10.0 1.0 11.0 ns - 6.3 9.7 1.0 11.5 1.0 12.5 ns - 9.0 13.2 1.0 15.0 1.0 16.5 ns - 4.3 6.8 1.0 8.0 1.0 8.5 ns - 6.1 8.8 1.0 10.0 1.0 11.0 ns - 10 - - - - - pF CL = 15 pF - 3.4 5.5 1.0 6.5 1.0 7.0 ns CL = 50 pF - 4.7 7.5 1.0 8.5 1.0 9.5 ns 1OE to 1Y; see Figure 6 [1] VCC = 3.0 V to 3.6 V [2] CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V [3] 2OE to 2Y; see Figure 7 [1] VCC = 3.0 V to 3.6 V [2] VCC = 4.5 V to 5.5 V [3] CL = 15 pF CL = 50 pF tdis disable time 1OE to 1Y; see Figure 6 [1] VCC = 3.0 V to 3.6 V [2] CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V [3] CL = 15 pF CL = 50 pF 2OE to 2Y; see Figure 7 [1] VCC = 3.0 V to 3.6 V [2] CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V [3] CL = 15 pF CL = 50 pF CPD −40 °C to +85 °C −40 °C to +125 °C Unit power per buffer; dissipation CL = 50 pF; fi = 1 MHz; capacitance VI = GND to VCC [4] 74AHCT2G241 tpd propagation delay nA to nY; see Figure 5 [1] VCC = 4.5 V to 5.5 V [3] 74AHC_AHCT2G241_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 January 2009 6 of 16 NXP Semiconductors 74AHC2G241; 74AHCT2G241 Dual buffer/line driver; 3-state Table 8. Dynamic characteristics …continued GND = 0 V; for test circuit see Figure 8. Symbol Parameter ten enable time 25 °C Conditions 1OE to 1Y; see Figure 6 [1] VCC = 4.5 V to 5.5 V [3] CL = 15 pF CL = 50 pF 2OE to 2Y; see Figure 7 [1] VCC = 4.5 V to 5.5 V [3] CL = 15 pF CL = 50 pF tdis disable time 1OE to 1Y; see Figure 6 [1] VCC = 4.5 V to 5.5 V [3] CL = 15 pF CL = 50 pF 2OE to 2Y; see Figure 7 [1] VCC = 4.5 V to 5.5 V [3] CL = 15 pF CL = 50 pF CPD power per buffer; dissipation CL = 50 pF; fi = 1 MHz; capacitance VI = GND to VCC [4] −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 3.9 5.1 1.0 6.0 1.0 6.5 ns - 5.1 7.5 1.0 8.5 1.0 9.5 ns - 3.4 5.6 1.0 6.3 1.0 6.5 ns - 4.8 7.5 1.0 9.0 1.0 9.5 ns - 4.5 6.8 1.0 8.0 1.0 8.5 ns - 6.1 8.8 1.0 10.0 1.0 11.0 ns - 4.0 6.8 1.0 8.0 1.0 8.5 ns - 5.7 8.8 1.0 10.0 1.0 11.0 ns - 10 - - - - - pF [1] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [2] Typical values are measured at VCC = 3.3 V. [3] Typical values are measured at VCC = 5.0 V. [4] CPD is used to determine the dynamic power dissipation PD (µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts. 74AHC_AHCT2G241_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 January 2009 7 of 16 74AHC2G241; 74AHCT2G241 NXP Semiconductors Dual buffer/line driver; 3-state 12. Waveforms VI VM nA input GND tPHL tPLH VOH VM nY output VOL mna230 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. The input (nA) to output (nY) propagation delays VI 1OE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VOL + 0.3 V VOL tPHZ VOH tPZH VOH − 0.3 V output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled 001aaa411 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. The input (1OE) to output 1Y enable and disable times 74AHC_AHCT2G241_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 January 2009 8 of 16 74AHC2G241; 74AHCT2G241 NXP Semiconductors Dual buffer/line driver; 3-state VI 2OE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VOL + 0.3 V VOL tPHZ VOH tPZH VOH − 0.3 V output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled 001aaa410 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. Table 9. The input (2OE) to output 2Y enable and disable times Measurement points Type Input Output VM VM 74AHC2G241 0.5VCC 0.5VCC 74AHCT2G241 1.5 V 0.5VCC 74AHC_AHCT2G241_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 January 2009 9 of 16 74AHC2G241; 74AHCT2G241 NXP Semiconductors Dual buffer/line driver; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT RT CL 001aad983 Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 8. Table 10. Test circuit for measuring switching times Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74AHC2G241 VCC ≤ 3 ns 15 pF, 50 pF 1 kΩ open GND VCC 74AHCT2G241 3V ≤ 3 ns 15 pF, 50 pF 1 kΩ open GND VCC 74AHC_AHCT2G241_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 January 2009 10 of 16 74AHC2G241; 74AHCT2G241 NXP Semiconductors Dual buffer/line driver; 3-state 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 Fig 9. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Package outline SOT505-2 (TSSOP8) 74AHC_AHCT2G241_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 January 2009 11 of 16 74AHC2G241; 74AHCT2G241 NXP Semiconductors Dual buffer/line driver; 3-state VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 MO-187 Fig 10. Package outline SOT765-1 (VSSOP8) 74AHC_AHCT2G241_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 January 2009 12 of 16 74AHC2G241; 74AHCT2G241 NXP Semiconductors Dual buffer/line driver; 3-state XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm B D SOT996-2 A A E A1 detail X terminal 1 index area e1 v w b e L1 1 4 8 5 C C A B C M M y y1 C L2 L X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 b D E e e1 L L1 L2 v w y y1 mm 0.5 0.05 0.00 0.35 0.15 2.1 1.9 3.1 2.9 0.5 1.5 0.5 0.3 0.15 0.05 0.6 0.4 0.1 0.05 0.05 0.1 REFERENCES OUTLINE VERSION IEC SOT996-2 --- JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-18 07-12-21 Fig 11. Package outline SOT996-2 (XSON8U) 74AHC_AHCT2G241_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 January 2009 13 of 16 74AHC2G241; 74AHCT2G241 NXP Semiconductors Dual buffer/line driver; 3-state 14. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT2G241_2 20090113 Product data sheet - 74AHC_AHCT2G241_1 Modifications: 74AHC_AHCT2G241_1 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Added type number 74AHC2G241GD and 74AHCT2G241GD (XSON8U package). 20040310 Product data 74AHC_AHCT2G241_2 Product data sheet - - © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 January 2009 14 of 16 NXP Semiconductors 74AHC2G241; 74AHCT2G241 Dual buffer/line driver; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74AHC_AHCT2G241_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 January 2009 15 of 16 NXP Semiconductors 74AHC2G241; 74AHCT2G241 Dual buffer/line driver; 3-state 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 13 January 2009 Document identifier: 74AHC_AHCT2G241_2