74ALVC541 Octal buffer/line driver; 3-state Rev. 02 — 5 November 2007 Product data sheet 1. General description The 74ALVC541 is an octal non-inverting buffer/line drivers with 3-state bus compatible outputs. The 3-state outputs are controlled by the output enable inputs OE0 and OE1. A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. 2. Features ■ Wide supply voltage range from 1.65 V to 3.6 V ■ Complies with JEDEC standard: ◆ JESD8-7 (1.65 V to 1.95 V) ◆ JESD8-5 (2.3 V to 2.5 V) ◆ JESD8B/JESD36 (2.7 V to 3.6 V) ■ 3.6 V tolerant inputs/outputs ■ CMOS low power consumption ■ Direct interface with TTL levels (2.7 V to 3.6 V) ■ Power-down mode ■ Latch-up performance exceeds 250 mA ■ ESD protection: ◆ HBM JESD22-A114E exceeds 2000 V ◆ MM JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVC541D −40 °C to +85 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74ALVC541PW −40 °C to +85 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74ALVC541BQ −40 °C to +85 °C DHVQFN20 plastic dual-in-line compatible thermal enhanced very thin quad flat package no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm SOT764-1 74ALVC541 NXP Semiconductors Octal buffer/line driver; 3-state 4. Functional diagram 2 3 4 5 6 A0 Y0 A1 Y1 A2 Y2 A3 Y3 A4 Y4 18 17 16 15 14 1 & 19 7 8 9 A5 A6 A7 Y5 Y6 Y7 13 12 11 OE0 1 19 Fig 1. Logic symbol OE1 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 mna179 mna180 Fig 2. IEC logic symbol 74ALVC541_2 Product data sheet EN © NXP B.V. 2007. All rights reserved. Rev. 02 — 5 November 2007 2 of 15 74ALVC541 NXP Semiconductors Octal buffer/line driver; 3-state 5. Pinning information 5.1 Pinning 1 terminal 1 index area 74ALVC541 20 VCC OE0 74ALVC541 A0 2 19 OE1 A1 3 18 Y0 A2 4 17 Y1 OE0 1 A0 2 20 VCC 19 OE1 A1 3 18 Y0 A3 5 16 Y2 A2 4 17 Y1 A4 6 15 Y3 A3 5 16 Y2 A5 7 A4 6 15 Y3 A6 8 A5 7 14 Y4 A6 8 13 Y5 A7 9 A7 9 12 Y6 GND 10 11 Y7 14 Y4 GND(1) 13 Y5 Y7 11 GND 10 12 Y6 001aah061 Transparent top view 001aah060 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 3. Pin configuration SO20, TSSOP20 Fig 4. Pin configuration DHVQFN20 5.2 Pin description Table 2. Pin description Symbol Pin Description OE0 1 output enable input (active LOW) A[0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input GND 10 ground (0 V) Y[0:7] 18, 17, 16, 15, 14, 13, 12, 11 data output OE1 19 output enable input (active LOW) VCC 20 supply voltage 74ALVC541_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 5 November 2007 3 of 15 74ALVC541 NXP Semiconductors Octal buffer/line driver; 3-state 6. Functional description Table 3. Functional table[1] Control Input Output OE0 OE1 An Yn L L L L L L H H X H X Z H X X Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI Conditions Min Max Unit supply voltage −0.5 +4.6 V input voltage −0.5 +4.6 V −50 - mA mA IIK input clamping current VI < 0 V IOK output clamping current VO > VCC or VO < 0 V output voltage VO [1] - ±50 output HIGH or LOW state [2] −0.5 VCC + 0.5 V output 3-state [2] −0.5 +4.6 V power-down mode, VCC = 0 V [3] −0.5 +4.6 V - ±50 mA IO output current VO = 0 V to VCC ICC supply current - 100 mA IGND ground current −100 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation Tamb = −40 °C to +85 °C SO20 package [4] - 500 mW TSSOP20 package [5] - 500 mW DHVQFN20 package [6] - 500 mW [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] When VCC = 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation. [4] Ptot derates linearly with 8 mW/K above 70 °C. [5] Ptot derates linearly with 5.5 mW/K above 60 °C. [6] Ptot derates linearly with 4.5 mW/K above 60 °C. 74ALVC541_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 5 November 2007 4 of 15 74ALVC541 NXP Semiconductors Octal buffer/line driver; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC Conditions Min Max Unit supply voltage 1.65 3.6 V VI input voltage 0 3.6 V VO output voltage output HIGH or LOW state 0 VCC V output 3-state 0 3.6 V power-down mode, VCC = 0 V 0 3.6 V −40 +85 °C Tamb ambient temperature ∆t/∆V input transition rise and fall rate VCC = 1.65 V to 2.7 V - 20 ns/V VCC = 2.7 V to 3.6 V - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter −40 °C to +85 °C Conditions Min VIH VIL VOH HIGH-level input voltage LOW-level input voltage Max 0.65 × VCC - - V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 1.65 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC − 0.2 - - V VCC = 1.65 V to 1.95 V 0.35 × VCC V HIGH-level output voltage VI = VIH or VIL LOW-level output voltage IO = 6 mA ; VCC = 1.65 V 1.25 - - V IO = 12 mA; VCC = 2.3 V 1.8 - - V IO = 18 mA; VCC = 2.3 V 1.7 - - V IO = 12 mA; VCC = 2.7 V 2.2 - - V IO = 18 mA; VCC = 3.0 V 2.4 - - V IO = 24 mA; VCC = 3.0 V 2.2 - - V - - 0.2 V VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 3.6 V IOZ Unit VCC = 2.3 V to 2.7 V IO = 100 µA; VCC = 1.65 V to 3.6 V VOL Typ[1] OFF-state output current IO = −6 mA ; VCC = 1.65 V - - 0.3 V IO = −12 mA; VCC = 2.3 V - - 0.4 V IO = −18 mA; VCC = 2.3 V - - 0.6 V IO = −12 mA; VCC = 2.7 V - - 0.4 V IO = −18 mA; VCC = 3.0 V - - 0.4 V IO = −24 mA; VCC = 3.0 V - - 0.55 V - ±0.1 ±10.0 µA VI = VIH or VIL; VO = VCC or GND; VCC = 3.6 V 74ALVC541_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 5 November 2007 5 of 15 74ALVC541 NXP Semiconductors Octal buffer/line driver; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter −40 °C to +85 °C Conditions Min Max - ±0.1 ±5.0 µA II input leakage current IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - ±0.1 ±10.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 3.6 V - 0.2 10 µA ∆ICC additional supply current per input pin; VCC = 3.0 V to 3.6 V; VI = VCC − 0.6 V; IO = 0 A; - 5 750 µA CI input capacitance - 3.5 - pF [1] VI = VCC or GND; VCC = 3.6 V Unit Typ[1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol tpd ten Parameter propagation delay enable time −40 °C to +85 °C Conditions Min Max VCC = 1.65 V to 1.95 V 1.0 3.0 4.6 ns VCC = 2.3 V to 2.7 V 1.0 2.2 3.3 ns VCC = 2.7 V 1.0 2.5 3.3 ns VCC = 3.0 V to 3.6 V 1.0 2.3 3.0 ns VCC = 1.65 V to 1.95 V 1.0 4.2 7.5 ns VCC = 2.3 V to 2.7 V 1.0 3.3 5.4 ns VCC = 2.7 V 1.0 3.7 5.8 ns 1.0 3.3 4.9 ns An to Yn; see Figure 5 OEn to Yn; see Figure 6 [2] [2] VCC = 3.0 V to 3.6 V tdis disable time OEn to Yn; see Figure 6 [2] VCC = 1.65 V to 1.95 V 1.0 4.8 7.5 ns VCC = 2.3 V to 2.7 V 1.0 3.1 4.5 ns VCC = 2.7 V 1.0 3.1 4.8 ns VCC = 3.0 V to 3.6 V 1.0 2.9 4.6 ns 74ALVC541_2 Product data sheet Unit Typ[1] © NXP B.V. 2007. All rights reserved. Rev. 02 — 5 November 2007 6 of 15 74ALVC541 NXP Semiconductors Octal buffer/line driver; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol CPD Parameter power dissipation capacitance −40 °C to +85 °C Conditions Unit Min Typ[1] Max outputs enabled - 25 - pF outputs disabled - 0 - pF per buffer; VI = GND to VCC; VCC = 3.3 V [3] [1] All typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V and 3.3 V. [2] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 11. Waveforms VI VM An input GND t PHL t PLH VOH VM Yn output VOL mna901 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Propagation delay input (An) to output (Yn) 74ALVC541_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 5 November 2007 7 of 15 74ALVC541 NXP Semiconductors Octal buffer/line driver; 3-state VI OEn input VM GND t PLZ t PZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled mna902 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Enable and disable times Table 8. Measurement points Supply voltage Input Output VCC VI VM VM VX VY 1.65 V to 1.95 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH − 0.15 V 2.3 V to 2.7 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH − 0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 74ALVC541_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 5 November 2007 8 of 15 74ALVC541 NXP Semiconductors Octal buffer/line driver; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistor Fig 7. Load circuitry for switching times Table 9. Test data Supply voltage Input VCC VI tr, tf Load CL RL VEXT tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open 2 × VCC GND 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × VCC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 6 GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 6 GND 74ALVC541_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 5 November 2007 9 of 15 74ALVC541 NXP Semiconductors Octal buffer/line driver; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 8. Package outline SOT163-1 (SO20) 74ALVC541_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 5 November 2007 10 of 15 74ALVC541 NXP Semiconductors Octal buffer/line driver; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. Package outline SOT360-1 (TSSOP20) 74ALVC541_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 5 November 2007 11 of 15 74ALVC541 NXP Semiconductors Octal buffer/line driver; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 10. Package outline SOT764-1 (DHVQFN20) 74ALVC541_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 5 November 2007 12 of 15 74ALVC541 NXP Semiconductors Octal buffer/line driver; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged-Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVC541_2 20071105 Product data sheet - 74ALVC541_1 Modifications: 74ALVC541_1 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN20 package added. Section 8: derating values added for DHVQFN20 package. Section 12: outline drawing added for DHVQFN20 package. 20020226 Product specification 74ALVC541_2 Product data sheet - - © NXP B.V. 2007. All rights reserved. Rev. 02 — 5 November 2007 13 of 15 74ALVC541 NXP Semiconductors Octal buffer/line driver; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74ALVC541_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 5 November 2007 14 of 15 74ALVC541 NXP Semiconductors Octal buffer/line driver; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 5 November 2007 Document identifier: 74ALVC541_2