DISCRETE SEMICONDUCTORS DATA SHEET BSH301 Dual N-channel enhancement mode MOS transistor Objective specification 1999 Apr 06 Philips Semiconductors Objective specification Dual N-channel enhancement mode MOS transistor BSH301 FEATURES • 40 mΩ on-state resistance at 2.5 V gate drive 8 handbook, halfpage 5 d1 s2 s2 g2 d1 s1 s1 g1 • RDSon rating down to 1.8 V • ESD gate protection. APPLICATIONS • Li-Ion safety switch • Power management. 1 DESCRIPTION 4 MAM423 Fig.1 Simplified outline (SOT530) and symbol. Two N-channel enhancement mode MOS transistors in an 8-pin plastic TSSOP8 package. CAUTION PINNING SOT530 (TSSOP8) PIN SYMBOL 1 d1 drain 1 2 s1 source 1 3 s1 source 1 4 g1 gate 1 5 g2 gate 2 6 s2 source 2 7 s2 source 2 8 d1 drain 1 The device is supplied in an antistatic package. The gate inputs must be protected against static discharge during transport or handling. DESCRIPTION QUICK REFERENCE DATA In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. − 20 V − 1 V − ±8 V VDS = VGS; ID = 1 mA 0.4 − V TS = 80 °C; note 1 − 5 A drain-source on-state resistance VGS = 2.5 V; ID = 3.5 A − 0.04 Ω total power dissipation TS = 80 °C − 1.75 W VDS drain-source voltage (DC) VSD source-drain diode forward voltage VGS gate-source voltage (DC) VGSth gate-source threshold voltage ID drain current (DC) RDSon Ptot VGD = 0; IS = 1.25 A Note 1. TS is the temperature at the soldering of the drain lead. Full Data Sheet will appear: on WWW (Internet; details in front section/back of this HB/CD-ROM) or updated Loose leaf 1999 Apr 06 UNIT 2 Philips Semiconductors Objective specification Dual N-channel enhancement mode MOS transistor BSH301 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per FET VDS drain-source voltage (DC) − 20 V VGS gate-source voltage (DC) − ±8 V ID drain current (DC) TS = 80 °C; note 1 − 5 A IDM peak drain current note 2 − 20 A Ptot total power dissipation TS = 80 °C; note 3 − 1.75 W Tamb = 25 °C; note 4 − 1.85 W Tamb = 25 °C; note 5 − 0.95 W Tstg storage temperature −55 +150 °C Tj operating junction temperature −55 +150 °C Source-drain diode IS source current (DC) TS = 80 °C − 1.75 A ISM peak pulsed source current note 2 − 7 A Notes 1. TS is the temperature at the soldering point of the drain lead. 2. Pulse width and duty cycle limited by maximum junction temperature. 3. Maximum permissible dissipation per transistor. Both devices may be loaded up to 3.5 W at the same time. 4. Maximum permissible dissipation per transistor. Device mounted on a printed-circuit board with Rth a-tp (ambient to tie-point) of 27.5 °C/W. 5. Maximum permissible dissipation per transistor. Device mounted on a printed-circuit board with Rth a-tp (ambient to tie-point) of 90 °C/W. 1999 Apr 06 3 Philips Semiconductors Objective specification Dual N-channel enhancement mode MOS transistor BSH301 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. 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