INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4510
BCD up/down counter
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
BCD up/down counter
74HC/HCT4510
parallel load input (PL), four parallel inputs (D0 to D3), four
parallel outputs (Q0 to Q3), an active LOW terminal count
output (TC), and an overriding asynchronous master reset
input (MR).
FEATURES
• Output capability: standard
• ICC category: MSI
Information on D0 to D3 is loaded into the counter while PL
is HIGH, independent of all other input conditions except
the MR input, which must be LOW. With PL LOW, the
counter changes on the LOW-to-HIGH transition of CP if
CE is LOW. UP/DN determines the direction of the count,
HIGH for counting up, LOW for counting down. When
counting up, TC is LOW when Q0 and Q3 are HIGH and CE
is LOW. When counting down, TC is LOW when Q0 to Q3
and CE are LOW. A HIGH on MR resets the counter (Q0 to
Q3 = LOW) independent of all other input conditions.
GENERAL DESCRIPTION
The 74HC/HCT4510 are high-speed Si-gate CMOS
devices and are pin compatible with the “4510” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4510 are edge-triggered synchronous
up/down BCD counters with a clock input (CP), an
up/down count control input (UP/DN), an active LOW
count enable input (CE), an asynchronous active HIGH
Logic equation for terminal count: TC = CE . {(UP/DN) . Q . Q +(UP/DN) . Q 0 . Q 1 . Q 2 . Q 3 }
0
3
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
tPHL/ tPLH
propagation delay CP to Qn
fmax
maximum clock frequency
CI
input capacitance
CPD
power dissipation capacitance per package
HCT
CL = 15 pF; VCC = 5 V 21
23
ns
57
58
MHz
3.5
3.5
pF
50
53
pF
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC. For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
BCD up/down counter
74HC/HCT4510
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
PL
parallel load input (active HIGH)
4, 12, 13, 3
D0 to D3
parallel inputs
5
CE
count enable input (active LOW)
6, 11, 14, 2
Q0 to Q3
parallel outputs
7
TC
terminal count output (active LOW)
8
GND
ground (0 V)
9
MR
asynchronous master reset input (active HIGH)
10
UP/DN
up/down control input
15
CP
clock input (LOW-to-HIGH, edge-triggered)
16
VCC
positive supply voltage
Fig.1 Pin configuration.
December 1990
Fig.2 Logic symbol.
3
Fig.3 IEC logic symbol.
Philips Semiconductors
Product specification
BCD up/down counter
74HC/HCT4510
FUNCTION TABLE
MR
PL
UP/DN
CE
CP
MODE
L
L
L
L
H
H
L
L
L
X
X
X
L
H
X
X
H
L
L
X
X
X
↑
↑
X
parallel load
no change
count down
count up
reset
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH clock transition
Fig.4 Functional diagram.
Fig.5 Timing diagram.
December 1990
4
Philips Semiconductors
Product specification
BCD up/down counter
74HC/HCT4510
Fig.6 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
BCD up/down counter
74HC/HCT4510
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
−40 to +85
+25
min.
typ.
max. min.
max.
−40 to +125
min.
UNIT
VCC WAVEFORMS
(V)
max.
tPHL/ tPLH
propagation delay
CP to Qn
69
25
20
220
44
37
275
55
47
330
66
56
ns
2.0
4.5
6.0
Fig.7
tPHL
propagation delay
MR to Qn
63
23
18
210
42
36
265
53
45
315
63
54
ns
2.0
4.5
6.0
Fig.10
tPLH/ tPHL
propagation delay
PL to Qn
77
28
22
250
50
43
315
63
54
375
75
64
ns
2.0
4.5
6.0
Fig.9
tPHL/ tPLH
propagation delay
CP to TC
74
27
22
260
52
44
325
65
55
395
78
66
ns
2.0
4.5
6.0
Fig.7
tPHL/ tPLH
propagation delay
CE to TC
36
13
10
125
25
21
155
31
26
190
38
32
ns
2.0
4.5
6.0
Fig.8
tPLH
propagation delay
MR to TC
69
25
20
235
47
40
295
59
50
355
71
60
ns
2.0
4.5
6.0
Fig.10
tPHL/ tPLH
propagation delay
PL to TC
91
33
26
300
60
51
375
75
64
450
90
77
ns
2.0
4.5
6.0
Fig.9
tTHL/ tTLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.9
tW
pulse width CP, CE
HIGH or LOW
80
16
14
25
9
7
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.7
tW
parallel load pulse
width
HIGH
80
16
14
22
8
7
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.10
tW
master reset pulse
width
HIGH
100
20
17
19
7
6
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.10
December 1990
6
Philips Semiconductors
Product specification
BCD up/down counter
74HC/HCT4510
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
+25
min.
typ.
−40 to +85
max. min.
max.
−40 to +125
min.
UNIT
VCC WAVEFORMS
(V)
max.
trem
removal time
MR to CP
80
16
14
28
10
8
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.10
trem
removal time
PL to CP
80
16
14
14
5
4
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.10
tsu
set-up time
UP/DN to CP
100
20
17
30
11
9
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.8
tsu
set-up time
CE to CP
100
20
17
19
7
6
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.8
tsu
set-up time
Dn to PL
100
20
17
17
6
5
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.11
th
hold time
CE to CP
5
5
5
0
0
0
5
5
5
5
5
5
ns
2.0
4.5
6.0
Fig.8
th
hold time
Dn to PL
3
3
3
−6
−2
−2
3
3
3
3
3
3
ns
2.0
4.5
6.0
Fig.11
th
hold time
UP/DN to CP
0
0
0
−19
−7
−6
0
0
0
0
0
0
ns
2.0
4.5
6.0
Fig.8
fmax
maximum clock pulse 6.0
frequency
30
35
17
52
62
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.7
December 1990
7
Philips Semiconductors
Product specification
BCD up/down counter
74HC/HCT4510
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below
INPUT
UNIT LOAD COEFFICIENT
Dn
PL, CE
UP/DN
CP
MR
0.75
1.00
1.00
1.25
1.50
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
−40 to +85
+25
min.
typ.
max. min.
max.
−40 to +125
min.
UNIT
VCC
(V)
WAVEFORMS
max.
tPHL/ tPLH
propagation delay
CP to Qn
27
50
63
75
ns
4.5
Fig.7
tPHL
propagation delay
MR to Qn
25
42
53
63
ns
4.5
Fig.10
tPLH/ tPHL
propagation delay
PL to Qn
28
53
66
80
ns
4.5
Fig.9
tPHL/ tPLH
propagation delay
CP to TC
29
58
73
87
ns
4.5
Fig.7
tPHL/ tPLH
propagation delay
CE to TC
17
31
39
47
ns
4.5
Fig.8
tPLH
propagation delay
MR to TC
31
50
63
75
ns
4.5
Fig.10
tPHL/ tPLH
propagation delay
PL to TC
35
68
85
102
ns
4.5
Fig.10
tTHL/ tTLH
output transition time
7
15
ns
4.5
Fig.9
tW
pulse width CP, CE
HIGH or LOW
16
9
20
24
ns
4.5
Fig.7
tW
parallel load pulse
width
HIGH
16
6
20
24
ns
4.5
Fig.10
tW
master reset pulse
width
HIGH
20
4
25
30
ns
4.5
Fig.10
December 1990
19
8
22
Philips Semiconductors
Product specification
BCD up/down counter
74HC/HCT4510
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
−40 to +85
+25
min.
typ.
max. min.
−40 to +125
max.
min.
UNIT
VCC
(V)
WAVEFORMS
max.
trem
removal time
MR to CP
23
13
29
35
ns
4.5
Fig.10
trem
removal time
PL to CP
17
10
21
26
ns
4.5
Fig.10
tsu
set-up time
UP/DN to CP
20
12
25
30
ns
4.5
Fig.8
tsu
set-up time
CE to CP
20
6
25
30
ns
4.5
Fig.8
tsu
set-up time
Dn to PL
20
6
25
30
ns
4.5
Fig.11
th
hold time
CE to CP
5
0
5
5
ns
4.5
Fig.8
th
hold time
Dn to PL
5
0
5
5
ns
4.5
Fig.11
th
hold time
UP/DN to CP
0
−5
0
0
ns
4.5
Fig.8
fmax
maximum clock pulse 30
frequency
53
24
20
MHz
4.5
Fig.7
AC WAVEFORMS
(1)
(1)
HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8
Fig.7
Waveforms showing the clock (CP) to
output (Qn) and terminal count (TC)
propagation delays, the clock pulse width
and the maximum clock pulse frequency.
December 1990
9
Waveforms showing the set-up and hold
times from count enable (CE) and
up/down (UP/DN) control inputs to the
clock pulse (CP), the propagation delays
from UP/DN, CE to TC.
Philips Semiconductors
Product specification
BCD up/down counter
(1)
HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9
(1)
74HC/HCT4510
(1)
Waveforms showing the preset enable
pulse width, preset enable to output
delays and output transition times.
Fig.10 Waveforms showing the master reset pulse,
master reset to terminal count and Qn delay
and master reset to clock removal time.
HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the data set-up and
hold times to parallel load (PL).
December 1990
HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
10
Philips Semiconductors
Product specification
BCD up/down counter
74HC/HCT4510
APPLICATION INFORMATION
Terminal count (TC) lines at the 2nd, 3rd, etc. stages may have a negative-going
glitch pulse resulting from differential delays of different 4510s. These
negative-going glitches do not affect proper 4510 operation. However, if the
terminal count signals are used to trigger other edge sensitive logic devices, such
as flip-flops or counters, the terminal count signals should be gated with the clock
signal using a 2-input OR gate such as HC/HCT32.
Fig.12 Cascading counter packages (parallel clocking).
Ripple clocking mode: the UP/DN control can be changed at any count. The only
restriction on changing the UP/DN control is that the clock input to the first counting
stage must be “HIGH”. For cascading counters operating in a fixed up-count or
down-count mode, the OR gates are not required between stages and TC is
connected directly to the CP input of the next stage with CE grounded.
Fig.13 Cascading counter packages (ripple clocking).
December 1990
11
Philips Semiconductors
Product specification
BCD up/down counter
74HC/HCT4510
Count-up mode: illegal states in
BCD counters corrected in one count.
Count-down mode: illegal states in
BCD counters corrected in one or
two counts.
Count-up mode.
Count-down mode.
Fig.14 State diagram.
Use the following formulae to calculate Ntotal:
N total
i
= ( 10 × N i ) + N 0
1
π
f in
f out = ------------N total
Formulae are only applicable if legal data is
provided to the parallel inputs.
Fig.15 Programmable cascaded frequency divider.
PACKAGE OUTLINES
parallel inputs
D3
D2
D1
D0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
count-up
n
count-down
n
9
8
7
6
5
4
3
2
1
(1)
(1)
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
1
2
3
4
5
6
7
8
9
Note
1. no count; fout is HIGH.
December 1990
12