PHILIPS 74AUP2G38GM

74AUP2G38
Low-power dual 2-input NAND gate; open drain
Rev. 04 — 8 October 2009
Product data sheet
1. General description
The 74AUP2G38 provides the dual 2-input NAND gate with open-drain output. The output
of the device is an open drain and can be connected to other open-drain outputs to
implement active-LOW wired-OR or active-HIGH wired-AND functions.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features
n Wide supply voltage range from 0.8 V to 3.6 V
n High noise immunity
n Complies with JEDEC standards:
u JESD8-12 (0.8 V to 1.3 V)
u JESD8-11 (0.9 V to 1.65 V)
u JESD8-7 (1.2 V to 1.95 V)
u JESD8-5 (1.8 V to 2.7 V)
u JESD8-B (2.7 V to 3.6 V)
n ESD protection:
u HBM JESD22-A114F Class 3A exceeds 5000 V
u MM JESD22-A115-A exceeds 200 V
u CDM JESD22-C101D exceeds 1000 V
n Low static power consumption; ICC = 0.9 µA (maximum)
n Latch-up performance exceeds 100 mA per JESD78B Class II
n Inputs accept voltages up to 3.6 V
n Low noise overshoot and undershoot < 10 % of VCC
n IOFF circuitry provides partial Power-down mode operation
n Multiple package options
n Specified from −40 °C to +85 °C and −40 °C to +125 °C
74AUP2G38
NXP Semiconductors
Low-power dual 2-input NAND gate; open drain
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AUP2G38DC
−40 °C to +125 °C
VSSOP8
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
74AUP2G38GT
−40 °C to +125 °C
XSON8
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 × 1.95 × 0.5 mm
74AUP2G38GD
−40 °C to +125 °C
XSON8U
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
74AUP2G38GM
−40 °C to +125 °C
XQFN8U
plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm
SOT902-1
4. Marking
Table 2.
Marking codes
Type number
Marking code[1]
74AUP2G38DC
a38
74AUP2G38GT
a38
74AUP2G38GD
a38
74AUP2G38GM
a38
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
&
1A
Y
1Y
1B
A
2A
&
2Y
2B
B
GND
001aah753
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74AUP2G38_4
Product data sheet
mnb131
001aah754
Fig 3.
Logic diagram (one gate)
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 8 October 2009
2 of 17
74AUP2G38
NXP Semiconductors
Low-power dual 2-input NAND gate; open drain
6. Pinning information
6.1 Pinning
74AUP2G38
1A
1
8
VCC
1B
2
7
1Y
2Y
3
6
2B
GND
4
5
2A
74AUP2G38
1A
1
8
VCC
1B
2
7
1Y
2Y
3
6
2B
GND
4
5
2A
001aaf548
Transparent top view
001aaf547
Fig 4.
Pin configuration SOT765-1 (VSSOP8)
Fig 5.
Pin configuration SOT833-1 (XSON8)
74AUP2G38
74AUP2G38
1
8
VCC
1B
2
7
1Y
2Y
3
6
2B
GND
4
5
2A
1
2B
2A
7
1A
2
6
1B
3
5
2Y
GND
001aak747
001aaf034
Transparent top view
Transparent top view
Fig 6.
8
1Y
4
1A
VCC
terminal 1
index area
Pin configuration SOT996-2 (XSON8U)
Fig 7.
Pin configuration SOT902-1 (XQFN8U)
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT765-1, SOT833-1 and
SOT996-2
SOT902-1
1A, 2A
1, 5
7, 3
data input
1B, 2B
2, 6
6, 2
data input
GND
4
4
ground (0 V)
1Y, 2Y
7, 3
1, 5
data output
VCC
8
8
supply voltage
74AUP2G38_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 8 October 2009
3 of 17
74AUP2G38
NXP Semiconductors
Low-power dual 2-input NAND gate; open drain
7. Functional description
Table 4.
Function table[1]
Input
Output
nA
nB
nY
L
L
Z
L
H
Z
H
L
Z
H
H
L
[1]
H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF state.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
Conditions
Min
−0.5
+4.6
V
VI < 0 V
−50
-
mA
−0.5
+4.6
V
−50
-
mA
−0.5
+4.6
V
-
+20
mA
[1]
VO < 0 V
[1]
Max
Unit
VO
output voltage
Active mode and Power-down mode
IO
output current
VO = 0 V to VCC
ICC
supply current
-
+50
mA
IGND
ground current
−50
-
mA
Tstg
storage temperature
−65
+150
°C
Ptot
total power dissipation
-
250
mW
Tamb = −40 °C to +125 °C
[2]
[1]
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For VSSOP8 packages: above 110 °C the value of Ptot derates linearly at 8.0 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
0.8
3.6
V
VI
input voltage
0
3.6
V
VO
output voltage
0
3.6
V
Tamb
ambient temperature
−40
+125
°C
∆t/∆V
input transition rise and fall rate
0
200
ns/V
Active mode and Power-down mode
VCC = 0.8 V to 3.6 V
74AUP2G38_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 8 October 2009
4 of 17
74AUP2G38
NXP Semiconductors
Low-power dual 2-input NAND gate; open drain
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VIH
VIL
VOL
HIGH-level input voltage
LOW-level input voltage
LOW-level output voltage
VCC = 0.8 V
0.70VCC
-
-
V
VCC = 0.9 V to 1.95 V
0.65VCC
-
-
V
VCC = 2.3 V to 2.7 V
1.6
-
-
V
VCC = 3.0 V to 3.6 V
2.0
-
-
V
VCC = 0.8 V
-
-
0.30VCC
V
VCC = 0.9 V to 1.95 V
-
-
0.35VCC
V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 3.0 V to 3.6 V
-
-
0.9
V
IO = 20 µA; VCC = 0.8 V to 3.6 V
-
-
0.1
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.3VCC
V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.31
V
VI = VIH or VIL
IO = 1.9 mA; VCC = 1.65 V
-
-
0.31
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.31
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.44
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.31
V
-
-
0.44
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
IO = 4.0 mA; VCC = 3.0 V
-
-
±0.1
µA
IOZ
OFF-state output current
VI = VIH or VIL; VO = 0 V to 3.6 V;
VCC = 0 V to 3.6 V
-
-
±0.1
µA
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
±0.2
µA
∆IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
±0.2
µA
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
0.5
µA
∆ICC
additional supply current
VI = VCC − 0.6 V; IO = 0 A;
VCC = 3.3 V
-
-
40
µA
CI
input capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
-
0.7
-
pF
CO
output capacitance
VO = GND; VCC = 0 V
-
0.9
-
pF
74AUP2G38_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 8 October 2009
5 of 17
74AUP2G38
NXP Semiconductors
Low-power dual 2-input NAND gate; open drain
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCC = 0.8 V
0.70VCC
-
-
V
VCC = 0.9 V to 1.95 V
0.65VCC
-
-
V
VCC = 2.3 V to 2.7 V
1.6
-
-
V
VCC = 3.0 V to 3.6 V
2.0
-
-
V
VCC = 0.8 V
-
-
0.30VCC
V
VCC = 0.9 V to 1.95 V
-
-
0.35VCC
V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 3.0 V to 3.6 V
-
-
0.9
V
Tamb = −40 °C to +85 °C
VIH
VIL
VOL
HIGH-level input voltage
LOW-level input voltage
LOW-level output voltage
VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
-
-
0.1
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.3VCC
V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.37
V
IO = 1.9 mA; VCC = 1.65 V
-
-
0.35
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.33
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.45
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.33
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.45
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
±0.5
µA
IOZ
OFF-state output current
VI = VIH or VIL; VO = 0 V to 3.6 V;
VCC = 0 V to 3.6 V
-
-
±0.5
µA
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
±0.5
µA
∆IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
±0.6
µA
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
0.9
µA
∆ICC
additional supply current
VI = VCC − 0.6 V; IO = 0 A;
VCC = 3.3 V
-
-
50
µA
74AUP2G38_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 8 October 2009
6 of 17
74AUP2G38
NXP Semiconductors
Low-power dual 2-input NAND gate; open drain
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCC = 0.8 V
0.75VCC
-
-
V
VCC = 0.9 V to 1.95 V
0.70VCC
-
-
V
VCC = 2.3 V to 2.7 V
1.6
-
-
V
VCC = 3.0 V to 3.6 V
2.0
-
-
V
VCC = 0.8 V
-
-
0.25VCC
V
VCC = 0.9 V to 1.95 V
-
-
0.30VCC
V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 3.0 V to 3.6 V
-
-
0.9
V
Tamb = −40 °C to +125 °C
VIH
VIL
VOL
HIGH-level input voltage
LOW-level input voltage
LOW-level output voltage
VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
-
-
0.11
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.33VCC
V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.41
V
IO = 1.9 mA; VCC = 1.65 V
-
-
0.39
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.36
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.50
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.36
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.50
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
±0.75
µA
IOZ
OFF-state output current
VI = VIH or VIL; VO = 0 V to 3.6 V;
VCC = 0 V to 3.6 V
-
-
±0.75
µA
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
±0.75
µA
∆IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
±0.75
µA
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
1.4
µA
∆ICC
additional supply current
VI = VCC − 0.6 V; IO = 0 A;
VCC = 3.3 V
-
-
75
µA
74AUP2G38_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 8 October 2009
7 of 17
74AUP2G38
NXP Semiconductors
Low-power dual 2-input NAND gate; open drain
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol
Parameter
25 °C
Conditions
−40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
(85 °C)
Max
(125 °C)
VCC = 0.8 V
-
13.5
-
-
-
-
VCC = 1.1 V to 1.3 V
1.9
4.6
10.4
1.8
11.4
12.6
ns
VCC = 1.4 V to 1.6 V
1.5
3.3
6.5
1.4
7.4
8.2
ns
VCC = 1.65 V to 1.95 V
1.2
2.9
5.1
1.1
5.9
6.5
ns
VCC = 2.3 V to 2.7 V
1.0
2.2
3.8
0.9
4.5
4.9
ns
VCC = 3.0 V to 3.6 V
0.9
2.3
4.0
0.8
4.5
4.9
ns
VCC = 0.8 V
-
16.3
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
2.3
5.6
12.3
2.1
13.7
15.1
ns
VCC = 1.4 V to 1.6 V
1.8
4.1
7.6
1.7
8.8
9.7
ns
VCC = 1.65 V to 1.95 V
1.6
3.8
6.1
1.4
7.1
7.8
ns
VCC = 2.3 V to 2.7 V
1.4
2.9
4.6
1.2
5.4
5.9
ns
VCC = 3.0 V to 3.6 V
1.3
3.2
5.7
1.1
6.4
7.0
ns
VCC = 0.8 V
-
19.0
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
2.6
6.6
14.2
2.4
15.8
17.4
ns
VCC = 1.4 V to 1.6 V
2.1
4.8
8.7
1.9
10.1
11.1
ns
VCC = 1.65 V to 1.95 V
1.9
4.6
7.6
1.7
8.5
9.3
ns
VCC = 2.3 V to 2.7 V
1.6
3.6
5.6
1.5
6.3
6.9
ns
VCC = 3.0 V to 3.6 V
1.6
4.1
7.5
1.4
8.3
9.1
ns
VCC = 0.8 V
-
27.0
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
3.6
9.5
19.5
3.2
21.8
24.0
ns
VCC = 1.4 V to 1.6 V
2.9
7.0
11.5
2.6
13.6
15.0
ns
VCC = 1.65 V to 1.95 V
2.6
7.0
12.1
2.3
13.3
14.6
ns
VCC = 2.3 V to 2.7 V
2.4
5.4
8.9
2.1
9.9
10.9
ns
VCC = 3.0 V to 3.6 V
2.3
6.5
12.7
2.1
13.9
15.3
ns
CL = 5 pF
tpd
propagation delay
nA, nB to nY; see Figure 8
[2]
ns
CL = 10 pF
tpd
propagation delay
nA, nB to nY; see Figure 8
[2]
CL = 15 pF
tpd
propagation delay
nA, nB to nY; see Figure 8
[2]
CL = 30 pF
tpd
propagation delay
nA, nB to nY; see Figure 8
[2]
74AUP2G38_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 8 October 2009
8 of 17
74AUP2G38
NXP Semiconductors
Low-power dual 2-input NAND gate; open drain
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol
Parameter
25 °C
Conditions
−40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
(85 °C)
Max
(125 °C)
VCC = 0.8 V
-
0.6
-
-
-
-
pF
VCC = 1.1 V to 1.3 V
-
0.7
-
-
-
-
pF
VCC = 1.4 V to 1.6 V
-
0.8
-
-
-
-
pF
VCC = 1.65 V to 1.95 V
-
0.9
-
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
1.1
-
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
1.4
-
-
-
-
pF
CL = 5 pF, 10 pF, 15 pF and 30 pF
power dissipation
capacitance
CPD
f = 1 MHz; VI = GND to VCC
[3]
[1]
All typical values are measured at nominal VCC.
[2]
tpd is the same as tPZL and tPLZ.
[3]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N where:
fi = input frequency in MHz;
VCC = supply voltage in V;
N = number of inputs switching.
12. Waveforms
VI
nA, nB input
VM
GND
t PZL
t PLZ
VCC
nY output
VM
VOL
VX
mnb132
Measurement points are given in Table 9.
Logic level VOL is a typical output voltage level that occurs with the output load.
Fig 8.
Table 9.
The data input (nA, nB) to output (nY) propagation delays
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
VX
0.8 V to 1.6 V
0.5VCC
0.5VCC
VOL + 0.1 V
1.65 V to 2.7 V
0.5VCC
0.5VCC
VOL + 0.15 V
3.0 V to 3.6 V
0.5VCC
0.5VCC
VOL + 0.3 V
74AUP2G38_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 8 October 2009
9 of 17
74AUP2G38
NXP Semiconductors
Low-power dual 2-input NAND gate; open drain
VCC
VEXT
5 kΩ
G
VI
VO
DUT
RT
CL
RL
001aac521
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 9.
Table 10.
Load circuitry for switching times
Test data
Supply voltage
Load
VEXT
RL[1]
VCC
CL
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ
[1]
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
open
GND
2VCC
For measuring enable and disable times RL = 5 kΩ.
For measuring propagation delays, set-up times, hold times and pulse width, RL = 1 MΩ.
74AUP2G38_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 8 October 2009
10 of 17
74AUP2G38
NXP Semiconductors
Low-power dual 2-input NAND gate; open drain
13. Package outline
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
D
E
SOT765-1
A
X
c
y
HE
v M A
Z
5
8
Q
A
A2
A1
pin 1 index
(A3)
θ
Lp
1
4
e
L
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
Q
v
w
y
Z(1)
θ
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.40
0.15
0.21
0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT765-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
MO-187
Fig 10. Package outline SOT765-1 (VSSOP8)
74AUP2G38_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 8 October 2009
11 of 17
74AUP2G38
NXP Semiconductors
Low-power dual 2-input NAND gate; open drain
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
1
2
SOT833-1
b
4
3
4×
(2)
L
L1
e
8
7
6
e1
5
e1
e1
8×
A
(2)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.25
0.17
2.0
1.9
1.05
0.95
0.6
0.5
0.35
0.27
0.40
0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT833-1
---
MO-252
---
EUROPEAN
PROJECTION
ISSUE DATE
07-11-14
07-12-07
Fig 11. Package outline SOT833-1 (XSON8)
74AUP2G38_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 8 October 2009
12 of 17
74AUP2G38
NXP Semiconductors
Low-power dual 2-input NAND gate; open drain
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
B
D
SOT996-2
A
A
E
A1
detail X
terminal 1
index area
e1
L1
v
w
b
e
1
4
8
5
C
C A B
C
M
M
y
y1 C
L2
L
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
b
D
E
e
e1
L
L1
L2
v
w
y
y1
mm
0.5
0.05
0.00
0.35
0.15
2.1
1.9
3.1
2.9
0.5
1.5
0.5
0.3
0.15
0.05
0.6
0.4
0.1
0.05
0.05
0.1
REFERENCES
OUTLINE
VERSION
IEC
SOT996-2
---
JEDEC
JEITA
---
EUROPEAN
PROJECTION
ISSUE DATE
07-12-18
07-12-21
Fig 12. Package outline SOT996-2 (XSON8U)
74AUP2G38_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 8 October 2009
13 of 17
74AUP2G38
NXP Semiconductors
Low-power dual 2-input NAND gate; open drain
XQFN8U: plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
B
D
SOT902-1
A
terminal 1
index area
E
A
A1
detail X
L1
e
e
C
∅v M C A B
∅w M C
L
4
y1 C
y
5
3
metal area
not for soldering
e1
b
2
6
e1
7
1
terminal 1
index area
8
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
b
D
E
e
e1
L
L1
v
w
y
y1
mm
0.5
0.05
0.00
0.25
0.15
1.65
1.55
1.65
1.55
0.55
0.5
0.35
0.25
0.15
0.05
0.1
0.05
0.05
0.05
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT902-1
---
MO-255
---
EUROPEAN
PROJECTION
ISSUE DATE
05-11-25
07-11-14
Fig 13. Package outline SOT902-1 (XQFN8U)
74AUP2G38_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 8 October 2009
14 of 17
74AUP2G38
NXP Semiconductors
Low-power dual 2-input NAND gate; open drain
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AUP2G38_4
20091008
Product data sheet
-
74AUP2G38_3
Modifications:
•
Added type number 74AUP2G38GD (XSON8U / SOT996-2) package.
74AUP2G38_3
20090616
Product data sheet
-
74AUP2G38_2
74AUP2G38_2
20080312
Product data sheet
-
74AUP2G38_1
74AUP2G38_1
20061016
Product data sheet
-
-
74AUP2G38_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 8 October 2009
15 of 17
74AUP2G38
NXP Semiconductors
Low-power dual 2-input NAND gate; open drain
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74AUP2G38_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 8 October 2009
16 of 17
74AUP2G38
NXP Semiconductors
Low-power dual 2-input NAND gate; open drain
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 8 October 2009
Document identifier: 74AUP2G38_4