PCA9621 65 mA 8-bit 2-wire bus output port Rev. 1 — 9 March 2011 Product data sheet 1. General description The PCA9621 is a monolithic CMOS integrated circuit for general purpose output drive configurable from a 2-wire bus interface (including I2C-bus, SMBus, PMBus, and other systems based on similar principles). Output ports have a 65 mA sink capability, making them ideal for driving LEDs. The state of the outputs is determined by a programmable 8-bit register which can be read and written via signals from the 2-wire bus (e.g., I2C-bus or similar). The 2-wire bus interface also has 30 mA Fast-mode Plus (Fm+) capability, and consequently can be run in excess of 1 MHz or up to 4000 pF capacitance. As such, the PCA9621 can be connected to other 2-wire devices across long cable connections. It can be mixed with other Fast-mode Plus slaves in systems driven by Fm+ buffers or by the PCA9646 (fully buffered 4-channel bus switch) to build large scale systems with high-speed or high-capacitance drive capability, for example large scale LED displays or controlled lighting. 2. Features and benefits 8 individually selectable open-drain output ports 65 mA static sink capability on all output ports Ports may be paralleled for up to 500 mA drive Ideal for simple LED or general purpose output drive Fast-mode Plus (30 mA, 4000 pF) 2-wire bus capability Works with I2C-bus (Standard-mode, Fast-mode, and Fast-mode Plus), SMBus (standard and high power mode), and PMBus Fast switching times allow operation in excess of 1 MHz Operating voltages from 2.7 V to 5.5 V 3. Applications LED and 7-segment displays Simple high-power (500 mA) LED dimming General purpose output Instrumentation indicators PCA9621 NXP Semiconductors 65 mA 8-bit 2-wire bus output port 4. Ordering information Table 1. Ordering information Tamb = −40 to +85 °C. Type number Topside mark Package Name Description Version PCA9621D PCA9621 SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 PCA9621PW PCA9621 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 5. Block diagram 2.7 V to 5.5 V R1 VDD R2 PCA9621 SCL 14 SDA 15 R3 R4 LED LED R5 R6 16 FILTER 4 P0 5 P1 6 P2 R7 7 P3 R8 9 P4 R9 R10 high current LED RESET 3 A0 1 A1 2 10 P5 A2 13 11 P6 output 12 P7 output I2C-BUS SLAVE TRANSCEIVER 8 VSS 002aaf379 Fig 1. Block diagram of PCA9621 PCA9621 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 March 2011 © NXP B.V. 2011. All rights reserved. 2 of 18 PCA9621 NXP Semiconductors 65 mA 8-bit 2-wire bus output port 6. Pinning information 6.1 Pinning A0 1 16 VDD A1 2 15 SDA RESET 3 14 SCL P0 4 13 A2 PCA9621D P1 5 12 P7 P2 6 11 P6 P3 7 VSS 8 A0 1 16 VDD A1 2 15 SDA RESET 3 14 SCL P0 4 P1 5 P2 6 11 P6 P3 7 10 P5 VSS 8 10 P5 9 P4 002aaf381 Fig 2. Pin configuration for SO16 PCA9621PW 13 A2 12 P7 9 P4 002aaf382 Fig 3. Pin configuration for TSSOP16 6.2 Pin description Table 2. PCA9621 Product data sheet Pin description Symbol Pin Description A0 1 address input 0 A1 2 address input 1 RESET 3 active LOW reset input P0 4 output port 0 P1 5 output port 1 P2 6 output port 2 P3 7 output port 3 VSS 8 negative supply (ground) P4 9 output port 4 P5 10 output port 5 P6 11 output port 6 P7 12 output port 7 A2 13 address input 2 SCL 14 serial clock line SDA 15 serial data line VDD 16 positive supply All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 March 2011 © NXP B.V. 2011. All rights reserved. 3 of 18 PCA9621 NXP Semiconductors 65 mA 8-bit 2-wire bus output port 7. Functional description Refer to Figure 1 “Block diagram of PCA9621”. 7.1 VDD, VSS — DC supply pins The power supply voltage for the PCA9621 may be any voltage in the range 2.7 V to 5.5 V. All other I/Os are clamped to VDD and VSS through ESD protection diodes. 7.2 SCL, SDA — 2-wire bus interface The state of the output ports is determined by the Control register, which is set and read via a 2-wire bus interface using I2C-bus style signalling. The interface is Fast-mode Plus (Fm+) I2C-bus compatible, though the ports contain ESD protection diodes to the positive and negative supplies. Consequently, VI2C-bus (voltage at SCL and SDA) must remain within the VDD and VSS supply levels. 7.3 P0 to P7 — output ports There are eight open-drain output ports whose state is determined by the Control register. Programming a ‘1’ or HIGH to the relevant register bit will turn on the corresponding port, resulting at a LOW or ‘0’ at the port. In the case of LED driving, this would result in the LED turning ON. Programming a ‘0’ or LOW in the register turns off the open-drain port, placing it in a high-impedance mode. The ports are protected by ESD diodes to the supplies so they must not be driven above the VDD or below the VSS levels. 7.4 RESET — reset IC to default state The active LOW RESET input is used to disable the buffer and reset it to its default state. The RESET signal will clear the contents of the Control register, turning off all output ports, and resetting the state of the I2C-bus slave transceiver block. 7.5 Power-On Reset (POR) During power-on, the PCA9621 is internally held in the reset condition for a maximum of trst = 500 ns. The default condition after reset is for the Control register to be erased (all zeros), resulting in all output ports being off (high-impedance). PCA9621 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 March 2011 © NXP B.V. 2011. All rights reserved. 4 of 18 PCA9621 NXP Semiconductors 65 mA 8-bit 2-wire bus output port 7.6 A0, A1, A2 — address lines The slave address of the PCA9621 is shown in Figure 4. The address pins (A2, A1, A0) must be driven to a HIGH or LOW level—they are not internally pulled to a default state. 1 1 0 0 A2 fixed A1 A0 R/W externally selectable read = 1 write = 0 002aaf383 Fig 4. Slave address The read/write bit must be set LOW to enable a write to the Control register, or HIGH to read from the Control register. 7.7 Control register The Control register of the PCA9621 is shown in Figure 5. Each of the four output ports can be activated independently by setting the appropriate bit in the Control register. MSB P7 P6 P5 P4 P3 P2 P1 P0 LSB 002aaf384 1 = ON (sinking) 0 = OFF (high-impedance) Fig 5. Control register A LOW or ‘zero’ bit indicates that the respective channel (P7 to P0) is disabled (high-impedance). The default reset condition of the register is all zeros, all ports high-impedance. A HIGH or ‘one’ bit indicates the respective channel is active (sinking). Example: Programming C1h (1100 0001b) into the Control register results in ports P0, P6 and P7 being ON (sinking) and the remaining ports being OFF (high-impedance). PCA9621 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 March 2011 © NXP B.V. 2011. All rights reserved. 5 of 18 PCA9621 NXP Semiconductors 65 mA 8-bit 2-wire bus output port 8. Bus transaction A typical I2C-bus write transaction to the PCA9621 is shown in Figure 6. During a write transaction, the output ports (P0 to P7) of the PCA9621 are updated upon receipt of the STOP condition. slave address S 1 1 0 0 A2 A1 Control register A0 START condition 0 R/W A P7 P6 P5 P4 P3 P2 acknowledge from slave P1 P0 A acknowledge from slave P STOP condition 002aaf385 Fig 6. PCA9621 write transaction to Control register A typical read transaction is shown in Figure 7. slave address S 1 1 0 0 A2 A1 START condition Control register A0 1 R/W A P7 P6 P5 P4 P3 acknowledge from slave P2 P1 P0 NA not acknowledge from master P STOP condition 002aaf386 Fig 7. PCA9621 read transaction from Control register 9. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDD supply voltage [1] −0.3 +7 V Vn voltage on any other pin [1] VSS − 0.5 VDD + 0.5 V input current [2] - 100 mA - 40 mA II output ports (P0 to P7) SDA, SCL pins - 20 mA ISS ground supply current address pins A0 to A2; RESET pin - 550 mA Ptot total power dissipation - 300 mW Tstg storage temperature −55 +125 °C Tamb ambient temperature −40 +85 °C operating [1] Voltages are specified with respect to pin 8 (VSS). [2] 100 mA for one pin only in the group P0 to P3, and one pin only in the group P4 to P7. Otherwise 70 mA maximum, any pin. PCA9621 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 March 2011 © NXP B.V. 2011. All rights reserved. 6 of 18 PCA9621 NXP Semiconductors 65 mA 8-bit 2-wire bus output port 10. Characteristics Table 4. Characteristics Tamb = −40 °C to +85 °C; voltages are specified with respect to ground (VSS); VDD = 5.5 V unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Power supply VDD supply voltage operating 2.7 - 5.5 V IDD supply current quiescent; VI (RESET pin) = 0 V; VDD = 5.5 V - - 1 μA I2C-bus ports (SCL, SDA) VI2C-bus I2C-bus voltage SDA, SCL VSS − 0.3 - VDD + 0.3 V VIL LOW-level input voltage VDD = 2.7 V [1] - - 0.4 V VDD = 5.5 V [1] - - 0.5 V VDD = 2.7 V [1] 1.2 - - V VDD = 5.5 V [1] VIH HIGH-level input voltage 2.0 - - V ILI input leakage current pin at VDD or VSS −1 - +1 μA VOL LOW-level output voltage IOL = 30 mA; VDD = 2.7 V - 260 450 mV IOL = 30 mA; VDD = 5.5 V - 140 275 mV Open-drain output ports (P0 to P7) IO(sink) output sink current LOW-level; port enabled 65 - - mA VOL LOW-level output voltage IOL = 65 mA - 440 725 mV IOL = 100 μA - 1 - mV VDD = 2.7 V 2.0 - - V VDD = 5.5 V 4.8 - - V RESET VIH HIGH-level input voltage VIL LOW-level input voltage VDD = 2.7 V - - 650 mV VDD = 5.5 V - - 900 mV Vhys hysteresis voltage VDD = 2.7 V 100 - - mV VDD = 5.5 V 200 - - mV −1 - +1 μA ILI input leakage current pin at VDD or VSS [2] tw(rst)L LOW-level reset time VI < VIL - 25 - ns trst reset time RESET pin; from VI > VIH - 250 500 ns tPOR power-on reset pulse time RESET pin; from VI > VIH - 250 500 ns Address pins (A0, A1, A2) VIH VIL ILI HIGH-level input voltage LOW-level input voltage input leakage current VDD = 2.7 V 1.7 - - V VDD = 5.5 V 3.5 - - V VDD = 2.7 V - - 0.7 V VDD = 5.5 V - - 1.5 V pin at VDD or VSS −1 - +1 μA RPU = 200 Ω; measured from 70 % VDD to 30 % VDD - 16 - ns - - 500 ns Timing characteristics tf fall time of both SDA and SCL signals tv(Q) data output valid time PCA9621 Product data sheet [3] All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 March 2011 © NXP B.V. 2011. All rights reserved. 7 of 18 PCA9621 NXP Semiconductors 65 mA 8-bit 2-wire bus output port [1] Supply voltage dependent; refer to graphs (Figure 8 through Figure 10) for typical trend. [2] Guaranteed by design, not subject to test. [3] Time between STOP condition and output port (P0 to P7) being asserted. 002aaf372 250 VOL (mV) 200 002aaf373 400 VOL (mV) 300 VDD = 2.7 V 150 200 100 5.5 V VDD = 5.5 V 100 50 2.7 V 0 0 200 400 600 0 −50 800 1000 RPU (Ω) Tamb = 25 °C Fig 8. 0 50 100 150 Tamb (C) IOL = 30 mA Typical SDA LOW-level output voltage versus pull-up resistance Fig 9. Typical SDA LOW-level output voltage versus ambient temperature 002aaf389 250 VOL (mV) 200 150 100 50 0 0 20 40 60 80 IO(sink) (mA) Tamb = 25 °C; VDD = 5.5 V Fig 10. Typical output port (P0 to P7) LOW-level output voltage versus LOW-level output sink current PCA9621 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 March 2011 © NXP B.V. 2011. All rights reserved. 8 of 18 PCA9621 NXP Semiconductors 65 mA 8-bit 2-wire bus output port 11. Application information Figure 11 shows the PCA9621 in conjunction with the PCA9646 bus multiplexer in a LED drive application. Each PCA9621 can drive 8 LEDs, and using the address pins on the IC, up to 8 uniquely addressed devices can sit on one bus branch. The PCA9646 has four such outputs, giving 256 LEDs in the structure shown. By additionally using the address pins on the PCA9646, the entire structure may be repeated 8 times, allowing 2048 LEDs to be uniquely driven. By additionally placing PCA9646’s in series (refer to the PCA9646 data sheet), the structure may be further extensively multiplied into a huge array. 5V R1 VDD R7 R2 R8 VDD SCL SCL SC0 SC0 SDA SDA SD0 SD0 U2 8 P[7:0] PCA9621 U3 R4 SD2 R9 SC3 SC3 SD3 SD3 Entire structure can be repeated 8 times using PCA9646 address pins (further expansion possible). A0 A1 SC1 SC1 SD1 SD1 A2 VSS U1 VDD R6 SCL R5 R10 SDA buses SC2/SD2, SC3/SD3 as shown for SC0/SD0, SC1/SD1 8 LEDs P[7:0] 8 P[7:0] PCA9621 U11 VDD SC2 SD2 PCA9621 SCL SC2 8 LEDs 8 U10 8 × PCA9621 each with 8 LEDs = 64 LEDs SDA R3 VDD SCL 8 LEDs P[7:0] SDA VDD PCA9646 SCL BUS MASTER SDA RESET 8 LEDs 8 PCA9621 U18 8 × PCA9621 each with 8 LEDs = 64 LEDs 002aaf397 Fig 11. PCA9621 in a large LED array PCA9621 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 March 2011 © NXP B.V. 2011. All rights reserved. 9 of 18 PCA9621 NXP Semiconductors 65 mA 8-bit 2-wire bus output port Figure 12 shows a simple 7-segment display drive arrangement. All of the 7 segments plus decimal point can be driven from a single PCA9621. By using the address pins, up to 8 digits can be addressed from a single bus. When running at 1 MHz, all 8 digits can be updated in less than 0.2 ms. Further, by using the arrangement described above and shown in Figure 11, the number of digits driven may be increased significantly. 5V R1 R2 SCL SDA VDD SCL SDA 3 A[2:0] RESET P0 P1 P2 P3 P4 P5 P6 P7 PCA9621 U1 repeat up to 8 times using address pins on PCA9621 002aaf398 Fig 12. PCA9621 as 7-segment display driver Figure 13 shows the PCA9621 used in conjunction with other NXP Semiconductors 2-wire bus buffers to form a multiplexer arrangement. Using the PCA9621 to control multiples of either PCA9521 or PCA9522 produces an isolating bus switch/multiplexer that has fully compliant I2C-bus I/O levels, low offset voltages, and large noise margins. Using PCA9522 in this arrangement additionally provides ‘hot-swap’ capability. 3.3 V R1 R2 SCL VCC SA1 SB1 SDA SDA 3 A[2:0] RESET 400 pF(1) PCA9521(1) VDD SCL SA2 SB2 P0 P1 P2 P3 P4 P5 P6 P7 PCA9621 U1 multiple isolated buses EN U2 3.3 V VCC SCLC SDAC SCLB SDAB 400 pF(1) PCA9522(1) EN RDY U3 002aaf399 Address lines allow this structure to be repeated 8 more times. (1) Or PCA9525 (400 pF), or PCA9605 (4000 pF), or PCA9646 (4 × 4000 pF). Fig 13. PCA9621 as part of a fully isolating I2C-bus multiplexer PCA9621 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 March 2011 © NXP B.V. 2011. All rights reserved. 10 of 18 PCA9621 NXP Semiconductors 65 mA 8-bit 2-wire bus output port 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 14. Package outline SOT109-1 (SO16) PCA9621 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 March 2011 © NXP B.V. 2011. All rights reserved. 11 of 18 PCA9621 NXP Semiconductors 65 mA 8-bit 2-wire bus output port TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 15. Package outline SOT403-1 (TSSOP16) PCA9621 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 March 2011 © NXP B.V. 2011. All rights reserved. 12 of 18 PCA9621 NXP Semiconductors 65 mA 8-bit 2-wire bus output port 13. Handling information CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling electrostatic sensitive devices. Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or equivalent standards. 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • PCA9621 Product data sheet Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 March 2011 © NXP B.V. 2011. All rights reserved. 13 of 18 PCA9621 NXP Semiconductors 65 mA 8-bit 2-wire bus output port 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 16) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 5 and 6 Table 5. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 6. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 16. PCA9621 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 March 2011 © NXP B.V. 2011. All rights reserved. 14 of 18 PCA9621 NXP Semiconductors 65 mA 8-bit 2-wire bus output port maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 16. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 7. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge I2C-bus Inter-Integrated Circuit bus I/O Input/Output IC Integrated Circuit LED Light-Emitting Diode PMBus Power Management Bus POR Power-On Reset SMBus System Management Bus 16. References [1] UM10204, “I2C-bus specification and user manual” — NXP Semiconductors; www.nxp.com/documents/user_manual/UM10204.pdf 17. Revision history Table 8. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9621 v.1 20110309 Product data sheet - - PCA9621 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 March 2011 © NXP B.V. 2011. All rights reserved. 15 of 18 PCA9621 NXP Semiconductors 65 mA 8-bit 2-wire bus output port 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. PCA9621 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 March 2011 © NXP B.V. 2011. All rights reserved. 16 of 18 PCA9621 NXP Semiconductors 65 mA 8-bit 2-wire bus output port Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCA9621 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 March 2011 © NXP B.V. 2011. All rights reserved. 17 of 18 PCA9621 NXP Semiconductors 65 mA 8-bit 2-wire bus output port 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 VDD, VSS — DC supply pins . . . . . . . . . . . . . . . 4 SCL, SDA — 2-wire bus interface . . . . . . . . . . 4 P0 to P7 — output ports . . . . . . . . . . . . . . . . . . 4 RESET — reset IC to default state . . . . . . . . . . 4 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 4 A0, A1, A2 — address lines . . . . . . . . . . . . . . . 5 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 5 Bus transaction . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application information. . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Handling information. . . . . . . . . . . . . . . . . . . . 13 Soldering of SMD packages . . . . . . . . . . . . . . 13 Introduction to soldering . . . . . . . . . . . . . . . . . 13 Wave and reflow soldering . . . . . . . . . . . . . . . 13 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 14 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 9 March 2011 Document identifier: PCA9621