PCA9545A/45B/45C
4-channel I2C-bus switch with interrupt logic and reset
Rev. 9 — 5 May 2014
Product data sheet
1. General description
The PCA9545A/45B/45C is a quad bidirectional translating switch controlled via the
I2C-bus. The SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any
individual SCx/SDx channel or combination of channels can be selected, determined by
the contents of the programmable control register. Four interrupt inputs, INT0 to INT3, one
for each of the downstream pairs, are provided. One interrupt output, INT, acts as an AND
of the four interrupt inputs.
An active LOW reset input allows the PCA9545A/45B/45C to recover from a situation
where one of the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin
LOW resets the I2C-bus state machine and causes all the channels to be deselected as
does the internal power-on reset function.
The pass gates of the switches are constructed such that the VDD pin can be used to limit
the maximum high voltage which is passed by the PCA9545A/45B/45C. This allows the
use of different bus voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can
communicate with 5 V parts without any additional protection. External pull-up resistors
pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
The PCA9545A, PCA9545B and PCA9545C are identical except for the fixed portion of
the slave address.
2. Features and benefits
1-of-4 bidirectional translating switches
I2C-bus interface logic; compatible with SMBus standards
4 active LOW interrupt inputs
Active LOW interrupt output
Active LOW reset input
2 address pins allowing up to 4 devices on the I2C-bus
Alternate address versions A, B and C allow up to a total of 12 devices on the bus for
larger systems or to resolve address conflicts
Channel selection via I2C-bus, in any combination
Power-up with all switch channels deselected
Low Ron switches
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
No glitch on power-up
Supports hot insertion
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
5 V tolerant Inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up protection exceeds 100 mA per JESD78
Three packages offered: SO20, TSSOP20, and HVQFN20
3. Ordering information
Table 1.
Ordering information
Type number
Topside
marking
Package
Name
Description
Version
PCA9545ABS
9545A
HVQFN20
plastic thermal enhanced very thin quad flat package;
no leads; 20 terminals; body 5 5 0.85 mm
SOT662-1
PCA9545AD
PCA9545AD
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
PCA9545APW
PA9545A
TSSOP20
SOT360-1
PCA9545BPW
PA9545B
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
PCA9545CPW
PA9545C
3.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order
quantity
Temperature range
PCA9545ABS
PCA9545ABS,118
HVQFN20
Reel 13” Q1/T1
*standard mark SMD
6000
Tamb = 40 C to +85 C
PCA9545AD
PCA9545AD,112
SO20
Standard marking
* IC’s tube - DSC bulk pack
1520
Tamb = 40 C to +85 C
PCA9545AD,118
SO20
Reel 13” Q1/T1
*standard mark SMD
2000
Tamb = 40 C to +85 C
PCA9545APW,112
TSSOP20
Standard marking
* IC’s tube - DSC bulk pack
1875
Tamb = 40 C to +85 C
PCA9545APW,118
TSSOP20
Reel 13” Q1/T1
*standard mark SMD
2500
Tamb = 40 C to +85 C
PCA9545BPW
PCA9545BPW,118
TSSOP20
Reel 13” Q1/T1
*standard mark SMD
2500
Tamb = 40 C to +85 C
PCA9545CPW
PCA9545CPW,118
TSSOP20
Reel 13” Q1/T1
*standard mark SMD
2500
Tamb = 40 C to +85 C
PCA9545APW
PCA9545A_45B_45C
Product data sheet
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Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
4. Block diagram
PCA9545A/PCA9545B/PCA9545C
SC0
SC1
SC2
SC3
SD0
SD1
SD2
SD3
VSS
VDD
RESET
SCL
SDA
SWITCH CONTROL LOGIC
POWER-ON
RESET
INPUT
FILTER
INT0
to
INT3
A0
I2C-BUS
CONTROL
A1
INT
INTERRUPT LOGIC
002aab168
Fig 1.
PCA9545A_45B_45C
Product data sheet
Block diagram of PCA9545A/45B/45C
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PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
5. Pinning information
5.1 Pinning
A0
1
1
20 VDD
2
20 VDD
19 SDA
A0
A1
A1
2
19 SDA
RESET
3
18 SCL
RESET
3
18 SCL
INT0
4
17 INT
INT0
4
SD0
5
16 SC3
SD0
5
SC0
6
15 SD3
SC0
6
INT1
7
14 INT3
INT1
7
14 INT3
SD1
8
13 SC2
SD1
8
13 SC2
SC1
9
12 SD2
SC1
9
12 SD2
VSS 10
11 INT2
VSS 10
11 INT2
PCA9545AD
17 INT
PCA9545APW
PCA9545BPW
PCA9545CPW
002aab165
15 SD3
002aab166
Pin configuration for TSSOP20
16 SCL
17 SDA
18 VDD
20 A1
terminal 1
index area
Fig 3.
19 A0
Pin configuration for SO20
RESET
1
15 INT
INT0
2
14 SC3
SD0
3
SC0
4
12 INT3
INT1
5
11 SC2
7
8
9
SC1
VSS
INT2
SD2 10
6
PCA9545ABS
SD1
Fig 2.
16 SC3
13 SD3
002aab167
Transparent top view
Fig 4.
PCA9545A_45B_45C
Product data sheet
Pin configuration for HVQFN20 (transparent top view)
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Rev. 9 — 5 May 2014
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PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
5.2 Pin description
Table 3.
Symbol
Product data sheet
Pin
Description
SO20, TSSOP20
HVQFN20
A0
1
19
address input 0
A1
2
20
address input 1
RESET
3
1
active LOW reset input
INT0
4
2
active LOW interrupt input 0
SD0
5
3
serial data 0
SC0
6
4
serial clock 0
INT1
7
5
active LOW interrupt input 1
SD1
8
6
serial data 1
SC1
9
7
serial clock 1
supply ground
VSS
10
8[1]
INT2
11
9
active LOW interrupt input 2
SD2
12
10
serial data 2
SC2
13
11
serial clock 2
INT3
14
12
active LOW interrupt input 3
SD3
15
13
serial data 3
SC3
16
14
serial clock 3
INT
17
15
active LOW interrupt output
SCL
18
16
serial clock line
SDA
19
17
serial data line
VDD
20
18
supply voltage
[1]
PCA9545A_45B_45C
Pin description
HVQFN20 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad must be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias must be
incorporated in the PCB in the thermal pad region.
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Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
6. Functional description
Refer to Figure 1 “Block diagram of PCA9545A/45B/45C”.
6.1 Device address
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9545A is shown in Figure 5. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
1
1
1
fixed
0
0
A1
A0 R/W
hardware
selectable
002aab169
Fig 5.
Slave address PCA9545A
The last bit of the slave address defines the operation to be performed. When set to
logic 1, a read is selected while a logic 0 selects a write operation.
The PCA9545BPW and PCA9545CPW are alternate address versions if needed for larger
systems or to resolve conflicts. The data sheet references the PCA9545A, but the
PCA9545B and PCA9545C function identically except for the slave address.
1
1
0
fixed
1
0
A1
A0 R/W
1
hardware
selectable
PCA9545A_45B_45C
Product data sheet
Slave address PCA9545B
1
0
A1
A0 R/W
hardware
selectable
002aab836
Fig 7.
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Rev. 9 — 5 May 2014
1
fixed
002aab835
Fig 6.
0
Slave address PCA9545C
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6 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master sends a
byte to the PCA9545A/45B/45C, which is stored in the control register. If multiple bytes
are received by the PCA9545A/45B/45C, it saves the last byte received. This register can
be written and read via the I2C-bus.
interrupt bits
(read only)
channel selection bits
(read/write)
7
6
5
4
INT INT INT INT
3
2
1
0
3
2
1
0
B3
B2
B1
B0
channel 0
channel 1
channel 2
channel 3
INT0
INT1
INT2
INT3
002aab170
Fig 8.
Control register
6.2.1 Control register definition
One or several SCx/SDx downstream pair, or channel, is selected by the contents of the
control register. This register is written after the PCA9545A/45B/45C has been addressed.
The 4 LSBs of the control byte are used to determine which channel is to be selected.
When a channel is selected, the channel will become active after a STOP condition has
been placed on the I2C-bus. This ensures that all SCx/SDx lines are in a HIGH state when
the channel is made active, so that no false conditions are generated at the time of
connection.
Table 4.
Control register: write (channel selection); read (channel status)
INT3
INT2
INT1
INT0
B3
B2
B1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
X
0
1
0
0
0
1
B0
Command
0
channel 0 disabled
1
channel 0 enabled
X
X
X
X
X
X
0
0
0
1
channel 1 disabled
channel 1 enabled
channel 2 disabled
channel 2 enabled
channel 3 disabled
channel 3 enabled
no channel selected;
power-up/reset default state
Remark: Several channels can be enabled at the same time. Example: B3 = 0, B2 = 1,
B1 = 1, B0 = 0, means that channel 0 and channel 3 are disabled and channel 1 and
channel 2 are enabled. Care should be taken not to exceed the maximum bus capacity.
PCA9545A_45B_45C
Product data sheet
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Rev. 9 — 5 May 2014
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PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
6.2.2 Interrupt handling
The PCA9545A/45B/45C provides 4 interrupt inputs, one for each channel, and one
open-drain interrupt output. When an interrupt is generated by any device, it is detected
by the PCA9545A/45B/45C and the interrupt output is driven LOW. The channel does not
need to be active for detection of the interrupt. A bit is also set in the control register.
Bit 4 through bit 7 of the control register corresponds to channel 0 through channel 3 of
the PCA9545A/45B/45C, respectively. Therefore, if an interrupt is generated by any
device connected to channel 1, the state of the interrupt inputs is loaded into the control
register when a read is accomplished. Likewise, an interrupt on any device connected to
channel 0 would cause bit 4 of the control register to be set on the read. The master can
then address the PCA9545A/45B/45C and read the contents of the control register to
determine which channel contains the device generating the interrupt. The master can
then reconfigure the PCA9545A/45B/45C to select this channel, and locate the device
generating the interrupt and clear it.
It should be noted that more than one device can provide an interrupt on a channel, so it is
up to the master to ensure that all devices on a channel are interrogated for an interrupt.
If the interrupt function is not required, the interrupt inputs may be used as
general-purpose inputs.
If unused, interrupt inputs must be connected to VDD through a pull-up resistor.
Table 5.
INT3
Control register: Read — interrupt
INT2
X
X
X
X
X
0
1
0
1
X
INT1
B3
B2
B1
B0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
INT0
0
1
Command
no interrupt on channel 0
interrupt on channel 0
no interrupt on channel 1
interrupt on channel 1
no interrupt on channel 2
interrupt on channel 2
no interrupt on channel 3
interrupt on channel 3
Remark: Several interrupts can be active at the same time. Example: INT3 = 0, INT2 = 1,
INT1 = 1, INT0 = 0, means that there is no interrupt on channel 0 and channel 3, and
there is interrupt on channel 1 and channel 2.
6.3 RESET input
The RESET input is an active LOW signal which may be used to recover from a bus fault
condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9545A/45B/45C
resets its registers and I2C-bus state machine and deselects all channels. The RESET
input must be connected to VDD through a pull-up resistor.
PCA9545A_45B_45C
Product data sheet
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Rev. 9 — 5 May 2014
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8 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
6.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the
PCA9545A/45B/45C in a reset condition until VDD has reached VPOR. At this point, the
reset condition is released and the PCA9545A/45B/45C registers and I2C-bus state
machine are initialized to their default states (all zeroes) causing all the channels to be
deselected. Thereafter, VDD must be lowered below 0.2 V for at least 5 s in order to reset
the device.
6.5 Voltage translation
The pass gate transistors of the PCA9545A/45B/45C are constructed such that the VDD
voltage can be used to limit the maximum voltage that is passed from one I2C-bus to
another.
002aaa964
5.0
Vo(sw)
(V)
4.0
(1)
(2)
3.0
(3)
2.0
1.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
(1) maximum
(2) typical
(3) minimum
Fig 9.
Pass gate voltage versus supply voltage
Figure 9 shows the voltage characteristics of the pass gate transistors (note that the graph
was generated using the data specified in Section 11 “Static characteristics” of this data
sheet). In order for the PCA9545A/45B/45C to act as a voltage translator, the Vo(sw)
voltage should be equal to, or lower than the lowest bus voltage. For example, if the main
bus was running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw)
should be equal to or below 2.7 V to clamp the downstream bus voltages effectively.
Looking at Figure 9, we see that Vo(sw)(max) is at 2.7 V when the PCA9545A/45B/45C
supply voltage is 3.5 V or lower, so the PCA9545A/45B/45C supply voltage could be set to
3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate
levels (see Figure 16).
More Information can be found in Application Note AN262: PCA954X family of I2C/SMBus
multiplexers and switches.
PCA9545A_45B_45C
Product data sheet
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Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
9 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
7. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse, as changes in the data line at this time
are interpreted as control signals (see Figure 10).
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Fig 10. Bit transfer
7.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the
STOP condition (P) (see Figure 11).
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Fig 11. Definition of START and STOP conditions
PCA9545A_45B_45C
Product data sheet
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Rev. 9 — 5 May 2014
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PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
7.3 System configuration
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 12).
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Fig 12. System configuration
7.4 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of 8 bits is followed by one acknowledge
bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the
master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
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Fig 13. Acknowledgement on the I2C-bus
PCA9545A_45B_45C
Product data sheet
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PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
7.5 Bus transactions
Data is transmitted to the PCA9545A/45B/45C control register using the Write mode as
shown in Figure 14.
slave address
SDA
S
1
1
1
0
0
control register
A1
A0
START condition
0
R/W
A
X
X
X
X
B3
B2
acknowledge
from slave
B1
B0
A
P
acknowledge
from slave
STOP condition
002aab172
Fig 14. Write control register
Data is read from PCA9545A/45B/45C using the Read mode as shown in Figure 15.
slave address
SDA
S
1
1
1
0
0
START condition
last byte
control register
A1
A0
1
R/W
A
INT3 INT2 INT1 INT0 B3
acknowledge
from slave
B2
B1
B0
NA
P
no acknowledge
from master
STOP condition
002aab173
Fig 15. Read control register
PCA9545A_45B_45C
Product data sheet
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PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
8. Application design-in information
VDD = 2.7 V to 5.5 V
VDD = 3.3 V
V = 2.7 V to 5.5 V
see note (1)
SDA
SDA
SD0
SCL
SCL
SC0
INT
INT0
channel 0
V = 2.7 V to 5.5 V
RESET
see note (1)
I2C-bus/SMBus master
SD1
channel 1
SC1
INT1
V = 2.7 V to 5.5 V
PCA9545A
SD2
see note (1)
channel 2
SC2
INT2
V = 2.7 V to 5.5 V
see note (1)
A1
SD3
A0
SC3
VSS
INT3
channel 3
002aab171
(1) If the device generating the interrupt has an open-drain output structure or can be 3-stated, a
pull-up resistor is required.
If the device generating the interrupt has a totem-pole output structure and cannot be 3-stated, a
pull-up resistor is not required.
The interrupt inputs should not be left floating.
Fig 16. Typical application
PCA9545A_45B_45C
Product data sheet
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PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
9. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
VSS (ground = 0 V).
Symbol
Parameter
VDD
VI
Conditions
Min
Max
Unit
supply voltage
0.5
+7.0
V
input voltage
0.5
+7.0
V
II
input current
-
20
mA
IO
output current
-
25
mA
IDD
supply current
-
100
mA
ISS
ground supply current
-
100
mA
Ptot
total power dissipation
-
400
mW
-
125
C
Tj(max)
maximum junction temperature
Tstg
storage temperature
Tamb
ambient temperature
[1]
[1]
operating
60
+150
C
40
+85
C
The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 125 C.
10. Thermal characteristics
Table 7.
PCA9545A_45B_45C
Product data sheet
Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction
to ambient
HVQFN20 package
32
C/W
SO20 package
90
C/W
TSSOP20 package
146
C/W
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Rev. 9 — 5 May 2014
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PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
11. Static characteristics
Table 8.
Static characteristics at VDD = 2.3 V to 3.6 V
VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. See Table 9 on page 16 for VDD = 4.5 V to 5.5 V[1].
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply
VDD
supply voltage
2.3
-
3.6
V
IDD
supply current
Operating mode; VDD = 3.6 V; no load;
VI = VDD or VSS; fSCL = 100 kHz
-
10
30
A
Istb
standby current
Standby mode; VDD = 3.6 V; no load;
VI = VDD or VSS
-
0.1
1
A
VPOR
power-on reset voltage
no load; VI = VDD or VSS
-
1.6
2.1
V
0.5
-
+0.3VDD
V
[2]
Input SCL; input/output SDA
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
IOL
LOW-level output current
0.7VDD
-
6
V
VOL = 0.4 V
3
7
-
mA
VOL = 0.6 V
6
10
-
mA
IL
leakage current
VI = VDD or VSS
1
-
+1
A
Ci
input capacitance
VI = VSS
-
10
13
pF
Select inputs A0, A1, INT0 to INT3, RESET
VIL
LOW-level input voltage
0.5
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
6
V
ILI
input leakage current
pin at VDD or VSS
1
-
+1
A
Ci
input capacitance
VI = VSS
-
1.6
3
pF
ON-state resistance
VDD = 3.6 V; VO = 0.4 V; IO = 15 mA
5
11
30
VDD = 2.3 V to 2.7 V; VO = 0.4 V;
IO = 10 mA
7
16
55
Vi(sw) = VDD = 3.3 V; Io(sw) = 100 A
-
1.9
-
V
Vi(sw) = VDD = 3.0 V to 3.6 V;
Io(sw) = 100 A
1.6
-
2.8
V
Vi(sw) = VDD = 2.5 V; Io(sw) = 100 A
-
1.5
-
V
Vi(sw) = VDD = 2.3 V to 2.7 V;
Io(sw) = 100 A
1.1
-
2.0
V
Pass gate
Ron
Vo(sw)
switch output voltage
IL
leakage current
VI = VDD or VSS
1
-
+1
A
Cio
input/output capacitance
VI = VSS
-
3
5
pF
IOL
LOW-level output current
VOL = 0.4 V
3
-
-
mA
IOH
HIGH-level output current
-
-
+10
A
INT output
[1]
For operation between published voltage ranges, refer to the worst-case parameter in both ranges.
[2]
VDD must be lowered to 0.2 V for at least 5 s in order to reset part.
PCA9545A_45B_45C
Product data sheet
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Rev. 9 — 5 May 2014
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15 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
Table 9.
Static characteristics at VDD = 4.5 V to 5.5 V
VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. See Table 8 on page 15 for VDD = 2.3 V to 3.6 V[1].
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
4.5
-
5.5
V
Supply
VDD
supply voltage
IDD
supply current
Operating mode; VDD = 5.5 V;
no load; VI = VDD or VSS;
fSCL = 100 kHz
-
25
100
A
Istb
standby current
Standby mode; VDD = 5.5 V;
no load; VI = VDD or VSS
-
0.3
1
A
VPOR
power-on reset voltage
no load; VI = VDD or VSS
-
1.7
2.1
V
[2]
Input SCL; input/output SDA
VIL
LOW-level input voltage
0.5
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
6
V
IOL
LOW-level output current
VOL = 0.4 V
3
-
-
mA
VOL = 0.6 V
6
-
-
mA
IL
leakage current
VI = VSS
1
-
+1
A
Ci
input capacitance
VI = VSS
-
10
13
pF
Select inputs A0, A1, INT0 to INT3, RESET
VIL
LOW-level input voltage
0.5
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
6
V
ILI
input leakage current
VI = VDD or VSS
1
-
+1
A
Ci
input capacitance
VI = VSS
-
2
5
pF
Ron
ON-state resistance
VDD = 4.5 V to 5.5 V; VO = 0.4 V;
IO = 15 mA
4
9
24
Vo(sw)
switch output voltage
Vi(sw) = VDD = 5.0 V;
Io(sw) = 100 A
-
3.6
-
V
Vi(sw) = VDD = 4.5 V to 5.5 V;
Io(sw) = 100 A
2.6
-
4.5
V
Pass gate
IL
leakage current
VI = VDD or VSS
1
-
+1
A
Cio
input/output capacitance
VI = VSS
-
3
5
pF
IOL
LOW-level output current
VOL = 0.4 V
3
-
-
mA
IOH
HIGH-level output current
-
-
+10
A
INT output
[1]
For operation between published voltage ranges, refer to the worst-case parameter in both ranges.
[2]
VDD must be lowered to 0.2 V for at least 5 s in order to reset part.
PCA9545A_45B_45C
Product data sheet
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Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
16 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
12. Dynamic characteristics
Table 10.
Dynamic characteristics
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
from SDA to SDx,
or SCL to SCx
Fast-mode I2C-bus Unit
Min
Max
Min
-
0.3[1]
Max
-
0.3[1] ns
0
100
0
400
4.7
-
1.3
-
s
4.0
-
0.6
-
s
tPD
propagation delay
fSCL
SCL clock frequency
tBUF
bus free time between a STOP and
START condition
tHD;STA
hold time (repeated) START condition
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
s
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
-
s
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
s
tSU;STO
set-up time for STOP condition
4.0
-
0.6
-
s
tHD;DAT
data hold time
0[3]
3.45
0[3]
0.9
s
[2]
kHz
tSU;DAT
data set-up time
250
-
100
-
ns
tr
rise time of both SDA and SCL
signals
-
1000
20 + 0.1Cb[4]
300
ns
tf
fall time of both SDA and SCL signals
-
300
20 + 0.1Cb[4]
300
ns
Cb
capacitive load for each bus line
-
400
-
400
pF
tSP
pulse width of spikes that must be
suppressed by the input filter
-
50
-
50
ns
tVD;DAT
data valid time
-
1
-
1
s
tVD;ACK
HIGH-to-LOW
[5]
LOW-to-HIGH
[5]
data valid acknowledge time
-
0.6
-
0.6
s
-
1
-
1
s
-
4
-
4
s
INT
tv(INTnN-INTN) valid time from INTn to INT signal
-
2
-
2
s
tw(rej)L
LOW-level rejection time
INTn inputs
1
-
1
-
s
tw(rej)H
HIGH-level rejection time
INTn inputs
0.5
-
0.5
-
s
4
-
4
-
ns
SDA clear
500
-
500
-
ns
0
-
0
-
ns
td(INTnN-INTN) delay time from INTn to INT inactive
RESET
tw(rst)L
LOW-level reset time
trst
reset time
tREC;STA
recovery time to START condition
[1]
Pass gate propagation delay is calculated from the 20 typical Ron and the 15 pF load capacitance.
[2]
After this period, the first clock pulse is generated.
[3]
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4]
Cb = total capacitance of one bus line in pF.
[5]
Measurements taken with 1 k pull-up resistor and 50 pF load.
PCA9545A_45B_45C
Product data sheet
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Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
17 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
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ACK or read cycle
START
SCL
SDA
30 %
trst
RESET
50 %
50 %
50 %
tREC;STA
tw(rst)L
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Fig 18. Definition of RESET timing
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Fig 19. I2C-bus timing diagram
PCA9545A_45B_45C
Product data sheet
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Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
18 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
SCL
2
1
0
A
70 %
30 %
P
SDA
INPUT
50 %
tv(INTnN−INTN)
td(INTnN−INTN)
INT
002aab176
Fig 20. Expanded view of read input port register
13. Test information
VDD
VDD
PULSE
GENERATOR
VI
VO
RL
500 Ω
D.U.T.
RT
CL
50 pF
002aab177
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 21. Test circuitry for switching times
PCA9545A_45B_45C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
19 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
14. Package outline
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Fig 22. Package outline SOT163-1 (SO20)
PCA9545A_45B_45C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
20 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
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Fig 23. Package outline SOT360-1 (TSSOP20)
PCA9545A_45B_45C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
21 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
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Fig 24. Package outline SOT662-1 (HVQFN20)
PCA9545A_45B_45C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
22 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCA9545A_45B_45C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
23 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
15.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 25) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 11 and 12
Table 11.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 12.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 25.
PCA9545A_45B_45C
Product data sheet
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Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
24 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 25. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCA9545A_45B_45C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
25 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
16. Soldering: PCB footprints
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Fig 27. PCB footprint for SOT163-1 (SO20); wave soldering
PCA9545A_45B_45C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
26 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
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Fig 28. PCB footprint for SOT360-1 (TSSOP20); reflow soldering
PCA9545A_45B_45C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
27 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
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Fig 29. PCB footprint for SOT662-1 (HVQFN20); reflow soldering
PCA9545A_45B_45C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
28 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
17. Abbreviations
Table 13.
Abbreviations
Acronym
Description
CDM
Charged-Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
IC
Integrated Circuit
I2C-bus
Inter-Integrated Circuit bus
LSB
Least Significant Bit
MSB
Most Significant Bit
PCB
Printed-Circuit Board
POR
Power-On Reset
SMBus
System Management Bus
18. Revision history
Table 14.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9545A_45B_45C v.9
20140505
Product data sheet
-
PCA9545A_45B_45C v.8
Modifications:
•
Section 6.4 “Power-on reset”, first paragraph, third sentence corrected from “Thereafter,
VDD must be lowered below 0.2 V to reset the device.”
to “Thereafter, VDD must be lowered below 0.2 V for at least 5 s in order to reset the
device.” (this is a correction to documentation only; no change to device)
•
Table 8 “Static characteristics at VDD = 2.3 V to 3.6 V”: Table note [2] corrected by inserting
phrase “for at least 5 s” (this is a correction to documentation only; no change to device)
•
Table 9 “Static characteristics at VDD = 4.5 V to 5.5 V”: Table note [2] corrected by inserting
phrase “for at least 5 s” (this is a correction to documentation only; no change to device)
PCA9545A_45B_45C v.8
20130514
Product data sheet
-
PCA9545A_45B_45C v.7
PCA9545A_45B_45C v.7
20090619
Product data sheet
-
PCA9545A_45B_45C v.6
PCA9545A_45B_45C v.6
20070319
Product data sheet
-
PCA9545A_45B_45C v.5
PCA9545A_45B_45C v.5
20061017
Product data sheet
-
PCA9545A v.4
PCA9545A v.4
20060925
Product data sheet
-
PCA9545A v.3
PCA9545A v.3
20050303
Product data sheet
-
PCA9545A v.2
PCA9545A v.2
20040929
Objective data sheet
-
PCA9545A v.1
PCA9545A v.1
20040728
Objective data sheet
-
-
PCA9545A_45B_45C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
29 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9545A_45B_45C
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
30 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCA9545A_45B_45C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
31 of 32
PCA9545A/45B/45C
NXP Semiconductors
4-channel I2C-bus switch with interrupt logic and reset
21. Contents
1
2
3
3.1
4
5
5.1
5.2
6
6.1
6.2
6.2.1
6.2.2
6.3
6.4
6.5
7
7.1
7.2
7.3
7.4
7.5
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
18
19
19.1
19.2
19.3
19.4
20
21
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 6
Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6
Control register . . . . . . . . . . . . . . . . . . . . . . . . . 7
Control register definition . . . . . . . . . . . . . . . . . 7
Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . 8
RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9
Voltage translation . . . . . . . . . . . . . . . . . . . . . . 9
Characteristics of the I2C-bus . . . . . . . . . . . . 10
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
START and STOP conditions . . . . . . . . . . . . . 10
System configuration . . . . . . . . . . . . . . . . . . . 11
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 12
Application design-in information . . . . . . . . . 13
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14
Thermal characteristics . . . . . . . . . . . . . . . . . 14
Static characteristics. . . . . . . . . . . . . . . . . . . . 15
Dynamic characteristics . . . . . . . . . . . . . . . . . 17
Test information . . . . . . . . . . . . . . . . . . . . . . . . 19
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20
Soldering of SMD packages . . . . . . . . . . . . . . 23
Introduction to soldering . . . . . . . . . . . . . . . . . 23
Wave and reflow soldering . . . . . . . . . . . . . . . 23
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 23
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 24
Soldering: PCB footprints. . . . . . . . . . . . . . . . 26
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 29
Legal information. . . . . . . . . . . . . . . . . . . . . . . 30
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Contact information. . . . . . . . . . . . . . . . . . . . . 31
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 5 May 2014
Document identifier: PCA9545A_45B_45C