PHILIPS 74AHC1G08

INTEGRATED CIRCUITS
DATA SHEET
74AHC1G08; 74AHCT1G08
2-input AND gate
Product specification
Supersedes data of 1998 Nov 25
File under Integrated Circuits, IC06
1999 Jan 27
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
FEATURES
• Symmetrical output impedance
• High noise immunity
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
TYPICAL
SYMBOL
PARAMETER
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A exceeds
200 V
tPHL/tPLH
propagation delay
inA, inB to outY
CI
input capacitance
• Low power dissipation
CPD
power dissipation
capacitance
CONDITIONS
UNIT
AHC1G AHCT1G
• Balanced propagation delays
• Very small 5-pin package
CL = 15 pF;
VCC = 5 V
notes 1 and 2;
CL = 50 pF;
f = 1 MHz
3.2
3.6
ns
1.5
1.5
pF
17
19
pF
Notes
• Output capability: standard.
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
DESCRIPTION
fi = input frequency in MHz;
The 74AHC1G/AHCT1G08 is a
high-speed Si-gate CMOS device.
fo = output frequency in MHz;
CL = output load capacitance in pF;
The 74AHC1G/AHCT1G08 provides
the 2-input AND function.
VCC = supply voltage in V.
2. The condition is VI = GND to VCC.
FUNCTION TABLE
See note 1.
INPUTS
PINNING
OUTPUT
PIN
SYMBOL
DESCRIPTION
inA
inB
outY
1
inB
data input
L
L
L
2
inA
data input
GND
ground (0 V)
L
H
L
3
H
L
L
4
outY
data output
H
H
H
5
VCC
DC supply voltage
Note
1. H = HIGH voltage level.
L = LOW voltage level.
ORDERING AND PACKAGE INFORMATION
PACKAGES
TYPE NUMBER
74AHC1G08GW
74AHCT1G08GW
1999 Jan 27
TEMPERATURE
RANGE
−40 to +85 °C
PINS
PACKAGE
MATERIAL
CODE
MARKING
5
SC-88A
plastic
SOT353
AE
5
SC-88A
plastic
SOT353
CE
2
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
handbook, halfpage
inB 1
inA 2
GND
5 VCC
handbook, halfpage
08
3
4
1
inB
2
inA
outY
4
outY
MNA113
MNA112
Fig.1 Pin configuration.
handbook, halfpage
1
Fig.2 Logic symbol.
handbook, halfpage
&
inB
4
2
outY
MNA114
inA
MNA115
Fig.3 IEC logic symbol.
1999 Jan 27
Fig.4 Logic diagram.
3
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
RECOMMENDED OPERATING CONDITIONS
74AHC1G
SYMBOL
PARAMETER
74AHCT1G
CONDITIONS
UNIT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
VCC
DC supply voltage
2.0
5.0
5.5
4.5
5.0
5.5
V
VI
input voltage
0
−
5.5
0
−
5.5
V
VO
output voltage
0
−
VCC
0
−
VCC
V
Tamb
operating ambient
temperature range
see DC and AC
characteristics per
device
−40
+25
+85
−40
+25
+85
°C
tr,tf (∆t/∆f)
input rise and fall times
except for
Schmitt-trigger inputs
VCC = 3.3 V ±0.3 V
−
−
100
−
−
−
ns/V
VCC = 5 V ±0.5 V
−
−
20
−
−
20
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
DC supply voltage
−0.5
+7.0
V
VI
input voltage range
−0.5
+7.0
V
IIK
DC input diode current
VI < −0.5
−
−20
mA
IOK
DC output diode current
VO < −0.5 or VO > VCC + 0.5 V; note 1
−
±20
mA
IO
DC output source or sink current −0.5 V < VO < VCC + 0.5 V
−
±25
mA
ICC
DC VCC or GND current
−
±75
mA
Tstg
storage temperature range
−65
+150
°C
PD
power dissipation per package
200
mW
temperature range: −40 to +85 °C; note 2 −
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above +55 °C the value of PD derates linearly with 2.5 mW/K.
1999 Jan 27
4
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
DC CHARACTERISTICS
Family 74AHC1G
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
VIL
VOH
VOH
VOL
VOL
−40 to +85
+25
OTHER
VIH
Tamb (°C)
HIGH-level input
voltage
LOW-level input voltage
VCC (V)
MIN.
TYP.
MAX.
MIN.
MAX.
2.0
1.5
−
−
1.5
−
3.0
2.1
−
−
2.1
−
5.5
3.85
−
−
3.85
−
2.0
−
−
0.5
−
0.5
3.0
−
−
0.9
−
0.9
5.5
−
−
1.65
−
1.65
2.0
1.9
2.0
−
1.9
−
3.0
2.9
3.0
−
2.9
−
HIGH-level output
voltage; all outputs
VI = VIH or VIL;
IO = −50 µA
4.5
4.4
4.5
−
4.4
−
HIGH-level output
voltage
VI = VIH or VIL;
IO = −4.0 mA
3.0
2.58
−
−
2.48
−
VI = VIH or VIL;
IO = −8.0 mA
4.5
3.94
−
−
3.8
−
VI = VIH or VIL;
IO = 50 µA
2.0
−
0
0.1
−
0.1
3.0
−
0
0.1
−
0.1
4.5
−
0
0.1
−
0.1
VI = VIH or VIL;
IO = 4 mA
3.0
−
−
0.36
−
0.44
VI = VIH or VIL;
IO = 8 mA
4.5
−
−
0.36
−
0.44
LOW-level output
voltage; all outputs
LOW-level output
voltage
UNIT
V
V
V
V
V
V
II
input leakage current
VI = VCC or GND
5.5
−
−
0.1
−
1.0
µA
ICC
quiescent supply
current
VI = VCC or GND; 5.5
IO = 0
−
−
1.0
−
10
µA
CI
input capacitance
−
1.5
10
−
10
pF
1999 Jan 27
5
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
Family 74AHCT1G
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
Tamb (°C)
PARAMETER
−40 to +85
+25
OTHER
VCC (V)
MIN.
TYP.
MAX.
MIN.
MAX.
UNIT
VIH
HIGH-level input voltage
4.5 to 5.5
2.0
−
−
2.0
−
V
VIL
LOW-level input voltage
4.5 to 5.5
−
−
0.8
−
0.8
V
VOH
HIGH-level output
voltage; all outputs
VI = VIH or VIL;
IO = −50 µA
4.5
4.4
4.5
−
4.4
−
V
VOH
HIGH-level output
voltage
VI = VIH or VIL;
IO = −8.0 mA
4.5
3.94
−
−
3.8
−
V
VOL
LOW-level output
voltage; all outputs
VI = VIH or VIL;
IO = 50 µA
4.5
−
0
0.1
−
0.1
V
VOL
LOW-level output voltage VI = VIH or VIL;
IO = 8 mA
4.5
−
−
0.36
−
0.44
V
II
input leakage current
VI = VIH or VIL
5.5
−
−
0.1
−
1.0
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0
5.5
−
−
1.0
−
10
µA
∆ICC
additional quiescent
supply current per input
pin
VI = 3.4 V
other inputs at
VCC or GND; IO = 0
5.5
−
−
1.35
−
1.5
mA
CI
input capacitance
−
1.5
10
−
10
pF
1999 Jan 27
6
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
AC CHARACTERISTICS
Type 74AHC1G08
GND = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
SYMBOL
Tamb (°C)
PARAMETER
−40 to +85
+25
WAVEFORMS
CL
VCC (V)
MIN.
TYP.
MAX.
MIN.
MAX.
UNIT
tPHL/tPLH
propagation delay
inA, inB to outY
see Figs 5 and 6
15 pF
3.0 to 3.6
−
4.6(1)
8.8
1.0
10.5
ns
tPHL/tPLH
propagation delay
inA, inB to outY
see Figs 5 and 6
50 pF
3.0 to 3.6
−
6.5(1)
12.3
1.0
14.0
ns
tPHL/tPLH
propagation delay
inA, inB to outY
see Figs 5 and 6
15 pF
4.5 to 5.5
−
3.2(2)
5.9
1.0
7.0
ns
tPHL/tPLH
propagation delay
inA, inB to outY
see Figs 5 and 6
50 pF
4.5 to 5.5
−
4.6(2)
7.9
1.0
9.0
ns
Notes
1. Typical values at VCC = 3.3 V.
2. Typical values at VCC = 5.0 V.
Type 74AHCT1G08
GND = 0 V; tr = tf ≤ 3.0 ns.
Tamb (°C)
TEST CONDITIONS
SYMBOL
−40 to +85
+25
PARAMETER
WAVEFORMS
CL
VCC (V)
MIN.
TYP.
MAX.
MIN.
MAX.
UNIT
tPHL/tPLH
propagation delay
inA, inB to outY
see Figs 5 and 6
15 pF
4.5 to 5.5
−
3.6(1)
6.9
1.0
8.0
ns
tPHL/tPLH
propagation delay
inA, inB to outY
see Figs 5 and 6
50 pF
4.5 to 5.5
−
5.1(1)
7.9
1.0
9.0
ns
Note
1. Typical values at VCC = 5.0 V.
1999 Jan 27
7
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
AC WAVEFORMS
handbook, halfpage
inA, inB INPUT
VCC
handbook, halfpage
VM(1)
PULSE
GENERATOR
tPLH
tPHL
VI
VO
D.U.T.
RT
outY OUTPUT
VM(1)
CL
MNA101
MNA116
FAMILY
VI INPUT
REQUIREMENTS
VM
INPUT
VM
OUTPUT
AHC1G
GND to VCC
50% VCC 50% VCC
AHCT1G
GND to 3.0 V
1.5 V
Fig.5
Definitions for test circuit;
(1) CL = Load capacitance including jig and probe capacitance.
(See Chapter “AC characteristics”).
(2) RT = Termination resistance should be equal to the output
impedance Zo of the pulse generator.
50% VCC
The input (inA, inB) to output (outY)
propagation delays.
1999 Jan 27
Fig.6 Load circuitry for switching times.
8
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
PACKAGE OUTLINE
Plastic surface mounted package; 5 leads
SOT353
D
E
B
y
X
A
HE
5
v M A
4
Q
A
A1
1
2
e1
3
bp
c
Lp
w M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
c
D
E (2)
e
e1
HE
Lp
Q
v
w
y
mm
1.1
0.8
0.1
0.30
0.20
0.25
0.10
2.2
1.8
1.35
1.15
1.3
0.65
2.2
2.0
0.45
0.15
0.25
0.15
0.2
0.2
0.1
OUTLINE
VERSION
SOT353
1999 Jan 27
REFERENCES
IEC
JEDEC
EIAJ
SC-88A
9
EUROPEAN
PROJECTION
ISSUE DATE
97-02-28
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
• For packages with leads on two sides and a pitch (e):
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1999 Jan 27
10
Philips Semiconductors
Product specification
2-input AND gate
74AHC1G08; 74AHCT1G08
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
HLQFP, HSQFP, HSOP, SMS
not
PLCC(3),
SO, SOJ
suitable
suitable(2)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(3)(4)
suitable
SSOP, TSSOP, VSO
not recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Jan 27
11
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252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1999
SCA61
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands
245002/00/02/pp12
Date of release: 1999 Jan 27
Document order number:
9397 750 04944