HEF4071B Quad 2-input OR gate Rev. 06 — 1 December 2009 Product data sheet 1. General description The HEF4071B is a quad 2-input OR gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over both the industrial (−40 °C to +85 °C) and automotive (−40 °C to +125 °C) temperature ranges. 2. Features Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Inputs and outputs are protected against electrostatic effects Operates across the automotive temperature range from −40 °C to +125 °C Complies with JEDEC standard JESD 13-B 3. Applications Automotive and industrial 4. Ordering information Table 1. Ordering information All types operate from −40 °C to +125 °C. Type number Package Name Description Version HEF4071BP DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 HEF4071BT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 HEF4071B NXP Semiconductors Quad 2-input OR gate 5. Functional diagram 1 2 1A 1B 1Y 3 5 6 2A 2B 2Y 4 8 9 3A 3B 3Y 10 12 13 4A 4B 4Y 11 nA nB 001aaj108 001aaj110 Fig 1. nY Functional diagram Fig 2. Logic diagram (one gate) 6. Pinning information 6.1 Pinning HEF4071B 1A 1 14 VDD 1B 2 13 4B 1Y 3 12 4A 2Y 4 11 4Y 2A 5 10 3Y 2B 6 9 3B VSS 7 8 3A 001aaj107 Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 5, 8, 12 input 1B to 4B 2, 6, 9, 13 input 1Y to 4Y 3, 4, 10, 11 output VSS 7 ground (0 V) VDD 14 supply voltage HEF4071B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 1 December 2009 2 of 11 HEF4071B NXP Semiconductors Quad 2-input OR gate 7. Functional description Table 3. Function table[1] Input Output nA nB nY L L L L H H H L H H H H [1] H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current - ±10 mA II/O input/output current - ±10 mA IDD supply current - 50 mA Tstg storage temperature −65 +150 °C Tamb ambient temperature −40 +125 °C Ptot total power dissipation P power dissipation Conditions Min VI < −0.5 V or VI > VDD + 0.5 V Unit +18 V - ±10 mA −0.5 VO < −0.5 V or VO > VDD + 0.5 V Max −0.5 VDD + 0.5 V Tamb = −40 °C to + 125 °C DIP14 [1] - 750 mW SO14 [2] - 500 mW - 100 mW per output [1] For DIP14 packages: above Tamb = 70 °C, Ptot derates linearly with 12 mW/K. [2] For SO14 packages: above Tamb = 70 °C, Ptot derates linearly with 8 mW/K. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Max Unit VDD supply voltage 3 15 V VI input voltage Tamb ambient temperature in free air 0 VDD V −40 +125 °C Δt/ΔV input transition rise and fall rate VDD = 5 V - 3.75 μs/V VDD = 10 V - 0.5 μs/V VDD = 15 V - 0.08 μs/V HEF4071B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 1 December 2009 3 of 11 HEF4071B NXP Semiconductors Quad 2-input OR gate 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage |IO| < 1 μA |IO| < 1 μA |IO| < 1 μA VDD Tamb = −40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit Min Max Min Max Min Max Min Max 5V 3.5 - 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 - 0.05 V V LOW-level output voltage |IO| < 1 μA 15 V - 0.05 - 0.05 - 0.05 - 0.05 HIGH-level output current VO = 2.5 V 5V −1.7 - −1.4 - −1.1 - −1.1 - mA VO = 4.6 V 5V −0.64 - −0.5 - −0.36 - −0.36 - mA VO = 9.5 V 10 V −1.6 - −1.3 - −0.9 - −0.9 - mA VO = 13.5 V 15 V −4.2 - −3.4 - −2.4 - −2.4 - mA VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA 15 V - ±0.1 - ±0.1 - ±1.0 - ±1.0 μA 5V all valid input combinations; 10 V IO = 0 A 15 V - 0.25 - 0.25 - 7.5 - 7.5 μA - 0.5 - 0.5 - 15.0 - 15.0 μA - 1.0 - 1.0 - 30.0 - 30.0 μA - - - 7.5 - - - - pF LOW-level output current II input leakage current IDD supply current CI Conditions input capacitance HEF4071B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 1 December 2009 4 of 11 HEF4071B NXP Semiconductors Quad 2-input OR gate 11. Dynamic characteristics Table 7. Dynamic characteristics Tamb = 25 °C; waveforms see Figure 4; test circuit see Figure 5; unless otherwise specified. [1] Symbol Parameter HIGH to LOW propagation delay tPHL LOW to HIGH propagation delay tPLH Conditions VDD nA or nB to nY Min Typ Max Unit 5V 28 ns + (0.55 ns/pF)CL - 55 115 ns 10 V 15 ns + (0.23 ns/pF)CL - 25 50 ns 15 V 12 ns + (0.16 ns/pF)CL - 20 35 ns 5V 18 ns + (0.55 ns/pF)CL - 45 90 ns 10 V 9 ns + (0.23 ns/pF)CL - 20 45 ns 15 V 7 ns + (0.16 ns/pF)CL - 15 30 ns 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns nA or nB to nY transition time tt Extrapolation formula [2] 5V [1] The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF). [2] tt is the same as tTHL and tTLH. Table 8. Dynamic power dissipation VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol Parameter PD VDD dynamic power dissipation Typical formula where: 5 V PD = 1150 × fi + Σ(fo × CL) × VDD (μW) 2 fi = input frequency in MHz; 10 V PD = 4800 × fi + Σ(fo × CL) × VDD2 (μW) fo = output frequency in MHz; 15 V PD = 19700 × fi + Σ(fo × CL) × VDD2 (μW) CL = output load capacitance in pF; Σ(fo × CL) = sum of the outputs; VDD = supply voltage in V. 12. Waveforms tr VI tf 90 % nA, nB input VM 0V 10 % tPLH VOH tPHL 90 % nY output VM VOL 10 % tTLH tTHL 001aai140 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 4. Input to output propagation delay and output transition times HEF4071B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 1 December 2009 5 of 11 HEF4071B NXP Semiconductors Quad 2-input OR gate Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD VDD VI VO G DUT CL RT 001aag182 Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 5. Test circuit Table 10. Test data Supply voltage Input Load VDD VI tr, tf CL 5 V to 15 V VSS or VDD ≤ 20 ns 50 pF HEF4071B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 1 December 2009 6 of 11 HEF4071B NXP Semiconductors Quad 2-input OR gate 13. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. Fig 6. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Package outline SOT27-1 (DIP14) HEF4071B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 1 December 2009 7 of 11 HEF4071B NXP Semiconductors Quad 2-input OR gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 7. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) HEF4071B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 1 December 2009 8 of 11 HEF4071B NXP Semiconductors Quad 2-input OR gate 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4071B_6 20091201 Product data sheet - HEF4071B_5 Modifications: • Section 9 “Recommended operating conditions” Δt/ΔV values updated. HEF4071B_5 20090728 Product data sheet - HEF4071B_4 HEF4071B_4 20081128 Product data sheet - HEF4071B_CNV_3 HEF4071B_CNV_3 19950101 Product specification - HEF4071B_CNV_2 HEF4071B_CNV_2 19950101 Product specification - - HEF4071B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 1 December 2009 9 of 11 HEF4071B NXP Semiconductors Quad 2-input OR gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. Definition [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] HEF4071B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 1 December 2009 10 of 11 HEF4071B NXP Semiconductors Quad 2-input OR gate 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 3 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Contact information. . . . . . . . . . . . . . . . . . . . . 10 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 1 December 2009 Document identifier: HEF4071B_6