DAC1201D125 Dual 12-bit DAC, up to 125 Msps Rev. 01 — 27 November 2008 Product data sheet 1. General description The DAC1201D125 is a dual-port, high-speed, 2-channel CMOS Digital-to-Analog Converter (DAC), optimized for high dynamic performance with low power dissipation. Supporting an update rate of up to 125 Msps, the DAC1201D125 is suitable for Direct IF applications. Separate write inputs allow data to be written to the two DAC ports independently of one another. Two separate clocks control the update rate of each DAC port. The DAC1201D125 can interface two separate data ports or one single interleaved high-speed data port. In Interleaved mode, the input data stream is demultiplexed into its original I and Q data and latched. The I and Q data is then converted by the two DACs and updated at half the input data rate. Each DAC port has a high-impedance differential current output, suitable for both single-ended and differential analog output configurations. The DAC1201D125 is pin compatible with the AD9765, DAC2902 and DAC5662. 2. Features n n n n Dual 12-bit resolution 125 Msps update rate Single 3.3 V supply Dual-port or Interleaved data modes n n n n Typical 185 mW power dissipation 16 mW power-down SFDR: 81 dBc; fo = 1 MHz; fs = 52 Msps SFDR: 78 dBc; fo = 10.4 MHz; fs = 78 Msps n 1.8 V, 3.3 V and 5 V compatible digital n SFDR: 74 dBc; fo = 1 MHz; inputs fs = 52 Msps; −12 dBFS n Internal and external reference n LQFP48 package n 2 mA to 20 mA full-scale output current n Industrial temperature range of −40 °C to +85 °C 3. Applications n Quadrature modulation n Medical/test instrumentation n Direct IF applications n Direct digital frequency synthesis n Arbitrary waveform generator DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 4. Ordering information Table 1. Ordering information Type number DAC1201D125HL Package Name Description Version LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2 5. Block diagram DA11 to DA0 12 INPUT A LATCH 12 DAC A LATCH 12 DAC A WRTA/IQWRT DAC1201D125 CONTROL AMPLIFIER CLKB/IQRESET 12 VDDA INPUT B LATCH AGND 12 VDDD DAC B LATCH DGND BVIRES GAINCTRL 12 DAC B IOUTBP IOUTBN 001aai976 Block diagram DAC1201D125_1 Product data sheet AVIRES PWD WRTB/IQSEL Fig 1. IOUTAN REFIO REFERENCE CLKA/IQCLK DB11 to DB0 IOUTAP © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 2 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 6. Pinning information 37 PWD 38 AGND 39 IOUTBP 40 IOUTBN 41 BVIRES 42 GAINCTRL 43 REFIO 44 AVIRES 45 IOUTAN 46 IOUTAP DA11 1 36 n.c. DA10 2 35 n.c. DA9 3 34 DB0 DA8 4 33 DB1 DA7 5 32 DB2 DA6 6 DA5 7 DA4 8 29 DB5 DA3 9 28 DB6 DA2 10 27 DB7 DA1 11 26 DB8 DA0 12 25 DB9 31 DB3 DB10 24 DB11 23 30 DB4 VDDD 22 DGND 21 WRTB/IQSEL 20 CLKB/IQRESET 19 CLKA/IQCLK 18 WRTA/IQWRT 17 VDDD 16 DGND 15 n.c. 14 DAC1201D125HL n.c. 13 Fig 2. 47 VDDA 48 MODE 6.1 Pinning 001aai975 Pin configuration SOT313-2 (LQFP48) 6.2 Pin description Table 2. Pin description Symbol Pin Type[1] Description DA11 1 I DAC A, data input bit 11 (MSB) DA10 2 I DAC A, data input bit 10 DA9 3 I DAC A, data input bit 9 DA8 4 I DAC A, data input bit 8 DA7 5 I DAC A, data input bit 7 DA6 6 I DAC A, data input bit 6 DA5 7 I DAC A, data input bit 5 DA4 8 I DAC A, data input bit 4 DA3 9 I DAC A, data input bit 3 DA2 10 I DAC A, data input bit 2 DA1 11 I DAC A, data input bit 1 DA0 12 I DAC A, data input bit 0 (LSB) n.c. 13 not connected DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 3 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps Table 2. Pin description …continued Type[1] Symbol Pin n.c. 14 Description DGND 15 G digital ground VDDD 16 S digital supply voltage not connected WRTA/IQWRT 17 I input write port A/input write IQ in Interleaved mode CLKA/IQCLK 18 I input clock port A/input clock IQ in Interleaved mode CLKB/IQRESET 19 I input clock port B/reset IQ in Interleaved mode WRTB/IQSEL 20 I input write port B/select IQ in Interleaved mode DGND 21 G digital ground VDDD 22 S digital supply voltage DB11 23 I DAC B, data input bit 11 (MSB) DB10 24 I DAC B, data input bit 10 DB9 25 I DAC B, data input bit 9 DB8 26 I DAC B, data input bit 8 DB7 27 I DAC B, data input bit 7 DB6 28 I DAC B, data input bit 6 DB5 29 I DAC B, data input bit 5 DB4 30 I DAC B, data input bit 4 DB3 31 I DAC B, data input bit 3 DB2 32 I DAC B, data input bit 2 DB1 33 I DAC B, data input bit 1 DB0 34 I DAC B, data input bit 0 (LSB) n.c. 35 not connected n.c. 36 not connected PWD 37 I Power-down mode enable input AGND 38 S analog ground IOUTBP 39 O DAC B current output IOUTBN 40 O complementary DAC B current output BVIRES 41 I adjust DAC B for full-scale output current GAINCTRL 42 I gain control mode enable input REFIO 43 I/O reference voltage input/output AVIRES 44 I adjust DAC A for full-scale output current IOUTAN 45 O complementary DAC A current output IOUTAP 46 O DAC A current output VDDA 47 S analog supply voltage MODE 48 I select between Dual-port or Interleaved mode [1] Type description: S = Supply; G = Ground; I = Input; O = Output; I/O = Input/Output. DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 4 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit −0.3 +5.0 V digital supply voltage [1] VDDA analog supply voltage [1] −0.3 +5.0 V ∆VDD supply voltage difference between analog and digital supply voltage −150 +150 mV VI input voltage digital inputs referenced to DGND −0.3 +5.5 V pins REFIO, AVIRES, BVIRES referenced to AGND −0.3 +5.5 V pins IOUTAP, IOUTAN, IOUTBP and IOUTBN referenced to AGND −0.3 VDDA + 0.3 V +150 VDDD VO output voltage Tstg storage temperature −55 Tamb ambient temperature −40 +85 °C Tj junction temperature - 125 °C [1] °C All supplies are connected together. 8. Thermal characteristics Table 4. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient in free air 89.3 K/W Rth(c-a) thermal resistance from case to ambient in free air 60.6 K/W 9. Characteristics Table 5. Characteristics VDDD = VDDA = 3.3 V; AGND and DGND connected together; IO(fs) = 20 mA and Tamb = −40 °C to +85 °C; typical values measured at Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit 3.0 3.3 3.65 V Supplies VDDD digital supply voltage VDDA analog supply voltage 3.0 3.3 3.65 V IDDD digital supply current fs = 65 Msps, fo = 1 MHz, VDD = 3.0 V to 3.6 V - 6 7 mA IDDA analog supply current fs = 65 Msps, fo = 1 MHz, VDD = 3.0 V to 3.6 V - 50 65 mA Ptot total power dissipation fs = 65 Msps, fo = 1 MHz, VDD = 3.0 V to 3.6 V - 185 260 mW Ppd power dissipation in power-down mode - 16.5 - mW DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 5 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps Table 5. Characteristics …continued VDDD = VDDA = 3.3 V; AGND and DGND connected together; IO(fs) = 20 mA and Tamb = −40 °C to +85 °C; typical values measured at Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit Digital inputs VIL LOW-level input voltage DGND - 0.9 V VIH HIGH-level input voltage 1.3 - VDDD V IIL LOW-level input current VIL = 0.9 V - 5 - µA IIH HIGH-level input current VIH = 1.3 V - 5 - µA - 5 - pF Ci [1] input capacitance Analog outputs (IOUTAP, IOUTAN, IOUTBP and IOUTBN) IO(fs) VO full-scale output current output voltage differential outputs compliance range 2 - 20 mA [1] −1 - +1.25 V - 150 - kΩ - 3 - pF 1.25 1.26 1.27 V - 100 - nA 1.0 - 1.26 V - 1 - MΩ Ro output resistance [1] Co output capacitance [1] Reference voltage input/output (REFIO) VO(ref) reference output voltage IO(ref) reference output current Vi input voltage Ri input resistance [1] compliance range Input timing, see Figure 18 fs sampling frequency - - 125 Msps tw(WRT) WRT pulse width pins WRTA, WRTB 2 - - ns tw(CLK) CLK pulse width pins CLKA, CLKB 2 - - ns th(i) input hold time 1 - - ns tsu(i) input set-up time 1.8 - - ns Output timing (IOUTAP, IOUTAN, IOUTBP and IOUTBN) td delay time - 1 - ns - 0.6 - ns - 40 - ns 25 °C ±0.4 ±0.55 ±0.70 LSB −40 °C to +85 °C ±0.3 - ±0.75 LSB −40 °C to +85 °C ±0.15 ±0.2 ±0.3 LSB −0.02 - +0.02 % with external reference −1.9 ±1.5 +2.5 % with internal reference −2.9 ±2.1 +2.9 % between DAC A and DAC B −0.36 ±0.05 +0.36 % tt transition time rising or falling transition (10 % to 90 % or 90 % to 10 %) [1] ts settling time ±1 LSB [1] Static linearity INL integral non-linearity DNL differential non-linearity Static accuracy (relative to full-scale) Eoffset offset error EG gain error ∆G gain mismatch DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 6 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps Table 5. Characteristics …continued VDDD = VDDA = 3.3 V; AGND and DGND connected together; IO(fs) = 20 mA and Tamb = −40 °C to +85 °C; typical values measured at Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit 0 dBFS - 81 - dBc −6 dBFS - 80 - dBc −12 dBFS - 74 - dBc - 79 - dBc fo = 10.4 MHz - 78 - dBc fo = 15.7 MHz - 71 - dBc fo = 5.04 MHz - 77 - dBc fo = 20.2 MHz 60 69 - dBc - 68 - dBc fs = 52 Msps; fo = 1 MHz; 2 MHz span - 89 - dBc fs = 52 Msps; fo = 5.24 MHz; 10 MHz span - 87 - dBc fs = 78 Msps; fo = 5.26 MHz; 2 MHz span - 90 - dBc fs = 125 Msps; fo = 5.04 MHz; 10 MHz span 79 90 - dBc Dynamic performance SFDR spurious free dynamic range B = Nyquist fs = 52 Msps; fo = 1 MHz fs = 52 Msps; 0 dBFS fo = 5.24 MHz fs = 78 Msps; 0 dBFS fs = 100 Msps; 0 dBFS fs = 125 Msps; 0 dBFS fo = 20.1 MHz within a window THD MTPR total harmonic distortion multitone power ratio fs = 52 Msps; fo = 1 MHz - −78 - dBc fs = 78 Msps; fo = 5.26 MHz - −76 - dBc fs = 100 Msps; fo = 5.04 MHz - −74 - dBc fs = 125 Msps; fo = 20.1 MHz - −64 −60 dBc fs = 65 Msps; 2 MHz < fo < 2.99 MHz; 8 tones at 110 kHz spacing at 0 dB full-scale - 80 - dBc NSD noise spectral density fs = 100 Msps; fo = 5.04 MHz - −148.7 - dBm/Hz αcs channel separation fs = 78 Msps; fo = 10.4 MHz - 88.0 - dBc fs = 125 Msps; fo = 20.1 MHz - 83.5 - dBc [1] Guaranteed by design. DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 7 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 001aai997 80 SFDR (dBc) (1) 76 (2) 72 (3) 68 (4) 64 −60 −20 0 20 60 100 T (°C) (1) fo = 5 MHz (2) fo = 10 MHz (3) fo = 15 MHz (4) fo = 20 MHz Fig 3. SFDR as a function of the ambient temperature at 125 Msps DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 8 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 001aai985 0 α (dBm) −20 −40 −60 −80 −100 0 10 20 30 f (MHz) a. fs = 52 Msps; fc = 5.24 MHz; α = 0 dBFS 001aai987 0 α (dBm) −20 −40 −60 −80 −100 0 10 20 30 40 50 f (MHz) b. fs = 100 Msps; fc = 20 MHz; α = 0 dBFS Fig 4. 1-tone SFDR DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 9 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 001aai988 0 α (dBm) −20 −40 −60 −80 −100 0 10 20 30 40 f (MHz) fs = 78 Msps; fc = 9.44 MHz, fc = 10.44 MHz; α = 0 dBFS Fig 5. 2-tone SFDR 001aai989 0 α (dBm) −20 −40 −60 −80 −100 0 10 20 30 f (MHz) fs = 52 Msps; fc = 6.25 MHz, fc = 6.75 MHz, fc = 7.25 MHz, fc = 7.75 MHz; α = 0 dBFS Fig 6. 4-tone SFDR DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 10 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 001aai990 0 α (dBm) −20 −40 −60 −80 −100 0 10 20 30 40 f (MHz) fs = 78 Msps; from fc = 9.5 MHz, 110 kHz spacing; α = 0 dBFS Fig 7. 8-tone SFDR 001aaj002 0.8 INL (dB) 0.4 0 −0.4 −0.8 0 744 1488 2232 2976 3720 4464 input code Fig 8. INL as a function of the input code DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 11 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 001aaj001 0.2 DNL (dB) 0.1 0 −0.1 −0.2 0 756 1512 2268 3024 3780 4536 input code Fig 9. DNL as a function of the input code 001aaj040 85 SFDR (dBc) 80 75 (1) 70 (2) 65 (3) 60 0 5 10 15 20 fo (MHz) (1) fo = 0 dBFS (2) fo = −6 dBFS (3) fo = −12 dBFS Fig 10. SFDR full-scale at 78 Msps as a function of the output frequency DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 12 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 001aaj044 85 SFDR (dBc) 80 75 70 (1) (2) 65 (3) 60 0 5 10 15 20 25 fo (MHz) (1) fo = 0 dBFS (2) fo = −6 dBFS (3) fo = −12 dBFS Fig 11. SFDR full-scale at 125 Msps as a function of the output frequency 001aai938 16 (1) IDDD (mA) (2) 12 (3) (4) 8 4 0 0 0.1 0.2 0.3 0.4 0.5 fo/fs (1) fs = 125 Msps (2) fs = 100 Msps (3) fs = 78 Msps (4) fs = 52 Msps Fig 12. Digital supply current as a function of fo/fs DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 13 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 001aaj032 60 IDDA (mA) 40 20 0 0 5 10 15 20 lO (mA) Fig 13. Analog supply current as a function of the output current 10. Application information 10.1 General description The DAC1201D125 is a dual 12-bit DAC operating up to 125 Msps. Each DAC consists of a segmented architecture, comprising a 7-bit thermometer sub-DAC and a 5-bit binary weighted sub-DAC. Two modes are available for the digital input depending on the status of pin MODE. In Dual-port mode, each DAC uses its own data input line at the same frequency as the update rate. In Interleaved mode, both DACs use the same data input line at twice the update rate. Each DAC generates on pins IOUTAP/IOUTAN and IOUTBP/IOUTBN two complementary current outputs. This provides a full-scale output current (IO(fs)), up to 20 mA. A single common or two independent full-scale current controls can be selected for both channels using pin GAINCTRL. An internal reference voltage is available for the reference current which is externally adjustable using pin REFIO. The DAC1201D125 operates at 3.3 V and has separate digital and analog power supplies. Pin PWD is used to power-down the device. The digital input is 1.8 V compliant, 3.3 V compliant and 5 V tolerant. 10.2 Input data The DAC1201D125 input follows a straight binary coding where DA11 and DB11 are the Most Significant Bits (MSB) and DA0 and DB0 are the Least Significant Bits (LSB). The setting applied to pin MODE defines whether the DAC1201D125 operates in Dual-port mode or in Interleaved mode, (see Table 6). DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 14 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps Table 6. Mode selection Mode Function DA11 to DA0 DB11 to DB0 Pin 17 Pin 18 Pin 19 Pin 20 LOW active off IQWRT IQCLK IQRESET IQSEL active active WRTA CLKA WRTB Interleaved mode HIGH Dual-port mode CLKB 10.2.1 Dual-port mode The data and clock circuit for Dual-port mode operation is shown in Figure 14. DA11 to DA0 12 INPUT A 12 LATCH DAC A LATCH 12 INPUT B 12 LATCH DAC B LATCH WRTA CLKA CLKB WRTB DB11 to DB0 001aai977 Fig 14. Dual-port mode operation Each DAC has its own independent data and clock inputs. The data enters the input latch on the rising edge of the WRTA/WRTB signal and is transferred to the DAC latch. The output is updated on the rising edge of the CLKA/CLKB signal. DA11 to DA0/ DB11 to DB0 N N+1 N+2 N+3 WRTA/ WRTB CLKA/ CLKB IOUTAP, IOUTAN/ IOUTBP, IOUTBN N−2 N−1 N N+1 N+2 001aaj115 Fig 15. Dual-port mode timing DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 15 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 10.2.2 Interleaved mode The data and clock circuit for Interleaved mode operation is illustrated in Figure 16. DA11 to DA0 12 INPUT A 12 LATCH DAC A LATCH 12 INPUT B 12 LATCH DAC B LATCH IQWRT IQSEL IQCLK IQRESET ÷2 001aai978 Fig 16. Interleaved mode In Interleaved mode, both DACs use the same data and clock inputs at twice the update rate. Data enters the latch on the rising edge of IQWRT. The data is sent to either latch A or latch B, depending on the value of IQSEL. The IQSEL transition must occur when IQWRT and IQCLK are LOW. The IQCLK is divided by 2 internally and the data is transferred to the DAC latch. It is updated on its rising edge. When IQRESET is HIGH, IQCLK is disabled, see Figure 17. DA11 to DA0/ DB11 to DB0 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 IQSEL IQWRT IQCLK IQRESET N IOUTAP, IOUTAN IOUTBP, IOUTBN N+4 XX N+2 N+1 XX N+3 N+5 001aaj116 Fig 17. Interleaved mode timing DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 16 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 10.3 Timing The DAC1201D125 can operate at an update rate up to 125 Msps. This generates an input data rate of 125 MHz in Dual-port mode and 250 MHz in Interleaved mode. The timing of the DAC1201D125 is shown in Figure 18. tsu(i) th(i) DA11 to DA0/ DB11 to DB0 WRTA/ WRTB td(clk) tw(WRT) CLKA/ CLKB td tw(CLK) 90 % IOUTAP, IOUTAN/ IOUTBP, IOUTBN 10 % tt ts 001aaj117 Fig 18. Timing of the DAC1201D125 The typical performances are measured at 50 % duty cycle but any timing within the limits of the characteristics will not alter the performance. • A configuration resulting in the same timing for the signals WRTA/WRTB and CLKA/CLKB, can be achieved either by synchronizing them or by connecting them together. • The rising edge of the CLKA/CLKB signal can also be placed in a range from half a period in front of the rising edge of the WRTA/WRTB signal to half a period minus 1 ns after the rising edge of the WRTA/WRTB signal. A typical set-up time of 0 ns and a hold time of 0.6 ns enables the DAC1201D125 to be easily integrated into any application. 10.4 DAC transfer function The full-scale output current for each DAC is the sum of the two complementary current outputs: (1) I O ( fs ) = I IOUTP + I IOUTN The output current depends on the digital input data: DATA I IOUTP = I O ( fs ) × ---------------- 4096 ( 4095 – DATA ) I IOUTN = I O ( fs ) × -------------------------------------- 4096 DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 17 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps Table 7 shows the output current as a function of the input data, when IO(fs) = 20 mA. Table 7. DAC transfer function Data DA11/DB11 to DA0/DB0 IOUTAP/IOUTBP IOUTAN/IOUTBN 0 0000 0000 0000 0 mA 20 mA ... ... ... ... 2047 1000 0000 0000 10 mA 10 mA ... ... ... ... 4095 1111 1111 1111 20 mA 0 mA 10.5 Full-scale current adjustment The DAC1201D125 integrates one 1.25 V reference and two current sources to adjust the full-scale current in both DACs. The internal reference configuration is shown in Figure 19. CURRENT SOURCE AVIRES RA AGND 1.25 V REFERENCE REFIO 100 nF AGND CURRENT SOURCE BVIRES RB AGND 001aai822 Fig 19. Internal reference configuration The bias current is generated by the output of the internal regulator connected to the inverting input of the internal operational amplifiers. The external resistors RA and RB are connected to pins AVIRES and BVIRES, respectively. This configuration is optimal for temperature drift compensation because the band gap can be matched with the voltage on the feedback resistors. The relationship between full-scale output current (IO(fs)) at the output of channel A or channel B and the resistor is: 24V REFIO I O ( fs ) = -----------------------RA (2) The output current of the two DACs is typically fixed at 20 mA when both resistors RA and RB are set to 1.5 kΩ. The operational range of DAC1201D125 is from 2 mA to 20 mA. It is recommended to decouple pin REFIO using a 100 nF capacitor. DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 18 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps An external reference can also be used for applications requiring higher accuracy or precise current adjustment. Due to the high input impedance of pin REFIO, applying an external source disables the band gap. 10.6 Gain control Table 8 shows how to select the different gain control modes. Table 8. Gain control GAINCTRL Mode DAC A full-scale control DAC B full-scale control LOW independent gain control AVIRES BVIRES HIGH common gain control AVIRES AVIRES In Independent gain mode, both full-scale currents can be adjusted independently using resistors RA on pin AVIRES and RB on pin BVIRES. In Common gain mode, both full-scale currents are adjusted with the same resistor and divided by two in both DACs. 10.7 Analog outputs See Figure 20 for the analog output circuit of one DAC. This circuit consists of a parallel combination of PMOS current sources and associated switches for each segment. IOUTAP/IOUTBP IOUTAN/IOUTBN RL AGND RL AGND 001aai821 Fig 20. Equivalent analog output circuit Cascode source configuration enables the output impedance of the source to be increased, thus improving the dynamic performance by reducing distortion. The DAC1201D125 can be used with either: • a differential output, coupled to a transformer (or operational amplifier) to reduce even-order harmonics and noise • a single-ended output for applications requiring unipolar voltage A typical configuration is to use a 1 V p-p level on each output IOUTAP/IOUTBP and IOUTAN/IOUTBN. Several combinations can be used but they must respect the voltage compliance range. DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 19 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 10.7.1 Differential output using transformer The use of a differential-coupled transformer output (see Figure 21) provides optimum distortion performance, and it helps to match the impedance and provides electrical isolation. T1-1T IOUTAP/ IOUTBP Rdiff IOUTAN/ IOUTBN Rload 1:1 001aai935 Fig 21. Differential output with transformer The center tap is grounded to allow the DC current flow to/from both outputs. If the center tap is open, the differential resistor must be replaced by two resistors connected to ground. 10.7.2 Single-ended output Using a single load resistor on one current output will provide a unipolar output range, typically from 0 V to 0.5 V with a 20 mA full-scale current at a 50 Ω load. 20 mA IOUTAP/ IOUTBP IOUTAN/ IOUTBN Z = 50 Ω 50 Ω 50 Ω 0 V to 0.5 V 25 Ω 001aai936 Fig 22. Single-ended output The resistor on the other current output is 25 Ω. 10.8 Power-down function The DAC1201D125 has a power-down function to reduce the power consumption when it is not active. Table 9. Power-down PWD Device function Power dissipation (typ) LOW active 185 mW HIGH not active 16.5 mW DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 20 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 10.9 Alternative devices The following alternative devices are also available. Table 10. Alternative devices Pin compatible Type number Description Sampling frequency DAC1001D125 dual 10-bit DAC up to 125 Msps DAC1401D125 dual 14-bit DAC up to 125 Msps DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 21 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 10.10 Application diagram RL AGND RL AGND AGND AGND 1.5 kΩ 100 Ω AGND 100 nF 100 Ω 1.5 kΩ DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 PWD AGND IOUTBP IOUTBN AGND BVIRES GAINCTRL REFIO AVIRES IOUTAN MODE VDDA IOUTAP 3.3 V 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 DAC1201D125 7 30 8 29 9 28 10 27 11 26 12 25 n.c. n.c. DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 100 nF DGND 3.3 V DB10 DB11 VDDD DGND WRTB/IQSEL CLKB/IQRESET CLKA/IQCLK WRTA/IQWRT VDDD DGND n.c. n.c. 13 14 15 16 17 18 19 20 21 22 23 24 100 nF DGND 3.3 V 001aaj125 Dual-port mode (MODE = HIGH) DAC active (PWD = LOW) Independent channel gain (GAINCTRL = LOW) Fig 23. Application diagram DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 22 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 11. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M θ bp pin 1 index Lp L 13 48 1 detail X 12 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 7.1 6.9 0.5 9.15 8.85 9.15 8.85 1 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) θ 0.95 0.55 7 o 0 0.95 0.55 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT313-2 136E05 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 24. Package outline SOT313-2 (LQFP48) DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 23 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 12. Abbreviations Table 11. Abbreviations Acronym Description DNL Differential Non-Linearity dBFS deciBel Full-Scale IF Intermediate Frequency INL Integral Non-Linearity LSB Least Significant Bit MSB Most Significant Bit PMOS Positive-channel Metal-Oxide Semiconductor SFDR Spurious-Free Dynamic Range 13. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes DAC1201D125_1 20081127 Product data sheet - - DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 24 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 14.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] DAC1201D125_1 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 27 November 2008 25 of 26 DAC1201D125 NXP Semiconductors Dual 12-bit DAC, up to 125 Msps 16. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.2.1 10.2.2 10.3 10.4 10.5 10.6 10.7 10.7.1 10.7.2 10.8 10.9 10.10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Application information. . . . . . . . . . . . . . . . . . 14 General description. . . . . . . . . . . . . . . . . . . . . 14 Input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Dual-port mode. . . . . . . . . . . . . . . . . . . . . . . . 15 Interleaved mode . . . . . . . . . . . . . . . . . . . . . . 16 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DAC transfer function . . . . . . . . . . . . . . . . . . . 17 Full-scale current adjustment . . . . . . . . . . . . . 18 Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Analog outputs . . . . . . . . . . . . . . . . . . . . . . . . 19 Differential output using transformer. . . . . . . . 20 Single-ended output . . . . . . . . . . . . . . . . . . . . 20 Power-down function . . . . . . . . . . . . . . . . . . . 20 Alternative devices . . . . . . . . . . . . . . . . . . . . . 21 Application diagram . . . . . . . . . . . . . . . . . . . . 22 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Contact information. . . . . . . . . . . . . . . . . . . . . 25 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 27 November 2008 Document identifier: DAC1201D125_1