PHILIPS PCB2421

INTEGRATED CIRCUITS
DATA SHEET
PCB2421
1K dual mode serial EEPROM
Preliminary specification
Supersedes data of 1995 Oct 11
File under Integrated Circuits, IC12
1997 Apr 01
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
PCB2421
CONTENTS
1
FEATURES
2
GENERAL DESCRIPTION
3
ORDERING INFORMATION
4
BLOCK DIAGRAM
5
PINNING
6
FUNCTIONAL DESCRIPTION
6.1
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.4
6.4.1
6.4.2
6.5
6.6
6.7
6.7.1
6.7.2
6.7.3
6.8
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
Transmit-only mode (DDC1)
Initialization procedure
Bidirectional mode (DDC2B, I2C-bus mode)
Bidirectional mode bus characteristics
Bus not busy (A)
Start condition (B)
Stop condition (C)
Data valid (D)
Acknowledge
Slave address
Write operation
Byte write
Page write
Acknowledge polling
Write protection
Read operation
Current address read
Random read
Sequential read
Pin description
SDA
SCL
VCLK
WP
Test
n.c.
1997 Apr 01
2
7
LIMITING VALUES
8
DC CHARACTERISTICS
9
EEPROM CHARACTERISTICS
10
AC CHARACTERISTICS
11
APPLICATION INFORMATION
11.1
11.2
Diode protection
Functional compatibility with microchip 24CL21
dual mode EEPROM
12
PACKAGE OUTLINES
13
SOLDERING
13.1
13.2
13.2.1
13.2.2
13.3
13.3.1
13.3.2
13.3.3
Introduction
DIP
Soldering by dipping or by wave
Repairing soldered joints
SO
Reflow soldering
Wave soldering
Repairing soldered joints
14
DEFINITIONS
15
LIFE SUPPORT APPLICATIONS
16
PURCHASE OF PHILIPS I2C COMPONENTS
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
1
PCB2421
FEATURES
2
• Single supply with operation 4.5 to 5.5 V
GENERAL DESCRIPTION
The Philips PCB2421 is a 128 × 8-bit dual mode serial
Electrically Erasable PROM (EEPROM).
This device is designed for use in applications requiring
storage and serial transmission of configuration and
control information. Two modes of operation have been
implemented: transmit-only mode (DDC1 mode) and
bidirectional mode (DDC2B, or I2C-bus mode). Upon
power-up, the device will be in the transmit-only mode,
sending a serial bitstream of the entire memory array
contents, clocked by the VCLK pin. A valid HIGH-to-LOW
transition on the SCL pin will cause the device to enter the
bidirectional mode, with byte selectable read/write
capability of the memory array. The PCB2421 is available
in a standard 8-pin dual in-line and 8-pin small outline
package operating in a commercial temperature range.
• Completely implements DDC1/DDC2B interface for
monitor identification
• Low power CMOS technology
• Two-wire I2C-bus interface
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• Write-protect pin
• 100 kHz I2C-bus compatibility
• Designed for 10000 erase/write cycles minimum
• Data retention greater than 10 years
• 8-pin DIP and SO package
• Temperature range 0 to +70 °C.
3
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
PCB2421P
DIP8
plastic dual in-line package; 8 leads (300 mil)
SOT97-1
PCB2421T
SO8
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
1997 Apr 01
3
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
4
PCB2421
BLOCK DIAGRAM
book, full pagewidth
VSS
VDD
4
8
HV GENERATOR
WP
SDA
SCL
VCLK
3
5
6
7
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
EEPROM
ARRAY
X
DECODER
PAGE LATCHES
Y
DECODER
PCB2421
n.c.
TEST(1)
2
SENSE AMPLIFIER
R/W CONTROL
1
MBG271
(1) Factory use only.
Fig.1 Block diagram.
5
PINNING
SYMBOL PIN
DESCRIPTION
TEST
1
factory use only: must be tied to VDD;
may not be left open-circuit
n.c.
2
may be tied to VSS, VDD, or left
open-circuit
WP
3
write protect input (LOW = write
protected, HIGH = not write protected);
may not be left open-circuit
VSS
4
ground
SDA
5
serial data input/output
SCL
6
serial clock input/output (DDC2B)
VCLK
7
serial clock input (transmit-only mode,
DDC1)
VDD
8
supply voltage
1997 Apr 01
handbook, halfpage
TEST
1
n.c.
2
8
VDD
7
VCLK
PCB2421
WP
3
6
SCL
VSS
4
5
SDA
MBG272
Fig.2 Pin configuration.
4
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
6
PCB2421
When the device has been switched into the bidirectional
mode, the VCLK input is disregarded. This mode supports
a two-wire bidirectional data transmission protocol
(I2C-bus protocol). In the I2C-bus protocol, a device that
sends data on the bus is defined to be the transmitter, and
a device that receives data from the bus is defined to be
the receiver. The bus must be controlled by a master
device that generates the bidirectional mode clock,
controls access to the bus, and generates the START and
STOP conditions, while the PCB2421 acts as slave. Both
master and slave can operate as transmitter or receiver,
but the master device determines which mode is activated.
FUNCTIONAL DESCRIPTION
The PCB2421 operates in two modes, the transmit-only
mode (DDC1) and the bidirectional mode (DDC2, or
I2C-bus mode). There is a separate two-wire protocol to
support each mode, each having a separate clock input
and sharing a common data line (SDA). The device enters
the transmit-only mode (DDC1) upon power-up. In this
mode the device transmits data bits on the SDA pin in
response to a clock signal on the VCLK pin. The device will
remain in this mode until a valid HIGH-to-LOW transition is
placed on the SCL input. When a valid transition on SCL is
recognized, the device will switch into the bidirectional
mode (see Fig.3). The only way to switch the device back
to the transmit-only mode (DDC1) is to remove power from
the device.
6.1
6.3.1
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is not
busy
Transmit-only mode (DDC1)
• During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as a
START or STOP condition.
The device will power-up in the transmit-only mode. This
mode supports a unidirectional two-wire protocol for
transmission of the contents of the memory array
(see Fig.12). The PCB2421 requires that it be initialized
prior to valid data being sent in the transmit-only mode
(see Section “Initialization procedure”, and Fig.4).
Accordingly, the following bus conditions have been
defined (see Fig.6).
In this mode, data is transmitted on the SDA pin in 8-bit
bytes, each byte followed by a ninth clock pulse during
which time SDA is left high-impedance. The clock source
for the transmit-only mode is provided on the VCLK pin;
a data bit is output on the rising edge on this pin. The 8 bits
in each byte are transmitted most significant bit first. Each
byte within the memory array will be output in sequence.
When the last byte in the memory array is transmitted, the
output will wrap around to the first location and continue.
The bidirectional mode clock (SCL) pin must be held HIGH
for the device to remain in the transmit-only mode.
6.2
6.3.2
6.3.3
START CONDITION (B)
A HIGH-to-LOW transition of the SDA line while SCL is
HIGH determines a START condition. All commands must
be preceded by a START condition.
6.3.4
STOP CONDITION (C)
A LOW-to-HIGH transition of the SDA line while SCL is
HIGH determines a STOP condition. All operations must
be ended with a STOP condition.
Initialization procedure
6.3.5
DATA VALID (D)
The state of the data line represents valid data when, after
a START condition, the data line is stable for the duration
of the HIGH period of the clock signal. The data on the line
must be changed during the LOW period of the clock
signal. There is one clock pulse per bit of data. Each data
transfer is initiated with a START condition and terminated
with a STOP condition. The maximum number of data
bytes transferred between the START and STOP
conditions during a write operation is 8 bytes (see Section
“Page write” and Fig.5).
Bidirectional mode (DDC2B, I2C-bus mode)
The PCB2421 can be switched into the bidirectional mode
(see Fig.3) by applying a valid HIGH-to-LOW transition on
the bidirectional mode clock (SCL).
1997 Apr 01
BUS NOT BUSY (A)
Both data (SDA) and clock (SCL) lines remain HIGH.
At power-on, after VDD has stabilized, the device will be in
the transmit-only mode. Nine clock cycles on the VCLK pin
must be given to the device for it to perform internal
synchronization. During this period, the SDA pin will be in
a high-impedance state. On the rising edge of the tenth
clock cycle, the device will output the first valid data bit
which will be the most significant bit of a byte. The device
will power-up with address pointer at 00H (see Fig.4).
6.3
BIDIRECTIONAL MODE BUS CHARACTERISTICS
5
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
PCB2421
The maximum number of data bytes transferred between
START and STOP conditions during a read operation is
unlimited.
6.3.6
and will be written into the address pointer of the
PCB2421. After receiving another acknowledge signal
from the PCB2421, the master device will transmit the data
word to be written into the addressed memory location.
The PCB2421 acknowledges again and the master
generates a STOP condition. This initiates the internal
write cycle, and during this time the PCB2421 will not
generate acknowledge signals.
ACKNOWLEDGE
The PCB2421, when addressed in DDC2B mode, is
obliged to generate an acknowledge after the reception of
each byte. The master device must generate an extra (9th)
clock pulse which is associated with this acknowledge bit.
The PCB2421 does not generate an acknowledge if an
internal programming cycle is in progress (SDA line is left
HIGH during the 9th clock pulse). The PCB2421 generates
an acknowledge by pulling down the SDA line during the
acknowledge pulse in such a way that the SDA line is
stable LOW during the HIGH period of the acknowledge
related clock pulse. Set-up and hold times must also be
taken into account. The master receiver must signal an
end of data to the PCB2421 by not generating an
acknowledge bit on the last byte that has been clocked out
of the slave transmitter. In this case, the slave transmitter
PCB2421 must leave the data line HIGH to enable the
master to generate the STOP condition.
6.3.7
6.4.2
For a page write, the write control byte, word address, and
the first data byte are transmitted to the PCB2421 in the
same way as in a single byte write. But instead of
generating a STOP condition the master transmits up to
eight data bytes to the PCB2421 which are temporarily
stored in the on-chip page buffer and will be written into the
memory after the master has transmitted a STOP
condition. After the receipt of each word, the three lower
order address pointer bits are internally incremented by
one. The higher order four bits of the word address remain
constant. A maximum of 8 bytes can be written in one
operation. As with the byte write operation, once the STOP
condition is received an internal write cycle will begin
(see Figs 5 and 8).
SLAVE ADDRESS
After generating a START condition, the bus master
transmits the slave address (MSB first) consisting of a 7-bit
device address (1010000) for the PCB2421. The eighth bit
of the slave address determines if the master device wants
to read or write to the PCB2421 (R/W bit) (see Fig.7).
The PCB2421 monitors the bus for its corresponding slave
address all the time. It generates an acknowledge bit if the
slave address was true and it is not in a programming
mode.
Table 1
SLAVE ADDRESS
R/W
Read
1010000
1
Write
1010000
0
6.4
6.4.1
6.5
6.6
Write operation
Write protection
Pin 3 is a write protect input (WP). In the DDC1 mode, the
PCB2421 can only be read according to the DDC1
protocol, hence the WP input has no effect in this mode.
In the DDC2B mode, when WP is connected to ground, the
entire EEPROM is write-protected, regardless of other pin
states. When connected to VDD, write-protection is
disabled and the EEPROM may be programmed. WP may
not be left open-circuit.
BYTE WRITE
Following the START condition from the master, the
device address (7 bits), and the R/W bit (logic LOW for
write) is placed on the bus by the master transmitter. This
indicates to the addressed slave receiver that a byte with
a word address will follow after it has generated an
acknowledge bit during the ninth clock cycle. Therefore the
next byte transmitted by the master is the word address
1997 Apr 01
Acknowledge polling
Since the device will not acknowledge during a write cycle,
this can be used to determine when the cycle is complete
(this feature can be used to maximize bus throughput).
Once the STOP condition for a write command has been
issued from the master, the device initiates the internally
timed write cycle. Acknowledge (ACK) polling can be
initiated immediately. This involves the master sending a
START condition followed by the control byte for a write
command (R/W = 0). If the device is still busy with the write
cycle, then no ACK will be returned. If the cycle is
complete, then the device will return the ACK and the
master can then proceed with the next read or write
command. See Fig.9 for flow diagram.
Slave address
OPERATION
PAGE WRITE
6
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
Table 2
PCB2421
opposed to a STOP condition in a random read.
This directs the PCB2421 to transmit the next sequentially
addressed 8-bit word. To provide sequential reads the
PCB2421 contains an internal address pointer which is
incremented by one at the completion of each operation.
This address pointer allows the entire memory contents to
be serially read during one operation.
Mode configurations
DDC
WP
MODE
DCC1
X(1)
R
DCC2
1
R/W
0
R
Note
6.8
1. Where X = don’t care.
6.8.1
6.7
Read operation
CURRENT ADDRESS READ
The PCB2421 contains an address counter that maintains
the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address ‘n’, the
next current address read operation would access data
from address n + 1. Upon receipt of the slave address with
R/W set to logic 1, the PCB2421 issues an acknowledge
and transmits the eight bit data word. The master will not
acknowledge the transfer but does generate a STOP
condition and the PCB2421 discontinues transmission
(see Fig.10).
6.8.2
RANDOM READ
VCLK
This pin is the clock input for the transmit-only mode
(DDC1). In the transmit-only mode, each bit is clocked out
on the rising edge of this signal. In DDC2B mode, this input
is a don’t care.
Random read operations allow the master to access any
memory location in a random manner. To perform this type
of read operation, the word address must first be set. This
is done by sending the word address to the PCB2421 as
part of a normal write operation. After the word address is
sent, the master generates a REPEATED START
condition following the acknowledge. This terminates the
write operation, but not before the internal address pointer
is set. The master then issues the control byte again but
with the R/W bit set to logic 1. The PCB2421 will then issue
an acknowledge and transmits the 8-bit data word.
The master will not acknowledge the transfer but does
generate a STOP condition and the PCB2421
discontinues transmission (see Fig.11).
6.7.3
SCL
This pin is the clock input for the bidirectional mode
(I2C-bus, DDC2B), and is used to synchronize data
transfer to and from the device. It is also used as the
signalling input to switch the device from the transmit-only
mode to the bidirectional mode. It must remain HIGH for
the chip to continue operation in the transmit-only mode
(DDC1).
6.8.3
6.7.2
SDA
This pin is used to transfer addresses and data into and
out of the device, when the device is in the bidirectional
(I2C-bus, DDC2B) mode. In the transmit-only mode
(DDC1), which only allows data to be read from the device,
data is also transferred on the SDA pin. This pin is an
open-drain terminal, therefore the SDA bus requires a
pull-up resistor connected to VDD (typically 10 kΩ for
100 kHz). See brochure “The I2C-bus and how to use it”
(order no. 9398 393 40011) or “Data Handbook IC12”.
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the slave
address is set to logic 1. There are three basic types of
read operations: current address read, random read, and
sequential read.
6.7.1
Pin description
6.8.4
WP
This pin is used to inhibit writing of the EEPROM. When
this pin is connected to ground, writing of the EEPROM is
inhibited. When connected to VDD (and VCLK = VDD), the
EEPROM can be programmed. WP may not be left
open-circuit. WP input is a ‘don’t care’ in DDC1 mode.
6.8.5
TEST
Pins 1 is a TEST pin for factory use only. It must be
connected to VDD in the application.
SEQUENTIAL READ
6.8.6
Sequential reads are initiated in the same way as a
random read except that after the PCB2421 transmits the
first data byte, the master issues an acknowledge as
1997 Apr 01
N.C.
This pin has no connection and may be tied to VSS, VDD or
left open-circuit.
7
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
PCB2421
transmit only mode
(DDC1)
handbook, full pagewidth
bidirectional mode
(DDC2)
SCL
tVHZ
SDA
VCLK
MBG275
Fig.3 Mode transition diagram.
dbook, full pagewidth
VDD
SCL
tVAA
SDA
tVAA
high-impedance for 9 clock cycles
1
bit 8
2
8
9
10
bit 7
11
VCLK
MBG276
tVPU
Fig.4 Device initialization diagram.
1997 Apr 01
8
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
handbook, full pagewidth
PCB2421
Word Address Row
X0000000
0
X0001. . .
1
X0010101
2
X0011. . .
3
column
1
2
3
4
5
6
0
1
4
2
5
3
4
6
7
8
1
2
3
5
6
7
MBG277
X = don’t care.
Fig.5 Example of writing 8 bytes with word address X0000000 and 6 bytes with word address X0010101.
handbook, full pagewidth
(A)
(B)
(D)
(D)
(C)
SCL
SDA
START
condition
data or
data allowed
acknowledge
to change
valid
Fig.6 DDC2B data transfer sequence on the I2C-bus.
1997 Apr 01
9
STOP
condition
MBG278
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
handbook, halfpage
1
0
PCB2421
1
0
0
0
0 R/W
MBG279
Fig.7 Slave address.
handbook, full pagewidth
S
acknowledgement
from slave
SLAVE ADDRESS
0 A X
acknowledgement
from slave
WORD ADDRESS
A
R/W don't
care
acknowledgement
from slave
DATA
A
P
n bytes
auto increment
memory word address
Fig.8 I2C-bus write protocol (n = maximum 8 bytes).
1997 Apr 01
10
WRITING
t WR
MBG280
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
handbook, halfpage
PCB2421
SEND
WRITE COMMAND
SEND STOP
CONDITION TO
INITIATE WRITE CYCLE
SEND START
SEND CONTROL BYTE
WITH R/W = 0
DID DEVICE
ACKNOWLEDGE
(ACK = 0)?
no
yes
NEXT OPERATION
MBG281
Fig.9 Acknowledge polling.
slave address + R/W
handbook, full pagewidth
data
START
STOP
SDA S
P
R/W
MBG282
NO ACK
ACK
Fig.10 Current address read.
1997 Apr 01
11
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
handbook, full pagewidth
slave address + R/W
PCB2421
DATA
rep START
slave address + R/W
DATA
STOP
START
SDA S
MBG283
S
R/W
R/W
ACK
ACK
Fig.11 Random read.
1997 Apr 01
P
12
NO ACK
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
PCB2421
7 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
−0.3
+7.0
V
−0.5
VDD(max) + 0.5
V
DC input current
−10
+10
mA
IO
DC output current
−10
+10
mA
Ptot
total power dissipation
−
150
mW
Po
power dissipation per output
−
50
mW
Tstg
storage temperature
−65
+150
°C
Tamb
operating ambient temperature
Ves
electrostatic discharge
VDD
supply voltage
Vn
input voltage on any pin
II
measured via 500 Ω resistor
without EEPROM retention
with EEPROM retention
note 1
−65
+70
°C
0
+70
°C
−2000
+2000
V
Note
1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
8 DC CHARACTERISTICS
VDD = 4.5 to 5.5 V; VSS = 0 V; Tamb = 0 to +70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
VDD
supply voltage
4.5
VIH
HIGH level input voltage (pins 3,
5 and 6)
VIL
TYP.
−
MAX.
UNIT
5.5
V
0.7VDD −
−
V
LOW level input voltage (pins 3,
5 and 6)
−
−
0.3VDD V
VIH(7)
HIGH level input voltage (pin 7)
2.0
−
−
V
VIL(7)
LOW level input voltage (pin 7)
−
−
0.8
V
VOL
LOW level output voltage
IOL = 3 mA; VDD = 4.5 V
−
−
0.4
V
ILI
input leakage current
VI = 0 to 5.5 V
−10
−
+10
µA
ILO
output leakage current
VO = 0 to 5.5 V
−10
−
+10
µA
IDD(write)
operating write current
fSCL = 100 kHz; VDD = 5.5 V
−
−
1000
µA
IDD(read)
operating read current
fSCL = 100 kHz; VDD = 5.5 V
−
−
400
µA
IDD(st)
standby current
VDD = 5.5 V; DDC2B mode;
VCLK = SDA = SCL = VDD
−
−
30
µA
9 EEPROM CHARACTERISTICS
VDD = 4.5 to 5.5 V; VSS = 0 V; Tamb = 0 to +70 °C; unless otherwise specified.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
tWR
EEPROM write time
−
20
ms
NCYC
EEPROM endurance
10000
−
E/W cycles
tRET
EEPROM retention
10
−
years
1997 Apr 01
13
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
PCB2421
10 AC CHARACTERISTICS
VDD = 4.5 to 5.5 V; VSS = 0 V; Tamb = 0 to +70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DDC1 mode (transmit-only; unidirectional)
tVAA
output valid from VCLK
see Fig.12; note 1
−
1
−
µs
tVHIGH
VCLK HIGH time
see Fig.12
20
−
−
µs
tVLOW
VCLK LOW time
see Fig.12
20
−
−
µs
see Fig.3; note 1
−
500
−
ns
−
−
100
ns
−
5
−
µs
tVHZ
mode transition time
tSP
input filter spike suppression time
tvpu
DDC1 mode power-up time
see Fig.4
DDC2B mode (bidirectional; I2C-bus mode); see Fig.13
fSCL
serial clock frequency
0
−
100
kHz
tHIGH
serial clock HIGH time
4
−
−
µs
tLOW
serial clock LOW time
4.7
−
−
µs
tr
SCL and SDA rise time
−
−
1
µs
tf
SCL and SDA fall time
−
−
0.3
µs
tHD;STA
START condition hold time
4
−
−
µs
tSU;STA
START condition set-up time
4.7
−
−
µs
tHD;DAT
data input hold time
0
−
−
µs
tSU;DAT
data input set-up time
250
−
−
ns
tSU;STO
STOP condition set-up time
4
−
−
µs
tBUF
bus free time
4.7
−
−
µs
tSP
input filter spike suppression
−
−
100
ns
note 2
Notes
1. The rise time for SDA returning HIGH must be observed after this period.
2. This is the time that the bus must be free before a new transmission can start.
1997 Apr 01
14
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
PCB2421
handbook, full pagewidth
SCL
tVAA
NULL BIT
SDA
BIT 1 (LSB)
BIT 8 (MSB)
BIT 7
VCLK
tVHIGH
MBG273
tVLOW
Fig.12 Transmit-only mode (DDC1).
handbook, full pagewidth
t SU;STA
BIT 6
(A6)
BIT 7
MSB
(A7)
START
CONDITION
(S)
PROTOCOL
t LOW
t HIGH
BIT 0
LSB
(R/W)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
1 / f SCL
SCL
t
tr
BUF
tf
SDA
t HD;STA
t SU;DAT
t
HD;DAT
Fig.13 DDC2B (I2C-bus timing).
1997 Apr 01
15
MBG274
t SU;STO
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
PCB2421
11 APPLICATION INFORMATION
3. Maximum 100 kHz DDC2B clock frequency
11.1
4. Maximum 25 kHz DDC1 VCLK clock frequency
Diode protection
5. During EEPROM programming a maximum write time
of 20 ms must be observed
There is no diode connection between VCLK and VDD,
SCL and VDD and SDA and VDD (see Fig.14). This allows
powering-down the device without affecting the I2C-bus
operation or loading the VCLK driver.
11.2
6. 8-byte maximum during page write must be observed
7. During operation VDD must be between 4.5 and 5.5 V
8. An operating temperature between 0 and +70 °C must
be observed
Functional compatibility with microchip
24CL21 dual mode EEPROM
9. Output valid from VCLK (tVAA) typical 1 µs must be
observed
The Philips PCB2421 is pin and function compatible with
the 24CL21 providing the following measures are taken in
the application.
10. DDC1 mode power-up time (tVPU) typical 5 µs should
be observed.
1. Pin 1 (TEST) must be tied to VDD
Remark: VCLK is ‘don’t care’ in the DDC2B mode.
2. Pin 3 (WP) must be tied to VDD. This inhibits the write
protection function which does not exist on the 24CL21
at this time
handbook, halfpage
PCB2421
TEST
1
8
VDD
n.c.
2
7
VCLK
WP
3
6
SCL
VSS
4
5
SDA
substrate
MBG284
Fig.14 PCB2421 diode protection.
1997 Apr 01
16
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
PCB2421
12 PACKAGE OUTLINES
DIP8: plastic dual in-line package; 8 leads (300 mil)
SOT97-1
ME
seating plane
D
A2
A
A1
L
c
Z
w M
b1
e
(e 1)
b
MH
b2
5
8
pin 1 index
E
1
4
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
b2
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.2
0.51
3.2
1.73
1.14
0.53
0.38
1.07
0.89
0.36
0.23
9.8
9.2
6.48
6.20
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
1.15
inches
0.17
0.020
0.13
0.068
0.045
0.021
0.015
0.042
0.035
0.014
0.009
0.39
0.36
0.26
0.24
0.10
0.30
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.045
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT97-1
050G01
MO-001AN
1997 Apr 01
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-02-04
17
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
PCB2421
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
4
1
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100
0.014 0.0075
0.20
0.19
0.16
0.15
0.244
0.039 0.028
0.050
0.041
0.228
0.016 0.024
inches
0.010 0.057
0.069
0.004 0.049
0.01
0.01
0.028
0.004
0.012
θ
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03S
MS-012AA
1997 Apr 01
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
97-05-22
18
o
8
0o
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
PCB2421
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
13 SOLDERING
13.1
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
13.3.2
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
13.2
13.2.1
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
DIP
SOLDERING BY DIPPING OR BY WAVE
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
13.2.2
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
13.3
13.3.1
13.3.3
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
1997 Apr 01
WAVE SOLDERING
19
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
PCB2421
14 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
15 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
16 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Apr 01
20
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
PCB2421
NOTES
1997 Apr 01
21
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
PCB2421
NOTES
1997 Apr 01
22
Philips Semiconductors
Preliminary specification
1K dual mode serial EEPROM
PCB2421
NOTES
1997 Apr 01
23
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1997
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417067/1200/02/pp24
Date of release: 1997 Apr 01
Document order number:
9397 750 01746