Not recommended for new designs – Please use 24LCS21A. 24LCS21 1K 2.5V Dual Mode I2C™ Serial EEPROM Package Types ™ • Completely implements DDC1 /DDC2 interface for monitor identification • Hardware write-protect pin • Single supply with operation down to 2.5V • Low-power CMOS technology: - 1 mA active current, typical - 10 A standby current, typical at 5.5V • 2-wire serial interface bus, I2C™ compatible (SCL) • Self-timed write cycle (including auto-erase) • Page-write buffer for up to 8 bytes • 100 kHz (2.5V) and 400 kHz (5V) compatibility (SCL) • 1,000,000 erase/write cycles ensured • Data retention > 200 years • 8-pin PDIP and SOIC package • Available for extended temperature ranges: - Commercial (C): 0°C to +70°C - Industrial (I) -40°C to +85°C PDIP NC 1 NC 2 WP 3 VSS 4 NC 1 NC 2 WP 3 VSS 4 24LCS21 ™ 8 VCC 7 VCLK 6 SCL 5 SDA 8 VCC 7 VCLK 6 SCL 5 SDA SOIC 24LCS21 Features: Description: The Microchip Technology Inc. 24LCS21 is a 128 x 8-bit dual-mode Electrically Erasable PROM. This device is designed for use in applications requiring storage and serial transmission of configuration and control information. Two modes of operation have been implemented: Transmit-Only mode and Bidirectional mode. Upon power-up, the device will be in the Transmit-Only mode, sending a serial bit stream of the entire memory array contents, clocked by the VCLK pin. A valid high-to-low transition on the SCL pin will cause the device to enter the Bidirectional mode, with byte selectable read/write capability of the memory array in standard I2C protocol. The 24LCS21 also enables the user to write-protect the entire memory contents using its write-protect pin. The 24LCS21 is available in a standard 8-pin PDIP and SOIC package in both commercial and industrial temperature ranges. 1995-2012 Microchip Technology Inc. Block Diagram WP HV Generator I/O Control Logic Memory Control Logic EEPROM XDEC Array Page Latches SDA SCL YDEC VCLK Sense Amp R/W Control VCC VSS DS21127G-page 1 24LCS21 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS ........................................................................................................ -0.6V to VCC + 1.0V Storage temperature ...............................................................................................................................-65C to +150C Ambient temperature with power applied ................................................................................................-40C to +125C Soldering temperature of leads (10 seconds) .......................................................................................................+300C ESD protection on all pins 4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Parameter VCC = +2.5V to 5.5V Commercial (C): TA = 0C to +70C Industrial (I): TA = -40C to +85C Symbol Min SCL and SDA pins: High-level input voltage Low-level input voltage VIH VIL 0.7 VCC Input levels on VCLK pin: High-level input voltage Low-level input voltage VIH VIL 2.0 .05 VCC Hysteresis of Schmitt Trigger inputs VHYS Low-level output voltage VOL1 Low-level output voltage VOL2 Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current Note 1: Max Units 0.3 VCC V V 0.8 0.2 VCC V V Conditions VCC 2.7V (Note 1) VCC < 2.7V (Note 1) — V (Note 1) 0.4 V IOL = 3 mA, VCC = 2.5V (Note 1) 0.6 V IOL = 6 mA, VCC = 2.5V ILI -10 10 A VIN = 0.1V to VCC ILO -10 10 A VOUT = 0.1V to VCC 10 pF VCC = 5.0V (Note 1), TA = 25C, FCLK = 1 MHz CINT ICC Write ICC Read — — 3 1 mA mA VCC = 5.5V, SCL = 400 kHz ICCS — 30 100 A A VCC = 3.0V, SDA = SCL = VCC VCC = 5.5V, SDA = SCL = VCC VCLK = VSS This parameter is periodically sampled and not 100% tested. DS21127G-page 2 1995-2012 Microchip Technology Inc. 24LCS21 TABLE 1-2: AC CHARACTERISTICS VCC = 2.5-5.5V Parameter VCC = 4.5-5.5V Symbol Units Min Max Min Max Clock frequency FCLK 0 100 0 400 kHz Clock high time THIGH 4000 — 600 — ns Clock low time TLOW 4700 — 1300 — ns TR — 1000 — 300 ns SDA and SCL rise time SDA and SCL fall time Remarks (Note 1) TF — 300 — 300 ns (Note 1) Start condition hold time THD:STA 4000 — 600 — ns After this period the first clock pulse is generated Start condition setup time TSU:STA 4700 — 600 — ns Only relevant for repeated Start condition Data input hold time THD:DAT 0 — 0 — ns (Note 2) Data input setup time TSU:DAT 250 — 100 — ns Stop condition setup time TSU:STO 4000 — 600 — ns TAA — 3500 — 900 ns (Note 2) Bus free time TBUF 4700 — 1300 — ns Time the bus must be free before a new transmission can start Output fall time from VIH minimum to VIL maximum TOF — 250 20 + 0.1 CB 250 ns (Note 1), CB 100 pF Input filter spike suppression (SDA and SCL pins) TSP — 100 — 50 ns (Note 3) Write cycle time TWR — 10 — 10 ms Byte or Page mode TVAA — 2000 — 1000 ns Output valid from clock Transmit-Only Mode Parameters Output valid from VCLK VCLK high time TVHIGH 4000 — 600 — ns VCLK low time TVLOW 4700 — 1300 — ns VCLK setup time TVHST 0 — 0 — ns VCLK hold time TSPVL 4000 — 600 — ns Mode transition time TVHZ — 500 — 500 ns Transmit-only power-up time TVPU 0 — 0 — ns Input filter spike suppression (VCLK pin) TSPV — 100 — 100 ns — 1M — 1M — cycles Endurance Note 1: 2: 3: 4: 25°C, VCC = 5.0V, Block mode (Note 4) Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide noise and spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. 1995-2012 Microchip Technology Inc. DS21127G-page 3 24LCS21 2.0 FUNCTIONAL DESCRIPTION The 24LCS21 operates in two modes, the TransmitOnly mode and the Bidirectional mode. There is a separate two-wire protocol to support each mode, each having a separate clock input but sharing a common data line (SDA). The device enters the Transmit-Only mode upon power-up. In this mode, the device transmits data bits on the SDA pin in response to a clock signal on the VCLK pin. The device will remain in this mode until a valid high-to-low transition is placed on the SCL input. When a valid transition on SCL is recognized, the device will switch into the Bidirectional mode. The only way to switch the device back to the Transmit-Only mode is to remove power from the device. 2.1 Transmit-Only Mode The device will power-up in the Transmit-Only mode at address 00h. This mode supports a unidirectional twowire protocol for continuous transmission of the contents of the memory array. This device requires that it be initialized prior to valid data being sent in the FIGURE 2-1: Transmit-Only mode (see Initialization Procedure, below). In this mode, data is transmitted on the SDA pin in 8-bit bytes, with each byte followed by a ninth, null bit (Figure 2-1). The clock source for the Transmit-Only mode is provided on the VCLK pin, and a data bit is output on the rising edge on this pin. The eight bits in each byte are transmitted Most Significant bit first. Each byte within the memory array will be output in sequence. When the last byte in the memory array is transmitted, the internal Address Pointers will wrap around to the first memory location (00h) and continue. The Bidirectional mode clock (SCL) pin must be held high for the device to remain in the Transmit-Only mode. 2.2 Initialization Procedure After VCC has stabilized, the device will be in the Transmit-Only mode. Nine clock cycles on the VCLK pin must be given to the device for it to perform internal synchronization. During this period, the SDA pin will be in a high-impedance state. On the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the Most Significant bit in address 00h. (Figure 2-2). TRANSMIT-ONLY MODE SCL TVAA TVAA SDA Null Bit Bit 1 (LSB) Bit 1 (MSB) Bit 7 VCLK TVHIGH FIGURE 2-2: TVLOW DEVICE INITIALIZATION VCC SCL SDA TVAA High-impedance for 9 clock cycles TVAA Bit 8 Bit 7 TVPU VCLK DS21127G-page 4 1 2 8 9 10 11 1995-2012 Microchip Technology Inc. 24LCS21 3.0 BIDIRECTIONAL MODE 3.1 The 24LCS21 can be switched into the Bidirectional mode (Figure 3-1) by applying a valid high-to-low transition on the Bidirectional mode clock (SCL). When the device has been switched into the Bidirectional mode, the VCLK input is disregarded, with the exception that a logic high level is required to enable write capability. This mode supports a two-wire bidirectional data transmission protocol (I2C™). In this protocol, a device that sends data on the bus is defined to be the transmitter and a device that receives data from the bus is defined to be the receiver. The bus must be controlled by a master device that generates the Bidirectional mode clock (SCL), controls access to the bus and generates the Start and Stop conditions, while the 24LCS21 acts as the slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. In this mode, the 24LCS21 only responds to commands for device ‘1010 000X’. Bidirectional Mode Bus Characteristics The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 3-2). 3.1.1 BUS NOT BUSY (A) Both data and clock lines remain high. 3.1.2 START DATA TRANSFER (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 3.1.3 STOP DATA TRANSFER (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. FIGURE 3-1: MODE TRANSITION Transmit-Only mode Bidirectional mode SCL TVHZ SDA VCLK FIGURE 3-2: SCL (A) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) Start Condition Address or Acknowledge Valid (D) (C) (A) SDA 1995-2012 Microchip Technology Inc. Data Allowed to Change Stop Condition DS21127G-page 5 24LCS21 3.1.4 DATA VALID (D) 3.1.5 The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Note: Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is theoretically unlimited, although only the last eight will be stored when doing a write operation. When an overwrite does occur, it will replace data in a first-in first-out (FIFO) fashion. Note: The 24LCS21 does not generate any Acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the Stop condition. Once switched into Bidirectional mode, the 24LCS21 will remain in that mode until power goes away. Removing power is the only way to reset the 24LCS21 into the Transmit-Only mode. FIGURE 3-3: ACKNOWLEDGE BUS TIMING START/STOP VHYS SCL THD:STA TSU:STA TSU:STO SDA Start FIGURE 3-4: Stop BUS TIMING DATA TF TR THIGH TLOW SCL TSU:STA THD:DAT TSU:DAT THD:STA SDA IN TSP TSU:STO TBUF TAA TAA SDA OUT DS21127G-page 6 1995-2012 Microchip Technology Inc. 24LCS21 3.1.6 SLAVE ADDRESS FIGURE 3-5: After generating a Start condition, the bus master transmits the slave address consisting of a 7-bit device code ‘1010000’ for the 24LCS21. Start Read/Write The eighth bit of the slave address determines whether the master device wants to read or write to the 24LCS21 (Figure 3-5). The 24LCS21 monitors the bus for its corresponding slave address continuously. It generates an Acknowledge bit if the slave address was true and it is not in a programming mode. Operation Slave Address R/W Read 1010000 1 Write 1010000 0 1995-2012 Microchip Technology Inc. CONTROL BYTE ALLOCATION Slave Address 1 0 1 0 0 R/W 0 A 0 DS21127G-page 7 24LCS21 4.0 WRITE OPERATION 4.1 Byte Write After receiving another Acknowledge signal from the 24LCS21, the master device will transmit the data word to be written into the addressed memory location. The 24LCS21 acknowledges again and the master generates a Stop condition. This initiates the internal write cycle, and during this time the 24LCS21 will not generate Acknowledge signals (Figure 4-1). Following the Start signal from the master, the slave address (4 bits), three zero bits (000) and the R/W bit, which is a logic low, are placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the Address Pointer of the 24LCS21. FIGURE 4-1: It is required that VCLK be held at a logic high level during command and data transfer in order to program the device. This applies to both byte write and page write operation. Note, however, that the VCLK is ignored during the self-timed program operation. Changing VCLK from high-to-low during the self-timed program operation will not halt programming of the device. BYTE WRITE S T A R T Bus Activity Activity SDA Line Word Address Control Byte S T O P Data S P A C K A C K Bus Activity A C K VCLK FIGURE 4-2: VCLK WRITE ENABLE TIMING SCL THD:STA SDA IN TSU:STO VCLK TVHST DS21127G-page 8 TSPVL 1995-2012 Microchip Technology Inc. 24LCS21 4.2 Page Write The write control byte, word address and the first data byte are transmitted to the 24LCS21 in the same way as in a byte write. But instead of generating a Stop condition, the master transmits up to eight data bytes to the 24LCS21, which are temporarily stored in the onchip page buffer and will be written into the memory after the master has transmitted a Stop condition. After the receipt of each word, the three lower order Address Pointer bits are internally incremented by one. The higher order five bits of the word address remains constant. If the master should transmit more than eight words prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received an internal write cycle will begin (Figure 5-2). 1995-2012 Microchip Technology Inc. It is required that VCLK be held at a logic high level during command and data transfer in order to program the device. This applies to both byte write and page write operation. Note, however, that the VCLK is ignored during the self-timed program operation. Changing VCLK from high-to-low during the self-timed program operation will not halt programming of the device. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size – 1]. If a page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. DS21127G-page 9 24LCS21 5.0 ACKNOWLEDGE POLLING FIGURE 5-1: Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 5-1 for the flow diagram. ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation FIGURE 5-2: PAGE WRITE Bus Activity Master S T A R T SDA Line S Bus Activity Word Address Control Byte S T O P Data n + 7 Data n + 1 Data (n) P A C K A C K A C K A C K A C K VCLK DS21127G-page 10 1995-2012 Microchip Technology Inc. 24LCS21 6.0 WRITE PROTECTION 7.0 When using the 24LCS21 in the Bidirectional mode, the VCLK pin operates as the write-protect control pin. Setting VCLK high allows normal write operations, while setting VCLK low prevents writing to any location in the array. Connecting the VCLK pin to VSS would allow the 24LCS21 to operate as a serial ROM, although this configuration would prevent using the device in the Transmit-Only mode. Additionally, pin 3 performs a flexible write-protect function. The 24LCS21 contains a write protection control fuse whose factory default state is cleared. Writing any data to address 7Fh (normally the checksum in DDC applications) sets the fuse which enables the WP pin. Until this fuse is set, the 24LCS21 is always write enabled (if VCLK = 1). After the fuse is set, the write capability of the 24LCS21 is determined by WP (Figure 6-1). TABLE 6-1: WRITE-PROTECT TRUTH TABLE VCLK WP Add. 7Fh Written 0 X X Mode Read-only READ OPERATION Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read and sequential read. 7.1 Current Address Read The 24LCS21 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24LCS21 issues an acknowledge and transmits the eight-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the 24LCS21 discontinues transmission (Figure 7-1). FIGURE 7-1: 1 X No R/W Bus Activity Master 1 1/open Yes R/W SDA Line 1 0 Yes Read-only CURRENT ADDRESS READ S T A R T S10100001 Control Byte Bus Activity 7.2 S T O P Data n P A C K N O A C K Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24LCS21 as part of a write operation. After the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24LCS21 will then issue an acknowledge and transmits the eight-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the 24LCS21 discontinues transmission (Figure 7-2). 1995-2012 Microchip Technology Inc. DS21127G-page 11 24LCS21 FIGURE 7-2: RANDOM READ Bus Activity Master S T A R T SDA Line S 1 0 1 0 0 0 0 0 Bus Activity Control Byte S T A R T Word Address Control Byte S T O P Data n S 1 0 1 0 0 0 0 1 A C K A C K P A C K N O A C K 7.3 Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24LCS21 transmits the first data byte, the master issues an acknowledge as opposed to a Stop condition in a random read. This directs the 24LCS21 to transmit the next sequentially addressed 8-bit word (Figure 8-1). To provide sequential reads, the 24LCS21 contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. 7.4 Noise Protection The 24LCS21 employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SDA, SCL and VCLK inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. DS21127G-page 12 1995-2012 Microchip Technology Inc. 24LCS21 8.0 PIN DESCRIPTIONS TABLE 8-1: 8.1 8.2 This pin is the clock input for the Bidirectional mode, and is used to synchronize data transfer to and from the device. It is also used as the signaling input to switch the device from the Transmit-Only mode to the Bidirectional mode. It must remain high for the chip to continue operation in the Transmit-Only mode. PIN FUNCTION TABLE Name Function WP Write-protect (active low) SCL VSS Ground SDA Serial Address/Data I/O SCL Serial Clock (Bidirectional mode) VCLK Serial Clock (Transmit-Only mode) VCC +2.5V to 5.5V Power Supply NC No Connection 8.3 VCLK This pin is the clock input for the Transmit-Only mode (DDC1). In the Transmit-Only mode, each bit is clocked out on the rising edge of this signal. In the Bidirectional mode, a high logic level is required on this pin to enable write capability. SDA 8.4 This pin is used to transfer addresses and data into and out of the device, when the device is in the Bidirectional mode. In the Transmit-Only mode, which only allows data to be read from the device, data is also transferred on the SDA pin. This pin is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10 K for 100 kHz, 2 K for 400 kHz). WP This pin is used for flexible write protection of the 24LCS21. When the last memory location (7Fh) is written with any data, this pin is enabled and determines the write capability of the 24LCS21 (Figure 6-1). For normal data transfer in the Bidirectional mode, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. FIGURE 8-1: SEQUENTIAL READ Bus Activity Master Data n Data n+2 Data n+1 S T O P Data n+X Control Byte P SDA Line Bus Activity A C K A C K A C K A C K N O A C K 1995-2012 Microchip Technology Inc. DS21127G-page 13 24LCS21 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP Example XXXXXXXX XXXXXNNN YYWW 24LCS21 017 0410 8-Lead SOIC (.150”) XXXXXXXX XXXXYYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: DS21127G-page 14 Example 24LCS21 /SN0410 017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 1995-2012 Microchip Technology Inc. 24LCS21 8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 E A2 A L c A1 B1 p eB B Units Dimension Limits n p INCHES* NOM 8 .100 .155 .130 MAX MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MAX Number of Pins Pitch Top to Seating Plane A .140 .170 4.32 Molded Package Thickness A2 .115 .145 3.68 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 8.26 Molded Package Width E1 .240 .250 .260 6.60 Overall Length D .360 .373 .385 9.78 Tip to Seating Plane L .125 .130 .135 3.43 c Lead Thickness .008 .012 .015 0.38 Upper Lead Width B1 .045 .058 .070 1.78 Lower Lead Width B .014 .018 .022 0.56 eB Overall Row Spacing § .310 .370 .430 10.92 Mold Draft Angle Top 5 10 15 15 Mold Draft Angle Bottom 5 10 15 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 1995-2012 Microchip Technology Inc. MIN MIN DS21127G-page 15 24LCS21 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil Body (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D 2 B n 1 h 45 c A2 A L Units Dimension Limits n p INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MAX Number of Pins Pitch Overall Height A .053 .069 1.75 Molded Package Thickness A2 .052 .061 1.55 Standoff § A1 .004 .010 0.25 Overall Width E .228 .244 6.20 Molded Package Width .146 .157 3.99 E1 Overall Length D .189 .197 5.00 Chamfer Distance h .010 .020 0.51 Foot Length L .019 .030 0.76 Foot Angle 0 8 8 c Lead Thickness .008 .010 0.25 Lead Width B .013 .020 0.51 Mold Draft Angle Top 0 15 15 Mold Draft Angle Bottom 0 15 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21127G-page 16 MIN A1 MIN 1995-2012 Microchip Technology Inc. 24LCS21 APPENDIX A: REVISION HISTORY Revision E Added note to page 1 header (Not recommended for new designs). Added Section 9.0: Package Marking Information. Added On-line Support page. Updated document format. Revision F Revised Section 8.4 Revision G Added a note to each package outline drawing. 1995-2012 Microchip Technology Inc. DS21127G-page 17 24LCS21 NOTES: DS21127G-page 18 1995-2012 Microchip Technology Inc. 24LCS21 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. 1995-2012 Microchip Technology Inc. DS21127G-page 19 24LCS21 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 24LCS21 Literature Number: DS21127G Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21127G-page 20 1995-2012 Microchip Technology Inc. 24LCS21 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Device: 24LCS21: Dual Mode I2C Serial EEPROM 24LCS21T: Dual Mode I2C Serial EEPROM (Tape and Reel) Temperature Range: Blank I = 0C to = -40C to Package: P SN = = . +70C +85C Plastic DIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body), 8-lead Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. Your local Microchip sales office The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 1995-2012 Microchip Technology Inc. DS21127G-page 21 24LCS21 NOTES: DS21127G-page 22 1995-2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 1995-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620767313 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 1995-2012 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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