PHILIPS BUK9621-30

Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting using ’trench’ technology.
The device features very low on-state
resistance and has integral zener
diodes giving ESD protection up to
2kV. It is intended for use in
automotive and general purpose
switching applications.
PINNING - SOT404 (D2PAK)
PIN
BUK9621-30
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 5 V
PIN CONFIGURATION
MAX.
UNIT
30
50
94
175
21
V
A
W
˚C
mΩ
SYMBOL
DESCRIPTION
d
mb
1
gate
2
drain
3
source
mb
drain
g
2
1
s
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
ID
ID
IDM
Ptot
Tstg, Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
RGS = 20 kΩ
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
- 55
30
30
10
50
29
200
94
175
V
V
V
A
A
A
W
˚C
TYP.
MAX.
UNIT
-
1.6
K/W
50
-
K/W
MIN.
MAX.
UNIT
-
2
kV
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
Rth j-mb
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
-
Rth j-a
pcb mounted, minimum
footprint
ESD LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
VC
Electrostatic discharge capacitor
voltage, all pins
Human body model
(100 pF, 1.5 kΩ)
July 1997
1
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9621-30
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
V(BR)DSS
Drain-source breakdown
voltage
Gate threshold voltage
VGS = 0 V; ID = 0.25 mA;
VGS(TO)
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 175˚C
Tj = -55˚C
IDSS
Zero gate voltage drain current
VDS = 30 V; VGS = 0 V;
IGSS
Gate source leakage current
VGS = ±5 V; VDS = 0 V
±V(BR)GSS
Gate-source breakdown
voltage
Drain-source on-state
resistance
IG = ±1 mA;
RDS(ON)
Tj = 175˚C
Tj = 175˚C
VGS = 5 V; ID = 25 A
Tj = 175˚C
MIN.
TYP.
MAX.
UNIT
30
27
1
0.5
10
1.5
0.05
0.02
-
2
2.3
10
500
1
10
-
V
V
V
V
V
µA
µA
µA
µA
V
-
19
-
21
39
mΩ
mΩ
MIN.
TYP.
MAX.
UNIT
DYNAMIC CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
gfs
Forward transconductance
VDS = 25 V; ID = 25 A
8
30
-
S
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 25 A; VDD = 30 V; VGS = 5 V
-
21
6
14
-
nC
nC
nC
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
1325
336
171
-
pF
pF
pF
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 25 A;
VGS = 5 V; RG = 10 Ω
Resistive load
-
20
106
72
77
-
ns
ns
ns
ns
Ld
Ld
Internal drain inductance
Internal drain inductance
-
3.5
4.5
-
nH
nH
Ls
Internal source inductance
Measured from tab to centre of die
Measured from drain lead solder
point to centre of die
Measured from source lead solder
point to source bond pad
-
7.5
-
nH
MIN.
TYP.
MAX.
UNIT
-
-
50
A
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL
PARAMETER
IDR
IDRM
VSD
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
IF = 25 A; VGS = 0 V
-
0.95
200
1.2
A
V
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 25 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 25 V
-
128
0.5
-
ns
µC
July 1997
CONDITIONS
2
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9621-30
AVALANCHE LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 25 A; VDD ≤ 25 V;
VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C
Normalised Power Derating
PD%
120
1000
MIN.
TYP.
MAX.
UNIT
-
-
70
mJ
PHP50N03T
ID, Drain current (Amps)
110
100
D
S/I
90
80
=
N)
100
VD
tp =
10 us
S(O
RD
70
100 us
60
50
40
1 ms
10
DC
30
10 ms
20
10
Tmb = 25 C
0
0
20
40
60
80 100
Tmb / C
120
140
160
1
180
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
10
VDS, Drain-source voltage (Volts)
100
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Normalised Current Derating
ID%
120
1
10
Transient thermal impedance, Zth j-mb (K/W) PHP50N03T
110
100
90
D=
1
80
0.5
70
0.2
60
50
0.1
0.1
40
30
0.05
0.02
PD
tp
D=
tp
T
20
10
0
0
0.01
0
20
40
60
80 100
Tmb / C
120
140
160
180
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
July 1997
1us
t
T
10us 100us 1ms 10ms
pulse width, tp (s)
0.1s
1s
10s
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
3
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
50
ID, Drain current (Amps)
5V
15 V
BUK9621-30
PHP50N03LT
PHP50N03LT
Transconductance, gfs (S)
40
Tj = 25 C
VDS = 30 V
3.5 V
40
30
Tj = 25 C
30
20
3V
20
175 C
10
10
VGS = 2.5 V
0
0
5
10
15
20
25
VDS, Drain-Source voltage (Volts)
0
30
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
RDS(on), Drain-Source on resistance (Ohms)
0.06
VGS = 2.5 V
10
20
30
Drain current, ID (A)
40
50
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
PHP50N03LT
3V
0
2.5
BUK959-60
Rds(on) normlised to 25degC
Tj = 25 C
0.05
2
0.04
0.03
1.5
3.5 V
5V
0.02
10 V
0.01
0
1
15 V
0
10
20
30
ID, Drain current (Amps)
40
0.5
-100
50
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
50
0
50
Tmb / degC
100
150
200
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V
PHP50N03LT
Drain current, ID (A)
-50
2.5
BUK959-60
VGS(TO) / V
VDS = 30 V
max.
40
2
30
1.5
20
1
typ.
min.
10
0
175 C
0
1
0.5
Tj = 25 C
2
3
Gate-source voltage, VGS (V)
4
0
-100
5
Fig.7. Typical transfer characteristics.
ID = f(VGS); parameter Tj
July 1997
-50
0
50
Tj / C
100
150
200
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
4
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9621-30
Sub-Threshold Conduction
1E-01
50
PHP50N03LT
Source-Drain diode current, IF(A)
VGS = 0 V
40
1E-02
2%
1E-03
typ
98%
30
Tj = 25 C
10
1E-05
0
1E-05
175 C
20
1E-04
0
0.5
1
1.5
2
2.5
0
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Capacitances, Ciss, Coss, Crss (pF)
10000
0.2
0.4
0.6
0.8
1
Source-Drain voltage, VSDS (V)
3
1.2
1.4
Fig.14. Typical reverse diode current.
IF = f(VSDS); parameter Tj
PHP50N03LT
120
WDSS%
110
100
90
80
70
Ciss
60
1000
50
40
30
Coss
20
10
Crss
100
1
10
Drain-source voltage, VDS (V)
0
20
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
15
40
60
80
100
120
Tmb / C
140
160
180
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb)
PHP50N03LT
VGS, Gate-Source voltage (Volts)
VDD = 30 V
ID = 25 A
Tj = 25 C
VDD
+
L
VDS
10
-
VGS
-ID/100
T.U.T.
0
5
RGS
0
0
10
20
Qg, Gate charge (nC)
30
40
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD )
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
July 1997
R 01
shunt
5
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9621-30
MECHANICAL DATA
Plastic single-ended package (Philips version of D2-PAK); 2 leads
SOT404
A
A1
E
D1
D
HD
Lp
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
D
D1
E
mm
4.5
4.1
1.40
1.27
0.85
0.60
0.64
0.46
9.65
8.65
1.6
1.2
10.3
9.7
OUTLINE
VERSION
e
Lp
HD
Q
2.54
2.9
2.1
15.4
14.8
2.60
2.20
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
97-06-16
SOT404
Fig.17. SOT404 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
July 1997
6
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9621-30
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.18. SOT404 : soldering pattern for surface mounting.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
July 1997
7
Rev 1.000