Philips Semiconductors Product specification N-channel TrenchMOS transistor FEATURES PHW35NQ20T SYMBOL QUICK REFERENCE DATA • ’Trench’ technology • Very low on-state resistance • Fast switching • Low thermal resistance d VDSS = 200 V ID = 35 A g RDS(ON) ≤ 70 mΩ s GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a plastic envelope using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. PINNING PIN SOT429 (TO247) DESCRIPTION 1 gate 2 drain 3 source tab drain 1 2 3 The PHW35NQ20T is supplied in the SOT429 (TO247) conventional leaded package. LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS VDGR VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ IDM PD Tj, Tstg Pulsed drain current Total power dissipation Operating junction and storage temperature - 55 200 200 ± 20 35 25 140 250 175 V V V A A A W ˚C MIN. MAX. UNIT - 462 mJ - 35 A Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS EAS Non-repetitive avalanche energy Unclamped inductive load, IAS = 35 A; tp = 100 µs; Tj prior to avalanche = 25˚C; VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V; refer to fig:15 IAS Non-repetitive avalanche current August 1999 1 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHW35NQ20T THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS in free air TYP. MAX. UNIT - 0.6 K/W 45 - K/W ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS VGS = 0 V; ID = 0.25 mA; VGS(TO) Drain-source breakdown voltage Gate threshold voltage Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C RDS(ON) MIN. TYP. MAX. UNIT 200 178 2.0 1.0 - 3.0 60 2 0.05 - 4.0 6 70 203 100 10 500 V V V V V mΩ mΩ nA µA µA Drain-source on-state resistance Gate source leakage current Zero gate voltage drain current VGS = 10 V; ID = 17 A VGS = 10 V; ID = 17 A; Tj = 175˚C VGS = ±10 V; VDS = 0 V VDS = 200 V; VGS = 0 V; Tj = 175˚C Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 35 A; VDD = 160 V; VGS = 10 V - 77 16 28 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 100 V; RD = 2.7 Ω; VGS = 10 V; RG = 5.6 Ω Resistive load - 22 100 80 90 - ns ns ns ns Ld Ld Ls Internal drain inductance Internal drain inductance Internal source inductance Measured from tab to centre of die Measured from drain lead to centre of die Measured from source lead to source bond pad - 3.5 4.5 7.5 - nH nH nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 4570 370 160 - pF pF pF IGSS IDSS REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IS VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge ISM August 1999 CONDITIONS MIN. TYP. MAX. UNIT - - 35 A - - 140 A IF = 35 A; VGS = 0 V - 0.85 1.2 V IF = 20 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 30 V - 160 1.0 - ns µC 2 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHW35NQ20T Normalised Power Derating, PD (%) Transient thermal impedance, Zth j-mb (K/W) 1 100 D = 0.5 90 80 0.2 0.1 70 0.1 60 0.05 50 0.02 40 P D 0.01 D = tp/T tp 30 single pulse 20 T 10 0.001 1E-06 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 Pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Drain Current, ID (A) 40 Normalised Current Derating, ID (%) VGS = 10V Tj = 25 C 100 35 90 80 8V 6V 30 70 5.2 V 25 60 5V 50 20 40 15 4.8 V 30 20 10 10 5 4.6 V 4.4 V 4.2 V 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 0 175 0 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); VGS ≥ 10 V 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS) Peak Pulsed Drain Current, IDM (A) 1000 0.2 Drain-Source On Resistance, RDS(on) (Ohms) 4.4 V 4.6 V Tj = 25 C 0.18 4.2 V RDS(on) = VDS/ ID 100 0.16 4.8 V 0.14 tp = 10 us 0.12 5V 0.1 100 us 5.2 V 0.08 10 D.C. 6V 0.06 1 ms 0.04 10 ms 1 VGS = 10V 8V 0.02 100 ms 0 1 10 100 Drain-Source Voltage, VDS (V) 1000 0 Fig.3. Safe operating area ID & IDM = f(VDS); IDM single pulse; parameter tp August 1999 5 10 15 20 25 Drain Current, ID (A) 30 35 40 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID) 3 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHW35NQ20T Drain current, ID (A) 4.5 40 VDS > ID X RDS(ON) Threshold Voltage, VGS(TO) (V) 4 35 maximum 3.5 30 typical 3 25 2.5 20 175 C minimum 2 15 1.5 Tj = 25 C 10 1 5 0.5 0 0 0 1 2 3 4 5 6 -60 -40 -20 Gate-source voltage, VGS (V) 45 40 60 80 100 120 140 160 180 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Transconductance, gfs (S) VDS > ID X RDS(ON) 20 Junction Temperature, Tj (C) Fig.7. Typical transfer characteristics. ID = f(VGS) 50 0 1.0E-01 Drain current, ID (A) Tj = 25 C 40 1.0E-02 35 175 C 30 minimum 1.0E-03 25 typical 1.0E-04 20 maximum 15 1.0E-05 10 5 1.0E-06 0 0 5 10 15 20 25 Drain current, ID (A) 30 35 0 40 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) 0.5 1 1.5 2 2.5 3 3.5 Gate-source voltage, VGS (V) 4 4.5 5 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C Normalised On-state Resistance 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 10000 Capacitances, Ciss, Coss, Crss (pF) Ciss 1000 Coss 100 Crss 10 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C) 0.1 Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 ˚C = f(Tj) August 1999 1 10 Drain-Source Voltage, VDS (V) 100 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 4 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PHW35NQ20T Gate-source voltage, VGS (V) Maximum Avalanche Current, IAS (A) ID = 35 A 100 Tj = 25 C VDD = 40 V 25 C VDD = 160 V 10 Tj prior to avalanche = 150 C 0 10 20 30 40 50 60 70 Gate charge, QG (nC) 80 90 1 0.001 100 0.01 0.1 1 10 Avalanche time, tAV (ms) Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG) Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load Source-Drain Diode Current, IF (A) 40 VGS = 0 V 35 30 175 C 25 20 Tj = 25 C 15 10 5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 Source-Drain Voltage, VSDS (V) Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj August 1999 5 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHW35NQ20T MECHANICAL DATA Plastic single-ended through-hole package; heatsink mounted; 1 mounting hole; 3-lead TO-247 SOT429 α E P A A1 β q S R D Y L1(1) Q b2 L 1 2 3 c w M b b1 e e 0 10 20 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 b2 c D E e L mm 5.3 4.7 1.9 1.7 1.2 0.9 2.2 1.8 3.2 2.8 0.9 0.6 21 20 16 15 5.45 16 15 (1) L1 4.0 3.6 P Q q R S w Y α β 3.7 3.3 2.6 2.4 5.3 3.5 3.3 7.5 7.1 0.4 15.7 15.3 6° 4° 17° 13° Note 1. Tinning of terminals are uncontrolled within zone L1. OUTLINE VERSION SOT429 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-04-07 99-08-04 TO-247 Fig.16. SOT429; pin 2 connected to mounting base Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT429 envelope. 3. Epoxy meets UL94 V0 at 1/8". August 1999 6 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHW35NQ20T DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 1999 7 Rev 1.000