PHILIPS BUK9219-55A

BUK9219-55A
TrenchMOS™ logic level FET
Rev. 01 — 24 October 2000
M3D300
Product specification
1. Description
N-channel enhancement mode field-effect power transistor in a plastic package using
TrenchMOS™1 technology, featuring very low on-state resistance.
Product availability:
BUK9219-55A in SOT428 (D-PAK).
2. Features
■
■
■
■
TrenchMOS™ technology
Q101 compliant
175 °C rated
Logic level compatible.
3. Applications
c
c
■ Automotive and general purpose power switching:
◆ 12 V and 24 V loads.
◆ Motors, lamps and solenoids.
4. Pinning information
Table 1:
Pinning - SOT428 (D-PAK), simplified outline and symbol
Pin
Description
1
gate (g)
2
drain (d)
3
source (s)
mb
drain (d)
Simplified outline
Symbol
mb
d
g
2
1
Top view
3
MBK091
SOT428 (D-PAK)
1.
TrenchMOS is a trademark of Royal Philips Electronics.
MBB076
s
BUK9219-55A
Philips Semiconductors
TrenchMOS™ logic level FET
5. Quick reference data
Table 2:
Quick reference data
Symbol Parameter
VDS
drain-source voltage (DC)
Conditions
Typ
Max
Unit
−
55
V
ID
drain current (DC)
Tmb = 25 °C; VGS = 5 V
−
55
A
Ptot
total power dissipation
Tmb = 25 °C
−
114
W
Tj
junction temperature
−
175
°C
RDSon
drain-source on-state resistance
VGS = 5 V; ID = 25 A
15
19
VGS = 4.5 V; ID = 25 A
−
20
mΩ
mΩ
6. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
VDS
drain-source voltage (DC)
VDGR
drain-gate voltage (DC)
VGS
gate-source voltage (DC)
VGSM
non-repetitive gate-source voltage
ID
drain current (DC)
Conditions
Min
Max
Unit
−
55
V
−
55
V
−
±10
V
tp ≤ 50 µs
−
±15
V
Tmb = 25 °C; VGS = 5 V; Figure 2 and 3
−
55
A
Tmb = 100 °C; VGS = 5 V; Figure 2
−
38
A
[1] −
219
A
RGS = 20 kΩ
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3
Tmb = 25 °C; Figure 1
Ptot
total power dissipation
−
114
W
Tstg
storage temperature
−55
+175
°C
Tj
operating junction temperature
−55
+175
°C
Source-drain diode
IDR
reverse drain current (DC)
Tmb = 25 °C
−
55
A
IDRM
pulsed reverse drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs
−
219
A
unclamped inductive load; ID = 49 A;
VDS ≤ 55 V; VGS = 5 V; RGS = 50 Ω;
starting Tj = 25 °C
−
120
mJ
Avalanche ruggedness
WDSS
[1]
non-repetitive avalanche energy
IDM is limited by chip, not package.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07642
Product specification
Rev. 01 — 24 October 2000
2 of 13
BUK9219-55A
Philips Semiconductors
TrenchMOS™ logic level FET
03aa24
03aa16
100
120
Ider
(%)
100
80
80
60
60
40
40
20
20
120
Pder
(%)
0
0
0
25
50
75
100
125
150
175
200
0
Tmb (oC)
25
50
75
100
125
150
175
200
Tmb (oC)
VGS ≥ 4.5 V
P tot
P der = ---------------------- × 100%
P
°
ID
I der = ------------------- × 100%
I
°
tot ( 25 C )
D ( 25 C )
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
03nb64
1000
ID
(A)
RDSon = VDS/ ID
100
tp = 10 us
100 us
δ=
P
10
tp
T
1 ms
D.C.
10 ms
t
tp
100 ms
T
1
1
10
VDS (V) 100
Tmb = 25 °C; IDM is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07642
Product specification
Rev. 01 — 24 October 2000
3 of 13
BUK9219-55A
Philips Semiconductors
TrenchMOS™ logic level FET
7. Thermal characteristics
Table 4:
Thermal characteristics
Symbol Parameter
Conditions
Value Unit
Rth(j-a)
thermal resistance from junction to ambient
minimum footprint, FR4 board
71.4
K/W
Rth(j-mb)
thermal resistance from junction to mounting
base
Figure 4
1.3
K/W
7.1 Transient thermal impedance
03nb65
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
0.1
0.05
0.02
δ=
P
tp
T
0.01
Single Shot
t
tp
T
0.001
10-6
10-5
10-4
10-3
10-2
10-1
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07642
Product specification
Rev. 01 — 24 October 2000
4 of 13
BUK9219-55A
Philips Semiconductors
TrenchMOS™ logic level FET
8. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tj = 25 °C
55
−
−
V
Tj = −55 °C
50
−
−
V
Static characteristics
V(BR)DSS drain-source breakdown voltage
VGS(th)
IDSS
gate-source threshold voltage
drain-source leakage current
ID = 0.25 mA; VGS = 0 V
ID = 1 mA; VDS = VGS; Figure 9
Tj = 25 °C
1
1.5
2
V
Tj = 175 °C
0.5
−
−
V
Tj = −55 °C
−
−
2.3
V
Tj = 25 °C
−
0.05
10
µA
Tj = 175 °C
−
−
500
µA
−
2
100
nA
Tj = 25 °C
−
15
19
mΩ
Tj = 175 °C
−
−
38
mΩ
−
−
20
mΩ
14
17.6
mΩ
VDS = 55 V; VGS = 0 V
IGSS
gate-source leakage current
VGS = ±10 V; VDS = 0 V
RDSon
drain-source on-state resistance
VGS = 5 V; ID = 25 A; Figure 7 and 8
VGS = 4.5 V; ID = 25 A
VGS = 10 V; ID = 25 A
Dynamic characteristics
−
2190 2920 pF
output capacitance
−
380
450
pF
Crss
reverse transfer capacitance
−
250
345
pF
td(on)
turn-on delay time
−
45
−
ns
tr
rise time
−
130
−
ns
td(off)
turn-off delay time
−
400
−
ns
tf
fall time
−
130
−
ns
Ld
internal drain inductance
measured from drain lead from package to
centre of die
−
2.5
−
nH
Ls
internal source inductance
measured from source lead from package to
source bond pad
−
7.5
−
nH
Ciss
input capacitance
Coss
VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 12
VDD = 30 V; RL = 1.2 Ω; VGS = 5 V; RG = 10 Ω
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07642
Product specification
Rev. 01 — 24 October 2000
5 of 13
BUK9219-55A
Philips Semiconductors
TrenchMOS™ logic level FET
Table 5: Characteristics…continued
Tj = 25 °C unless otherwise specified
Symbol Parameter
Conditions
Min
Typ
Max
Unit
−
0.85
1.2
V
−
51
−
ns
−
102
−
nC
Source-drain diode
VSD
source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 15
trr
reverse recovery time
Qr
recovered charge
IS = 20 A; dIS/dt = −100 A/µs
VGS = −10 V; VDS = 30 V
03nb60
35
RDSON
(mΩ)
03nb61
300
ID
(A)
250
VGS (V) = 10
8
30
9
7
6
200
25
5
150
20
4
100
15
50
3
10
2.2
0
0
2
4
6
8
2
10
VDS (V)
Tj = 25 °C
4
6
8
10
VGS (V)
Tj = 25 °C; ID = 25 A
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6. On-state resistance: typical values.
03aa28
03nb62
22
RDSon
(mΩ)
20
VGS (V) = 3.4
3.6
2.2
a
2
1.8
1.6
4.0
18
4.2
16
4.6
5.0
14
1.4
1.2
1
0.8
0.6
0.4
12
0.2
0
10
20
30
40
50
60
70
80
-60
90 100
ID (A)
Tj = 25 °C
20
60
100
140
180
Tj (oC)
R DSon
a = --------------------------R DSon ( 25 °C )
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain source on-state resistance
factor as a function of junction temperature.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07642
Product specification
-20
Rev. 01 — 24 October 2000
6 of 13
BUK9219-55A
Philips Semiconductors
TrenchMOS™ logic level FET
03aa36
10-1
03aa33
2.5
VGS(th)
ID
(V)
max
(A) 10-2
2
typ
10-3
1.5
min
1
10-4
0.5
10-5
0
10-6
-60
-20
20
60
100
min
0
140
180
Tj (oC)
0.5
1
typ
1.5
max
2
2.5
3
VGS (V)
Tj = 25 °C; VDS = VGS
ID = 1 mA; VDS = VGS
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
03nb58
60
gfs
(S)
50
03nb63
6000
C (pF)
5000
40
4000
30
3000
20
2000
10
1000
0
0
0
20
40
60
80
ID (A)
100
Tj = 25 °C; VDS = 25 V
Ciss
Coss
Crss
0.01
1
10
VDS (V)
100
VGS = 0 V; f = 1 MHz
Fig 11. Forward transconductance as a function of
drain current; typical values.
Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07642
Product specification
0.1
Rev. 01 — 24 October 2000
7 of 13
BUK9219-55A
Philips Semiconductors
TrenchMOS™ logic level FET
03nb59
100
ID
(A)
03nb57
6
VGS
(V)
5
O
Tj = 25 C
80
4
60
VDS= 14 V
O
Tj = 175 C
3
VDS= 44 V
40
2
20
1
0
0
0
1
2
3
4
5
0
VGS (V)
20
40
QG (nC)
60
Tj = 25 °C; ID = 25 A
VDS = 25 V
Fig 13. Transfer characteristics; typical values.
Fig 14. Turn-on gate charge characteristics; typical
values.
03nb56
120
IS
(A)
100
80
O
Tj = 175 C
60
O
Tj = 25 C
40
20
0
0.0
0.5
1.0
VSD (V) 1.5
VGS = 0 V
Fig 15. Reverse diode current; typical values.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07642
Product specification
Rev. 01 — 24 October 2000
8 of 13
BUK9219-55A
Philips Semiconductors
TrenchMOS™ logic level FET
9. Package outline
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
seating plane
y
A
E
A2
A
A1
b2
D1
mounting
base
E1
D
HE
L2
2
L1
L
1
3
b1
w M A
b
c
e
e1
0
10
20 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT max.
2.38
2.22
mm
A1(1)
A2
b
b1
max.
b2
c
0.65
0.45
0.89
0.71
0.89
0.71
1.1
0.9
5.36
5.26
0.4
0.2
D1
E
D
max. max. max.
E1
min.
6.22
5.98
4.0
6.73
6.47
4.81
4.45
e
e1
2.285 4.57
HE
max.
L
L1
min.
L2
w
y
max.
10.4
9.6
2.95
2.55
0.5
0.7
0.5
0.2
0.2
Note
1. Measured from heatsink back to lead.
OUTLINE
VERSION
SOT428
REFERENCES
IEC
JEDEC
EIAJ
TO-252
SC-63
EUROPEAN
PROJECTION
ISSUE DATE
98-04-07
99-09-13
Fig 16. SOT428 (D-PAK).
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07642
Product specification
Rev. 01 — 24 October 2000
9 of 13
BUK9219-55A
Philips Semiconductors
TrenchMOS™ logic level FET
10. Revision history
Table 6:
Revision history
Rev Date
01
20001024
CPCN
Description
-
Product specification; initial version.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07642
Product specification
Rev. 01 — 24 October 2000
10 of 13
BUK9219-55A
Philips Semiconductors
TrenchMOS™ logic level FET
11. Data sheet status
Datasheet status
Product status
Definition [1]
Objective specification
Development
This data sheet contains the design target or goal specifications for product development. Specification may
change in any manner without notice.
Preliminary specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any
time without notice in order to improve design and supply the best possible product.
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
12. Definitions
13. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products
are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
© Philips Electronics N.V. 2000 All rights reserved.
9397 750 07642
Product specification
Rev. 01 — 24 October 2000
11 of 13
BUK9219-55A
Philips Semiconductors
TrenchMOS™ logic level FET
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Building BE, P.O. Box 218, 5600 MD EINDHOVEN,
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Internet: http://www.semiconductors.philips.com
(SCA70)
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 07642
Product specification
Rev. 01 — 24 October 2000
12 of 13
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Philips Semiconductors
TrenchMOS™ logic level FET
Contents
1
2
3
4
5
6
7
7.1
8
9
10
11
12
13
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
© Philips Electronics N.V. 2000.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 24 October 2000
Document order number: 9397 750 07642