PSoC® Creator™ PSoC 3/PSoC 5LP System Reference Guide cy_boot Component v5.0 Document Number: 001-96074, Rev. ** Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intl): 408.943.2600 http://www.cypress.com Copyrights © Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. ® PSoC is a registered trademark, and PSoC Creator™ and Programmable System-on-Chip™ are trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 2 Contents 1 Introduction .................................................................................................................................... 9 Conventions ............................................................................................................................. 10 References .............................................................................................................................. 10 Sample Firmware Source Code .............................................................................................. 10 Revision History ....................................................................................................................... 10 2 Standard Types, APIs, and Defines ............................................................................................ 11 Base Types .............................................................................................................................. 11 Hardware Register Types ........................................................................................................ 11 Compiler Defines ..................................................................................................................... 11 Keil 8051 Compatibility Defines ............................................................................................... 12 Return Codes........................................................................................................................... 12 Interrupt Types and Macros ..................................................................................................... 13 Interrupt vector address type ............................................................................................ 13 Intrinsic Defines ....................................................................................................................... 13 Device Version Defines ........................................................................................................... 13 Variable Attributes .................................................................................................................... 13 Instance APIs ........................................................................................................................... 14 General APIs ..................................................................................................................... 14 Low Power APIs ................................................................................................................ 15 PSoC Creator Generated Defines ........................................................................................... 16 Project Type ...................................................................................................................... 16 Chip Configuration Mode .................................................................................................. 16 Debugging Mode ............................................................................................................... 17 Chip Protection Mode........................................................................................................ 17 Stack and Heap ................................................................................................................. 17 Voltage Settings ................................................................................................................ 17 System Clock Frequency .................................................................................................. 18 JTAG/Silicon ID ................................................................................................................. 18 IP Block Information .......................................................................................................... 18 3 Clocking ........................................................................................................................................ 19 PSoC Creator Clocking Implementation .................................................................................. 19 Overview ........................................................................................................................... 19 Clock Connectivity............................................................................................................. 20 ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 3 Contents Clock Synchronization ...................................................................................................... 20 Routed Clock Implementation ........................................................................................... 22 Using Asynchronous Clocks ............................................................................................. 26 Clock Crossing .................................................................................................................. 26 Gated Clocks..................................................................................................................... 27 Fixed-Function Clocking ................................................................................................... 28 UDB-Based Clocking ........................................................................................................ 28 Changing Clocks in Run-time ........................................................................................... 29 Low Voltage Analog Boost Clocks ........................................................................................... 29 APIs ......................................................................................................................................... 30 void SetAnalogRoutingPumps(uint8 enabled) .................................................................. 30 uint8 CyPLL_OUT_Start(uint8 wait) .................................................................................. 31 void CyPLL_OUT_Stop() .................................................................................................. 31 void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) ....................................... 31 void CyPLL_OUT_SetSource(uint8 source) ..................................................................... 32 void CyIMO_Start(uint8 wait) ............................................................................................ 32 void CyIMO_Stop() ............................................................................................................ 32 void CyIMO_SetFreq(uint8 freq) ....................................................................................... 33 void CyIMO_SetSource(uint8 source) .............................................................................. 33 void CyIMO_EnableDoubler() ........................................................................................... 33 void CyIMO_DisableDoubler() .......................................................................................... 34 void CyBusClk_SetDivider(uint16 divider) ........................................................................ 34 void CyCpuClk_SetDivider(uint8 divider) .......................................................................... 34 void CyMasterClk_SetSource(uint8 source) ..................................................................... 35 void CyMasterClk_SetDivider(uint8 divider) ..................................................................... 35 void CyUsbClk_SetSource(uint8 source) ......................................................................... 35 void CyILO_Start1K() ........................................................................................................ 36 void CyILO_Stop1K() ........................................................................................................ 36 void CyILO_Start100K() .................................................................................................... 36 void CyILO_Stop100K() .................................................................................................... 36 void CyILO_Enable33K() .................................................................................................. 36 void CyILO_Disable33K() ................................................................................................. 37 void CyILO_SetSource(uint8 source) ............................................................................... 37 uint8 CyILO_SetPowerMode(uint8 mode) ........................................................................ 37 uint8 CyXTAL_Start(uint8 wait) ......................................................................................... 38 void CyXTAL_Stop() .......................................................................................................... 38 void CyXTAL_EnableErrStatus() ....................................................................................... 38 void CyXTAL_DisableErrStatus() ...................................................................................... 38 uint8 CyXTAL_ReadStatus() ............................................................................................. 39 void CyXTAL_EnableFaultRecovery() .............................................................................. 39 void CyXTAL_DisableFaultRecovery() .............................................................................. 39 void CyXTAL_SetStartup(uint8 setting) ............................................................................. 39 ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 4 Introduction void CyXTAL_SetFbVoltage(uint8 setting) ........................................................................ 39 void CyXTAL_SetWdVoltage(uint8 setting) ....................................................................... 40 void CyXTAL_32KHZ_Start() ............................................................................................ 40 void CyXTAL_32KHZ_Stop() ............................................................................................ 40 uint8 CyXTAL_32KHZ_ReadStatus() ................................................................................ 40 uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) ........................................................ 40 void CySetScPumps(uint8 enable) ................................................................................... 41 4 Power Management ..................................................................................................................... 42 Implementation ........................................................................................................................ 42 Low Power Usage ............................................................................................................. 42 Clock Configuration ........................................................................................................... 42 Wakeup Time Configuration .............................................................................................. 43 Wakeup Source Configuration .......................................................................................... 44 Power Management APIs ................................................................................................. 45 5 Interrupts....................................................................................................................................... 53 APIs ......................................................................................................................................... 53 CyGlobalIntEnable ............................................................................................................ 53 CyGlobalIntDisable ........................................................................................................... 53 uint32 CyDisableInts() ....................................................................................................... 53 void CyEnableInts(uint32 mask) ....................................................................................... 53 void CyIntEnable(uint8 number) ....................................................................................... 54 void CyIntDisable(uint8 number)....................................................................................... 54 uint8 CyIntGetState(uint8 number) ................................................................................... 54 cyisraddress CyIntSetVector(uint8 number, cyisraddress address) ................................. 54 cyisraddress CyIntGetVector(uint8 number) ..................................................................... 54 cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) ........................... 55 cyisraddress CyIntGetSysVector(uint8 number) ............................................................... 55 void CyIntSetPriority(uint8 number, uint8 priority) ............................................................ 55 uint8 CyIntGetPriority(uint8 number) ................................................................................ 55 void CyIntSetPending(uint8 number) ................................................................................ 56 void CyIntClearPending(uint8 number) ............................................................................. 56 6 Pins ................................................................................................................................................ 57 APIs ......................................................................................................................................... 57 uint8 CyPins_ReadPin(uint16/uint32 pinPC) .................................................................... 57 void CyPins_SetPin(uint16/uint32 pinPC) ........................................................................ 57 void CyPins_ClearPin(uint16/uint32 pinPC) ..................................................................... 57 void CyPins_SetPinDriveMode(uint16/uint32 pinPC, uint8 mode) ................................... 58 uint8 CyPins_ReadPinDriveMode(uint16/uint32 pinPC)................................................... 58 void CyPins_FastSlew(uint16/uint32 pinPC) .................................................................... 58 void CyPins_SlowSlew(uint16/uint32 pinPC) ................................................................... 58 ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 5 Contents 7 Register Access ........................................................................................................................... 59 APIs ......................................................................................................................................... 59 uint8 CY_GET_REG8(uint16/uint32 reg) .......................................................................... 59 void CY_SET_REG8(uint16/uint32 reg, uint8 value) ........................................................ 59 uint16 CY_GET_REG16(uint16/uint32 reg) ...................................................................... 60 void CY_SET_REG16(uint16/uint32 reg, uint16 value) .................................................... 60 uint32 CY_GET_REG24(uint16/uint32 reg) ...................................................................... 60 void CY_SET_REG24(uint16/uint32 reg, uint32 value) .................................................... 60 uint32 CY_GET_REG32(uint16/uint32 reg) ...................................................................... 60 void CY_SET_REG32(uint16/uint32 reg, uint32 value) .................................................... 61 uint8 CY_GET_XTND_REG8(uint32 reg) ......................................................................... 61 void CY_SET_XTND_REG8(uint32 reg, uint8 value) ....................................................... 61 uint16 CY_GET_XTND_REG16(uint32 reg) ..................................................................... 61 void CY_SET_XTND_REG16(uint32 reg, uint16 value) ................................................... 61 uint32 CY_GET_XTND_REG24(uint32 reg) ..................................................................... 62 void CY_SET_XTND_REG24(uint32 reg, uint32 value) ................................................... 62 uint32 CY_GET_XTND_REG32(uint32 reg) ..................................................................... 62 void CY_SET_XTND_REG32(uint32 reg, uint32 value) ................................................... 62 8 DMA ............................................................................................................................................... 63 9 Flash and EEPROM ...................................................................................................................... 64 Implementation ........................................................................................................................ 64 Flash Architecture ............................................................................................................. 64 EEPROM Architecture....................................................................................................... 65 Working with Flash and EEPROM .................................................................................... 65 Flash and EEPROM APIs ................................................................................................. 68 10 System Functions ........................................................................................................................ 73 General APIs............................................................................................................................ 73 uint8 CyEnterCriticalSection(void) .................................................................................... 73 void CyExitCriticalSection(uint8 savedIntrStatus) ............................................................. 73 void CYASSERT(uint32 expr) ........................................................................................... 74 void CyHalt(uint8 reason) ................................................................................................. 74 void CySoftwareReset(void) ............................................................................................. 74 void CyGetUniqueID(uint32* uniqueId) ............................................................................. 74 CyDelay APIs ........................................................................................................................... 74 void CyDelay(uint32 milliseconds) .................................................................................... 75 void CyDelayUs(uint16 microseconds) ............................................................................. 75 void CyDelayFreq(uint32 freq) .......................................................................................... 75 void CyDelayCycles(uint32 cycles) ................................................................................... 76 Voltage Detect APIs ................................................................................................................. 76 Functional Description ...................................................................................................... 76 Device Reset ..................................................................................................................... 76 ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 6 Introduction Low/High-Voltage Detection .............................................................................................. 76 Interrupt Configuration ...................................................................................................... 77 Best Practices ................................................................................................................... 77 APIs ................................................................................................................................... 78 Cache Functionality ................................................................................................................. 81 PSoC 3 .............................................................................................................................. 81 PSoC 5LP ......................................................................................................................... 82 11 Startup and Linking...................................................................................................................... 83 PSoC 3 .................................................................................................................................... 84 PSoC 5LP ................................................................................................................................ 84 Unaligned Transfers (PSoC 5LP) ...................................................................................... 84 GCC Implementation......................................................................................................... 84 Realview Implementation (applicable for MDK ................................................................. 85 CMSIS Support ................................................................................................................. 85 High-Level I/O Functions ......................................................................................................... 87 The printf() Usage Model .................................................................................................. 87 Preservation of Reset Status ................................................................................................... 88 PSoC 3/PSoC 5LP ............................................................................................................ 88 API Memory Usage ................................................................................................................. 88 PSoC 3 (Keil PK51)........................................................................................................... 88 PSoC 5LP (GCC) .............................................................................................................. 89 Performance ............................................................................................................................ 89 Functions Execution Time ................................................................................................. 89 Critical Sections Duration .................................................................................................. 90 12 Watchdog Timer (WDT)................................................................................................................ 91 APIs ......................................................................................................................................... 91 void CyWdtStart(uint8 ticks, uint8 lpMode) ....................................................................... 91 void CyWdtStart(uint8 ticks, uint8 lpMode) (continued) .................................................... 91 void CyWdtClear() ............................................................................................................. 92 13 MISRA Compliance ...................................................................................................................... 93 Verification Environment .......................................................................................................... 93 Project Deviations .................................................................................................................... 94 Documentation Related Rules ................................................................................................. 95 PSoC Creator Generated Sources Deviations ........................................................................ 96 [] cy_boot Component-Specific Deviations ............................................................................... 97 14 System Timer (SysTick) ............................................................................................................... 99 Functional Description ............................................................................................................. 99 APIs ......................................................................................................................................... 99 Functions ........................................................................................................................... 99 Global Variables .............................................................................................................. 103 ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 7 Contents 15 cy_boot Component Changes .................................................................................................. 104 Version 5.0 ............................................................................................................................. 104 Version 4.20 ........................................................................................................................... 105 Version 4.11 ........................................................................................................................... 108 Version 4.10 ........................................................................................................................... 108 Version 4.0 ............................................................................................................................. 109 Version 3.40 and Older .......................................................................................................... 110 Version 3.40 .................................................................................................................... 110 Version 3.30 .................................................................................................................... 110 Version 3.20 ..................................................................................................................... 111 Version 3.10 ..................................................................................................................... 111 Version 3.0 ....................................................................................................................... 111 Version 2.40 and Older .......................................................................................................... 113 Version 2.40 .................................................................................................................... 113 Version 2.30 .................................................................................................................... 113 Version 2.21 .................................................................................................................... 115 ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 8 1 Introduction This System Reference Guide describes functions supplied by the PSoC Creator cy_boot component. The cy_boot component provides the system functionality for a project to give better access to chip resources. The functions are not part of the component libraries but may be used by them. You can use the function calls to reliably perform needed chip functions. The cy_boot component is unique: Included automatically into every project Only a single instance can be present No symbol representation Not present in the Component Catalog (by default) As the system component, cy_boot includes various pieces of library functionality. This guide is organized by these functions: DMA Flash Clocking Power management Startup code Various library functions Linker scripts The cy_boot component presents an API that enables user firmware to accomplish the tasks described in this guide. There are multiple major functional areas that are described separately. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 9 Introduction Conventions The following table lists the conventions used throughout this guide: Convention Usage Courier New Displays file locations and source code: C:\ …cd\icc\, user entered text Displays file names and reference documentation: sourcefile.hex Displays keyboard commands in procedures: [Enter] or [Ctrl] [C] Represents menu paths: File > New Project > Clone Displays commands, menu paths and selections, and icon names in procedures: Click the Debugger icon, and then click Next. Displays cautions or functionality unique to PSoC Creator or the PSoC device. Italics [bracketed, bold] File > New Project Bold Text in gray boxes References This guide is one of a set of documents pertaining to PSoC Creator and PSoC devices. Refer to the following other documents as needed: PSoC Creator Help PSoC Creator Component Datasheets PSoC Creator Component Author Guide PSoC Technical Reference Manual (TRM) Sample Firmware Source Code PSoC Creator provides numerous example projects that include schematics and example code in the Find Example Project dialog. For component-specific examples, open the dialog from the Component Catalog or an instance of the component in a schematic. For general examples, open the dialog from the Start Page or File menu. As needed, use the Filter Options in the dialog to narrow the list of projects available to select. Refer to the “Find Example Project” topic in the PSoC Creator Help for more information. Revision History Document Title: PSoC® Creator™ PSoC 3/PSoC 5LP System Reference Guide, cy_boot Component v5.0 Document Number: 001-96074 Revision Date Description of Change ** 4/30/2015 New document for version 5.0 of the cy_boot component. Refer to the change section for component changes from previous versions of cy_boot. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 10 2 Standard Types, APIs, and Defines To support the operation of the same code across multiple CPUs with multiple compilers, the cy_boot component provides types and defines (in the cytypes.h file) that create consistent results across platforms. Base Types Type Description char8 uint8 uint16 uint32 int8 int16 int32 float32 float64 int64 uint64 8-bit (signed or unsigned, depending on the compiler selection for char) 8-bit unsigned 16-bit unsigned 32-bit unsigned 8-bit signed 16-bit signed 32-bit signed 32-bit float 64-bit float (unavailable for PSoC 3) 64-bit signed (unavailable for PSoC 3) 64-bit unsigned (unavailable for PSoC 3) Hardware Register Types Hardware registers typically have side effects and therefore are referenced with a volatile type. Define Description reg8 reg16 reg32 Volatile 8-bit unsigned Volatile 16-bit unsigned Volatile 32-bit unsigned Compiler Defines The compiler being used can be determined by testing for the definition of the specific compiler. For example, to test for the PSoC 3 Keil compiler: #if defined(__C51__) Define Description __C51__ __GNUC__ Keil 8051 compiler ARM GCC compiler ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 11 Standard Types, APIs, and Defines __ARMCC_VERSION ARM Realview compiler used by Keil MDK and RVDS tool sets Keil 8051 Compatibility Defines The Keil 8051 compiler supports type modifiers that are specific to this platform. For other platforms these modifiers must not be present. For compatibility these types are supported by defines that map to the appropriate string when compiled for Keil and an empty string for other platforms. These defines are used to create optimized Keil 8051 code while still supporting compilation on other platforms. Define Keil Type CYBDTA CYBIT CYCODE CYCOMPACT CYDATA CYFAR CYIDATA CYLARGE CYPDATA CYREENTRANT CYSMALL CYXDATA bdata bit code compact data far idata large pdata reentrant small xdata Other Platforms uint8 Return Codes Return codes from Cypress routines are returned as an 8-bit unsigned value type: cystatus. The standard return values are: Define Description CYRET_SUCCESS CYRET_UNKNOWN CYRET_BAD_PARAM CYRET_INVALID_OBJECT CYRET_MEMORY CYRET_LOCKED CYRET_EMPTY CYRET_BAD_DATA CYRET_STARTED CYRET_FINISHED CYRET_CANCELED CYRET_TIMEOUT CYRET_INVALID_STATE Successful Unknown failure One or more invalid parameters Invalid object specified Memory related failure Resource lock failure No more objects available Bad data received (CRC or other error check) Operation started, but not necessarily completed yet Operation completed Operation canceled Operation timed out Operation not setup or is in an improper state ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 12 Standard Types, APIs, and Defines Interrupt Types and Macros Types and macros provide consistent definition of interrupt service routines across compilers and platforms. Note that the macro to use is different between the function definition and the function prototype. Function definition example: CY_ISR(MyISR) { /* ISR Code here */ } Function prototype example: CY_ISR_PROTO(MyISR); Interrupt vector address type Type Description cyisraddress Interrupt vector (address of the ISR function) Intrinsic Defines Define Description CY_NOP Processor NOP instruction Device Version Defines Define Description CY_PSOC3 CY_PSOC5 Any PSoC 3 Device Any PSoC 5 Device Variable Attributes Define Description CY_NOINIT Specifies that a variable should be placed into uninitialized data section that prevents this variable from being initialized to zero on startup. For PSoC 3 no code is generated for this macro. CY_ALIGN Specifies a minimum alignment (in bytes) for variables of the specified type. CY_PACKED, Attached to an enum, struct, or union type definition, specified that the minimum CY_PACKED_ATTR required memory be used to represent the type. Example: CYPACKED typedef struct { uint8 freq; uint8 absolute; } CYPACKED_ATTR imoTrim; ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 13 Standard Types, APIs, and Defines Define Description CY_INLINE Specifies that compiler can perform inline expansion: insert the function code at the address of each function call. Instance APIs General APIs Most components have an instance-specific set of the APIs that allow you to initialize, enable and disable the component. These functions are listed below generically. Refer to the individual datasheet for specific information. `=instance_name`_InitVar Description: This global variable Indicates whether the component has been initialized. The variable is initialized to 0 and set to 1 the first time _Start() is called. This allows the component to restart without reinitialization after the first call to the _Start() routine. If reinitialization of the component is required, then the _Init() function can be called before the _Start() or _Enable() function. void `=instance_name`_Start (void) Description: This function intended to start component operation. The _Start() sets the _initVar variable, calls the _Init function, and then calls the _Enable function. Parameters: None Return Value: None void `=instance_name`_Stop (void) Description: Disables the component operation. Parameters: None Return Value: None void `=instance_name`_Init (void) Description: Initializes component's parameters to those set in the customizer placed on the schematic. All registers will be reset to their initial values. This reinitializes the component. Usually called in _Start(). Parameters: None Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 14 Standard Types, APIs, and Defines void `=instance_name`_Enable (void) Description: Enables the component block operation. Parameters: None Return Value: None Low Power APIs Most components have an instance-specific set of low power APIs that allow you to put the component into its low power state. These functions are listed below generically. Refer to the individual datasheet for specific information regarding register retention information if applicable. void `=instance_name`_Sleep (void) Description: The _Sleep() function checks to see if the component is enabled and saves that state. Then it calls the _Stop() function and calls _SaveConfig() function to save the user configuration. • PSoC 3/PSoC 5LP: Call the _Sleep() function before calling the CyPmSleep() or the CyPmHibernate() function. Parameters: None Return Value: None void `=instance_name`_Wakeup (void) Description: The _Wakeup() function calls the _RestoreConfig() function to restore the user configuration. If the component was enabled before the _Sleep() function was called, the _Wakeup() function will re-enable the component. Parameters: None Return Value: None Side Effects: Calling the _Wakeup() function without first calling the _Sleep() or _SaveConfig() function may produce unexpected behavior. void `=instance_name`_SaveConfig(void) Description: This function saves the component configuration. This will save non-retention registers. This function will also save the current component parameter values, as defined in the Configure dialog or as modified by appropriate APIs. This function is called by the _Sleep() function. Parameters: None Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 15 Standard Types, APIs, and Defines void `=instance_name`_RestoreConfig(void) Description: This function restores the component configuration. This will restore non-retention registers. This function will also restore the component parameter values to what they were prior to calling the _Sleep() function. Parameters: None Return Value: None Side Effects: Calling this function without first calling the _Sleep() or _SaveConfig() function may produce unexpected behavior. PSoC Creator Generated Defines PSoC Creator generates the following macros in the cyfitter.h file. Project Type The following are defines for project type (from Project > Build Settings): CYDEV_PROJ_TYPE CYDEV_PROJ_TYPE_BOOTLOADER CYDEV_PROJ_TYPE_LOADABLE CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER CYDEV_PROJ_TYPE_STANDARD CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER Chip Configuration Mode The following are defines for chip configuration mode (from System DWR). Options vary by device: All CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED CYDEV_CONFIGURATION_MODE_DMA CYDEV_CONFIGURATION_MODE_UNCOMPRESSED CYDEV_DEBUGGING_ENABLE or CYDEV_PROTECTION_ENABLE (Debugging or protection enabled. Mutually exclusive.) PSoC 3 CYDEV_CONFIGURATION_CLEAR_SRAM (Startup code clear SRAM?) PSoC 3 and PSoC 5LP CYDEV_CONFIGURATION_COMPRESSED (Configuration data compressed?) CYDEV_CONFIGURATION_DMA (Configuration data loaded via DMA?) CYDEV_CONFIGURATION_ECC (Configuration data stored in ECC?) CYDEV_CONFIG_FASTBOOT_ENABLED (Device startup at 48 MHz at boot? If not, 12 MHz.) ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 16 Standard Types, APIs, and Defines CYDEV_INSTRUCT_CACHE_ENABLED (Instruction cache enabled?) CYDEV_DMA_CHANNELS_AVAILABLE (Number of DMA channels available for configuration.) CYDEV_ECC_ENABLE (ECC enabled?) CYDEV_DEBUGGING_XRES (Optional XRES pin enabled as XRES?) PSoC 5LP CYDEV_USE_BUNDLED_CMSIS (Include the CMSIS standard library.) Debugging Mode The following are defines for debugging mode (from System DWR): CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_Disable CYDEV_DEBUGGING_DPS_JTAG_4 CYDEV_DEBUGGING_DPS_JTAG_5 CYDEV_DEBUGGING_DPS_SWD CYDEV_DEBUGGING_DPS_SWD_SWV Chip Protection Mode The following are defines for chip protection mode (from System DWR): CYDEV_DEBUG_PROTECT CYDEV_DEBUG_PROTECT_KILL CYDEV_DEBUG_PROTECT_OPEN CYDEV_DEBUG_PROTECT_PROTECTED Stack and Heap The following are defines for the number of bytes allocated to the stack and heap (from System DWR). These are only for PSoC 5LP. CYDEV_HEAP_SIZE CYDEV_STACK_SIZE Voltage Settings The following are defines for voltage settings (from System DWR). Options vary by device: CYDEV_VARIABLE_VDDA CYDEV_VDDA CYDEV_VDDA_MV CYDEV_VDDD CYDEV_VDDD_MV CYDEV_VDDIO0 CYDEV_VDDIO0_MV ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 17 Standard Types, APIs, and Defines CYDEV_VDDIO1 CYDEV_VDDIO1_MV CYDEV_VDDIO2 CYDEV_VDDIO2_MV CYDEV_VDDIO3 CYDEV_VDDIO3_MV CYDEV_VIO0 CYDEV_VIO0_MV CYDEV_VIO1 CYDEV_VIO1_MV CYDEV_VIO2 CYDEV_VIO2_MV CYDEV_VIO3 CYDEV_VIO3_MV System Clock Frequency The following are defines for system clock frequency (from Clock DWR): PSoC 3 and PSoC 5 BCLK__BUS_CLK__HZ BCLK__BUS_CLK__KHZ BCLK__BUS_CLK__MHZ JTAG/Silicon ID The following is the define for JTAG/Silicon ID for the current device: CYDEV_CHIP_JTAG_ID IP Block Information PSoC Creator generates the following macros in the cyfitter.h file for the IP blocks that exist on the current device: #define CYIPBLOCK_<BLOCK NAME>_VERSION <version> For example: #define CYIPBLOCK_P3_TIMER_VERSION 0 #define CYIPBLOCK_P3_USB_VERSION 0 #define CYIPBLOCK_P3_VIDAC_VERSION 0 ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 18 3 Clocking PSoC Creator Clocking Implementation PSoC devices supported by PSoC Creator have flexible clocking capabilities. These clocking capabilities are controlled in PSoC Creator by selections within the Design-Wide Resources settings, connectivity of clocking signals on the design schematic, and API calls that can modify the clocking at runtime. The clocking API is provided in the CyLib.c and CyLib.h files. This section describes how PSoC Creator maps clocks onto the device and provides guidance on clocking methodologies that are optimized for the PSoC architecture. The System Clock consolidates Bus Clock (BUS_CLK) on PSoC 3/PSoC 5LP devices. The Master Clock consolidates Master Clock (MASTER_CLK) on PSoC 3/PSoC 5LP devices. Overview The clock system includes these clock resources: Four internal clock sources increase system integration: 3 to 48 MHz Internal Main Oscillator (IMO) ±1% at 3 MHz 1 kHz, 33 kHz, 100 kHz Internal Low Speed Oscillator (ILO) outputs USB Clock Domain, sourced from IMO, MHz External Crystal Oscillator (MHzECO), and Digital System Interconnect (DSI) 24 to 67 MHz fractional Phase-Locked Loop (PLL) sourced from IMO, MHzECO, and DSI Clock generated using a DSI signal from an external I/O pin or other logic Two external clock sources provide high precision clocks: ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 19 Clocking 4 to 25 MHzECO 32.768 kHz External Crystal Oscillator (kHzECO) for Real Time Clock (RTC) Dedicated 16-bit divider for bus clock Eight individually sourced 16-bit clock dividers for the digital system peripherals Four individually sourced 16-bit clock dividers with skew for the analog system peripherals IMO has a USB mode that synchronizes to USB host traffic, requiring no external crystal for USB. (USB equipped parts only) Clock Connectivity The PSoC architecture includes flexible clock generation logic. Refer to the Technical Reference Manual for a detailed description of all the clocking sources available in a particular device. The usage of these various clocking sources can be categorized by how those clocks are connected to elements of a design. System Clock This is a special clock. It is closely related to Master Clock. For most designs, Master Clock and System Clock will be the same frequency and considered to be the same clock. These must be the highest speed clocks in the system. The CPU will be running off of System Clock and all the peripherals will communicate to the CPU and DMA using System Clock. When a clock is synchronized, it is synchronized to Master Clock. When a pin is synchronized it is synchronized to System Clock. Global Clock This is a clock that is placed on one of the global low skew digital clock lines. This also includes System Clock. When a clock is created using a Clock component, it will be created as a global clock. This clock must be directly connected to a clock input or may be inverted before connection to a clock input. Global clock lines connect only to the clock input of the digital elements in PSoC. If a global clock line is connected to something other than a clock input (that is, combinatorial logic or a pin), then the signal is not sent using low skew clock lines. Routed Clock Any clock that is not a global clock is a routed clock. This includes clocks generated by logic (with the exception of a single inverter) and clocks that come in from a pin. Clock Synchronization Each clock in a PSoC device is either synchronous or asynchronous. This is in reference to System Clock and Master Clock. PSoC is designed to operate as a synchronous system. This was done to enable communication between the programmable logic and either the CPU or DMA. If these are not synchronous to a common clock, then any communication requires clocking crossing circuitry. Generally, asynchronous clocking is not supported except for PLD logic that does not interact with the CPU system. Synchronous Clock (PSoC 3/ PSoC 5LP) Examples of synchronous clocks include: Global clock with sync to Master Clock option set. This option is set by default on the Advanced tab of the Clock component Configure dialog. Clock from an input pin with the "Input Synchronized" option selected. This option is set by default on the Input tab of the Pins component Configure dialog. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 20 Clocking Clock derived combinatorially from signals that were all generated from registers that are clocked by synchronous clocks. Asynchronous Clock (PSoC 3/ PSoC 5LP) An asynchronous clock is any clock that is not synchronous. Some examples are: Any signal coming in from the Digital System Interconnect (DSI) other than a synchronized pin. These signals must be considered asynchronous because their timing is not guaranteed. This includes: What would normally be a global clock (if connected directly to a clock input) that is fed through logic before being used as a clock Fixed function block outputs (that is, Counter, Timer, PWM) Digital signals from the analog blocks Global clock without the sync option set Clock from an input pin with Input Synchronized not selected Clock that is combinatorially created using any asynchronous signal Making Signals Synchronous (PSoC 3/ PSoC 5LP) Depending on the source of the clock signal, it can be made synchronous using different methods: An asynchronous global clock can be made synchronous by checking the Sync with MASTER_CLK option in the Clock component Configure dialog (this is the default selection). A routed clock coming from a pin can be made synchronous by checking the Input Synchronized option in the Pins component Configure dialog (this is the default selection, under the Pins tab). Any signal can be made synchronous by using the Sync component and a synchronous clock as the clock signal. When synchronizing a signal: The synchronizing clock must be at least 2x the frequency of the signal being synchronized. If this rule is violated, then incoming clock edges can be missed and therefore not reflected in the resulting synchronized clock. The clock signal output will have all its transitions on the rising edge of the synchronizing clock. The clock signal output will have its edges moved from their original timing. The clock signal output will have variation in the high and low pulse widths unless the incoming clock and the synchronizing clock are directly related to each other. The following example shows two clocks that have been synchronized to System Clock. Clock_1 has exactly 2x the period of System Clock. Clock_2 has a period of approximately 3x the period of System Clock. That results in the high and low pulse widths varying between 1 and 2 System Clock periods. In both cases all transitions occur at the rising edge of System Clock. System Clock Clock_1 Clock_2 ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 21 Clocking Routed Clock Implementation The clocking implementation in PSoC directly connects global clock signals to the clock input of clocked digital logic. This applies to both synchronous and asynchronous clocks. Since global clocks are distributed on low skew clock lines, all clocked elements connected to the same global clock will be clocked at the same time. Routed clocks are distributed using the general digital routing fabric. This results in the clock arriving at each destination at different times. If that clock signal was used directly as the clock, then it would force the clock to be considered an asynchronous clock. This is because it cannot be guaranteed to transition at the rising edge of System Clock. This can also result in circuit failures if the output of a register clocked by an early arriving clock is used by a register clocked by a late arriving version of the same clock. Under some circumstances, PSoC Creator can transform a routed clock circuit into a circuit that uses a global clock. If all the sources of a routed clock can be traced back to the output of registers that are clocked by common global clocks, then the circuit is transformed automatically by PSoC Creator. The cases where this is possible are: All signals are derived from the same global clock. This global clock can be asynchronous or synchronous. All signals are derived from more than one synchronous global clock. In this case, the common global clock is System Clock. The clocking implementation in PSoC includes a built-in edge detection circuit that is used in this transformation. This does not use PLD resources to implement. The following shows the logical implementation and the resulting clock timing diagram. RoutedClk (Enable) Latch (Transparent when Low) Clk GlobalClk (Effective Clock) GlobalClk RoutedClk Clk This diagram shows that the resulting clock occurs synchronous to the global clock on the first clock after a rising edge of the routed clock. When analyzing the design to determine the source of a routed clock, another routed clock that was transformed may be encountered. In that case, the global clock used in that transformation is considered the source clock for that signal. The clock transformation used for every routed clock is reported in the report file. This file is located in the Workspace Explorer under the Results tab after a successful build. The details are shown under the ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 22 Clocking "Initial Mapping" heading. Each routed clock will be shown with the "Effective Clock" and the "Enable Signal". The "Effective Clock" is the global clock that is used and the "Enable Signal" is the routed clock that is edge detected and used as the enable for that clock. Example with a Divided Clock A simple divided clock circuit can be used to observe how this transformation is done. The following circuit clocks the first flip-flop (cydff_1) with a global clock. This generates a clock that is divided by 2 in frequency. That signal is used as a routed clock that clocks the next flip-flop (cydff_2). The report file indicates that one global clock has been used and that the single routed clock has been transformed using the global clock as the effective clock. The resulting signals generated by this circuit are as follows. Clock_1 Div2 Div4 It may appear that the Div4 signal is generated by the falling edge of the Div2 signal. This is not the case. The Div4 signal is generated on the first Clock_1 rising edge following a rising edge on Div2. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 23 Clocking Example with a Clock from a Pin In the following circuit, a clock is brought in on a pin with synchronization turned on. Since synchronization of pins is done with System Clock, the transformed circuit uses System Clock as the Effective Clock and uses the rising edge of the pin as the Enable Signal. If input synchronization was not enabled at the pin, there would not be a global clock to use to transform the routed clock, and the routed clock would be used directly. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 24 Clocking Example with Multiple Clock Sources In this example, the routed clock is derived from flip-flops that are clocked by two different clocks. Both of these clocks are synchronous, so System Clock is the common global clock that becomes the Effective Clock. If either of these clocks had been asynchronous, then the routed clock would have been used directly. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 25 Clocking Overriding Routed Clock Transformations The automatic transformation that PSoC Creator performs on routed clocks is generally the implementation that should be used. There is however a method to force the routed clock to be used directly. The UDBClkEn component configured in Async mode will force the clock used to be the routed clock, as shown in the following circuit. Using Asynchronous Clocks Asynchronous clocks can be used with PLD logic. However, they are not automatically supported by control registers, status registers and datapath elements because of the interaction with the CPU those elements have. Most Cypress library components will only work with synchronous clocks. They specifically force the insertion of a synchronizer automatically if the clock provided is asynchronous. Components that are designed to work with asynchronous clocks such as the SPI Slave will specifically describe how they handle clocking in their datasheet. If an asynchronous clock is connected directly to something other than PLD logic, then a Design Rule Check (DRC) error is generated. For example, if an asynchronous pin is connected to a control register clock, a DRC error is generated. As stated in the error message, the error can be removed by using a UDBClkEn component in async mode. That won’t remove the underlying synchronization issue, but it will allow the design to override the error if the design has handled synchronization in some other way. Clock Crossing Multiple clock domains are commonly needed in a design. Often these multiple domains do not interact and therefore clocking crossings do not occur. In the case where signals generated in one clock domain need to be used in another clock domain, special care must be taken. There is the case where the two clock domains are asynchronous from each other and the case where both clock domains are synchronous to System Clock. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 26 Clocking When both clocks are synchronous to System Clock, signals from the slower clock domain can be freely used in the other clock domain. In the other direction, care must be taken that the signals from the faster clock domain are active for a long enough period that they will be sampled by the slower clock domain. In both directions the timing constraints that must be met are based on the speed of System Clock not the speed of either of the clock domains. The only guarantee between the clock domains is that their edges will always occur on a rising edge of System Clock. That means that the rising edges of the two clock domains can be as close as a single System Clock cycle apart. This is true even when the clock domains are multiples of each other, since their clock dividers are not necessarily aligned. If combinatorial logic exists between the two clock domains, a flip-flop may need to be inserted to keep from limiting the frequency of System Clock operation. By inserting the flip-flop, the crossing from one clock domain to the other is a direct flip-flop to flip-flop path. When the clock domains are unrelated to each other, a synchronizer must be used between the clock domains. The Sync component can be used to implement the synchronization function. It should be clocked by the destination clock domain. The Sync component is implemented using a special mode of the status register that implements a double synchronizer. The input signal must have a pulse width of at least the period of the sampling clock. The exact delay to go through the synchronizer will vary depending on the alignment of the incoming signal to the synchronizing clock. This can vary from just over one clock period to just over two clock periods. If multiple signals are being synchronized, the time difference between two signals entering the synchronizer and those same two signals at the output can change by as much as one clock period, depending on when each is successfully sampled by the synchronizer. Gated Clocks Global clocks should not be used for anything other than directly clocking a circuit. If a global clock is used for logic functionality, the signal is routed using an entirely different path without guaranteed timing. A circuit such as the following should be avoided since timing analysis cannot be performed. This circuit is implemented with a routed clock, has no timing analysis support, and is prone to the generation of glitches on the clock signal when the clock is enabled and disabled. The following circuit implements the equivalent function and is supported by timing analysis, only uses global clocks, and has no reliability issues. This circuit does not gate the clock, but instead logically enables the clocking of new data or maintains the current data. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 27 Clocking If access to a clock is needed, for example to generate a clock to send to a pin, then a 2x clock should be used to clock a toggle flip-flop. The output of that flip-flop can then be used with the associated timing analysis available. Fixed-Function Clocking On the schematic, the clock signals sent to fixed-function peripherals and to UDB-based peripherals appear to be the same clock. However, the timing relationship between the clock signals as they arrive at these different peripheral types is not guaranteed. Additionally the routing delay for the data signals is not guaranteed. Therefore when fixed-function peripherals are connected to signals in the UDB array, the signals must be synchronized as shown in the following example. No timing assumptions should be made about signals coming from fixed-function peripherals. UDB-Based Clocking If the component allows asynchronous clocks, you may use any clock input frequency within the device's frequency range. If the component requires synchronization to the bus clock, then when using a routed clock for the component, the frequency of the routed clock cannot exceed one half the routed clock’s source clock frequency. If the routed clock is synchronous to the bus clock, then it is one half the bus clock. If the routed clock is synchronous to one of the clock dividers, its maximum is one half of that clock rate. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 28 Clocking Changing Clocks in Run-time Impact on Components Operation The components with internal clocks are directly impacted by the change of the system clock frequencies or sources. The components clock frequencies obtained using design-time dividers. The run-time change of components clock source will correspondingly change the internal component clock. Refer to the component datasheet for the details. CyDelay APIs The CyDelay APIs implement simple software-based delay loops. The loops compensate for system clock frequency. The CyDelayFreq() function must be called in order to adjust CyDelay(), CyDelayUs() and CyDelayCycles() functions to the new system clock value. Cache Configuration If the CPU clock frequency increases during device operation, the number of clock cycles cache will wait before sampling data coming back from Flash should be adjusted. If the CPU clock frequency decreases, the number of clock cycles can be also adjusted to improve CPU performance. See CyFlash_SetWaitCycles() function description for more information. Low Voltage Analog Boost Clocks When the operating voltage (Vdda) of a PSoC device drops below 4.0 V, the analog pumps for the analog routing switches must be enabled by calling the SetAnalogRoutingPumps() function with the corresponding parameter. When Vdda rises above 4.0 V, the analog pumps for the analog routing switches must be disabled on PSoC 3/PSoC 5LP devices. It is the user's responsibility to monitor the Vdda level at run-time and enable/disable the pumps as appropriate. The analog pumps for the analog routing switches are configured on device startup based on the Vdda and Variable Vdda design-time options. The Variable Vdda option in the System tab of the PSoC Creator Design-Wide Resources (DWR) file is added to allow for designs in which the value of Vdda is expected to vary at runtime. If Variable Vdda is enabled, the SetAnalogRoutingPumps() function described above will be generated. If Vdda < 4.0 V, the routing pumps will be automatically enabled on reset. Additionally, on PSoC 3/PSoC 5 LP devices, analog positive pumps of the SC-blocks require a boost clock input in order to keep performance within specification when Vdda is below 2.7 V. Between 2.7 V and 4.0 V, the boost is optional and may improve performance. Above 4.0 V, the boost must not be used. If Vdda < 2.7 V or Variable Vdda is selected, a design-wide analog clock resource (ScBoostClk) is created to be used as a boost clock source for analog blocks. This clock is created with a desired frequency of 10 MHz. This means that one of the system clock sources (MASTER_CLK, PLL_OUT, XTAL, etc) should have a value which can produce a 10-12 MHz frequency via an integer divide. In order to ensure that sufficient current is provided to the SC-block by the pump, this value cannot be changed. In previous releases of PSoC Creator, an analog clock resource was silently reserved for every component instance of the requiring the boost (TIA, Mixer, PGA, and PGA_Inv). This means that analog designs would prematurely exhaust available resources when Vdda was low. The design-wide clock allows for optimal resource usage by permitting all SC-block-based components to share a single clock resource. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 29 Clocking Components that are implemented in SC-blocks (TIA, Mixer, PGA, and PGA_Inv) will be initialized based on Vdda and Variable Vdda design-time options. The CySetScPumps() function can be used to enable/disable positive pumps and boost clock at run-time if operating voltage (Vdda) drops below the 2.7 V level. As with the switch pumps, it is the user's responsibility to monitor the Vdda level and call this function as appropriate. The dependency between Vdda and Variable Vdda values configured in the System tab of the PSoC Creator Design-Wide Resources (DWR) file and their impact on design behavior is explained in the following table. Vdda < 2.7 V ≥ 2.7 V ≥ 2.7 V Variable Vdda Routing pumps enabled on reset ScBoostClk clock created (PSoC 3/PSoC 5LP Only) ScBoostClk started on reset (PSoC 3/PSoC 5LP Only) Always Enabled Yes Yes Enabled If Vdda < 4.0 V Yes Disabled If Vdda < 4.0 V No Yes No No Note The previous versions SC-block components (TIA, Mixer, PGA and, and PGA_Inv) will continue to use a dedicated local clock and the new Low Voltage Analog Boost Clocks APIs will not affect those clocks. APIs There is one API used for all devices: the SetAnalogRoutingPumps() function. Then, there is a set of APIs used for PSoC 3 and PSoC 5LP devices. void SetAnalogRoutingPumps(uint8 enabled) Description: Enables or disables the analog pumps feeding analog routing switches. Intended to be called at startup, based on the Vdda system configuration; may be called during operation when the user informs us that the Vdda voltage crossed the pump threshold. Parameters: enabled: • • 1: Enable the pumps. 0: Disable the pumps. Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 30 Clocking uint8 CyPLL_OUT_Start(uint8 wait) Description: Enables the PLL. Optionally waits for it to become stable. Waits at least 250 us or until it is detected that the PLL is stable. Parameters: wait: • • Return Value: Status • • 0: Return immediately after configuration 1: Wait for PLL lock or timeout CYRET_SUCCESS - Completed successfully CYRET_TIMEOUT - Timeout occurred without detecting a stable clock. If the input source of the clock is jittery, then the lock indication may not occur. However, after the timeout has expired the generated PLL clock can still be used. Side Effects and If wait is enabled, this function uses the Fast Time Wheel (FTW) to time the wait. Restrictions: Any other use of the FTW will be stopped during the period of this function and then restored. This function uses the 100 KHz ILO. If the 100 KHz ILO is not enabled, this function will enable it for the duration of this function execution. No changes to the setup of the ILO, FTW, Central Time Wheel (CTW) or Once Per Second interrupt may be made by interrupt routines for the duration of this function execution. The current operation of the ILO, CTW and Once Per Second interrupt are maintained during the operation of this function, provided the reading of the Power Manager Interrupt Status Register is only done using the CyPmReadStatus() function. void CyPLL_OUT_Stop() Description: Disables the PLL. Parameters: None Return Value: None void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) Description: Sets the P and Q dividers and the charge pump current. The Frequency Out will be P/Q * Frequency In. The PLL must be disabled before calling this function. Parameters: P: Valid range [8 - 255] Q: Valid range [1 - 16]. Input Frequency / Q must be in the range of 1 MHz to 3 MHz. current: Valid range [1 - 7]. Charge pump current in uA. Refer to the device TRM and datasheet for more information. Return Value: None Side Effects and If the CPU clock frequency increases during device operation, call Restrictions: CyFlash_SetWaitCycles() with the appropriate parameter to adjust the number of clock cycles cache will wait before sampling data coming back from Flash. If the CPU clock frequency decreases, you can call CyFlash_SetWaitCycles() to improve CPU performance. See "CyFlash_SetWaitCycles()" for more information. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 31 Clocking void CyPLL_OUT_SetSource(uint8 source) Description: Sets the input clock source to the PLL. The PLL must be disabled before calling this function. Parameters: source: One of the three available PLL clock sources Define Source CY_PLL_SOURCE_IMO CY_PLL_SOURCE_XTAL CY_PLL_SOURCE_DSI IMO MHz Crystal DSI Return Value: None Side Effects and If the CPU clock frequency increases during device operation, call Restrictions: CyFlash_SetWaitCycles() with the appropriate parameter to adjust the number of clock cycles cache will wait before sampling data coming back from Flash. If the CPU clock frequency decreases, you can call CyFlash_SetWaitCycles() to improve CPU performance. See "CyFlash_SetWaitCycles()" for more information. void CyIMO_Start(uint8 wait) Description: Enables the IMO. Optionally waits at least 6us for it to settle. Parameters: wait: • • 0: Return immediately after configuration 1: Wait for at least 6us for the IMO to settle Return Value: None Side Effects and If wait is enabled, this function uses the FTW to time the wait. Any other use of Restrictions: the FTW will be stopped during the period of this function and then restored. This function uses the 100 KHz ILO. If the 100 KHz ILO is not enabled, this function will enable it for the duration of this function execution. No changes to the setup of the ILO, FTW, CTW, or Once Per Second interrupt may be made by interrupt routines for the duration of this function execution. The current operation of the ILO, CTW, and Once Per Second interrupt are maintained during the operation of this function, provided the reading of the Power Manager Interrupt Status Register is only done using the CyPmReadStatus() function. void CyIMO_Stop() Description: Disables the IMO. Parameters: None Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 32 Clocking void CyIMO_SetFreq(uint8 freq) Description: Sets the frequency of the IMO. Changes may be made while the IMO is running. Parameters: freq: Frequency of IMO operation Return Value: Define Frequency CY_IMO_FREQ_3MHZ CY_IMO_FREQ_6MHZ CY_IMO_FREQ_12MHZ CY_IMO_FREQ_24MHZ CY_IMO_FREQ_48MHZ CY_IMO_FREQ_62MHZ CY_IMO_FREQ_74MHZ CY_IMO_FREQ_USB 3 MHz 6 MHz 12 MHz 24 MHz 48 MHz 62.6 MHz 74.7 MHz 24 MHz (Trimmed for USB operation) None Side Effects and If the CPU clock frequency increases during device operation, call Restrictions: CyFlash_SetWaitCycles() with the appropriate parameter to adjust the number of clock cycles cache will wait before sampling data coming back from Flash. If the CPU clock frequency decreases, you can call CyFlash_SetWaitCycles() to improve CPU performance. See "CyFlash_SetWaitCycles()" for more information. When the USB setting is chosen, the USB clock locking circuit is enabled. Otherwise this circuit is disabled. The USB block must be powered before selecting the USB setting. void CyIMO_SetSource(uint8 source) Description: Sets the source of the clock output from the IMO block. The output from the IMO is by default the IMO itself. Optionally the MHz Crystal or a DSI input can be the source of the IMO output instead. Parameters: source: One of the three available IMO output sources Define Source CY_IMO_SOURCE_IMO CY_IMO_SOURCE_XTAL CY_IMO_SOURCE_DSI IMO MHz Crystal DSI Return Value: None Side Effects and If the CPU clock frequency increases during device operation, call Restrictions: CyFlash_SetWaitCycles() with the appropriate parameter to adjust the number of clock cycles cache will wait before sampling data coming back from Flash. If the CPU clock frequency decreases, you can call CyFlash_SetWaitCycles() to improve CPU performance. See "CyFlash_SetWaitCycles()" for more information. void CyIMO_EnableDoubler() Description: Enables the IMO doubler. The 2x frequency clock is used to convert a 24 MHz input to a 48 MHz output for use by the USB block. Parameters: None Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 33 Clocking void CyIMO_DisableDoubler() Description: Disables the IMO doubler. Parameters: None Return Value: None void CyBusClk_SetDivider(uint16 divider) Description: Sets the divider value used to generate Bus Clock. Parameters: divider: Valid range [0-65535]. The clock will be divided by this value + 1. For example to divide by 2 this parameter should be set to 1. Return Value: None Side Effects and If the CPU clock frequency increases during device operation, call Restrictions: CyFlash_SetWaitCycles() with the appropriate parameter to adjust the number of clock cycles cache will wait before sampling data coming back from Flash. If the CPU clock frequency decreases, you can call CyFlash_SetWaitCycles() to improve CPU performance. See "CyFlash_SetWaitCycles()" for more information. void CyCpuClk_SetDivider(uint8 divider) Description: Sets the divider value used to generate the CPU Clock. Applies to PSoC 3 only. Parameters: divider: Valid range [0-15]. The clock will be divided by this value + 1. For example to divide by 2 this parameter should be set to 1. Return Value: None Side Effects and If the CPU clock frequency increases during device operation, call Restrictions: CyFlash_SetWaitCycles() with the appropriate parameter to adjust the number of clock cycles cache will wait before sampling data coming back from Flash. If the CPU clock frequency decreases, you can call CyFlash_SetWaitCycles() to improve CPU performance. See "CyFlash_SetWaitCycles()" for more information. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 34 Clocking void CyMasterClk_SetSource(uint8 source) Description: Sets the source of the master clock. Parameters: source: One of the four available Master clock sources Define Source CY_MASTER_SOURCE_IMO CY_MASTER_SOURCE_PLL CY_MASTER_SOURCE_XTAL CY_MASTER_SOURCE_DSI IMO PLL MHz Crystal DSI Return Value: None Side Effects and The current source and the new source must both be running and stable before Restrictions: calling this function. If the CPU clock frequency increases during device operation, call CyFlash_SetWaitCycles() with the appropriate parameter to adjust the number of clock cycles cache will wait before sampling data coming back from Flash. If the CPU clock frequency decreases, you can call CyFlash_SetWaitCycles() to improve CPU performance. See "CyFlash_SetWaitCycles()" for more information. void CyMasterClk_SetDivider(uint8 divider) Description: Sets the divider value used to generate Master Clock. Parameters: divider: Valid range [0-255]. The clock will be divided by this value + 1. For example to divide by 2 this parameter should be set to 1. Return Value: None Side Effects and When changing the Master or Bus Clock divider value from div-by-n to div-by-1, Restrictions: the first clock cycle output after the div-by-1 can be up to 4 ns shorter than the final/expected div-by-1 period. If the CPU clock frequency increases during device operation, call CyFlash_SetWaitCycles() with the appropriate parameter to adjust the number of clock cycles cache will wait before sampling data coming back from Flash. If the CPU clock frequency decreases, you can call CyFlash_SetWaitCycles() to improve CPU performance. See "CyFlash_SetWaitCycles()" for more information. void CyUsbClk_SetSource(uint8 source) Description: Sets the source of the USB clock. Parameters: source: One of the four available USB clock sources Define Source CY_USB_SOURCE_IMO2X CY_USB_SOURCE_IMO CY_USB_SOURCE_PLL CY_USB_SOURCE_DSI IMO 2x IMO PLL DSI Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 35 Clocking void CyILO_Start1K() Description: Enables the ILO 1 KHz oscillator. Note The ILO 1 KHz oscillator is always enabled by default, regardless of the selection in the Clock Editor. Therefore, this API is only needed if the oscillator was turned off manually. Parameters: None Return Value: None void CyILO_Stop1K() Description: Disables the ILO 1 KHz oscillator. Note The ILO 1 KHz oscillator must be enabled if Sleep or Hibernate low power mode APIs are expected to be used. For more information, refer to the Power Management section of this document. Parameters: None Return Value: None void CyILO_Start100K() Description: Enables the ILO 100 KHz oscillator. Parameters: None Return Value: None void CyILO_Stop100K() Description: Disables the ILO 100 KHz oscillator. Parameters: None Return Value: None void CyILO_Enable33K() Description: Enables the ILO 33 KHz divider. Note The 33 KHz clock is generated from the 100 KHz oscillator, so it must also be running in order to generate the 33 KHz output. Parameters: None Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 36 Clocking void CyILO_Disable33K() Description: Disables the ILO 33 KHz divider. Note that the 33 KHz clock is generated from the 100 KHz oscillator, but this API does not disable the 100 KHz clock. Parameters: None Return Value: None void CyILO_SetSource(uint8 source) Description: Sets the source of the clock output from the ILO block. Parameters: source: One of the three available ILO output sources Define Source CY_ILO_SOURCE_100K CY_ILO_SOURCE_33K CY_ILO_SOURCE_1K ILO 100 KHz ILO 33 KHz ILO 1 KHz Return Value: None uint8 CyILO_SetPowerMode(uint8 mode) Description: Sets the power mode used by the ILO during power down. Allows for lower power down power usage resulting in a slower startup time. Parameters: mode: Define Description CY_ILO_FAST_START Faster start-up, internal bias left on when powered down. Slower start-up, internal bias off when powered down. CY_ILO_SLOW_START Return Value: Previous power mode ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 37 Clocking uint8 CyXTAL_Start(uint8 wait) Description: Enables the MHz crystal. Waits until the XERR bit is low (no error) for a millisecond or until the number of milliseconds specified by the wait parameter has expired. Parameters: wait: Valid range [0-255]. This is the timeout value in milliseconds. The appropriate value is crystal specific. Return Value: Status CYRET_SUCCESS - Completed successfully CYRET_TIMEOUT - Timeout occurred without detecting a low value on XERR. Side Effects and If wait is enabled (non-zero wait), this function uses the FTW to time the wait. Any Restrictions: other use of the FTW will be stopped during the period of this function and then restored. This function also uses the 100 KHz ILO. If the 100 KHz is not enabled, this function will enable it for the duration of this function execution. No changes to the setup of the ILO, FTW, CTW, or Once Per Second interrupt may be made by interrupt routines for the duration of this function execution. The current operation of the ILO, CTW, and Once Per Second interrupt are maintained during the operation of this function provided the reading of the Power Manager Interrupt Status Register is only done using the CyPmReadStatus() function. void CyXTAL_Stop() Description: Disables the megahertz crystal oscillator. Parameters: None Return Value: None void CyXTAL_EnableErrStatus() Description: Enables the generation of the XERR status bit for the megahertz crystal. Parameters: None Return Value: None void CyXTAL_DisableErrStatus() Description: Disables the generation of the XERR status bit for the megahertz crystal. Parameters: None Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 38 Clocking uint8 CyXTAL_ReadStatus() Description: Reads the XERR status bit for the megahertz crystal. This status bit is a sticky clear on read value. Parameters: None Return Value: Status: 0: No error, 1: Error void CyXTAL_EnableFaultRecovery() Description: Enables the fault recovery circuit which will switch to the IMO in the case of a fault in the megahertz crystal circuit. The crystal must be up and running with the XERR bit at 0, before calling this function to prevent immediate fault switchover. Parameters: None Return Value: None void CyXTAL_DisableFaultRecovery() Description: Disables the fault recovery circuit which will switch to the IMO in the case of a fault in the megahertz crystal circuit. Parameters: None Return Value: None void CyXTAL_SetStartup(uint8 setting) Description: Sets the startup settings for the crystal. Parameters: setting: Valid range [0-31]. Value is dependent on the frequency and quality of the crystal being used. Refer to the device TRM and datasheet for more information. Return Value: None void CyXTAL_SetFbVoltage(uint8 setting) Description: Sets the feedback reference voltage to use for the crystal circuit. Parameters: setting: Valid range [0-15]. Refer to the device TRM and datasheet for more information. Return Value: None Side Effects and The feedback reference voltage must be greater than the watchdog reference Restrictions: voltage. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 39 Clocking void CyXTAL_SetWdVoltage(uint8 setting) Description: Sets the reference voltage used by the watchdog to detect a failure in the crystal circuit. Parameters: setting: Valid range [0-7]. Refer to the device TRM and datasheet for more information. Return Value: None Side Effects and The feedback reference voltage must be greater than the watchdog reference Restrictions: voltage. void CyXTAL_32KHZ_Start() Description: Enables the 32 KHz Crystal Oscillator. Parameters: None Return Value: None void CyXTAL_32KHZ_Stop() Description: Disables the 32 KHz Crystal Oscillator. Parameters: None Return Value: None uint8 CyXTAL_32KHZ_ReadStatus() Description: Reads the two status bits for the 32 KHz oscillator. Parameters: None Return Value: Status Define Source CY_XTAL32K_ANA_STAT Analog measurement 1: Stable 0: Not stable uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) Description: Sets the power mode for the 32 KHz oscillator used during sleep mode. Allows for lower power during sleep when there are fewer sources of noise. During active mode the oscillator is always run in high power mode. Parameters: mode: • • 0: High power mode 1: Low power mode during sleep Return Value: Previous power mode ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 40 Clocking void CySetScPumps(uint8 enable) Description: Starts/stops analog boost clock and configures SC-blocks positive pumps. Parameters: enable: • • 1: Starts analog boost clock and enables positive pumps. 0: Disables positive pumps for enabled SC-blocks and stops analog boost clock if all SC-blocks are disabled. Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 41 4 Power Management There is a full range of power modes supported by PSoC devices to control power consumption and the amount of available resources. See the following table for the supported power modes. Table 1. Power modes Architecture PSoC 3 / PSoC 5LP Family Active Alternate Active Sleep Deep Sleep Hibernate Stop All PSoC 3/PSoC 5LP devices support the following power modes (in order of high to low power consumption): Active, Alternate Active, Sleep, and Hibernate. For the ARM-based devices (PSoC 5LP), an interrupt is required for the CPU to wake up. The Power Management implementation assumes that wakeup time is configured with a separate component (component-based wakeup time configuration) for an interrupt to be issued on terminal count. For more information, refer to the "Wakeup Time Configuration" section. All pending interrupts should be cleared before the device is put into low power mode, even if they are masked. The Power Management API is provided in the CyPm.c and CyPm.h files. Implementation Low Power Usage PSoC 5 devices will not go into low power modes while the debugger is running. For PSoC 3/PSoC 5LP devices, the power manager will not put the device into a low power state if the system performance controller (SPC) is executing a command. The device will go into low power mode after the SPC completes command execution. The SPC is used by Flash API, EEPROM and DieTemp components. Please refer to the corresponding component datasheet for the more information. Clock Configuration There are a few device configuration requirements for proper low power mode entry and wakeup. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 42 Power Management The clock system should be prepared before entering Sleep and Hibernate mode to ensure that it will switch between Active modes and low power modes as expected. The CyPmSaveClocks() and CyPmRestoreClocks() functions are responsible for preparing clock configuration before entering low power mode and after waking up to Active mode, respectively. In general, CyPmSaveClocks() saves the configuration and sets the requirements for low power mode entry. CyPmRestoreClocks() restores the clock configuration to its original state. The IMO is required to be the source for the Master clock. So, the IMO clock value is set corresponding to the "Enable Fast IMO During Startup" option on the Design-Wide Resources System Editor. If this option is enabled, the IMO clock frequency is set to 48 MHz; otherwise, is set to 12 MHz. Note The IMO value must be 12 MHz just before entering Sleep and Hibernate modes. The IMO frequency is set to 12 MHz by CyPmSleep()/CyPmHibernate() just before entering the specified low power mode (without correcting the number of wait cycles for the flash). The IMO frequency is restored immediately on wakeup. The PLL and MHz ECO are turned off once the Master clock is sourced by IMO. The Bus and Master clock dividers are set to a divide-by-one value and the new value of flash wait cycles is set to match the new value of the CPU frequency. Refer to the description of the CyFlash_SetWaitCycles() function for more information. The 1 KHz ILO must be enabled (it is always enabled by default, regardless of the selection in the Clock Editor) for all devices for correct operation in Sleep and Hibernate low power modes. It is used to measure the Hibernate/Sleep regulator settling time after a reset. During this time, the system ignores requests to enter these modes. The hold-off delay is measured using rising edges of the 1 kHz ILO. The terminal count is set by the Sleep Regulator Trim Register (PWRSYS_SLP_TR). Caution Do not modify this register. Refer to the corresponding device Registers TRM for more information. The 32.768-kHz external crystal oscillator (32kHzECO) provides precision timing with minimal power consumption using an external 32.768-kHz watch crystal. The oscillator’s power mode during device’s Sleep mode configured by the CyXTAL_32KHZ_SetPowerMode() function. By default, oscillator runs in the high power mode. Calling the CyPmSaveClocks() function will modify device clocking configuration. As a result, any component that relies on clocking should not be used until calling the CyPmRestoreClocks() function, which will restore the original clocking configuration. For information on component clocking requirements, refer to the corresponding component datasheet. Wakeup Time Configuration There are three timers that can wake up a device from low power mode: CTW, FTW, and one pulse per second (One PPS). Refer to the device TRM and datasheet for more information on these timers. There are two ways of configuring wakeup time: Parameter-based wakeup time configuration is done by calling the CyPmSleep() and CyPmAltAct() functions with desired parameters. This configuration method is available only for the PSoC 3 devices. Component-based wakeup time configuration. The CTW wakeup interval is configured with the Sleep Timer component. The one second interval is configured with the RTC component. There is no wakeup time configuration available for the Hibernate mode. It is important to keep in mind that it is only guaranteed that the first CTW and FTW intervals will be less than specified. To make subsequent intervals to have nominal values, the corresponding timer is enabled ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 43 Power Management by the CyPmSleep() and CyPmAltAct() functions, and the timer left enabled. Note that some APIs can also use this timer. This can cause the timer to always be enabled (the timer interval can be changed only if the corresponding timer is disabled) before low power mode entry and hence the wakeup interval will always be less than expected. The CyPmReadStatus() function must be called just after wakeup with a corresponding parameter (for example, with CY_PM_CTW_INT if the device is configured to wake up on CTW) to clear interrupt status bits. When CTW is used as a wakeup timer, the CyPmReadStatus() function must always be called (when wakeup is configured in a parameter or component based method) after wakeup to clear the CTW interrupt status bit. It is required for this function to be called within 1 ms (1 clock cycle of the ILO) after the CTW event occurred. Wakeup Source Configuration You can configure which wakeup source may wake up the device from Alternate Active and Sleep low power modes. The source is not configured to wake up the device; it just allows doing that. The component associated with the wakeup source has to be properly configured to act as a wakeup source. For PSoC 5LP devices, the interrupts associated with wakeup sources must also be enabled to also wake up the CPU. PSoC 3 Alternate Active Mode Specific Issues Any interrupt, whether it is enabled at the interrupt controller or not, will wake the device from Alternate Active power mode. The edge detector is also bypassed, so the wakeup source is always level triggered. Directly connected DMA interrupts will not wake from this mode. They must be routed through the DSI in order to generate a wakeup condition. PSoC 5LP Specific Issues For PSoC 5LP, the wakeup source is available for Sleep mode and is not available for Alternate Active mode. In the case of Alternate Active mode, the wakeup source argument is ignored and any of the available sources will wake the device. For PSoC 5LP, the interrupt component connected to the wakeup source may not use the "RISING_EDGE" detect option. Use the "LEVEL" option instead. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 44 Power Management Power Management APIs void CyPmSaveClocks() Description: This function is called in preparation for entering sleep or hibernate low power modes. Saves all state of the clocking system that doesn’t persist during sleep/hibernate or that needs to be altered in preparation for sleep/hibernate. Shuts down all the digital and analog clock dividers for the active power mode configuration. Switches the master clock over to the IMO and shuts down the PLL and MHz Crystal. The IMO frequency is set to either 12 MHz or 48 MHz to match the Design-Wide Resources System Editor "Enable Fast IMO During Startup" setting. The ILO and 32 KHz oscillators are not impacted. The current Flash wait state setting is saved and the Flash wait state setting is set for the current IMO speed. Note If the Master Clock source is routed through the DSI inputs, then it must be set manually to another source before using the CyPmSaveClocks() / CyPmRestoreClocks() functions. Parameters: None Return Value: None Side Effects and All peripheral clocks will be off after this API method call. Restrictions: void CyPmRestoreClocks() Description: Restores any state that was preserved by the last call to CyPmSaveClocks. The Flash wait state setting is also restored. Note If the Master Clock source is routed through the DSI inputs, then it must be set manually to another source before using the CyPmSaveClocks() / CyPmRestoreClocks() functions. The merge region could be used to process state when the megahertz crystal is not ready after the hold-off timeout. Parameters: None Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 45 Power Management void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) Description: Puts the part into the Alternate Active (Standby) state. The Alternate Active state can allow for any of the capabilities of the device to be active, but the operation of this function is dependent on the CPU being disabled during the Alternate Active state. The configuration code and the component APIs will configure the template for the Alternate Active state to be the same as the Active state with the exception that the CPU will be disabled during Alternate Active. Note Before calling this function, you must manually configure the power mode of the source clocks for the timer that is used as the wakeup timer. PSoC 3: Before switching to Alternate Active, if a wakeupTime other than NONE is specified, then the appropriate timer state is configured as specified with the interrupt for that timer disabled. The wakeup source will be the combination of the values specified in the wakeupSource and any timer specified in the wakeupTime argument. Once the wakeup condition is satisfied, then all saved state is restored and the function returns in the Active state. Note If the wakeupTime is made with a different value, the period before the wakeup occurs can be significantly shorter than the specified time. If the next call is made with the same wakeupTime value, then the wakeup will occur the specified period after the previous wakeup occurred. If a wakeupTime other than NONE is specified, then upon exit the state of the specified timer will be left as specified by wakeupTime with the timer enabled and the interrupt disabled. If the CTW, FTW or One PPS is already configured for wakeup, for example with the Sleep Timer or RTC components, then specify NONE for the wakeupTime and include the appropriate source for wakeupSource. PSoC 5LP: Neither parameter is used. That means NONE should be passed for the parameters. The device will go into Alternate Active mode until an enabled interrupt occurs. Parameters: wakeupTime: Specifies a timer wakeup source and the frequency of that source. For PSoC 5LP this parameter is ignored. Define PM_ALT_ACT_TIME_NONE PM_ALT_ACT_TIME_ONE_PPS PM_ALT_ACT_TIME_CTW_2MS PM_ALT_ACT_TIME_CTW_4MS PM_ALT_ACT_TIME_CTW_8MS PM_ALT_ACT_TIME_CTW_16MS PM_ALT_ACT_TIME_CTW_32MS PM_ALT_ACT_TIME_CTW_64MS PM_ALT_ACT_TIME_CTW_128MS PM_ALT_ACT_TIME_CTW_256MS PM_ALT_ACT_TIME_CTW_512MS PM_ALT_ACT_TIME_CTW_1024MS PM_ALT_ACT_TIME_CTW_2048MS PM_ALT_ACT_TIME_CTW_4096MS PM_ALT_ACT_TIME_FTW(1-256) Time None One PPS: 1 second CTW: 2 ms CTW: 4 ms CTW: 8 ms CTW: 16 ms CTW: 32 ms CTW: 64 ms CTW: 128 ms CTW: 256 ms CTW: 512 ms CTW: 1024 ms CTW: 2048 ms CTW: 4096 ms FTW: 10 µs to 2.56 ms The PM_ALT_ACT_TIME_FTW() macro takes an argument that specifies how many increments of 10 µs to delay. For PSoC 3 silicon the valid range of values is 1 to 256. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 46 Power Management CyPmAltAct (Continued) Parameters: wakeupSource: Specifies a bitwise mask of wakeup sources. In addition, if a wakeupTime has been specified, the associated timer will be included as a wakeup source. The wakeup source configuration is restored before function exit. For PSoC 5LP this parameter is ignored. Define Source PM_ALT_ACT_SRC_NONE PM_ALT_ACT_SRC_COMPARATOR0 PM_ALT_ACT_SRC_COMPARATOR1 PM_ALT_ACT_SRC_COMPARATOR2 PM_ALT_ACT_SRC_COMPARATOR3 PM_ALT_ACT_SRC_INTERRUPT PM_ALT_ACT_SRC_PICU PM_ALT_ACT_SRC_I2C PM_ALT_ACT_SRC_BOOSTCONVERTER PM_ALT_ACT_SRC_FTW PM_ALT_ACT_SRC_VD None Comparator 0 Comparator 1 Comparator 2 Comparator 3 Interrupt PICU I2C Boost Converter Fast Time Wheel High and Low Voltage Detection Central Time Wheel One PPS LCD PM_ALT_ACT_SRC_CTW PM_ALT_ACT_SRC_ONE_PPS PM_ALT_ACT_SRC_LCD Note CTW and One PPS wakeup signals are in the same mask bit. FTW and Low Voltage Interrupt (LVI)/High Voltage Interrupt (HVI) wakeup signals are in the same mask bit. When specifying a Comparator as the wakeupSource, use an instance specific define that will track with the specific comparator for that instance. As an example, for a Comparator instance named "MyComp" the value to OR into the mask is: MyComp_ctComp__CMP_MASK. When CTW, FTW, or One PPS is used as a wakeup source, the CyPmReadStatus function must be called upon wakeup, with the corresponding parameter. Refer to the CyPmReadStatus API for more information. Return Value: None Side Effects and For PSoC 5LP, the wakeup source is not selectable. In this case the Restrictions: wakeupSource argument is ignored and any of the available wakeup sources will wake the device. If a wakeupTime other than NONE is specified, then upon exit the state of the specified timer will be left as specified by wakeupTime with the timer enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is used as wakeup time) or ILO 100 KHz (if FTW timer is used as wakeup time) will be left started. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 47 Power Management void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) Description: Puts the part into the Sleep state. Note Before calling this function, you must manually configure the power mode of the source clocks for the timer that is used as wakeup timer. Note Before calling this function, you must prepare clock tree configuration for the low power mode by calling CyPmSaveClocks(). And restore clock configuration after CyPmSleep() execution by calling CyPmRestoreClocks(). See Power Management section, Clock Configuration subsection of the System Reference Guide for more information. PSoC 3: Before switching to Sleep, if a wakeupTime other than NONE is specified, then the appropriate timer state is configured as specified with the interrupt for that timer disabled. The wakeup source will be the combination of the values specified in the wakeupSource and any timer specified in the wakeupTime argument. Once the wakeup condition is satisfied, then all saved state is restored and the function returns in the Active state. Note If the wakeupTime value is different from the previous value, the period before the wakeup occurs can be significantly shorter than the specified time. If the next call is made with the same wakeupTime value, then the wakeup will occur with the specified period after the previous wakeup occurred. If a wakeupTime other than NONE is specified, then upon exit the state of the specified timer will be left as specified by wakeupTime with the timer enabled and the interrupt disabled. If the CTW or One PPS is already configured for wakeup, for example with the Sleep Timer or RTC components, then specify NONE for the wakeupTime and include the appropriate source for wakeupSource. PSoC 5LP: The wakeupTime parameter is not used and the only NONE can be specified. The wakeup time must be configured with the component, Sleep Timer for CTW intervals and RTC for 1PPS interval. The component must be configured to generate an interrupt. Parameters: wakeupTime: Specifies a timer wakeup source and the frequency of that source. For PSoC 5LP, this parameter is ignored. Define Time PM_SLEEP_TIME_NONE PM_SLEEP_TIME_ONE_PPS PM_SLEEP_TIME_CTW_2MS PM_SLEEP_TIME_CTW_4MS PM_SLEEP_TIME_CTW_8MS PM_SLEEP_TIME_CTW_16MS PM_SLEEP_TIME_CTW_32MS PM_SLEEP_TIME_CTW_64MS PM_SLEEP_TIME_CTW_128MS PM_SLEEP_TIME_CTW_256MS PM_SLEEP_TIME_CTW_512MS PM_SLEEP_TIME_CTW_1024MS PM_SLEEP_TIME_CTW_2048MS PM_SLEEP_TIME_CTW_4096MS None One PPS: 1 second CTW: 2 ms CTW: 4 ms CTW: 8 ms CTW: 16 ms CTW: 32 ms CTW: 64 ms CTW: 128 ms CTW: 256 ms CTW: 512 ms CTW: 1024 ms CTW: 2048 ms CTW: 4096 ms ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 48 Power Management CyPmSleep (Continued) Parameters: wakeupSource: Specifies a bitwise mask of wakeup sources. In addition, if a wakeupTime has been specified, the associated timer will be included as a wakeup source. The wakeup source configuration is restored before function exit. Define Source PM_SLEEP_SRC_NONE PM_SLEEP_SRC_COMPARATOR0 PM_SLEEP_SRC_COMPARATOR1 PM_SLEEP_SRC_COMPARATOR2 PM_SLEEP_SRC_COMPARATOR3 PM_SLEEP_SRC_PICU PM_SLEEP_SRC_I2C PM_SLEEP_SRC_BOOSTCONVERTER PM_SLEEP_SRC_VD None Comparator 0 Comparator 1 Comparator 2 Comparator 3 PICU I2C Boost Converter High and Low Voltage Detection Central Time Wheel One PPS LCD PM_SLEEP_SRC_CTW PM_SLEEP_SRC_ONE_PPS PM_SLEEP_SRC_LCD Note CTW and One PPS wakeup signals are in the same mask bit. When specifying a Comparator as the wakeupSource, use an instance specific define that will track with the specific comparator for that instance. As an example for a Comparator instance named "MyComp" the value to OR into the mask is: MyComp_ctComp__CMP_MASK. When CTW or One PPS is used as a wakeup source, the CyPmReadStatus function must be called upon wakeup, with the corresponding parameter. Refer to the CyPmReadStatus API for more information. Return Value: None Side Effects and If a wakeupTime other than NONE is specified, then upon exit the state of the Restrictions: specified timer will be left as specified by wakeupTime with the timer enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is used as wake up time) will be left started. The 1 kHz ILO clock is expected to be enabled to measure Hibernate/Sleep regulator settling time after a reset. The hold-off delay is measured using rising edges of the 1 kHz ILO. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 49 Power Management void CyPmHibernate() Description: Puts the part into the Hibernate state. Before switching to Hibernate, the current status of the PICU wakeup source bit is saved and then set. This configures the device to wake up from the PICU. Make sure you have at least one pin configured to generate a PICU interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]." In the Pins component datasheet, this register is referred to as the IRQ option. Once the wakeup occurs, the PICU wakeup source bit is restored and the PSoC returns to the Active state. Parameters: None Return Value: None Side Effects and Applications must wait 20 µs before re-entering hibernate or sleep after waking Restrictions: up from hibernate. The 20 µs allows the sleep regulator time to stabilize before the next hibernate / sleep event occurs. The 20 µs requirement begins when the device wakes up. There is no hardware check that this requirement is met. The specified delay should be done on ISR entry. After wakeup PICU interrupt occurs, the Pin_ClearInterrupt() function (where "Pin" is the instance name of the Pins component) must be called to clear the latched pin events. This allows proper Hibernate mode entry and enables detection of future events. The 1 kHz ILO clock is expected to be enabled to measure Hibernate/Sleep regulator settling time after a reset. The hold-off delay is measured using rising edges of the 1 kHz ILO. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 50 Power Management void CyPmHibernateEx(uint16 wakeupSource) Description: Puts the part into the Hibernate state. The following wake up sources can be configured: PICU interrupt, Comparator0, Comparator1, Comparator2, and Comparator3 output. Before switching to Hibernate, the current status of the wakeup source bit is saved and then set. This configures the device to wake up from the particular interrupt. If using PICU as the wake up source, make sure you have at least one pin configured to generate a PICU interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]." In the Pins component datasheet, this register is referred to as the IRQ option. Once the wakeup occurs, the PICU wakeup source bit is restored and the PSoC returns to the Active state. If using a comparator as the wake up source, make sure you call this function with the 'wakeupSource' parameter set to the appropriate comparator. The part is configured for the requested wakeup source by setting the corresponding bits in PM_WAKEUP_CFG1 register. Function call CyPmHibernateEx(CY_PM_HIB_SRC_PICU) will act in the same way as CyPmHibernate(). Parameters: wakeupSource: Parameter Value Description CY_PM_HIB_SRC_PICU CY_PM_HIB_SRC_COMPARATOR0 CY_PM_HIB_SRC_COMPARATOR1 CY_PM_HIB_SRC_COMPARATOR2 CY_PM_HIB_SRC_COMPARATOR3 PICU interrupt is set as the wake up source Comparator 0 is set as the wake up source Comparator 1 is set as the wake up source Comparator 2 is set as the wake up source Comparator 3 is set as the wake up source Return Value: None Side Effects and Applications must wait 20 µs before re-entering hibernate or sleep after waking Restrictions: up from hibernate. The 20 µs allows the sleep regulator time to stabilize before the next hibernate / sleep event occurs. The 20 µs requirement begins when the device wakes up. There is no hardware check that this requirement is met. The specified delay should be done on ISR entry. After wakeup PICU interrupt occurs, the Pin_ClearInterrupt() function (where "Pin" is the instance name of the Pins component) must be called to clear the latched pin events. This allows proper Hibernate mode entry and enables detection of future events. The 1 kHz ILO clock is expected to be enabled to measure Hibernate/Sleep regulator settling time after a reset. The hold-off delay is measured using rising edges of the 1 kHz ILO. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 51 Power Management uint8 CyPmReadStatus(uint8 mask) Description: Manages the Power Manager Interrupt Status Register. This register has the interrupt status for the one pulse per second, CTW, and FTW timers. This hardware register clears on read. To allow for only clearing the bits of interest and preserving the other bits, this function uses a shadow register that retains the state. This function reads the status register and ORs that value with the shadow register. That is the value that is returned. Then the bits in the mask that are set are cleared from this value and written back to the shadow register. Note You must call this function within 1 ms (1 clock cycle of the ILO) after a CTW event has occurred. Parameters: mask: Bits in the shadow register to clear Define Source CY_PM_FTW_INT CY_PM_CTW_INT CY_PM_ONEPPS_INT Fast Time Wheel Central Time Wheel One Pulse Per Second Return Value: Status. Same enumerated bit values as used for the mask parameter. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 52 5 Interrupts The APIs in this chapter apply to all architectures except as noted. The Interrupts API is provided in the CyLib.c and CyLib.h files. Refer also to the Interrupt component datasheet for more information about interrupts. Note For PSoC 3, Keil C compiler run-time libraries do not disable interrupts. The only exception is found in the C51 run-time library when using large reentrant functions. Interrupts are disabled for 4 CPU instructions (8 CPU cycles) to adjust the large reentrant stack. APIs CyGlobalIntEnable Description: Macro statement that enables interrupts using the global interrupt mask. CyGlobalIntDisable Description: Macro statement that disables interrupts using the global interrupt mask. uint32 CyDisableInts() Description: Disables all interrupts. Parameters: None Return Value: 32-bit mask of interrupts previously enabled void CyEnableInts(uint32 mask) Description: Enables all interrupts specified in the 32-bit mask. Parameters: mask: 32-bit mask of interrupts to enable Return Value: None Note Interrupt service routines must follow the policy that they restore the CYDEV_INTC_CSR_EN register bits and interrupt enable state (EA) to the way they were found on entry. The ISR does not need to do anything special as long as it uses properly nested CyEnterCriticalSection() and CyExitCriticalSection() function calls. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 53 Interrupts void CyIntEnable(uint8 number) Description: Enables the specified interrupt number. Parameters: number: Interrupt number. Valid range: [0-31] Return Value: None Note Interrupt service routines must follow the policy that they restore the CYDEV_INTC_CSR_EN register bits and interrupt enable state (EA) to the way they were found on entry. The ISR does not need to do anything special as long as it uses properly nested CyEnterCriticalSection() and CyExitCriticalSection() function calls. void CyIntDisable(uint8 number) Description: Disables the specified interrupt number. Parameters: number: Interrupt number. Valid range: [0-31] Return Value: None Note Interrupt service routines must follow the policy that they restore the CYDEV_INTC_CSR_EN register bits and interrupt enable state (EA) to the way they were found on entry. The ISR does not need to do anything special as long as it uses properly nested CyEnterCriticalSection() and CyExitCriticalSection() function calls. uint8 CyIntGetState(uint8 number) Description: Gets the enable state of the specified interrupt number. Parameters: number: Interrupt number. Valid range: [0-31] Return Value: Enable status: 1 if enabled, 0 if disabled cyisraddress CyIntSetVector(uint8 number, cyisraddress address) Description: Sets the interrupt vector of the specified interrupt number. Parameters: number: Interrupt number. Valid range: [0-31] address: Pointer to an interrupt service routine Return Value: Previous interrupt vector value cyisraddress CyIntGetVector(uint8 number) Description: Gets the interrupt vector of the specified interrupt number. Parameters: number: Interrupt number. Valid range: [0-31] Return Value: Interrupt vector value ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 54 Interrupts cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) Description: This function applies to ARM based processors only and therefore does not apply to the PSoC 3 device. It sets the interrupt vector of the specified exception. These exceptions in the ARM architecture operate similar to user interrupts, but are specified by the system architecture of the processor. The number of each exception is fixed. Note that the numbering of these exceptions is separate from the numbering used for user interrupts. Parameters: number: Exception number. Valid range: [0-15]. Define Exception Number CY_INT_NMI_IRQN CY_INT_HARD_FAULT_IRQN CY_INT_MEM_MANAGE_IRQN CY_INT_BUS_FAULT_IRQN CY_INT_USAGE_FAULT_IRQN CY_INT_SVCALL_IRQN CY_INT_DEBUG_MONITOR_IRQN CY_INT_PEND_SV_IRQN CY_INT_SYSTICK_IRQN Non Maskable Interrupt. Hard Fault Interrupt. Memory Management Interrupt. Bus Fault Interrupt. Usage Fault Interrupt. SV Call Interrupt. Debug Monitor Interrupt. Pend SV Interrupt. System Tick Interrupt. address: Pointer to an interrupt service routine Return Value: Previous interrupt vector value cyisraddress CyIntGetSysVector(uint8 number) Description: This function applies to ARM based processors only and therefore does not apply to the PSoC 3 device. It gets the interrupt vector of the specified exception. These exceptions in the ARM architecture operate similar to user interrupts, but are specified by the system architecture of the processor. The number of each exception is fixed. Note that the numbering of these exceptions is separate from the numbering used for user interrupts. Parameters: number: Exception number. Valid range: [0-15]. Return Value: Interrupt vector value void CyIntSetPriority(uint8 number, uint8 priority) Description: Sets the priority of the specified interrupt number. Parameters: number: Interrupt number. Valid range: [0-31] priority: Interrupt priority. 0 is the highest priority. Valid range: [0-7] Return Value: None uint8 CyIntGetPriority(uint8 number) Description: Gets the priority of the specified interrupt number. Parameters: number: Interrupt number. Valid range: [0-31] Return Value: Interrupt priority ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 55 Interrupts void CyIntSetPending(uint8 number) Description: Forces the specified interrupt number to be pending. Parameters: number: Interrupt number. Valid range: [0-31] Return Value: None void CyIntClearPending(uint8 number) Description: Clears any pending interrupt for the specified interrupt number. Parameters: number: Interrupt number. Valid range: [0-31] Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 56 6 Pins In addition to the functionality provided for pins as part of the Pins component, a library of pin macros is provided in the cypins.h file for the PSoC 3/PSoC 5LP devices. These macros all make use of the port pin configuration register that is available for every pin on the PSoC 3/PSoC 5LP device. The address of that register is provided in the cydevice_trm.h file. Each of these pin configuration registers is named: CYREG_PRTx_PCy where x is the port number and y is the pin number within the port. APIs uint8 CyPins_ReadPin(uint16/uint32 pinPC) Description: Reads the current value on the pin (pin state, PS). Parameters: pinPC: Port pin configuration register (uint16 PSoC 3, uint32 PSoC 5LP) Return Value: Pin state 0: Logic low value Non-0: Logic high value void CyPins_SetPin(uint16/uint32 pinPC) Description: Set the output value for the pin (data register, DR) to a logic high. Note that this only has an effect for pins configured as software pins that are not driven by hardware. Parameters: pinPC: Port pin configuration register (uint16 PSoC 3, uint32 PSoC 5LP) Return Value: None void CyPins_ClearPin(uint16/uint32 pinPC) Description: Clear the output value for the pin (data register, DR) to a logic low. Note that this only has an effect for pins configured as software pins that are not driven by hardware. Parameters: pinPC: Port pin configuration register (uint16 PSoC 3, uint32 PSoC 5) Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 57 Pins void CyPins_SetPinDriveMode(uint16/uint32 pinPC, uint8 mode) Description: Sets the drive mode for the pin (DM). Parameters: pinPC: Port pin configuration register (uint16 PSoC 3, uint32 PSoC 5LP) mode: Desired drive mode Define Source CY_PINS_DM_ALG_HIZ CY_PINS_DM_DIG_HIZ CY_PINS_DM_RES_UP CY_PINS_DM_RES_DWN CY_PINS_DM_OD_LO CY_PINS_DM_OD_HI CY_PINS_DM_STRONG CY_PINS_DM_RES_UPDWN Analog HiZ Digital HiZ Resistive pull up Resistive pull down Open drain - drive low Open drain - drive high Strong CMOS Output Resistive pull up/down Return Value: None uint8 CyPins_ReadPinDriveMode(uint16/uint32 pinPC) Description: Reads the drive mode for the pin (DM). Parameters: pinPC: Port pin configuration register (uint16 PSoC 3, uint32 PSoC 5LP) Return Value: Current drive mode for the pin Define Source CY_PINS_DM_ALG_HIZ CY_PINS_DM_DIG_HIZ CY_PINS_DM_RES_UP CY_PINS_DM_RES_DWN CY_PINS_DM_OD_LO CY_PINS_DM_OD_HI CY_PINS_DM_STRONG CY_PINS_DM_RES_UPDWN Analog HiZ Digital HiZ Resistive pull up Resistive pull down Open drain - drive low Open drain - drive high Strong CMOS Output Resistive pull up/down void CyPins_FastSlew(uint16/uint32 pinPC) Description: Set the slew rate for the pin to fast edge rate. Note that this only applies for pins in strong output drive modes, not to resistive drive modes. Parameters: pinPC: Port pin configuration register (uint16 PSoC 3, uint32 PSoC 5LP) Return Value: None void CyPins_SlowSlew(uint16/uint32 pinPC) Description: Set the slew rate for the pin to slow edge rate. Note that this only applies for pins in strong output drive modes, not to resistive drive modes. Parameters: pinPC: Port pin configuration register (uint16 PSoC 3, uint32 PSoC 5LP) Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 58 7 Register Access A library of macros provides read and write access to the registers of the device. These macros are used with the defined values made available in the generated cydevice_trm.h and cyfitter.h files. Access to registers should be made using these macros and not the functions that are used to implement the macros. This allows for device independent code generation. PSoC 3 is an 8-bit architecture, so the processor does not have endianness. However, the compiler for an 8-bit architecture will implement endianness. For PSoC 3, the Keil compiler implements a big endian (MSB in lowest address) ordering. The PSoC 5LP processor architectures use little endian ordering. SRAM and Flash storage in all architectures is done using the endianness of the architecture and compilers. However, the registers in all these chips are laid out in little endian order. These macros allow register accesses to match this little endian ordering. If you perform operations on multi-byte registers without using these macros, you must consider the byte ordering of the specific architecture. Examples include usage of DMA to transfer between memory and registers, as well as function calls that are passed an array of bytes in memory. The PSoC 3 is an 8-bit processor, so all accesses will be done a byte at a time. The PSoC 5LP will perform accesses using the appropriate 8-, 16- and 32-bit accesses. APIs uint8 CY_GET_REG8(uint16/uint32 reg) Description: Reads the 8-bit value from the specified register. For PSoC 3, the address must be in the lower 64 K address range. Parameters: reg: Register address (uint16 PSoC 3, uint32 PSoC 5LP) Return Value: Read value void CY_SET_REG8(uint16/uint32 reg, uint8 value) Description: Writes the 8-bit value to the specified register. For PSoC 3 the address must be in the lower 64 K address range. Parameters: reg: Register address (uint16 PSoC 3, uint32 PSoC 5LP) value: Value to write Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 59 uint16 CY_GET_REG16(uint16/uint32 reg) Description: Reads the 16-bit value from the specified register. This macro implements the byte swapping required for proper operation. For PSoC 3 the address must be in the lower 64 K address range. Parameters: reg: Register address (uint16 PSoC 3, uint32 PSoC 5LP) Return Value: Read value void CY_SET_REG16(uint16/uint32 reg, uint16 value) Description: Writes the 16-bit value to the specified register. This macro implements the byte swapping required for proper operation. For PSoC 3 the address must be in the lower 64 K address range. Parameters: reg: Register address (uint16 PSoC 3, uint32 PSoC 5LP) value: Value to write Return Value: None uint32 CY_GET_REG24(uint16/uint32 reg) Description: Reads the 24-bit value from the specified register. This macro implements the byte swapping required for proper operation. For PSoC 3 the address must be in the lower 64 K address range. Parameters: reg: Register address (uint16 PSoC 3, uint32 PSoC 5LP) Return Value: Read value void CY_SET_REG24(uint16/uint32 reg, uint32 value) Description: Writes the 24-bit value to the specified register. This macro implements the byte swapping required for proper operation. For PSoC 3 the address must be in the lower 64 K address range. Parameters: reg: Register address (uint16 PSoC 3, uint32 PSoC 5LP) value: Value to write Return Value: None uint32 CY_GET_REG32(uint16/uint32 reg) Description: Reads the 32-bit value from the specified register. This macro implements the byte swapping required for proper operation. For PSoC 3 the address must be in the lower 64 K address range. Parameters: reg: Register address (uint16 PSoC 3, uint32 PSoC 5LP) Return Value: Read value ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 60 Register Access void CY_SET_REG32(uint16/uint32 reg, uint32 value) Description: Writes the 32-bit value to the specified register. This macro implements the byte swapping required for proper operation. For PSoC 3 the address must be in the lower 64 K address range. Parameters: reg: Register address (uint16 PSoC 3, uint32 PSoC 5LP) value: Value to write Return Value: None uint8 CY_GET_XTND_REG8(uint32 reg) Description: Reads the 8-bit value from the specified register. Supports the full address space for PSoC 3, but requires more execution cycles than the standard register get function. Identical to CY_GET_REG8 for PSoC 5LP. Parameters: reg: Register address Return Value: Read value void CY_SET_XTND_REG8(uint32 reg, uint8 value) Description: Writes the 8-bit value to the specified register. Supports the full address space for PSoC 3, but requires more execution cycles than the standard register set function. Identical to CY_SET_REG8 for PSoC 5LP. Parameters: reg: Register address value: Value to write Return Value: None uint16 CY_GET_XTND_REG16(uint32 reg) Description: Reads the 16-bit value from the specified register. This macro implements the byte swapping required for proper operation. Supports the full address space for PSoC 3, but requires more execution cycles than the standard register get function. Identical to CY_GET_REG16 for PSoC 5LP. Parameters: reg: Register address Return Value: Read value void CY_SET_XTND_REG16(uint32 reg, uint16 value) Description: Writes the 16-bit value to the specified register. This macro implements the byte swapping required for proper operation. Supports the full address space for PSoC 3, but requires more execution cycles than the standard register set function. Identical to CY_SET_REG16 for PSoC 5LP. Parameters: reg: Register address value: Value to write Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 61 uint32 CY_GET_XTND_REG24(uint32 reg) Description: Reads the 24-bit value from the specified register. This macro implements the byte swapping required for proper operation. Supports the full address space for PSoC 3, but requires more execution cycles than the standard register get function. Identical to CY_GET_REG24 for PSoC 5LP. Parameters: reg: Register address Return Value: Read value void CY_SET_XTND_REG24(uint32 reg, uint32 value) Description: Writes the 24-bit value to the specified register. This macro implements the byte swapping required for proper operation. Supports the full address space for PSoC 3, but requires more execution cycles than the standard register set function. Identical to CY_SET_REG24 for PSoC 5LP. Parameters: reg: Register address Value to write Return Value: None uint32 CY_GET_XTND_REG32(uint32 reg) Description: Reads the 32-bit value from the specified register. This macro implements the byte swapping required for proper operation. Supports the full address space for PSoC 3, but requires more execution cycles than the standard register get function. Identical to CY_GET_REG32 for PSoC 5LP. Parameters: reg: Register address Return Value: Read value void CY_SET_XTND_REG32(uint32 reg, uint32 value) Description: Writes the 32-bit value to the specified register. This macro implements the byte swapping required for proper operation. Supports the full address space for PSoC 3, but requires more execution cycles than the standard register set function. Identical to CY_SET_REG32 for PSoC 5LP. Parameters: reg: Register address value: Value to write Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 62 DMA 8 DMA The DMA files provide the API functions for the DMA controller, DMA channels and Transfer Descriptors. This API is the library version, not the code that is generated when the user places a DMA component on the schematic. The automatically generated code would use the APIs in this module. Refer to the DMA component datasheet for more information. Note The linked list of all the Transfer Descriptors to be allocated is created (by CyDmacConfigure() function call from the startup code) only if a DMA component is placed onto the schematic. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 63 9 Flash and EEPROM Implementation Flash Architecture Flash memory in PSoC devices provides nonvolatile storage for user firmware, user configuration data, bulk data storage, and optional error correcting code (ECC) data. The main flash memory area contains up to 256 KB of user program space, depending on the device type. Flash is organized as a set of arrays. Each array consists of 64, 128, or 256 rows. Each row contains 256 data bytes plus 32 bytes of ECC area. If ECC is not used, this space can store device configuration data and bulk user data. User code may not be run out of the ECC flash memory section. Flash Memory Array Structure Row 0 Data (256 bytes) ECC (32 bytes) Row 1 Data ECC Row N Data ECC PSoC 3 flash memory has the following features: organized as one array of 64, 128, or 256 rows; each row contains 256 data bytes plus 32 bytes for either ECC or data storage. PSoC 5LP flash memory has the following features: organized as either one array of 128 or 256 rows, or as multiple arrays of 256 rows each; each row contains 256 data bytes plus 32 bytes for either ECC or data storage. See the device datasheet and TRM for more information on Flash architecture. The System tab of the PSoC Creator Design-Wide Resources (DWR) file contains configuration options that define ECC area utilization: DWR Option ECC Function Enable Error Correcting Code (ECC) ECC corrects one bit error and detect multiple bit errors per 8 bytes. ECC area stores error correcting code data. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 64 Flash and EEPROM DWR Option ECC Function Store Configuration Data in ECC Memory The device configuration data will be stored in ECC area to reduce main FLASH memory usage. Error correction may not be used when this option is enabled. Note This option is always disabled for bootloader projects, as ECC area is dedicated for bootloadable projects. ECC function is disabled. The user data can be stored in the ECC area. None For more information on using ECC, refer to the Flash Program Memory chapter of the TRM. PSoC devices include a flexible flash-protection model that prevents access and visibility to on-chip flash memory. The device offers the ability to assign one of four protection levels to each row of flash: Unprotected Factory Upgrade Field Upgrade Full Protection The required protection level can be selected using the Flash Security tab of the PSoC Creator DWR file. Flash protection levels can only be changed by performing a complete flash erase. The Flash programming APIs will fail to write a row with Full Protection level. For more information on protection model, refer to the Flash Security Editor section in the PSoC Creator Help. EEPROM Architecture PSoC EEPROM memory is byte-addressable nonvolatile memory. The EEPROM is also organized as a set of arrays. Both PSoC 3 and PSoC 5LP architectures have one EEPROM array, the size of which is 512 bytes, 1 KB, or 2 KB. The array consists of 32, 64, or 128 rows, depending on the device. Each row contains 16 bytes of data. Working with Flash and EEPROM Flash and EEPROM are mapped into memory space and can be read directly. To get the address of the first Flash / EEPROM row in a specified array ID, the array ID should be multiplied by array size, and added to Flash / EEPROM base address. To access any row in the same array ID, the size of the row should be multiplied by the desired row number and added to the first row address of the specified array. Note When writing Flash, data in the instruction cache can become stale. Therefore, the cache data does not correlate to the data just written to Flash. A call to CyFlushCache() is required to invalidate the data in cache and force fresh information to be loaded from Flash. The following table provides definitions of the device-specific Flash parameters that can be used to operate with the Flash: Value Description CY_FLASH_BASE CY_FLASH_SIZE CY_FLASH_SIZEOF_ARRAY CY_FLASH_SIZEOF_ROW CY_FLASH_SIZEOF_ECC_ROW CY_FLASH_NUMBER_ROWS CY_FLASH_NUMBER_ARRAYS The base address of the Flash memory. The size of the Flash memory. The size of Flash array. The size of the Flash row. The size of the ECC row. The number of Flash row. The number of Flash arrays. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 65 Flash and EEPROM The EEPROM API provides the following device-specific definitions: Value Description CY_EEPROM_BASE CY_EEPROM_SIZE CY_EEPROM_SIZEOF_ARRAY CY_EEPROM_SIZEOF_ROW CY_EEPROM_NUMBER_ROWS CY_EEPROM_NUMBER_ARRAYs CY_EEPROM_NUMBER_SECTORS CY_EEPROM_SIZEOF_SECTOR The base address of the EEPROM memory. The size of the EEPROM memory. The size of EEPROM array. The size of the EEPROM row. The number of EEPROM row. The number of EEPROM arrays. The number of EEPROM sectors. The size of EEPROM sector. Both Flash and EEPROM are programmed through the system performance controller (SPC). To interface with the SPC, information is pushed into, and pulled from, a single register. The Flash/EEPROM specific API provides unified approach to work with Flash as well as EEPROM and simplifies interacting with the SPC by abstracting the details away. In PSoC 3/PSoC 5LP devices, flash can be read either by the cache controller or the SPC. Flash write can be performed only by SPC. Both SPC and cache cannot simultaneously access the flash memory. If the cache controller tries to access flash at the same time as the SPC, then it must wait until the SPC completes its flash access operation. The CPU, which accesses the flash memory through the cache controller, is therefore also stalled in this circumstance. If a CPU code fetch has to be done from the flash memory due to a cache miss condition, then the cache would have to wait till the SPC completes the flash write operation. Thus the CPU code execution will also be halted till the flash write is complete. It can take as many as 20 milliseconds to write to EEPROM or Flash. During this time the device should not be reset, or unexpected changes may be made to portions of EEPROM or Flash. Reset sources include XRES pin, software reset, and watchdog; care should be taken to make sure that these are not inadvertently activated. Also, the low voltage detect circuits should be configured to generate an interrupt instead of a reset. PSoC devices have an on-chip temperature sensor that is used to measure the internal die temperature. You must acquire the temperature at least once to use Flash and EEPROM write functions. If the application will be used in an environment where the die temperature changes 10 °C or more, the temperature should be refreshed to adjust the write times to the Flash for optimal performance. The die temperature is obtained by calling the CySetTemp() function. This function queries SPC for the die temperature and stores it in a global variable, which is used implicitly while performing Flash and EEPROM write operations. When programming Flash with error detection/correction function disabled (ECC flash space is used for data storage), there are multiple methods for writing a row of data: Use CyWriteRowFull() to write the entire row including ECC; Use CyWriteRowData() to write the entire row without ECC; Use CyWriteRowConfig() to write just the ECC memory. Flash or EEPROM can be written by one row at a time by calling the CyWriteRowData() function. The first parameter determines the Flash or EEPROM array. The number of arrays that are Flash and the number of arrays that are EEPROM are specific to the exact device selected. Refer to device TRM to determine which array IDs are valid. The row numbering starts from 0 for each array ID. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 66 Flash and EEPROM Flash Programming Diagram CyFlash_Start() (optional) CySetTemp() Data row + ECC row Data type ECC row Data row CyWriteRowFull() CyWriteRowData() CyWriteRowConfig() (ECC Disabled) EEPROM Programming Diagram CyEEPROM_Start() CySetTemp() CyWriteRowFull() CyWriteRowData() Power Modes For PSoC 3/PSoC 5LP devices, the power manager will not put the device into a low power state if the system performance controller (SPC) is executing a command. The device will go into low power mode after the SPC completes command execution. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 67 Flash and EEPROM Flash and EEPROM APIs cystatus CySetTemp() Description: Updates the static snapshot of current chip temperature value obtained from on- chip temperature sensor. This function must be called once before executing a series of Flash / EEPROM writing functions. In case the application will be used in an environment where the die temperature changes significantly (10 °C or more), care should be taken to keep the temperature snapshot value up-to-date to adjust the write times to the Flash for optimal performance. Parameters: None Return Value: Status Value Description CYRET_SUCCESS CYRET_LOCKED CYRET_UNKNOWN Successful Flash / EEPROM writing already in use Failure Side Effects and The function does not return until the SPC has returned to an idle state. Restrictions: ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 68 Flash and EEPROM cystatus CyWriteRowFull(uint8 arrayId, uint16 rowAddress, uint8 *rowData, uint16 rowSize) Description: Allows a row to be erased and programmed. If the array is a Flash array: DWR Flash configuration Description Enable ECC – ON Store Configuration Data in ECC Memory – N/A Enable ECC – OFF Store Configuration Data in ECC Memory – ON Data are written to the flash row. The ECC for these data are calculated and written automatically. The size of the data equals the size of the flash row. Data are written to both flash and ECC rows. To prevent overwriting of the configuration data stored in the ECC flash space, the size of the data must be equal to the size of the flash row. Data are written to both flash and ECC rows. The size of the data equals the sum of flash row and ECC row sizes. Enable ECC – OFF Store Configuration Data in ECC Memory – OFF If the array is an EEPROM array, the size of data equals EEPROM row size. Parameters: uint8 arrayId: ID of the array to write. The type of write, Flash or EEPROM, is determined from the array ID. The arrays in the part are sequential starting at the first ID for the specific memory type. The array ID for the Flash memory lasts from 0x00 to 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F. uint16 rowAddress: Row address within the specified arrayId. uint8 *rowData: Address of the data to be programmed. uint16 rowSize: Number of bytes of row data Return Value: Status Value Description CYRET_SUCCESS CYRET_LOCKED CYRET_CANCELED Other non-zero Successful Flash / EEPROM writing already in use Command not accepted Failure ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 69 Flash and EEPROM cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, uint8 *rowData) Description: Writes a row of Flash or EEPROM. If the array is a Flash array: DWR Flash configuration Description Enable ECC – ON Store Configuration Data in ECC Memory – N/A Data are written to the flash row. The ECC for these data are calculated and written automatically. The size of the data that is passed to this function equals the size of the flash row. Data are written to the flash memory. The data stored in ECC memory are preserved. Enable ECC – OFF Store Configuration Data in ECC Memory – ON/OFF If the array is an EEPROM array, the size of data equals EEPROM row size. Parameters: uint8 arrayId: ID of the array to write. The type of write, Flash or EEPROM, is determined from the array ID. The arrays in the part are sequential starting at the first ID for the specific memory type. The array ID for the Flash memory lasts from 0x00 to 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F. uint16 rowAddress: Row address within the specified arrayId. uint8 *rowData: Address of the data to be programmed. Return Value: Status Value Description CYRET_SUCCESS CYRET_LOCKED CYRET_CANCELED Other non-zero Successful Flash / EEPROM writing already in use Command not accepted Failure ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 70 Flash and EEPROM cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, uint8 *rowECC) Description: Writes the ECC portion of a Flash. This function is only valid for Flash array IDs (not for EEPROM). DWR Flash configuration Description Enable ECC – ON Store Configuration Data in ECC Memory – N/A Enable ECC – OFF Store Configuration Data in ECC Memory – ON Enable ECC – OFF Store Configuration Data in ECC Memory – OFF This function is not available for this configuration as the ECC is stored in the ECC memory. This function is not available for this configuration as the Configuration Data are stored in the ECC memory. Data are written to the ECC row. The data stored in Flash row are preserved. Parameters: uint8 arrayId: ID of the array to write. The arrays in the part are sequential starting at the first ID for the specific memory type. The array ID for the Flash memory lasts from 0x00 to 0x3F. uint16 rowAddress: Row address within the specified arrayId. uint8 *rowECC: Address of the data to be programmed. Return Value: Status Value Description CYRET_SUCCESS CYRET_LOCKED CYRET_CANCELED Other non-zero Successful Flash / EEPROM writing already in use Command not accepted Failure void CyFlash_Start() Description: Enables the Flash. By default Flash is enabled. Parameters: None Return Value: None void CyFlash_Stop() Description: Disables the Flash. This setting is ignored as long as the CPU is currently running. This will only take effect when the CPU is later disabled. Parameters: None Return Value: None void CyFlash_SetWaitCycles(uint8 freq) Description: Sets the number of clock cycles the cache will wait before it samples data coming back from Flash. This function must be called before increasing CPU clock frequency. It can optionally be called after lowering CPU clock frequency in order to improve CPU performance. Parameters: freq: CPU operation frequency in Megahertz. Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 71 Flash and EEPROM void CyEEPROM_Start() Description: Enables the EEPROM. The EEPROM is controlled by a separate bit and must be started before it can be used. Parameters: None Return Value: None void CyEEPROM_Stop() Description: Disables the EEPROM. The EEPROM is controlled by a separate bit and can be stopped independently. Parameters: None Return Value: None void CyEEPROM_ReadReserve() Description: Request access to the EEPROM for reading and waits until that access is available. The access to EEPROM is arbitrated between the controller that writes to the EEPROM and the normal access to read from EEPROM. It is not required to reserve access to the EEPROM for reading, but if a write is still active and a read is attempted a fault is generated and the wrong data is returned. Parameters: None Return Value: None void CyEEPROM_ReadRelease() Description: Releases the read reservation of the EEPROM. If the EEPROM has been reserved for reading, then it must be released before further writes to the EEPROM can be performed. Parameters: None Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 72 10 System Functions These functions apply to all architectures. General APIs uint8 CyEnterCriticalSection(void) Description: CyEnterCriticalSection disables interrupts and returns a value indicating whether interrupts were previously enabled (the actual value depends on the device architecture). Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit with interrupts still enabled. The test and set of the interrupt bits is not atomic; this is true for all architectures. Therefore, to avoid corrupting the processor state, it must be the policy that all interrupt routines restore the interrupt enable bits as they were found on entry. Parameters: None Return Value: uint8 PSoC 3 – Returns a value containing two bits: bit 0: 1 if interrupts were enabled before CyEnterCriticalSection was called. bit 1: 1 if IRQ generation was disabled before CyEnterCriticalSection was called. PSoC 5LP – Returns 0 if interrupts were previously enabled or 1 if interrupts were previously disabled. void CyExitCriticalSection(uint8 savedIntrStatus) Description: CyExitCriticalSection re-enables interrupts if they were enabled before CyEnterCriticalSection was called. The argument should be the value returned from CyEnterCriticalSection. Parameters: uint8 savedIntrStatus: Saved interrupt status returned by the CyEnterCriticalSection function. Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 73 System Functions void CYASSERT(uint32 expr) Description: Macro that evaluates the expression and if it is false (evaluates to 0) then the processor is halted. This macro is evaluated unless NDEBUG is defined. If NDEBUG is defined, then no code is generated for this macro. NDEBUG is defined by default for a Release build setting and not defined for a Debug build setting. Parameters: expr: Logical expression. Asserts if false. Return Value: None void CyHalt(uint8 reason) Description: Halts the CPU. Parameters: reason: Value to be passed for debugging. This value may be useful to know the reason why CyHalt() was invoked. Return Value: None void CySoftwareReset(void) Description: Forces a software reset of the device. Parameters: None Return Value: None void CyGetUniqueID(uint32* uniqueId) Description: Returns the 64-bit unique id of the device Parameters: uniqueId: Pointer to a two element 32-bit unsigned integer array. Return Value: Returns the 64-bit unique id of the device by loading them into the integer array pointed to by uniqueId. CyDelay APIs There are four CyDelay APIs that implement simple software-based delay loops. The loops compensate for bus clock frequency. The CyDelay functions provide a minimum delay. If the processor is interrupted, the length of the loop will be extended by as long as it takes to implement the interrupt. Other overhead factors, including function entry and exit, may also affect the total length of time spent executing the function. This will be especially apparent when the nominal delay time is small. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 74 System Functions void CyDelay(uint32 milliseconds) Description: Delay by the specified number of milliseconds. By default the number of cycles to delay is calculated based on the clock configuration entered in PSoC Creator. If the clock configuration is changed at run-time, then the function CyDelayFreq is used to indicate the new Bus Clock frequency. CyDelay is used by several components, so changing the clock frequency without updating the frequency setting for the delay can cause those components to fail. Parameters: milliseconds: Number of milliseconds to delay. Return Value: None Side Effects and CyDelay has been implemented with the instruction cache assumed enabled. Restrictions: When instruction cache is disabled on PSoC 5LP, CyDelay will be two times larger. For example, with instruction cache disabled CyDelay(100) would result in about 200 ms delay instead of 100 ms. void CyDelayUs(uint16 microseconds) Description: Delay by the specified number of microseconds. By default the number of cycles to delay is calculated based on the clock configuration entered in PSoC Creator. If the clock configuration is changed at run-time, then the function CyDelayFreq is used to indicate the new Bus Clock frequency. CyDelayUs is used by several components, so changing the clock frequency without updating the frequency setting for the delay can cause those components to fail. Parameters: microseconds: Number of microseconds to delay. Return Value: Void Side Effects and CyDelayUS has been implemented with the instruction cache assumed enabled. Restrictions: When instruction cache is disabled on PSoC 5LP, CyDelayUs will be two times larger. For example, with instruction cache disabled CyDelayUs(100) would result in about 200 us delay instead of 100 us. If the bus clock frequency is a small non-integer number, the actual delay can be up to twice as long as the nominal value. The actual delay cannot be shorter than the nominal one. void CyDelayFreq(uint32 freq) Description: Sets the Bus Clock frequency used to calculate the number of cycles needed to implement a delay with CyDelay. By default the frequency used is based on the value determined by PSoC Creator at build time. Parameters: freq: Bus clock frequency in Hz. 0: Use the default value non-0: Set frequency value Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 75 System Functions void CyDelayCycles(uint32 cycles) Description: Delay by the specified number of cycles using a software delay loop. PSoC 3: The execution overhead is in range of 20-46 cycles depending on the number of the delay cycles. PSoC 5: The execution overhead is in range of 8-23 cycles depending on the number of the delay cycles. The 20-cycle overhead means that CyDelayCycles(100), will be executed for 120 cycles. Parameters: cycles: Number of cycles to delay. Valid range is from 0 to the maximum uint32 type value. Return Value: None Voltage Detect APIs Functional Description Voltage monitoring circuits in these devices can be configured to generate an interrupt when Vdda or Vddd is outside a defined range. Low-voltage interrupts are available for both the analog and digital supplies, and a high-voltage interrupt is available for the analog supply. The trip levels for the low-voltage detectors are independently configurable. The trip level for the high-voltage detector is fixed at 5.75 V. The analog and digital low-voltage monitoring circuits can also be configured to reset the device instead of generating an interrupt. Device Reset Bits [2:0] in the Reset and Voltage Detection Status Register 1 (RESET_CR1) register control whether or not the voltage monitoring circuits generate an interrupt if the supply is outside the trip level. If the lowvoltage interrupts are enabled, then bits [7:6] in Reset and Voltage Detection Status Register 3 (RESET_CR3) register control whether or not the device is reset when a low-voltage event occurs. The low-voltage interrupt resets are part of the precision reset circuit and generate a momentary hardware POR reset. Low/High-Voltage Detection The status of the voltage monitor circuits is stored in two different ways: CyVdStickyStatus() function operates with the bits [2:0] of the Reset and Voltage Detection Status Register 0 (RESET_SR0) register that are set to 1 if a low-voltage or high-voltage event has occurred. This register is cleared when read or upon POR reset. CyVdRealTimeStatus() function operates with the bits [2:0] of the Reset and Voltage Detection Status Register 2 (RESET_SR2) register that holds the real-time status of the voltage monitor circuits’ outputs, which means they will only be set to ‘1’ for the duration that the event is occurring. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 76 System Functions Interrupt Configuration The GlobalSignalRef component can be used to connect the LVI and HVI interrupt signals to other components in the project schematic, or an interrupt component if you wish to execute an interrupt on an LVI/HVI event. If “Low/High Voltage Detect (LVI/HVI)” is selected in the component, the output of GlobalSignalRef is set to 1 whenever any of the enabled LVI or HVI circuits detect an event. The output will remain at 1 as long as an LVI or HVI event is occurring. Refer to the GlobalSignalRef component datasheet for more information. Note that the interrupt is level sensitive. This means that interrupt will continue to fire as long as the voltage monitor detects the event. The solution may be to disable the LVD interrupt (using Interrupt component API) when the interrupt executes the first time. Then re-enable the interrupt when the CyVdRealTimeStatus() function no longer reports the event conditions. Remember to clear the pending interrupt before re-enabling the interrupts. Best Practices If the Vddd and Vdda supplies are tied together, you can configure an interrupt and a low-voltage reset. Configure one of the voltage monitors to detect a particular threshold to indicate a low voltage condition, and configure the other voltage monitor to generate a reset when the voltage goes too low. For instance, the analog voltage monitor could detect a 2.5 volt condition (indicating batteries are getting low) and the digital voltage monitor circuit could be used to issue a reset when the voltage reached 2.3 volts. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 77 System Functions APIs The following API functions configure and manage the voltage monitoring circuits and associated interrupt status registers. For more information on the voltage monitoring circuits, refer to the Voltage Monitoring section of the device TRM and the Power Voltage Level Monitors section of the device datasheet. void CyVdLvDigitEnable(uint8 reset, uint8 threshold) Description: Sets the voltage trip level, enables the output of the digital low-voltage monitor, and optionally configures voltage monitor to reset device upon the low-voltage event instead of generating an interrupt. Note The associated interrupt enable/disable state is not changed by the function. The Interrupt component’s API should be used to register the interrupt service routine and to enable/disable associated interrupt. Parameters: reset: Enables device reset on digital low-voltage event: • Zero - Interrupt on digital low-voltage event • Non-zero - Reset on digital low-voltage event threshold: Sets the trip point of the digital low-voltage monitoring circuit in steps of approximately 250 mV in range from 1.70 V (0x00) to 5.45 V (0x0F). For example, the trip point is set to 1.80 V when the threshold parameter value is 0x04. Refer to the device TRM for the exact trip voltage values. Return Value: None Side Effects and The voltage resets are momentary. When a voltage reset (analog/digital lowRestrictions voltage and analog high-voltage) occurs, the RESET_CR1 and RESET_CR3 registers are restored to their default values. This means that the voltage monitor circuit is no longer enabled and the device exits reset. If the supply is below the trip level and firmware enables the voltage reset functionality, the device will reset again. This will continue as long as the supply is below the trip level or as long as the user enables the reset functionality of the voltage monitor functionality. When any voltage reset occurs, the RESET_SR0 and RESET_SR2 status registers are cleared. This means that analog low-voltage, digital low-voltage and analog high-voltage status bits are not persistent across any voltage reset. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 78 System Functions void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) Description: Sets the voltage trip level, enables the output of the analog low-voltage monitor, and optionally configures voltage monitor to reset device upon the low-voltage event instead of generating an interrupt. Note The associated interrupt enable/disable state is not changed by the function. The Interrupt component’s API should be used to register the interrupt service routine and to enable/disable associated interrupt. Parameters: reset: Enables device reset on analog low-voltage event: • Zero - Interrupt on analog low-voltage event. • Non-zero - Reset on analog low-voltage event. threshold: Sets the trip point of the analog low-voltage monitoring circuit in steps of approximately 250 mV in range from 1.70 V (0x00) to 5.45 V (0x0F). For example, the trip point is set to 1.80 V when value of the threshold parameter is 0x04. Please refer to the device TRM for the exact trip voltage values. Return Value: None Side Effects and The voltage resets are momentary. When a voltage reset (analog/digital lowRestrictions voltage and analog high-voltage) occurs, the RESET_CR1 and RESET_CR3 registers are restored to their default values. This means that the voltage monitor circuit is no longer enabled and the device exits reset. If the supply is below the trip level and firmware enables the voltage reset functionality, the device will reset again. This will continue as long as the supply is below the trip level or as long as the user enables the reset functionality of the voltage monitor functionality. When any voltage reset occurs, the RESET_SR0 and RESET_SR2 status registers are cleared. This means that analog low-voltage, digital low-voltage and analog high-voltage status bits are not persistent across any voltage reset. void CyVdLvDigitDisable(void) Description: Disables the digital low-voltage monitor, turns off device reset upon the digital low-voltage event, and clears the associated persistent status bit. Note The associated interrupt enable/disable state is not changed by the function. The pending interrupt status is not cleared. The Interrupt component’s API should be used to manipulate with the associated interrupts. Parameters: None Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 79 System Functions void CyVdLvAnalogDisable(void) Description: Disables the analog low-voltage monitor, turns off device reset upon the analog low-voltage event, and clears the associated persistent status bit. Note The associated interrupt enable/disable state is not changed by the function. The pending interrupt status is not cleared. The Interrupt component’s API should be used to manipulate with the associated interrupts. Parameters: None Return Value: None void CyVdHvAnalogEnable(void) Description: Enables the output of the analog high-voltage monitor and sets 5.75 V threshold detection for Vdda. Note The associated interrupt enable/disable state is not changed by the function. The Interrupt component’s API should be used to register the interrupt service routine and to enable/disable associated interrupt. Parameters: None Return Value: None void CyVdHvAnalogDisable(void) Description: Disables the analog high-voltage monitor and clears the associated persistent status bit. Note The associated interrupt enable/disable state is not changed by the function. The pending interrupt status is not cleared. The Interrupt component’s API should be used to manipulate with the associated interrupts. Parameters: None Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 80 System Functions uint8 CyVdStickyStatus(uint8 mask) Description: Reads and clears the voltage detection status bits in the RESET_SR0 register. The bits are set to 1 by the voltage monitor circuit when the supply is outside the detector’s trip point. They stay set to 1 until they are read or a POR / LVI / PRES reset occurs. This function uses a shadow register, so only the bits passed in the parameter will be cleared in the shadow register. Parameters: mask: Bits in the RESET_SR0 shadow register to clear and return. Value Definition Register [bits] CY_VD_LVID CY_VD_LVIA CY_VD_HVIA Persistent status of digital LVI Persistent status of analog LVI Persistent status of analog HVI RESET_SR0 [0] RESET_SR0 [1] RESET_SR0 [2] Return Value: Status. Same enumerated bit values as used for the mask parameter. A zero is returned for bits not used in the mask parameter. Side Effects and When an LVI reset occurs, the RESET_SR0 status registers are cleared. This Restrictions means that the voltage detection status bits are not persistent across an LVI reset and cannot be used to determine a reset source. uint8 CyVdRealTimeStatus(void) Description: Reads the real-time voltage detection status bits in the RESET_SR2 register. The bits are set to 1 by the voltage monitor circuit when the supply is outside the detector’s trip point, and set to 0 when the supply is inside the trip point. Parameters: None Return Value: Status of the LVID, LVIA, and HVIA bits in the RESET_SR2 register. Value CY_VD_LVID CY_VD_LVIA CY_VD_HVIA Definition Real-time status of digital LVI Real-time status of analog LVI Real-time status of analog HVI Register [bits] RESET_SR0 [0] RESET_SR0 [1] RESET_SR0 [2] Side Effects and When an LVI reset occurs, the RESET_SR2 status registers are cleared. This Restrictions means that the voltage detection status bits are not persistent across an LVI reset and cannot be used to determine a reset source. Cache Functionality PSoC 3 The PSoC 3 cache is enabled by default. It can be disabled using the PSoC Creator Design-Wide Resources System Editor. There are no defines, functions or macros for cache handling for PSoC 3. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 81 System Functions PSoC 5LP void CyFlushCache() Description: Flushes the PSoC 5/PSoC 5LP cache by invalidating all entries. Parameters: None Return Value: None Side Effects and When writing Flash, data in the instruction cache can become stale. Therefore, the Restrictions: cache data does not correlate to the data just written to Flash. A call to CyFlushCache() is required to invalidate the data in cache and force fresh information to be loaded from Flash. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 82 11 Startup and Linking The cy_boot component is responsible for the startup of the system. The following functionality has been implemented: Provide the reset vector Setup processor for execution Setup interrupts Setup the stack including the reentrant stack for the 8051 Configure the device Initialize static and global variables with initialization values Clear all remaining static and global variables Integrate with the bootloader functionality Preserve the reset status Call main() C entry point See application note AN60616 for more details on PSoC 3 and PSoC 5LP startup. The device startup procedure configures the device to meet datasheet and PSoC Creator project specifications. Startup begins after the release of a reset source, or after the end of a power supply ramp. There are two main portions of startup: hardware startup and firmware startup. During hardware startup, the CPU is halted, and other resources configure the device. During firmware startup, the CPU runs code generated by PSoC Creator to configure the device. When startup ends, the device is fully configured, and its CPU begins execution of user-authored main() code. The hardware startup configures the device to meet the general performance specifications given in the datasheet. The hardware startup phase begins after a power supply ramp or reset event. There are two phases of hardware startup: reset and boot. After hardware startup ends, code execution from Flash begins. Firmware startup configures the PSoC device to behave as described in the PSoC Creator project. It begins at the end of hardware startup. The PSoC device’s CPU begins executing user-authored main() code after the completion of firmware startup. The main task of firmware startup is to populate configuration registers such that the PSoC device behaves as designed in the PSoC Creator project. This includes configuring analog and digital peripherals, as well as system resources such as clocks and routing. The startup procedure may be altered to better fit a specific application’s needs. There are two ways to modify device startup: using the PSoC Creator design-wide resources (DWR) interface, and modifying the device startup code. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 83 Startup and Linking PSoC 3 Startup is all handled by a single assembly file (KeilStart.a51), which is based on a template provided by Keil. There isn’t a file specifically associated with linking. The linker directives are used instead. For more information on the 8051 architecture, refer to the Language Extensions section on www.keil.com. For the more information on the PSoC 3’s architecture refer to the AN54181. PSoC 5LP The startup and linker scripts have been custom developed by Cypress, but both of the toolchain vendors that we currently support provide example linker implementations and complete libraries that solve many of the issues that have been created by our custom implementations. The memory layout of the final binary and hex images, as well as the placement in PSoC 5LP memory is described in the linker descriptor (.scat) file generated as part of the PSoC Creator build. The custom linker descriptor file can be used when building the project instead of the default one by going to Build Settings window and specifying path to the file in the Custom Linker Script field of the Linker category. For the more information on the PSoC 5LP’s CPU architecture, refer to the Cortex™-M3 Technical Reference Manual on infocenter.arm.com. There is also Application Note 179 - Cortex™ -M3 Embedded Software Development on infocenter.arm.com. Unaligned Transfers (PSoC 5LP) The PSoC 5LP supports unaligned transfers on single accesses with a number of limitations common for Cortex-M3 platform. When unaligned transfers are used, they are actually converted into multiple aligned transfers. This conversion is transparent from the software point of view. When an unaligned transfer takes place, it is broken into separate transfers. So, it takes more clock cycles for a single data access. To get the best performance and to ensure code compatibility through PSoC processors family, the unaligned transfers should be avoided. In PSoC 5LP, SRAM is located at Cortex-M3 Code/SRAM regions boundary. The unaligned accesses that cross memory map boundaries are architecturally unpredictable. The linker configuration files used for PSoC 5LP do not protect against unaligned accesses that cross this boundary. When unaligned accesses must be used, use a function that checks for the possible boundary problem and do byte accesses at the boundary or modify the linker script to force the memory that needs to be accessed in an unaligned fashion to not span this border. GCC Implementation PSoC Creator integrates the GCC ARM Embedded compiler including making the Newlib-nano and newlib libraries. Refer to the Red Hat newlib C Library for the C library reference manual. The newlib-nano is configured by default. To choose newlib library, open the Build Settings dialog > ARM GCC 4.8.4 > Linker > General, and set the “Use newlib-nano” option to False. By default, with the GNU ARM compiler, the string formatting functions in the C run-time library return empty strings for floating-point conversions. The newlib-nano library is a stripped-down version of the full C newlib. It does not include support for floating point formatting and other memory-intensive features. There are two solutions to this problem: enable floating-point formatting support in newlib-nano, or change the library to the full newlib. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 84 Startup and Linking To enable floating-point formatting, open the Build Settings dialog, go to the Linker page, and add the string -u _printf_float to the command line options. This change will result in an increase in Flash and RAM usage in your application. Note If you also wish to use the scanf functions with floating-point numbers you should add the string –u _scanf_float as well, with another increase in Flash and RAM usage. Realview Implementation (applicable for MDK Use all the standard libraries (C standardlib, C microlib, fplib, mathlib). All of these libraries are linked in by default. Support for RTOS and user replacement of routines. This is possible because the library routines are denoted as "weak" allowing their replacement if another implementation is provided. A mechanism is provided that allows for the replacement of the provided linker/scatter file with a user version. This is implemented by allowing the user to create the file local to their project and having a build setting that allows the specification of this file as the linker/scatter file instead of the file provided automatically. Currently the heap and stack size are specified as a fixed quantity (4 K Stack, 1 K Heap). If possible the requirement to specify Heap and Stack sizes should be removed entirely. If that is not possible, then these values should be the defaults with the option to choose other values in the Design-Wide Resources GUI. All the code in the Generated Source tree is compiled into a single library as part of the build process. Then that compiled library is linked in with the user code in the final link. CMSIS Support Cortex Microcontroller Software Interface Standard (CMSIS) is a standard from ARM for interacting with Cortex M-series processors. There are multiple levels of support. The Core Peripheral Access Layer (CMSIS Core) support is provided. For the more information refer to CMSIS - Cortex Microcontroller Software Interface Standard on www.arm.com. PSoC Creator 3.2 provides support for CMSIS Core version 4.0. Also, PSoC Creator 3.2 provides the ability to use a custom version of the CMSIS Core. The following diagram shows how CMSIS Core version 4.0 files are integrated into the cy_boot component and how custom version of CMSIS Core files can be integrated. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 85 Startup and Linking core_cm4_simd.h core_cmInstr.h core_cmInstr.h core_cmFunc.h core_cmFunc.h core_cm3.h core_<cpu>.h core_cm3_psoc5.h <device>.h Cm3RealView.scat (cm3gcc.ld) startup_<device>.s Cm3Start.c system_<device>.h system_<device>.c main.c cy_boot CMSIS v3.20 <user>.c/c++ CMSIS-CORE Device Files (Cypress) CMSIS-CORE Standard Files (ARM) User Program CMSIS custom version The following describe each file from the diagram: The Cm3Start.c and cm3gcc.ld files (part of the cy_boot component) contain Cortex-M3 device startup code and interrupt vector tables and completely substitute CMSIS startup_<device>.s template file. Vendor-specific device file <device>.h that includes CMSIS Core standard files is represented in cy_boot component by core_cm3_psoc5.h. The core_cmInstr.h file defines intrinsic functions to access special Cortex-M instructions and core_cmFunc.h file provides functions to access the Cortex-M core peripherals. These files were added since CMSIS Core version 2.0. The core_cm4_simd.h file added to the CMSIS SIMD Instruction Access is relevant for Cortex-M4 only. system_<device>.h, system_<device>.c – Generic files for system configuration (i.e. processor clock and memory bus system), are partially covered by Cm3Start.c. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 86 Startup and Linking Manual addition of the CMSIS Core files Beginning with PSoC Creator 2.2, the “Include CMSIS Core Peripheral Library Files” option is added to the System tab of the DWR file. By default, this option is enabled and CMSIS Core version 4.0 files are added to the project. This option should be disabled if you wish to manually add CMSIS Core files. Un-check “Include CMSIS Core Peripheral Library Files” option on the System tab of the DWR file to detach CMSIS 4.0 files from the cy_boot component. Add the following CMSIS Core files to the project: core_cmInstr.h core_cmFunc.h core_cm3.h Based on the CMSIS vendor-specific template file (<device>.h), create device header file, copy device specific definitions from core_cm3_psoc5.h file and add following definitions at the top of the file: #include <cytypes.h> #define __CHECK_DEVICE_DEFINES #define __CM3_REV 0x0201 #define __MPU_PRESENT #define __NVIC_PRIO_BITS #define __Vendor_SysTickConfig 0 3 0 Include the previously created vendor-specific device header file to the application. High-Level I/O Functions To use high-level input/output functions, like printf() or scanf(), the application must implement the base I/O functions. The base I/O API depends on compiler and used C library: Keil – Library Reference on keil.com GCC - Red Hat newlib C Library on sourceware.org/newlib. MDK/RVDS – The ARM C and C++ Libraries on infocenter.arm.com. MDK/RVDS - The ARM C Micro-library on infocenter.arm.com. The printf() Usage Model The printf() function formats a series of strings and numeric values and builds a string to write to the output stream. Its implementation relies on the following low-level library functions: Keil compiler use the putchar() GCC use _write() MDK/RVDS use _sys_write() or fputc(). The micro-library use fputc(). The application should implement these functions and call the communication component API to send data via selected interface. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 87 Startup and Linking Preservation of Reset Status PSoC 3/PSoC 5LP The value of the reset status register (RESET_SR0) is read and cleared any time the device is booted. That value is saved to a global SRAM variable. Note The imprecise power-on-reset (IPOR), precision power-on-reset (PRES), external reset (XRES), and low-voltage interrupt (LVI) reset sources clear the RESET_SR0 register. The watchdog reset (WRES) and software initiated reset (SRES) sources preserve the RESET_SR0 register. For more information, refer to the device datasheet and TRM. Note When the voltage detection is enabled and the configured threshold is below VDDA/VDDD during the software reset (SRES), the hardware reset (LVI reset) might occur. During the software reset, the LVI reset might get enabled (default state of the RESET_CR3 register) and hence the hardware reset might occur instead of the software reset. Some PSoC 3 devices perform an additional software reset. If any other than a software device reset previously occurred, it will reload the NVLs and apply the correct settings. This operation is transparent to the normal boot process and will not interfere with bootloading, debugging, or normal device functionality. See the device errata for more information. To retain user-defined status that persists through many resets, use the CY_RESET_GP0 and CY_RESET_GP1 bits in the RESET_SR0 register. The CyResetStatus variable is used to obtain value of these bits after a device reset. These bits are used by Bootloader and Bootloadable projects and cannot be used by user. uint8 CyResetStatus Name Description CY_RESET_WD CY_RESET_SW CY_RESET_GP0 CY_RESET_GP1 Watchdog reset Software reset General purpose bit 0 General purpose bit 1 API Memory Usage API memory usage varies significantly depending on the compiler, device, design-wide resource configuration, and component configuration used in the design. The following tables provide the memory usage for the entire empty project with the default design-wide resource configuration options. The measurements have been done with an associated compiler configured in Release mode with optimization set for Size. For a specific design, the map file generated by the compiler can be analyzed to determine the memory usage. The following data is provided for a blank design with default settings. Resource usage may increase if any of unused by default cy_boot APIs are used in some particular project. PSoC 3 (Keil PK51) Configuration Default Flash Bytes SRAM Bytes Stack 1792 95 2 ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 88 Startup and Linking PSoC 5LP (GCC) Configuration Flash Bytes SRAM Bytes Stack 1024 301 10 Default Performance Functions Execution Time The API execution time varies depending on the compiler, device, and design-wide resource configuration. The measurements have been done with the default compiler (PK51 for PSoC 3 device and GCC for all other devices) configured in Release mode with optimization set for Size. The project uses default designwide resource configuration for the measurements. The following table provides the numbers for the functions whose execution time is considered to have significant impact. PSoC 3 Description Min Typ Max Units Device initialization time (from reset to the main() entry) - 5.84 - ms The CyPmSaveClocks() function execution time - 398.0 - μs The CyPmRestoreClocks() function execution time - 1.036 - ms The CyPmSleep() function execution before Sleep mode entry - 57.90 - μs The CyPmSleep() function execution after Sleep mode exit - 30.48 - μs The CyWriteRowFull() function execution time - 10.74 - ms Min Typ Max Units Device initialization time (from reset to the main() entry) - 4.44 - ms The CyPmSaveClocks() function execution time - 1085 - cycles The CyPmRestoreClocks() function execution time - 2939 - cycles The CyPmSleep() function execution before Sleep mode entry - 619 - cycles The CyPmSleep() function execution after Sleep mode exit - 311 - cycles The CyWriteRowFull() function execution time - 12.1 - ms PSoC 5LP Description ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 89 Startup and Linking Critical Sections Duration The duration of critical sections (code sections with disabled interrupts) varies depending on the compiler, device and, design-wide resource configuration. The measurements have been done with the default compiler (PK51 for PSoC 3 device and GCC for all other devices) configured in Release mode with optimization set for Size. The project used default designwide resource configuration for the measurements. The following table provides the numbers for the functions whose critical section duration might have meaningful impact. PSoC 3 Description Conditions Min Typ Max Units The CyBusClk_SetDivider() function critical section time The CyDisableInts() function critical section time The CyEnableInts() function critical section time The CyPmSleep() function critical section time The CyPmHibernate() function critical section time Default Default Default Default Default - 34.16 62.5 48.8 82.32 103.7 - μs μs μs μs μs Description Conditions Min Typ Max Units The CyBusClk_SetDivider() function critical section time The CyDisableInts() function critical section time The CyEnableInts() function critical section time The CyFlushCache() function critical section time The CyPmSleep() function critical section time The CyPmHibernate() function critical section time Default Default Default Default Default Default - 144 56 47 93 932 1718 - cycles cycles cycles cycles cycles cycles PSoC 5LP ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 90 12 Watchdog Timer (WDT) APIs void CyWdtStart(uint8 ticks, uint8 lpMode) Description: Enables the watchdog timer. The timer is configured for the specified count interval, the CTW is cleared, the setting for low power mode is configured, and the watchdog timer is enabled. The hardware implementation of the watchdog timer prevents any modification of the timer once it has been enabled. It also prevents the timer from being disabled once it has been enabled. This protects the watchdog timer from changes caused by errant code. As a result, only the first call to CyWdtStart() after reset will have any effect. The watchdog counts each time the CTW reaches the period specified. The watchdog must be cleared using the CyWdtClear() function before the watchdog counts to three. The CTW is free running, so this will occur after between 2 and 3 timer periods elapse. arameters: ticks: One of the four available timer periods. Once WDT enabled, the interval cannot be changed. Define Time CYWDT_2_TICKS CYWDT_16_TICKS CYWDT_128_TICKS CYWDT_1024_TICKS 4 – 6 ms 32 – 48 ms 256 – 384 ms 2.048 – 3.072 s void CyWdtStart(uint8 ticks, uint8 lpMode) (continued) Parameters lpMode: Low power mode configuration. Define Effect CYWDT_LPMODE_NOCHANGE CYWDT_LPMODE_MAXINTER CYWDT_LPMODE_DISABLED No Change Switch to longest timer mode during sleep / hibernate Disable WDT during sleep / hibernate Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 91 Watchdog Timer (WDT) void CyWdtClear() Description: Clears (feeds) the watchdog timer. Parameters: None Return Value: None ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 92 13 MISRA Compliance This chapter describes the MISRA-C:2004 compliance and deviations for the PSoC Creator cy_boot component and code generated by PSoC Creator. MISRA stands for Motor Industry Software Reliability Association. The MISRA specification covers a set of 122 mandatory rules and 20 advisory rules that apply to firmware design and has been put together by the Automotive Industry to enhance the quality and robustness of the firmware code embedded in automotive devices. There are two types of deviations defined: project deviations – deviations that are applicable for all PSoC Creator components specific deviations – deviations that are applicable for the specific component This section provides information on the following items: Verification Environment Project Deviations Documentation Related Rules PSoC Creator Generated Sources Deviations cy_boot Component-Specific Deviations Verification Environment This section provides MISRA compliance analysis environment description. Component Name Version Test Specification MISRA-C:2004 Guidelines for the use of the C language in critical systems. PSoC 3 October 2004 Production PSoC 5LP Production PK51 9.51 GCC 4.8.4 Generation Tool PSoC Creator 3.2 MISRA Checking Tool Programming Research QA C source code analyzer for Windows 8.1-R Programming Research QA C MISRA-C:2004 Compliance Module (M2CM) 3.2 Target Device Target Compiler ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 93 MISRA Compliance The MISRA rules 1.5, 2.4, 3.3, and 5.7 are not enforced by Programming Research QA C. The compliance with these rules was verified manually by code review. Project Deviations A Project Deviations are defined as a permitted relaxation of the MISRA rules requirements that are applied for source code that is shipped with PSoC Creator. The list of deviated rules is provided in the table below. 1 MISRA-C: 2004 Rule Rule Class Rule Description [ 1] (R/A) Description of Deviation(s) 1.1 R This rule states that code shall conform to C ISO/IEC 9899:1990 standard. 5.1 R 5.7 A This rule says that both internal and external identifiers shall not rely on the significance of more than 31 characters. Verify that no identifier name should is reused. Some C language extensions (like interrupt keyword) relate to device hardware functionality and cannot be practically avoided. In the main.c file that is generate by PSoC Creator the non-standard main() declaration is used: “void main()”. The standard declaration is “int main()” The number of macro definitions exceeds 1024 - program does not conform strictly to ISO:C90. The length of names based on user-defined names depends on the length of the userdefine names. 8.7 R Objects shall be defined at block scope if they are only accessed from within a single function. 8.10 R 11.3 A All declarations and definitions of objects or functions at file scope shall have internal linkage unless external linkage is required. This rule states that cast should not be performed between a pointer type and an integral type. 14.1 R There shall be no unreachable code. Local variables with the same name may appear in different functions. Aside from commonly used names such as 'i', generated API functions for multiple instances of the same component will have identical local variable names. The object 'InstanceName_initVar' is only referenced by function 'InstanceName_Start', in the translation unit where it is defined. The intention of this publicly available global variable is to be used by user application. Components API are designed to be used in user application and might not be used in component API. The cast from unsigned int to pointer does not have any unintended effect, as it is a consequence of the definition of a structure based on hardware registers. Some functions that are part of the component API are not used within component API. Components API are designed to be used in user application and might not be used in component API. Required / Advisory ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 94 MISRA Compliance MISRA-C: 2004 Rule Rule Class Rule Description [ 1] (R/A) Description of Deviation(s) 21.1 R Some components in some specific configurations can contain redundant operations introduced because of generalized implementation approach. Minimization of run-time failures shall be ensured by the use of at least one of: a) static analysis tools/techniques; b) dynamic analysis tools/techniques; c) explicit coding of checks to handle run-time faults. Documentation Related Rules This section provides information on implementation-defined behavior of the toolchains supported by PSoC Creator. The list of deviated rules is provided in the table below. MISRA-C: 2004 Rule Rule Class Rule Description [1] (R/A) Description 1.3 R Multiple compilers and/or languages shall only be used if there is a common defined interface standard for object code to which the languages/compilers/assemblers conform. 1.4 R 1.5 A 3.1 R The compiler/linker shall be checked to ensure that 31 character significance and case sensitivity are supported for external identifiers. Rule states that floating-point implementation should comply with a defined floating-point standard. All usage of implementation-defined behavior shall be documented. No multiple compilers and languages can be used at a time for PSoC Creator projects. The PK51 linker produces OMF-51 object module format. The GCC linker produces EABI format files. The RVDS and MDK linkers produce files of ARM ELF format. PK51 and GCC treat more than 31 characters of internal and external identifier length, and are case sensitive (e.g., Id and ID are not equal). Floating-point arithmetic implementation conforms to IEEE-754 standard. 3.2 R The character set and the corresponding encoding shall be documented. 3.3 A 3.5 R 3.6 R This rule states that implementation of integer division should be documented. This rules requires implementation defined behavior and packing of bit fields be documented. All libraries used in production code shall be written to comply with the provisions of this document, and shall have been subject to appropriate validation. For the documentation on PK51 and GCC compilers, refer to the Help menu, Documentation sub-menu, Keil and GCC commands respectively. The Windows-1252 (CP-1252) character set encoding is used. Some characters that are used for source code generation in PSoC Creator are not included in character set, defined by ISO-IEC 9899-1900 "Programming languages — C". When dividing two signed integers, one of which is positive and one negative compiler rounds up with a negative remainder. The use of bit-fields is avoided. The C standard libraries provided with C51, GCC, and RVCT have not been reviewed for compliance. Some code uses memset and memcpy. The compiler may also insert calls to its vendor-specific compiler support library. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 95 MISRA Compliance PSoC Creator Generated Sources Deviations This section provides the list of deviations that are applicable for the code that is generated by PSoC Creator. The list of deviated rules is provided in the table below. MISRA-C: 2004 Rule Rule Class Rule Description [1] (R/A) 3.4 R 11.4 A 14.1 R 15.2 R 15.3 R 17.4 R 19.7 A Description of Deviation(s) All uses of the #pragma directive shall be documented. The #pragma directive is required to ensure that the C51 compiler produces efficient code for generated functions related to the AMuxSeq component. This rule states that cast should not be CYMEMZERO8 and CYCONFIGCPY8 use performed between a pointer to object void * arguments for compatibility with type and a different pointer to object memset/memcpy but must use a pointer to an type. actual type internally. Rule requires that there shall be no The CYMEMZERO, CYMEMZERO8, unreachable code. CYCONFIGCPY, CYCONFIGCPY8, CYCONFIGCPYCODE, and CYCONFIGCPYCODE8 are often but not always used. Switch cases must end with break The code structure is required to ensure that statements. the C51 compiler produces efficient code for generated functions related to the AMuxSeq component. default must be the last clause in a The code structure is required to ensure that switch statement. the C51 compiler produces efficient code for generated functions related to the AMuxSeq component. Array indexing shall be only allowed The CYMEMZERO8 and CYCONFIGCPY8 form of pointer arithmetic. have void * arguments for compatibility with memset/memcpy. The rule says that function shall be The CYMEMZERO, CYMEMZERO8, used instead of function-like macro. CYCONFIGCPY, CYCONFIGCPY8, CYCONFIGCPYCODE, and CYCONFIGCPYCODE8 macros are used to call cymemzero, cyconfigcpy, and cyconfigcpycode in a device-independent way. The macros cannot be converted to functions without significantly increasing the time and memory required for each function call (this is a limitation of C51). The macros have been converted to functions for GCC/RVCT. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 96 MISRA Compliance cy_boot Component-Specific Deviations [2] This section provides the list of cy_boot component specific-deviations. The list of deviated rules is provided in the table below. MISRA-C: 2004 Rule Rule Class [1] (R/A) Rule Description Description of Deviation(s) 6.3 A typedefs that indicate size and signedness should be used in place of the basic types. 8.7 R Objects shall be defined at block scope if they are only accessed from within a single function. 8.12 R 8.8 R When an array is declared with external linkage, its size shall be stated explicitly or defined implicitly by initialization. An external object or function shall be declared in one and only one file. For PSoC 5LP, the RealView C Library initialization function __main(void) in startup file (Cm0Start.c/Cm3Start.c) file returns value of basic type 'int'. For PSoC 5LP, the cySysNoInitDataValid variable is intentionally declared as global in Cm0Start.c/Cm3Start.c files to prevent linker from CY_NOINIT section removal. For PSoC 5LP (Cm0Start.c/Cm3Start.c), the __cy_regions array of structures is declared with unknown size. 10.1 R 10.3 R 14.3 R 11.4 A 11.5 14.7 2 R For the PSoC 5LP, some objects is being declared with external linkage in Cm3Start.c/Cm3Start.c file and this declaration is not in a header file. The value of an expression of integer PSoC 5LP: CMSIS Core: An integer constant type shall not be implicitly converted to of 'essentially unsigned' type is being a different underlying type under some converted to signed type on assignment in circumstances. CMSIS Core hardware abstraction layer. The value of a complex expression of The DMA API has a composite expression of integer type may only be cast to a type 'essentially unsigned' type (unsigned char) is that is narrower and of the same being cast to a wider unsigned type, 'unsigned signedness as the underlying type of long'. the expression. Before preprocessing, a null statement The CYASSERT() macro has null statement is shall only occur on a line by itself; it located close to other code. may be followed by a comment provided that the first character following the null statement is a whitespace character. A cast should not be performed The DMA and Interrupt API use casts between between a pointer to object type and a a pointer to object type and a different pointer different pointer to object type. to object type. A cast shall not be performed that The volatile qualification is lost during pointer removes any const or volatile cast to pointer to void before passing to the qualification from the type addressed memcpy() function. by a pointer. A function shall have a single point of The CyPmSleep() and CyPmHibernate() exit at the end of the function. functions has complex conditional structure and one more `return` path is added for PSoC 3/PSoC 5LP to return immediately if device is not ready for low power mode entry. The MISRA rules deviations of the CMSIS files are not documented here. Refer to the CMSIS documentation for the list of the deviated rules. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 97 MISRA Compliance MISRA-C: 2004 Rule Rule Class [1] (R/A) Rule Description 17.4 R Array indexing shall be the only allowed form of pointer arithmetic. 19.4 R 19.7 A 20.5 R Description of Deviation(s) The DMA, Flash and Interrupt APIs use array indexing that are applied to an object of pointer type to access hardware registers, buffer allocated by user and vector tables correspondingly. C macros shall only expand to a The CYASSERT(), braced initializer, a constant, a INTERRUPT_DISABLE_IRQ, parenthesized expression, a type INTERRUPT_ENABLE_IRQ, qualifier, a storage class specifier, or a CyGlobalIntEnable, and CyGlobalIntDisable do-while-zero construct. macro defines a braced code statement block. A function should be used in Deviated since function-like macros are used preference to a function-like macro. to allow more efficient code. The error indicator errno shall not be Caused by use of the error indicator errno used. used by the sbrk() function. It is used to report errors to the malloc() function if no heap memory is available. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 98 14 System Timer (SysTick) Functional Description The SysTick timer is part of the Cortex M3 (PSoC 5LP) devices. The timer is a down counter with a 24-bit reload/tick value that is clocked by the System clock. The timer has the capability to generate an interrupt when the set number of ticks expires and the counter is reloaded. This interrupt is available as part of the Nested Vectored Interrupt Controller (NVIC) for service by the CPU and can be used for general purpose timing control in user code. Since the timer is independent of the CPU (except for the clock), this can be handy in applications requiring precise timing that don’t have a dedicated timer/counter available for the job. Refer to the SysTick section (Section 4.4) of the ARM reference guide for complete details on the registers and their usage. APIs Functions Function Description CySysTickStart() CySysTickInit() CySysTickEnable() CySysTickStop() CySysTickEnableInterrupt() CySysTickDisableInterrupt() CySysTickSetReload() CySysTickGetReload() CySysTickGetValue() CySysTickSetClockSource() CySysTickGetCountFlag() CySysTickClear() CySysTickSetCallback() Configures and starts the SysTick timer. Configures the SysTick timer. Enables the SysTick timer and its interrupt. Stops the SysTick timer. Enables the SysTick interrupt. Disables the SysTick interrupt. Sets value the counter is set to on startup and after it reaches zero. Returns SysTick reload value. Gets current SysTick counter value. Sets the clock source for the SysTick counter. Returns the SysTick count flag value. Clears the SysTick counter for well-defined startup. Sets the address(es) to the function(s) that will be called on a SysTick interrupt. Gets the specified callback pointer. CySysTickGetCallback() ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 99 System Timer (SysTick) void CySysTickStart(void) Description: Configures the SysTick timer to generate an interrupt every 1 ms by calling the CySysTickInit() function and starts the timer by calling the CySysTickEnable() function. Refer to the corresponding function description for the details. Parameters: None Return Value: None Side Effects and Clears SysTick count flag if it was set. Restrictions: void CySysTickInit(void) Description: Initializes the callback addresses with pointers to NULL, associates the SysTick system vector with the function that is responsible for calling registered callback functions, configures SysTick timer to generate interrupt every 1 ms. Parameters: None Return Value: None Side Effects and Clears SysTick count flag if it was set. Restrictions: The 1 ms interrupt interval is configured based on the frequency determined by PSoC Creator at build time. If System clock frequency is changed in runtime, the CyDelayFreq() with the appropriate parameter should be called to ensure that actual frequency used for SysTick reload value calculation. void CySysTickEnable(void) Description: Enables the SysTick timer and its interrupt. Parameters: None Return Value: None Side Effects and Clears SysTick count flag if it was set. Restrictions: void CySysTickStop(void) Description: Stops the system timer (SysTick). Parameters: None Return Value: None Side Effects and Clears SysTick count flag if it was set. Restrictions: ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 100 System Timer (SysTick) void CySysTickEnableInterrupt(void) Description: Enables the SysTick interrupt. Parameters: None Return Value: None Side Effects and Clears SysTick count flag if it was set. Restrictions: void CySysTickDisableInterrupt(void) Description: Disables the SysTick interrupt. Parameters: None Return Value: None Side Effects and Clears SysTick count flag if it was set. Restrictions: void CySysTickSetReload(uint32 value) Description: Sets value the counter is set to on startup and after it reaches zero. Parameters: value: Counter reset value. Valid range [0x0-0x00FFFFFF]. For example, if the SysTick timer is configured to be clocked off the 48 MHz System Clock and interrupt every 100 us is desired, the function parameter should be 4,800 (48,000,000 Hz multiplied by 100/1,000,000 seconds). Return Value: None Side Effects and None Restrictions: uint32 CySysTickGetReload(void) Description: Returns SysTick reload value. Parameters: None Return Value: None Side Effects and Returns SysTick reload value. Restrictions: uint32 CySysTickGetValue(void) Description: Gets current SysTick counter value. Parameters: None Return Value: Returns SysTick counter value. Side Effects and None Restrictions: ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 101 System Timer (SysTick) void CySysTickSetClockSource(uint32 clockSource) Description: Sets the clock source for the SysTick counter. Parameters: uint32 clockSource: Constant Description CY_SYS_SYST_CSR_CLK_SRC_SYSCLK SysTick is clocked by the System clock. CY_SYS_SYST_CSR_CLK_SRC_LFCLK SysTick is clocked by the low frequency clock. (ILO 100 KHz for PSoC 5LP). Return Value: None Side Effects and Clears SysTick count flag if it was set. Restrictions: uint32 CySysTickGetCountFlag(void) Description: The count flag is set once SysTick counter reaches zero. The flag is cleared on read. Parameters: None Return Value: Returns non-zero value if the counter is set, otherwise zero is returned. Side Effects and Clears SysTick count flag if it was set. Restrictions: void CySysTickClear(void) Description: Clears the SysTick counter for well-defined startup. This function should be called if SysTick configuration (reload value or timer clock source) is changed. The function is called as part of the CySysTickStart() execution. Parameters: None Return Value: None Side Effects and None Restrictions: (void *) CySysTickSetCallback(uint32 number, void(*CallbackFunction)(void)) Description: This function allows up to five user -defined interrupt service routine functions to be associated with the SysTick interrupt. These are specified through the use of pointers to the function. Parameters: uint32 number: The number of the callback function addresses to be set. The valid range is from 0 to 4. void(*CallbackFunction(void): A pointer to the function that will be associated with the SysTick ISR for the specified number. Return Value: Returns the address of the previous callback function. NULL is returned if the specified function address in not initialized. Side Effects and The registered callback functions will be executed in the interrupt. Restrictions: ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 102 System Timer (SysTick) (void *) CySysTickGetCallback(uint32 number) Description: The function get the specified callback pointer. Parameters: uint32 number: The number of callback function address to get. The valid range is from 0 to 4. Return Value: Returns the address of the specified callback function. The NULL is returned if the specified address in not initialized. Side Effects and None Restrictions: Global Variables Function Description uint32 cySysTickInitVar Indicates whether or not the SysTick has been initialized. The variable is initialized to 0 and set to 1 the first time CySysTickStart() is called. This allows the component to restart without reinitialization after the first call to the CySysTickStart() routine. If reinitialization of the SysTick is required, call CySysTickInit() before calling CySysTickStart(). Alternatively, the SysTick can be reinitialized by calling the CySysTickInit() and CySysTickEnable() functions. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 103 15 cy_boot Component Changes Version 5.0 This section lists and describes the major changes in the cy_boot component version 5.0: Description of Version 5.0 Changes Reason for Changes / Impact New example projects for flash/EEPROM, voltage detection, interrupts, unique id have been added. System Reference Guide is now divided into This change was done for ease of use of content. System Reference Guide - PSoC 3/PSoC 5LP System Reference Guide - PSoC 4 System Reference Guide - DMA (PSoC 4) System Reference Guide - CyLFClk (PSoC 4) New CyGetUniqueID() function support for all PSoC The new API assists users in identifying each PSoC device on the field using an unique families. identification number. Updated CMSIS-Core version from 3.20 to 4.0. Removed the Bootloader Migration section. Section was for older versions of Creator and not applicable to v5.0. Added CyPmHibernateEx(uint16 wakeupSource) The function puts device into Hibernate mode with the following wake up source can be function. configured: PICU interrupt, Comparator0, Comparator1, Comparator2, and Comparator3 output. Function call CyPmHibernateEx(CY_PM_HIB_SRC_PICU) will act in the same way as CyPmHibernate(). Voltage Detect API: Updated implementation of the CyVdStickyStatus() and CyVdRealTimeStatus() functions to ensure that a zero is returned for bits not used in the mask parameter. Also, added the shadow register in CyVdStickyStatus() function, so only the bits passed in the parameter will be cleared. Voltage Detect API: Updated the section with the more detailed description of the API. Clarified the way associated interrupts should be handled. Voltage Detect API: Updated CyVdLvDigitEnable(), The Interrupt component’s API should be used to CyVdLvAnalogEnable() and register the interrupt service routine and to CyVdHvAnalogEnable() function to not enable enable/disable associated interrupt. corresponding interrupts. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 104 cy_boot Component Changes Description of Version 5.0 Changes Reason for Changes / Impact Voltage Detect API: Updated implementation of the CyVdLvDigitEnable(), CyVdLvAnalogEnable(), CyVdLvDigitDisable(), CyVdLvAnalogDisable(), CyVdHvAnalogEnable(), and CyVdHvAnalogDisable() functions to use CyVdStickyStatus() with the corresponding parameter instead of direct register read-back. The register is cleared on read. Flash API: Fixed the value of the CY_EEPROM_SIZEOF_ARRAY macro definition to report size of the EEPROM array instead of the size of the EEPROM section. PM API: Updated implementation of the CyPmReadStatus() function to ensure that a zero is returned for bits not used in the mask parameter. PM API: PSoC 5LP: Replaced 'asm' with '__asm'. DMA API: Masked lowest bit in the return value of the CyDmacError() as it is not used. PSoC 5LP: SysTick API: Fixed incorrect mask being applied in the CySysTickGetValue(). PSoC 5LP: Bootloader: Fixed the issue when bootloadable application was not allowed to be placed in the first available flash row when the “Manual application image placement” option is enabled in the Bootloadable component. Added support for the combination project type. See Bootloader component datasheet for the details. Corrected references to #defines in CySysTickSetClockSource() function Omit unintentional clearing of the status bits. To support -std GCC options. To ensure that correct values is returned. Added support for a new functionality of the Bootloader component. Version 4.20 This section lists and describes the major changes in the cy_boot component version 4.20: Description of Version 4.20 Changes Reason for Changes / Impact Added support for the PSoC 4100 BLE and PSoC 4200 BLE families. New device support. Added CySysClkSetLfclkSource() function for the LFCLK clock source selection. PSoC 3/PSoC5LP: Updated CyWriteRowFull() function implementation to return CYRET_BAD_PARAM if invalid parameters values are passed. PSoC 3: Fixed a defect that caused the CyResetStatus global variable to lose its value on bootloadable application entry. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 105 cy_boot Component Changes Description of Version 4.20 Changes PSoC 4: The implementation of the CY_SYS_PINS_READ_PIN macro was optimized in order to increase performance. PSoC 4100/PSoC 4200/PSoC 4100 BLE/ PSoC 4200 BLE: Updated implementation of the CySysClkIloStop() to ensure proper pulse length on LFCLK. PSoC 4100/PSoC 4200: WDT API: Fixed the defect in CySysWdtWriteClearOnMatch() that caused clear on match feature fails to be disabled. PSoC 4100/PSoC 4200/PSoC 4100 BLE/ PSoC 4200 BLE: Updated CySysPmStop() function implementation to match hardware requirements: the software delay was replaced with 2 register read-backs and corrected the procedure of the low power mode entry. PSoC 4100/PSoC 4200/PSoC 4100 BLE/ PSoC 4200 BLE: Fixed the order of the Stop mode entry in the CySysPmStop() function to ensure that Stop mode token is set at the beginning of the low power mode entry. Added following attribute macros: CY_PACKED, CY_PACKED_ATTR and CY_INLINE. The declaration of the IntDefaultHandler created in CyLib.h. PSoC 4000: Corrected the lower bound of the HFCLK frequency change from the current IMO frequency divided by 8 to divided by 4 in the wside effects section of the CySysFlashWriteRow() function. PSoC 3/ PSoC 5LP: Updated implementation of the CySetTemp() function in order to improve execution time of the first call after Power-On-Reset (POR). PSoC 4/PSoC 5LP: Added sbrk() function, which is used by malloc() and other heap-utilizing functions to check for available memory. PSoC 4/ PSoC 5LP: Added the following MISRA rule deviations: 20.5. Reason for Changes / Impact Omit the situation when GPIO pins remain frozen after the reset if reset occurred after IO pin freeze but before Stop mode entry. Previously, the IntDefaultHandler was declared in both interrupt source file and Cm0Start.c files. Significantly improved the first Flash write after POR. The fix ensures that malloc(), et al, now correctly handle heap overflow. Note that some projects will now fail to execute due to a lack of available heap. The resolution is to increase the heap size in the Design-Wide Resources System Editor (<project>.cydwr file), and re-build the project. Caused by use of the error indicator errno used by sbrk() function. It is used to report error to the malloc() function if no heap memory available. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 106 cy_boot Component Changes Description of Version 4.20 Changes Reason for Changes / Impact PSoC 4100/PSoC 4200/PSoC 4100 BLE/ PSoC 4200 BLE: • Updated CySysWdtEnable() function implementation to ensure that WDT is enabled upon function exit; • Updated CySysWdtWriteMatch() function implementation to ensure that match value is updated properly: add delay before (ensures that last update applied properly) and after value change (ensures that match update synchronization started). • Updated CySysWdtDisable() function implementation to ensure that WDT is disabled upon function exit. PSoC 4/PSoC 5LP: Updated IAR linker script file to eliminate warning generated by the IAR EW-ARM v7.10. PSoC 4: The CySysFlashWriteRow() function return To follow hardware-defined error codes. The basic behavior remains the same: zero for type changed from cystatus to uint32. success and non-zero for any type of failure. PSoC 5LP: The CyFlash_SetWaitCycles() function is updated with 80 MHz parts support. PSoC 4/PSoC 5LP: Added System Timer (SysTick) API. PSoC 3/PSoC 5LP: Flash/EEPROM API: updated No need to allocate buffer and pass it to implementation to eliminate requirement to call CySetFlashEEBuffer() for both Flash and CySetFlashEEBuffer() function, if the Flash ECC EEPROM programming. feature is disabled. PSoC 3/PSoC 5LP: Flash API: added Defined macros for the number of EEPROM CY_EEPROM_NUMBER_SECTORS and sectors and size of EEPROM sector. CY_EEPROM_SIZEOF_SECTOR. PSoC 4/PSoC 5LP: Interrupt API: added macros for the CyIntSetSysVector() and CyIntGetSysVector() functions exception type numbers. PSoC 3: The CyPmSleep() and CyPmHibernate() Satisfy interrupt controller usage model. functions disable clock to the interrupt controller before Sleep and Hibernate mode entry and reenable on wakeup. PSoC 3/PSoC 5LP: Updated CyFlash_Start() and To ensure that EEPROM and Flash are ready for CyEEPROM_Start() functions implementation. operation on corresponding function exit. PSoC 5LP: Changed CyFlushCache() To use Instruction Synchronization Barrier (ISB) instruction instead of multiple no operation implementation. instructions. PSoC 4: The CY_SYS_PINS_READ_PIN macro was optimized for the better performance. PSoC 4200/PSoC 4100: updated CySysClkWriteImoFreq() function for better performance. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 107 cy_boot Component Changes Description of Version 4.20 Changes Reason for Changes / Impact PSoC 4: Added the following MISRA rule deviations: 19.12 and 19.13. Added the possibility for existing PSoC 3 and PSoC 5LP per-pin APIs to be used in PSoC 4 designs. Updated the following MISRA rule deviations: 12.10, 12.13, 13.2, and 13.5. PSoC 4000: Update WDT API description to clarify that CySysWdtEnable() and CySysWdtDisable() correspondingly enables and disables the watchdog timer reset generation. PSoC 4000: Fixed the implementation of the CySysWdtReadIgnoreBits() to return correct number of the ignored bits in the WDT counter. PSoC 3/PSoC 5LP: removed LVI/HVI reset constants for the CyResetStatus global variable in section “Preservation of Reset Status”. PSoC 4100/PSoC 4200: Power Management API: Updated CySysPmDeepSleep() function to bypass the flash accelerator before Deep Sleep mode entry and restore it upon wakeup. The LVI and HVI resets are not reported by CyResetStatus variable. Cypress identified a defect with the Flash write functionality upon wakeup from deep-sleep in PSoC 4100 and PSoC 4200 devices. The corrupted data has the potential to be sent to the CPU on device wakeup. Version 4.11 This section lists and describes the major changes in the cy_boot component version 4.11: Description of Version 4.11 Changes Reason for Changes / Impact The CySysFlashWriteRow() function now checks the data to be written and, if necessary, modifies it to have a non-zero checksum. After writing to Flash, the modified data is replaced (Flash program) with the correct (original) data. Cypress identified a defect with the Flash write functionality of the PSoC 4000, PSoC 4100, and PSoC 4200 devices. The CySysFlashWriteRow() function in the cy_boot [v4.0 and v4.10] component fails to write a row of flash memory if the data to be written has a zero in the lower 32bits of the checksum. Version 4.10 This section lists and describes the major changes in the cy_boot component version 4.10: Description of Version 4.10 Changes Reason for Changes / Impact PSoC 4: Added CySysGetResetReason() function. Reports the cause for the latest reset(s) that occurred in the system. New device support. Added support for the PSoC 4000 family. PSoC 3: Added reentrancy support for the CySpcLock() and CySpcUnlock() functions. PSoC 3/ PSoC 5LP: Fixed the defect in CyPmRestoreClocks() function, that can might to the device halt during the function execution, in some clock system configurations, when PLL is not sourced by IMO and IMO is manually stopped by user code. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 108 cy_boot Component Changes Description of Version 4.10 Changes Reason for Changes / Impact PSoC 4: Added note that enabling or disabling a WDT requires three LFCLK cycles to come into effect, during that period the SYSCLK should be available. PSoC 4: Added note that, after waking from Deep Sleep, the WDT internal timer value is set to zero until the ILO loads the register with the correct value. The device should not put into Deep Sleep mode during that period. This led to an increase in low-power mode current consumption. The work around is to wait for the first positive edge of the ILO clock before allowing the WDT_CTR_* registers to be read by CySysWdtReadCount() function. Added note to the Working with Flash and EEPROM section with the information that CPU code execution can be halted till the flash write is complete. Added note to the Working with Flash and EEPROM section with the information that power manager will not put the device into a low power state if the system performance controller (SPC) is executing a command. PSoC 3 / PSoC 5LP: The CyPmRestoreClocks() implementation was enhanced by polling status and proceed as soon as PLL is locked. Added merge section to add ability of handling cases when predefined timeout is not enough. PSoC 4: Fixed a defect in CySysWdtClearInterrupt() that caused unintentional clearing of the WDT interrupt status bit. Version 4.0 This section lists and describes the major changes in the cy_boot component version 4.0: Description of Version 4.0 Changes Added note to the Flash and EEPROM section about unavailability of the Store Configuration Data in ECC Memory DWR option for the bootloader project type. Added note to the Working with Flash and EEPROM section that when writing Flash, data in the instruction cache can become stale. Fixed issue in the CyDmaChEnable() and CyDmaChDisable() functions. Removed references to PSoC 5 device. PSoC Creator Generated Sources Deviations section was updated with the MISRA deviations related to the AMuxSeq component. Reason for Changes / Impact Call CyFlushCache() to invalidate the data in cache and force fresh information to be loaded from Flash. If DMA request occurred during these functions, the DMA channels configuration could be corrupted. The APIs were changed to address this problem. PSoC 5 has been replaced by PSoC 5LP. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 109 cy_boot Component Changes Description of Version 4.0 Changes Reason for Changes / Impact The CY_IMO_FREQ_74MHZ parameter was added to the CyIMO_SetFreq() function. PSoC 4: Added CyExitCriticalSection() function call after WFI instruction in the CySysPmHibernate() function. Support of the 80 MHZ PSoC 5LP devices. If any interrupt occurred between CyEnterCriticalSection() and WFI instruction execution, the device could skip low power mode entry request and continue code execution with global interrupts disabled. Version 3.40 and Older Version 3.40 This section lists and describes the major changes in the cy_boot component version 3.40: Description of Version 3.40 Changes Reason for Changes / Impact Added PSoC 4 device support. PSoC 3: Updated CyPmSleep() function description with the information that hardware buzz must be disabled before sleep mode entry. New device support. Using hardware buzz in conjunction with other device wakeup sources can cause the device to lockup, halting further code execution. Refer to the device errata for more information. As hardware buzz is required for LVI, HVI, and Brown Out detect operations – they must be disabled before sleep mode entry and restored on wakeup. If LVI or HVI is enabled, CyPmSleep() will halt device if project is compiled in debug mode. Version 3.30 This section lists and describes the major changes in the cy_boot component version 3.30: Description of Version 3.30 Changes Updates to support PSoC Creator 2.2. Added MISRA Compliance section. Added Low Voltage Analog Boost Clocks section. Added requirement about interrupt configuration, when interrupt is sources from PICU and used as a wakeup event. The delay between Bus clock and analog clocks configuration save/restore moved from CyPmSleep() and CyPmHibernate() functions to CyPmSaveClocks() / CyPmRestoreClocks(). Reason for Changes / Impact New feature for the SC-based (TIA, Mixer, PGA and PGA_Inv) components. For PSoC 5LP, the interrupt component connected to the wakeup source may not use the "RISING_EDGE" detect option. Use the "LEVEL" option instead. This modification decrease CyPmSleep() and CyPmHibernate() functions execution time. The components that use analog clock must not be used after CyPmSaveClocks() execution till the clocks configuration will be restored by CyPmRestoreClocks(). Added float32 and float64 data types. The type float64 is not available for PSoC 3 devices. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 110 cy_boot Component Changes Version 3.20 This section lists and describes the major changes in the cy_boot component version 3.20: Description of Version 3.20 Changes Reason for Changes / Impact Many minor edits throughout the document to distinguish features of PSoC 5 and PSoC 5LP devices. The PSoC 5LP Alternate Active usage model was changed to be same as for PSoC 5. Improve PSoC 5 and PSoC 5LP documentation. The interface of the CyIMO_SetFreq() function was updated for PSoC 5LP to support 62 and 72 MHz frequencies. No parameters are used for CyPmAltAct(). That means NONE should be passed for the parameters. The device will go into Alternate Active mode until an enabled interrupt occurs. Added interface to configure IMO to 62 and 72 MHz on PSoC 5LP. Version 3.10 This section lists and describes the major changes in the cy_boot component version 3.10: Description of Version 3.10 Changes Reason for Changes / Impact The Bootloader system was redesigned in cy_boot version 3.0 to separate the Bootloader and Bootloadable components. The change is listed here as well for migrating from older versions. A few edits were applied to the Voltage Detect APIs: fixed a typo in the register definition, added CyVdLvDigitEnable() function threshold parameter mask to protect from invalid parameter values, updated CyVdLvDigitEnable() and CyVdLvAnalogEnable() functions to use delay instead of while loop during hardware initialization. Minor updates to the CyPmSleep() function. See Bootolader Migration section in cy_boot version 3.10 System Reference Guide. To improve the overall implementation of these APIs. Better support of latest PSoC 3 devices. Version 3.0 This section lists and describes the major changes in the cy_boot component version 3.0: Description of Version 3.0 Changes Reason for Changes / Impact The Bootloader system was redesigned to separate the Bootloader and Bootloadable components. The CyPmSleep() function implementation was updated to preserve/restore PRES state before/after Sleep mode. The support of the HVI/LVI functionality added. Added following Voltage Detect APIs: CyVdLvDigitEnable(),CyVdLvAnalogEnable(),CyVd LvDigitDisable(),CyVdLvAnalogDisable(),CyVdHvA nalogEnable(),CyVdHvAnalogDisable(),CyVdSticky Status() and CyVdRealTimeStatus(). The implementation of the Flash API was slightly modified as the SPC API used in Flash APIs was refactored. See Bootolader Migration section in cy_boot version 3.0 System Reference Guide. New functionality support. Added voltage monitoring APIs. The implementation quality improvements. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 111 cy_boot Component Changes Description of Version 3.0 Changes Reason for Changes / Impact The implementation of the CyXTAL_32KHZ_Start(), CyXTAL_32KHZ_Stop(), CyXTAL_32KHZ_ReadStatus() and CyXTAL_32KHZ_SetPowerMode() APIs was updated. The implementation of the CyXTAL_Start() function for PSoC 5 parts was changed. For more information on function see Clocking section. The following APIs were removed for PSoC 5 parts: CyXTAL_ReadStatus(), CyXTAL_EnableErrStatus(), CyXTAL_DisableErrStatus(), CyXTAL_EnableFaultRecovery(), CyXTAL_DisableFaultRecovery(). The CyDmacConfigure() function is now called by the startup code only if DMA component is placed onto design schematic. Added additional timeouts to ensure proper block start-up. The CyXTAL_32KHZ_ReadStatus() function implementation was changed by removing digital measurement status return. Updated description of following APIs: CyFlash_SetWaitCycles(). The address of the top of reentrant stack was decremented from CYDEV_SRAM_SIZE to (CYDEV_SRAM_SIZE - 3) for PSoC 3. The CyIMO_SetFreq() function implementation was updated by removing support of 74 and 62 MHz parameters for PSoC 5 parts. The minimal P divider value for the CyPLL_OUT_SetPQ() was risen from 4 up to 8. The CyXTAL_SetFbVoltage()/SetWdVoltage() were added for PSoC 5LP devices. The description of the CyWdtStart() was updated. Changes were made to make sure that MHZ XTAL starts successfully on PSoC 5 parts. The functionality provided within these APIs is not supported by the PSoC 5 part. Increase device startup time in case if DMA is not used within design. The CyDmacConfigure() function should be called manually if DMA functionality is used without DMA component. The analog status measurement is the only reliable source. Changes were made to improve power mode configuration. Prevent rewriting CyResetStatus variable with the parameters and/or local variables of the reentrant function during its execution. Removal of the functionality that is not supported by device. To meet hardware requirements The functionality provided by these APIs is available in PSoC 5LP. Added notes on WDT operation during low power modes for PSoC 5. The implementation of the CyPmSleep() for PSoC 5 Not putting CTW in reset state on wakeup allows to combine CTW usage in both Active and low was changed not to hold CTW in reset on wakeup. power modes for PSoC 5. The Preservation of Reset Status section was The software reset behavior of other resets is explained. Explained how the reset status updated with more detailed information. variable can be used. Updated description of following APIs: To reflect implementation better. CyMasterClk_SetDivider(),CyWdtStart(),CyWdtStart (). The Startup and Linking section was updated. The To provide more information on device operation. information on using custom linker script was added. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 112 cy_boot Component Changes Description of Version 3.0 Changes Reason for Changes / Impact Following macros were removed: CYWDT_TICKS CYWDT_CLEAR, CYWDT_ENABLE CYWDT_DISABLE_AUTO_FEED. The CyCpuClk_SetDivider() was removed for PSoC 5 devices. The cystrcpy(), cystrlen(), CyGetSwapReg16() and CySetSwapReg16() APIs were removed. The return value description for CyEnterCriticalSection() function was updated for PSoC 5. Added all APIs with the CYREENTRANT keyword when they are included in the .cyre file. The CyWdtStart() and CyWdtClear() should be used instead. The hardware does not support this functionality. The library functions should be used. Function returns 0 if interrupts were previously enabled or 1 if interrupts were previously disabled. Not all APIs are truly reentrant. Comments in the component API source files indicate which functions are candidates. This change is required to eliminate compiler warnings for functions that are not reentrant used in a safe way: protected from concurrent calls by flags or Critical Sections. Added PSoC 5LP support Version 2.40 and Older Version 2.40 This section lists and describes the major changes in the cy_boot component version 2.40: Description of Version 2.40 Changes Reason for Changes / Impact Updated the CyPmSleep() and CyPmHibernate() APIs. Changes were made to improve power mode configuration. Version 2.30 This section lists and describes the major changes in the cy_boot component version 2.30: Description of Version 2.30 Changes Reason for Changes / Impact CyIntEnable and CyIntDisable functions have been changed to be CYREENTRANT by default. Many components require CyIntEnable and CyIntDisable to be reentrant and these components have no way to cause that to happen. This means you no longer need to populate a cyre file for these functions that you do not call. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 113 cy_boot Component Changes Description of Version 2.30 Changes Reason for Changes / Impact The implementation of CyPmSleep() and CyPmAltActive() functions were modified by removing 32 KHz ECO,100 KHz and 1 KHz ILO power mode configuration before device low power mode entry. User was made responsible for clock power modes configuration during Sleep and Alternate Active mode. The implementation of the CyPmSaveClocks() was updated to set IMO clock frequency to 48 MHz when "Enable Fast IMO during startup" is enabled, and to 12 MHz otherwise. The IMO frequency is always set to 12 MHz just before the low power mode entry and restored immediately after wakeup. The CyPmRestoreClocks() restores original value of the IMO clock. The implementation of the CyPmRestoreClocks() function was updated by removing restoring MHz ECO and PLL disabled state. Global interrupts are disabled on CyPmSleep()/CyPmHibernate() entry and restored before return from the function. The CyPmSleep() and CyPmAltAct() function implementations for PSoC 5 devices were updated to ignore all parameters. The PSoC 5 device will go into Sleep mode until it is woken by an interrupt from one of three wakeup sources: CTW, Once per second, or Port Interrupt Controller (PICU). These wakeup sources must already be configured to generate an interrupt. The CTW is configured using the Sleep Timer component and the Once per second interrupt using the Real Time Clock component. Updated architecture- and silicon-specific #defines to be used across the content. Improved performance of non-DMA configuration on 8051 devices. The implementation of the CyPmRestoreClocks() was updated for PSoC 5 silicon. The megahertz crystal is given 130 ms to stabilize. Its readiness is not verified after the hold-off timeout. The power mode of the source clocks for the timer used as the wakeup timer was removed from PM API functions. PSoC Creator Power Management section was updated. The CyILO_SetPowerMode() and CyXTAL_32KHZ_SetPowerMode() can be used to configure clock power modes. The information regarding user responsibility of clock power mode configuration was added at the PM API section. The IMO value should match FIMO and FIMO is always 12 MHz. The CyPmRestoreClocks() function is expected to be called only after CyPmSaveClocks(), while the last one always disables MHz ECO and PLL. Interrupts are disabled to prevent their occurrence before the state of the device has been restored. The CyPmSleep() and CyPmAltAct() functions have to be used only with the following parameters: CyPmSleep(PM_SLEEP_TIME_NONE, PM_SLEEP_SRC_NONE) and CyPmAltAct(PM_ALT_ACT_TIME_NONE, PM_ALT_ACT_SRC_NONE). These modifications decrease the startup time and slightly reduce consumption of code memory and internal data memory. These modifications increase crystal startup time, but ensure that crystal is ready to be used. Before calling PM API function, you must manually configure the power mode of the source clocks for the timer that will be used as the wakeup timer. More detailed information on Power Management API usage was added. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 114 cy_boot Component Changes Version 2.21 Version 2.21 and older are obsolete. ® PSoC Creator™ PSoC 3/PSoC 5LP System Reference Guide, Document Number: 001-96074, Rev. ** 115