Component - Timer V2.20 Datasheet.pdf

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PSoC Creator™ Component Datasheet
Timer
2.20
Features
 Fixed-function (FF) and universal digital block (UDB)
implementations




8-, 16-, 24-, or 32-bit timer
Optional capture input
Enable, trigger, and reset inputs, for synchronizing with other components
Continuous or one shot run modes
General Description
The Timer component provides a method to measure intervals. It can implement a basic timer
function and offers advanced features such as capture with capture counter and interrupt/DMA
generation.
This component can be implemented using FF blocks or UDBs. A UDB implementation typically
has more features than an FF implementation. If your design is simple enough, consider using
FF and save UDB resources for other purposes.
The following table shows the major feature differences between FF and UDB. There are also
many specific functional differences between the FF and UDB implementations and differences
between the FF implementation in different devices. See the Configurations section for detailed
timing waveforms for the various implementations.
Feature
FF
UDB
Number of bits
8 or 16
8, 16, 24, or 32
Run mode
Continuous or one shot
Continuous, one shot, or one shot halt on interrupt
Count mode
Down only
Down only
Enable input
Yes (hardware or software enable)
Yes (hardware or software enable)
Capture input
Yes
Yes
Capture mode
Rising edge only
Rising edge, falling edge, either edge, or software
controlled
Capture FIFO
No (one capture register)
Yes (up to four captures)
Trigger input
No
Yes
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-73563 Rev. **
Revised November 11, 2011
®
Timer
PSoC Creator™ Component Datasheet
Feature
FF
UDB
Trigger mode
None
Rising edge, falling edge, either edge, or software
controlled
Reset input
Yes
Yes
Terminal count output
Yes
Yes
Interrupt output
Yes (PSoC 3 only)
Yes
Interrupt conditions
TC, capture
TC, capture, and FIFO full
Capture output
No
Yes
Period register
Yes
Yes
Period reload
Yes (always reload on reset or TC)
Yes (always reload on reset or TC)
Clock input
Limited to digital clocks in the clock Any signal
system
When to Use a Timer
The default use of the Timer is to generate a periodic event or interrupt signal. However, there
are other potential uses:

Create a clock divider by driving a clock into the clock input and using the terminal count
output as the divided clock output.

Measure the length of time between hardware events by driving a clock into the clock input
and driving the test signal to the enable or capture input.
Note A Counter component is better used in situations focused on counting events. A PWM
component is better used in situations requiring multiple compare outputs with more control
features like center alignment, output kill, and dead band outputs.
A Timer is typically used to record the number of clock cycles between events. An example of
this is measuring the number of clocks between two rising edges as might be generated by a
tachometer sensor. A more complex use is to measure the period and duty cycle of a PWM
input. For PWM measurement, the Timer component is configured to start on a rising edge,
capture the next falling edge, and then capture and stop on the next rising edge. An interrupt on
the final capture signals the CPU that all of the captured values are ready in the FIFO.
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PSoC Creator™ Component Datasheet
Timer
Input/Output Connections
This section describes the various input and output connections for the Timer. Some I/Os may
be hidden on the symbol under the conditions listed in the description of that I/O.
Note All signals are active high unless otherwise specified.
Input
May Be
Hidden
Description
clock
N
The clock input defines the operating frequency of the Timer component. That is, the timer
period counter value is decremented on the rising edge of this input while the Timer
component is enabled.
reset
N
This input is a synchronous reset. It requires at least one rising edge of the clock to implement
the resets of the counter value and the capture counter. It resets the period counter to the
period value. It also resets the capture counter.
enable
Y
This input is the Timer hardware enable. This connection enables the period counter to
decrement on each rising edge of the clock. If this input is low the outputs are still active but
the Timer component does not change states. This input is visible when the Enable Mode
parameter is set to Hardware Only or Software and Hardware.
capture
Y
The capture input captures the current count value to a capture register or FIFO. The input is
visible if the Capture Mode parameter is set to any mode other than None. Capture may take
place on a rising edge, falling edge, or either edge applied to this input, depending on the
Capture Mode setting. The capture input is sampled on the clock input. No values are
captured if the Timer is disabled. The capture input may be left floating with no external
connection. If nothing is connected to the capture line, the component will assign it a constant
logic 0.
trigger
Y
The trigger input enables the timer to start and stop counting based on configurable hardware
events. The input is visible if the Trigger Mode parameter is set to any mode other than
None. It causes the Timer to delay counting until the appropriate edge is detected. The trigger
edge is not captured nor does it generate an interrupt.
Output
May Be
Hidden
Description
tc
N
Terminal count is a synchronous output that indicates that the count value equals zero.
The output is synchronous to the clock input of the Timer. The exact timing of this output
depends on the device and whether a UDB or FF implementation is used.
interrupt
N
The interrupt output is driven by the interrupt sources configured in the hardware. All
sources are ORed together to create the final output signal. The sources of the interrupt
can be: Terminal Count, Capture, or FIFO full.
After an interrupt is triggered, the interrupt output remains asserted until the status
register is read.
The interrupt connection is not supported for the FF implementation on PSoC 5. If you
need this functionality, you can connect an interrupt component to the tc signal or you
can use the UDB implementation.
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Timer
Output
PSoC Creator™ Component Datasheet
May Be
Hidden
capture_out Y
Description
The capture_out output is an indicator of when a hardware capture has been triggered.
This signal is available for the UDB implementation only. This output is synchronized to
the clock input of the Timer.
Schematic Macro Information
The default Timer in the Component Catalog is a schematic macro using a Timer component
with default settings. It is connected to bus clock and a Logic Low component.
Component Parameters
Drag a Timer onto your design and double-click it to open the Configure dialog.
Hardware versus Software Configuration Options
Hardware configuration options change the way the project is synthesized and placed in the
hardware. You must rebuild the hardware if you make changes to any of these options. Software
configuration options do not affect synthesis or placement. When setting these parameters
before build time you are setting their initial values. These may be modified at any time with the
APIs provided. Most parameters described in the next sections are hardware options. The
software options are noted as such.
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PSoC Creator™ Component Datasheet
Timer
Configure Tab
Resolution
The Resolution parameter defines the bit-width resolution of the Timer. This value may be set to
8, 16, 24, or 32 for maximum count values of 255, 65535, 16777215, and 4294967295
respectively. For FF implementations, the resolution is limited to 8 or 16 bits.
Implementation
The Implementation parameter allows you to choose between a fixed-function block
implementation and a UDB implementation of the Timer. If FF is selected, UDB functions are
disabled.
Period (Software Option)
The Period parameter defines the period of the counter. The max count value (or rollover point)
for the Timer component is equal to the Period minus one. The Period minus one is the initial
value loaded into the period register. The software can change this register at any time with the
Timer_WritePeriod() API. To get the equivalent result using this API, the Period value from the
customizer, minus one, must be used as the argument in the function.
The limits of this value are defined by the Resolution parameter. For 8-, 16-, 24-, and 32-bit
Resolution, the Period is: 2^8, 2^16, 2^24, and 2^32 or 256, 65536, 16777216, and
4294967296 respectively.
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Timer
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PSoC Creator™ Component Datasheet
Trigger Mode (Software Option)
The Trigger Mode parameter configures the implementation of the trigger input. This parameter
is only active when Implementation is set to UDB.
Trigger Mode can be set to any of the following values:





None (default) – No trigger implemented and the trigger input pin is hidden
Rising Edge – Trigger (enable) counting on the first rising edge of the trigger input
Falling Edge – Trigger (enable) counting on the first falling edge of the trigger input
Either Edge – Trigger (enable) counting on the first edge (rising or falling) of the trigger input
Software Controlled – The trigger mode can be set during run time, to one of the four trigger
modes listed above, using the Timer_SetTriggerMode() API call. The default trigger is None
until another value is set using this API.
Capture Mode (Software Option)
The Capture Mode section contains three parameters: Capture Mode Value, Enable Capture
Counter, and Capture Count.
Capture Mode
The Capture Mode parameter configures when a capture takes place. The capture input is
sampled on the rising edge of the clock input. This mode can be set to any of the following
values (for the fixed-function implementation, only None and Rising Edge are available):


None – No capture implemented and the capture input pin is hidden
Rising Edge – Capture the counter value on a rising edge of the capture input with respect to
the clock input.

Falling Edge – Capture the counter value on a falling edge of the capture input with respect
to the clock input.

Either Edge – Capture the counter value on either edge of the capture input with respect to
the clock input.

Software Controlled – The capture mode can be set during run time, to one of the four
capture modes listed above, using the Timer_SetCaptureMode() API call. The default trigger
is None until another value is set using this API.
Enable Capture Counter (Software Option)
The Enable Capture Counter parameter allows you to define how many capture events happen
before the counter is actually captured. For example, it may be necessary to capture every third
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PSoC Creator™ Component Datasheet
Timer
event, in which case you should set the capture counter to a value of 3. This parameter is only
available for a UDB implementation.
Capture Count (Software Option)
The Capture Count parameter sets the initial number of capture events that occur before the
counter is actually captured. It can be set to a value from 2 to 127. The capture count value may
be modified at run time by calling the API function Timer_SetCaptureCount(). This parameter is
only available for a UDB implementation.
Enable Mode
The Enable Mode parameter configures the enable implementation of the Timer. The enable
input is sampled on the rising edge of the clock input. This mode can be set to any of the
following values:



Software Only – The Timer is enabled based on the enable bit of the control register only.
Hardware Only – The Timer is enabled based on the enable input only. (UDB only)
Software and Hardware – The Timer is enabled if both hardware and software enables are
true.
Run Mode
The Run Mode parameter allows you to configure the Timer component to run continuously or in
a one-shot mode:



Continuous – The Timer runs continuously while it is enabled.
One Shot – The Timer starts counting and stops counting when zero is reached. After it is
reset, it begins another cycle. On stop, for a UDB Timer, it reloads Period into the count
register; for a fixed-function Timer the count register remains at terminal count.
One Shot (Halt on Interrupt) – The Timer starts counting and stops counting when zero is
reached or an interrupt occurs. After it is reset, it begins another cycle. On stop, for a UDB
Timer, it reloads Period into the count register; for a fixed-function Timer the count register
remains at terminal count.
Note In order to be sure that One Shot mode does not start prematurely, you should use a
Trigger Mode to control the start time, or use some form of software enable mode (Software
Only or Software and Hardware).
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Timer
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PSoC Creator™ Component Datasheet
Interrupt (Software Option)
The Interrupt parameters allow you to configure the initial interrupt sources. An interrupt is
generated when one or more of the following selected events occur. The software can
reconfigure this mode at any time; this parameter defines an initial configuration.



On TC –This parameter is always active; it is cleared by default.
On Capture (1-4) – Allows you to interrupt on a given number of captures; it is cleared by
default.
On FIFO Full – Allows you to interrupt when the capture FIFO is full; it is cleared by default.
Clock Selection
See the Clock component datasheet and the appropriate device datasheet for more details on
the PSoC 3 or PSoC 5 clocking system.
Fixed-Function Components
When configured to use the FF block in the device, the Timer component has the following
restrictions:


The clock input must be a digital clock from the clock system.
If the frequency of the clock is to be the same as bus clock, then the clock must actually be
the bus clock.
Open the Configure dialog of the appropriate Clock component to configure the Clock Type
parameter as Existing and the Source parameter as BUS_CLK. A clock at this frequency
cannot be divided from any other source, such as the master clock, IMO, and so on.
For UDB-based Components
You can connect any digital signal from any source to the clock input. The frequency of that
signal is limited to the frequency range defined in the DC and AC Electrical Characteristics (UDB
Implementation) section of this datasheet.
Placement
PSoC Creator places the Timer component in the device based on the Implementation
parameter. If it is set to Fixed Function, this component is placed in any available FF
counter/timer block. If it is set to UDB, this component is placed within the UDB array in the best
possible configuration.
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PSoC Creator™ Component Datasheet
Timer
Resources
API Memory
(Bytes)
Digital Blocks
Resolution
Datapaths
Macro
cells
Status
Registers
Control
Registers
Counter7
Flash
RAM
Pins (per
External I/O)
8-bit UDB
1
Timer
1
6
1
1
0
257
5
-
8-bit FF
2
Time r
0
0
0
0
0
234
2
-
16-bit UDB
1
Timer
2
6
1
1
0
295
6
-
16-bit FF
2
Timer
0
0
0
0
0
248
2
24-bit UDB
1
Timer
3
6
1
1
0
287
8
-
32-bit UDB
1
Timer
4
6
1
1
0
287
8
-
8-bit UDB
Timer One
3
Shot
1
8
1
1
0
257
5
-
16-bit UDB
Timer One
3
Shot
2
8
1
1
0
295
6
-
1
The UDB Timer with corresponding resolution is configured for Software Only Enable mode, Rising Edge Trigger mode,
Continuous Run mode and Interrupt on TC with no Capture mode.
2
The FF Timer with corresponding resolution is configured for Software Only Enable mode, Rising Edge Capture mode,
Continuous Run mode and Interrupt on TC.
3
The UDB Timer with corresponding resolution is configured for Software Only Enable mode, Rising Edge Trigger mode, One
Shot mode Interrupt on TC with no Capture mode.
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Timer
PSoC Creator™ Component Datasheet
Application Programming Interface
Application Programming Interface (API) routines allow you to configure the component using
software. The following table lists and describes the interface to each function. The subsequent
sections cover each function in more detail.
By default, PSoC Creator assigns the instance name “Timer_1” to the first instance of a
component in a given design. You can rename it to any unique value that follows the syntactic
rules for identifiers. The instance name becomes the prefix of every global function name,
variable, and constant symbol. For readability, the instance name used in the following table is
“Timer”.
Function
Description
Timer_Start()
Sets the initVar variable, calls the Timer_Init() function, and then calls
the Enable function.
Timer_Stop()
Disables the Timer.
Timer_SetInterruptMode()
Enables or disables the sources of the interrupt output.
Timer_ReadStatusRegister()
Returns the current state of the status register.
Timer_ReadControlRegister()
Returns the current state of the control register.
Timer_WriteControlRegister()
Sets the bit-field of the control register.
Timer_WriteCounter()
Writes a new value directly into the counter register. (UDB only)
Timer_ReadCounter()
Forces a capture, and then returns the capture value.
Timer_WritePeriod()
Writes the period register.
Timer_ReadPeriod()
Reads the period register.
Timer_ReadCapture()
Returns the contents of the capture register or the output of the FIFO.
Timer_SetCaptureMode()
Sets the hardware or software conditions under which a capture will
occur.
Timer_SetCaptureCount()
Sets the number of capture events to count before capturing the counter
register to the FIFO.
Timer_ReadCaptureCount()
Reports the current setting of the number of capture events.
Timer_SoftwareCapture()
Forces a capture of the counter to the capture FIFO
Timer_SetTriggerMode()
Sets the hardware or software conditions under which a trigger will
occur.
Timer_EnableTrigger()
Enables the trigger mode of the timer.
Timer_DisableTrigger()
Disables the trigger mode of the timer.
Timer_SetInterruptCount()
Sets the number of captures to count before an interrupt is triggered.
Timer_ClearFIFO()
Clears the capture FIFO.
Timer_Sleep()
Stops the Timer and saves its current configuration.
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PSoC Creator™ Component Datasheet
Timer
Function
Description
Timer_Wakeup()
Restores the Timer configuration and re-enables the Timer.
Timer_Init()
Initializes or restores the Timer per the Configure dialog settings.
Timer_Enable()
Enables the Timer.
Timer_SaveConfig()
Saves the current configuration of the Timer.
Timer_RestoreConfig()
Restores the configuration of the Timer.
Global Variables
Variable
Description
Timer_initVar Indicates whether the Timer has been initialized. The variable is initialized to 0 and set to 1 the first
time Timer_Start() is called. This allows the component to restart without reinitialization after the
first call to the Timer_Start() routine.
If reinitialization of the component is required, then the Timer_Init() function can be called before
the Timer_Start() or Timer_Enable() function.
void Timer_Start(void)
Description:
This is the preferred method to begin component operation. Timer_Start() sets the initVar
variable, calls the Timer_Init() function, and then calls the Timer_Enable() function.
Parameters:
None
Return Value:
None
Side Effects:
If the initVar variable is already set, this function only calls the Timer_Enable() function.
void Timer_Stop(void)
Description:
For fixed-function implementations this disables the Timer and powers it down. For UDB
implementations the Timer is disabled only in software enable modes.
Parameters:
None
Return Value:
None
Side Effects:
Because fixed-function Timers are powered down by this function, the TC output will be driven
low.
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Timer
PSoC Creator™ Component Datasheet
void Timer_SetInterruptMode(uint8 interruptMode)
Description:
Enables or disables the sources of the interrupt output.
Parameters:
uint8: Interrupt sources. For bit definitions, refer to the Mode Register section of this
datasheet.
Return Value:
None
Side Effects:
The bit locations are different between FF and UDB. Mask #defines are provided to
encapsulate the differences.
uint8 Timer_ReadStatusRegister(void)
Description:
Returns the current state of the status register.
Parameters:
None
Return Value:
uint8: Current status register value
For bit definitions, refer to the Status Register section of this datasheet.
Side Effects:
Some of these bits are cleared when status register is read. Clear-on-read bits are defined in
the Status Register section of this datasheet.
uint8 Timer_ReadControlRegister(void)
Description:
Returns the current state of the control register. This API is not available in the special case
when the control register is not required (UDB implementation, enable mode is hardware
only, capture mode not software controlled, and trigger mode not software controlled).
Parameters:
None
Return Value:
uint8: Control register bit field
For bit definitions, refer to the Control Register section of this datasheet.
Side Effects:
None
void Timer_WriteControlRegister(uint8 control)
Description:
Sets the bit field of the control register. This API is not available in the special case when the
control register is not required (UDB implementation, enable mode is hardware only, capture
mode not software controlled, and trigger mode not software controlled).
Parameters:
uint8: Control register bit field
For bit definitions, refer to the Control Register section of this datasheet.
Return Value:
None
Side Effects:
None
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PSoC Creator™ Component Datasheet
Timer
void Timer_WriteCounter(uint8/16/32 counter)
Description:
Writes a new value directly into the counter register. This function is available only for the
UDB implementation.
Parameters:
uint8/16/32: New counter value. For 24-bit Timers, the parameter is uint32.
Return Value:
None
Side Effects:
Overwrites the counter value. This can cause undesired behavior on the terminal count
output or period width. This is not an atomic write and the function may be interrupted. The
Timer should be disabled before calling this function.
uint8/16/32 Timer_ReadCounter(void)
Description:
Forces a capture, and then returns the capture value.
Parameters:
None
Return Value:
uint8/16/32: Current counter value. For 24-bit Timers, the return type is uint32.
Side Effects:
Returns the contents of the capture register or the output of the FIFO (UDB only).
void Timer_WritePeriod(uint8/16/32 period)
Description:
Writes the period register.
Parameters:
uint8/16/32: New period value. For 24-bit Timers, the parameter is uint32.
Return Value:
None
Side Effects:
The period of the Timer does not change until the counter is reloaded from the period
register.
uint8/16/32 Timer_ReadPeriod(void)
Description:
Reads the period register.
Parameters:
None
Return Value:
uint8/16/32: Current period value. For 24-bit Timers, the return type is uint32.
Side Effects:
None
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Timer
PSoC Creator™ Component Datasheet
uint8/16/32 Timer_ReadCapture(void)
Description:
Returns the contents of the capture register or the output of the FIFO (UDB).
Parameters:
None
Return Value:
uint8/16/32: Current capture value. For 24-bit Timers, the return type is uint32.
Side Effects:
In the UDB implementation, the value is removed from the FIFO.
void Timer_SetCaptureMode(uint8 captureMode)
Description:
Sets the capture mode. This function is available only for the UDB implementation and when
the Capture Mode parameter is set to Software Controlled.
Parameters:
uint8: Enumerated capture mode. Refer also to the Control Register section:
Timer__B_TIMER__CM_NONE
Timer__B_TIMER__CM_RISINGEDGE
Timer__B_TIMER__CM_FALLINGEDGE
Timer__B_TIMER__CM_EITHEREDGE
Timer__B_TIMER__CM_SOFTWARE
Return Value:
None
Side Effects:
None
void Timer_SetCaptureCount(uint8 captureCount)
Description:
Sets the number of capture events to count before a capture is performed. This function is
available only for the UDB implementation and when the Enable Capture Counter
parameter is selected in the Configure dialog.
Parameters:
uint8 captureCount: The number of capture events you want to count before capturing the
counter value to the capture FIFO. A value from 2 to 127 is valid.
Return Value:
None
Side Effects:
None
uint8 Timer_ReadCaptureCount(void)
Description:
Reads the current value setting for the captureCount parameter as set in the
Timer_SetCaptureCount() function. This function is only available for the UDB
implementation and when the Enable Capture Counter parameter is selected in the
Configure dialog.
Parameters:
None
Return Value:
uint8: Current capture count
Side Effects:
None
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PSoC Creator™ Component Datasheet
Timer
void Timer_SoftwareCapture(void)
Description:
Forces a software capture of the current counter value to the FIFO. This function is available
only for UDB implementation.
Parameters:
None
Return Value:
None:
Side Effects:
None
void Timer_SetTriggerMode(uint8 triggerMode)
Description:
Sets the trigger mode. This function is available only for UDB implementation and when
Trigger Mode parameter is set to Software Controlled.
Parameters:
uint8: Enumerated capture mode. Refer also to the Control Register section.
Timer__B_TIMER__TM_NONE
Timer__B_TIMER__TM_RISINGEDGE
Timer__B_TIMER__TM_FALLINGEDGE
Timer__B_TIMER__TM_EITHEREDGE
Timer__B_TIMER__TM_SOFTWARE
Return Value:
None
Side Effects:
None
void Timer_EnableTrigger(void)
Description:
Enables the trigger. This function is available only when Trigger Mode is set to Software
Controlled.
Parameters:
None
Return Value:
None
Side Effects:
None
void Timer_DisableTrigger(void)
Description:
Disables the trigger. This function is available only when Trigger Mode is set to Software
Controlled.
Parameters:
None
Return Value:
None
Side Effects:
None
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Timer
PSoC Creator™ Component Datasheet
void Timer_SetInterruptCount(uint8 interruptCount)
Description:
Sets the number of captures to count before an interrupt is generated for the
InterruptOnCapture source. This function is available only when InterruptOnCaptureCount is
enabled.
Parameters:
uint8 interruptCount: The number of capture events to count before the interrupt on capture
is generated. A value from 0 to 3 is valid.
Return Value:
None
Side Effects:
None
void Timer_ClearFIFO(void)
Description:
Clears the capture FIFO. This function is available only for the UDB implementation. Refer to
UDB FIFOs in the Functional Description section of this datasheet.
Parameters:
None
Return Value:
None
Side Effects:
None
void Timer_Sleep(void)
Description:
This is the preferred routine to prepare the component for sleep. Timer_Sleep() saves the
current component state. Then it calls the Timer_Stop() function and calls
Timer_SaveConfig() to save the hardware configuration.
Call the Timer_Sleep() function before calling the CyPmSleep() or the CyPmHibernate()
function. Refer to the PSoC Creator System Reference Guide for more information about
power-management functions.
Parameters:
None
Return Value:
None
Side Effects:
For the FF implementation, all registers are retained across low-power modes. For the UDB
implementation, the control register and counter value register are saved and restored.
Additionally when calling Timer_Sleep(), the enable state is stored in case you call
Timer_Sleep() without calling Timer_Stop().
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PSoC Creator™ Component Datasheet
Timer
void Timer_Wakeup(void)
Description:
This is the preferred routine to restore the component to the state when Timer_Sleep() was
called. The Timer_Wakeup() function calls the Timer_RestoreConfig() function to restore the
configuration. If the component was enabled before the Timer_Sleep() function was called,
the Timer_Wakeup() function also re-enables the component.
Parameters:
None
Return Value:
None
Side Effects:
Calling the Timer_Wakeup() function without first calling the Timer_Sleep() or
Timer_SaveConfig() function may produce unexpected behavior.
void Timer_Init(void)
Description:
Initializes or restores the component according to the customizer Configure dialog settings.
It is not necessary to call Timer_Init() because the Timer_Start() routine calls this function
and is the preferred method to begin component operation..
Parameters:
None
Return Value:
None
Side Effects:
All registers will be set to values according to the customizer Configure dialog.
void Timer_Enable(void)
Description:
Activates the hardware and begins component operation. It is not necessary to call
Timer_Enable() because the Timer_Start() routine calls this function, which is the preferred
method to begin component operation. This function enables the Timer for either of the
software controlled enable modes.
Parameters:
None
Return Value:
None
Side Effects:
If the Enable Mode parameter is set to Hardware Only, this function has no effect on the
operation of the Timer.
void Timer_SaveConfig(void)
Description:
This function saves the component configuration and nonretention registers. It also saves
the current component parameter values, as defined in the Configure dialog or as modified
by appropriate APIs. This function is called by the Timer_Sleep() function.
Parameters:
None
Return Value:
None
Side Effects:
None
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Page 17 of 46
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Timer
PSoC Creator™ Component Datasheet
void Timer_RestoreConfig(void)
Description:
This function restores the component configuration and nonretention registers. It also
restores the component parameter values to what they were before calling the Timer_Sleep()
function.
Parameters:
None
Return Value:
None
Side Effects:
Calling this function without first calling the Timer_Sleep() or Timer_SaveConfig() function
may produce unexpected behavior.
Sample Firmware Source Code
PSoC Creator provides many example projects that include schematics and example code in the
Find Example Project dialog. For component-specific examples, open the dialog from the
Component Catalog or an instance of the component in a schematic. For general examples,
open the dialog from the Start Page or File menu. As needed, use the Filter Options in the
dialog to narrow the list of projects available to select.
Refer to the “Find Example Project” topic in the PSoC Creator Help for more information.
Functional Description
As described previously, the Timer component can be configured for multiple uses. This section
describes those configurations in more detail.
General Operation
On each rising edge of the clock input, the Timer component always counts down. It reloads the
counter register from the period register on the next clock edge after the counter reaches a value
of zero.
The timer remains disabled until enabled by hardware or software, depending on the
configuration setting. You cannot use the component until Timer_Start() is called because this
function sets the registers for the defined configuration.
Timer Outputs
The counter register can be monitored and reloaded. The tc output is available to monitor the
current value of the counter register; it is high while the counter is zero.
Page 18 of 46
Document Number: 001-73563 Rev. **
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PSoC Creator™ Component Datasheet
Timer
Timer Inputs
A capture operation can be done in either hardware or firmware. The current value in the counter
register is copied into either a capture register or a FIFO. Firmware can then read the captured
value at a later time.
Reset and enable features allow the Timer component to be synchronized to other components.
The Timer component counts only when enabled and not held in reset. Counting can also be
initiated on a trigger input event. It can be reset or enabled by either hardware or firmware. All
triggering is hardware.
Note All of the inputs for the FF Timer implementations (capture, reset, and enable) are double
synchronized in the FF Timer. The synchronizer is run at BUS_CLK speed. This results in a
delay between when these signals are applied and when they take effect. The delay depends on
the ratio between BUS_CLK and the clock that runs the Timer. All waveforms shown for the FF
implementations show the signal after it has been synchronized.
Timer Interrupt
An interrupt output is available to communicate event occurrences to the CPU or to other
components. You can set the interrupt to be active on a combination of one or more events. You
should design the interrupt handler carefully so that you can determine the source of the interrupt
and whether it is edge- or level-sensitive, and clear the source of the interrupt.
Timer Registers
There are three registers: mode, status, and control. Refer to the Registers section.
Configurations
Default Configuration
When you drag a Timer component onto a PSoC Creator schematic, the default configuration is
an 8-bit, FF timer that decrements the counter register on a rising edge at the clock input.
Figure 1 shows the default schematic macro and Configure dialog settings.
Document Number: 001-73563 Rev. **
Page 19 of 46
Timer
®
PSoC Creator™ Component Datasheet
Figure 1. Default Timer Configuration
The exact functionality of this timer differs for different implementations and different silicon. The
following figures show the functionality of this timer with the UDB implementation and for the FF
implementation on different silicon.
The functionality of the default configuration when configured for the UDB implementation is
shown in Figure 2.
The counter is preloaded during Timer configuration and it is reloaded each time the counter
reaches zero. In the default configuration, the Period is set to 256. This results in 0xFF being
loaded into the counter because counting from 0xFF through 0 yields a period of 256.
The reset signal forces the counter to reload from its period register. The counter is held at this
state until the reset signal is removed.
Terminal count indicates that the timer has counted down to zero. It is active on the clock cycle
that follows the clock cycle where the count value has reached zero. The terminal count signal is
not generated based on a reset event.
By default, the capture functionality is configured to capture on every rising edge of the capture
input. Regardless of the width of the capture pulse, a single value is captured. In this example,
the values 0xFE and 0x01 are captured and can be read by the CPU.
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PSoC Creator™ Component Datasheet
Timer
Figure 2. Default UDB Timer Implementation Example Waveform
The functionality of the default configuration when configured for the fixed-function
implementation on PSoC 3 is shown in Figure 3.
For the fixed-function implementations, the counter value is not preloaded during configuration
time; instead, the counter starts with a value of zero. For PSoC 3 this results in a three-cycle
initial lag time for the FF implementation versus the UDB implementation. This is a two-cycle
delay before the Timer starts counting and one cycle to load the counter from the period register.
After the Timer is running, the period is the same as the UDB implementation.
The reset signal forces the counter to load from the period register and remain at that count until
reset is removed. Once reset is removed, there is a two-cycle lag before the counter begins
counting down.
Terminal count indicates that the timer has counted down to zero. It is active on the clock cycle
that follows the clock cycle where the count value has reached zero. The terminal count signal is
not generated based on a reset event or because of the initial counter value of zero.
By default, the capture functionality is configured to capture on every rising edge of the capture
input. Regardless of the width of the capture pulse, a single value is captured. In this example,
the values 0xFF and 0x01 are captured and can be read by the CPU. This functionality is the
same as the UDB implementation.
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Page 21 of 46
Timer
®
PSoC Creator™ Component Datasheet
Figure 3. Default PSoC 3 FF Timer Implementation Example Waveform
The functionality of the default configuration when configured for the fixed function
implementation on PSoC 5 is shown in Figure 4.
For fixed-function implementations, the counter value is not preloaded during configuration time;
instead, the counter starts with a value of zero. For PSoC 5 this results in a two-cycle initial lag
time for the FF implementation versus the UDB implementation. This is a one-cycle delay before
the Timer starts counting and one cycle to load the counter from the period register. After the
Timer is running, the period is the same as the UDB implementation.
The reset signal forces the counter to clear and it remains at zero until reset is removed. The
functionality after reset looks the same as the functionality from the initial state with the first
period being two cycles longer than the UDB implementation.
Terminal count indicates that the timer has a value of zero. When combined with the initial value
of the counter and the value when reset, this results in a two-cycle TC pulse at initialization and
after a reset. TC is held low while reset is active, but then is high for two cycles after the reset is
removed.
By default, the capture functionality is configured to capture on every rising edge of the capture
input. Regardless of the width of the capture pulse, a single value is captured. In this example,
the values 0xFF and 0x01 are captured and can be read by the CPU. This functionality is the
same as the UDB implementation.
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PSoC Creator™ Component Datasheet
Timer
Figure 4. Default PSoC 5 FF Timer Implementation Example Waveform
Software and Hardware Enable Configuration
The functionality of the hardware enable varies based on the specific implementation. The
functionality of the Timer when configured for Software and Hardware enable with the UDB
implementation is shown in Figure 5.
The counter is decremented on every cycle when the Timer is enabled. During the cycle when
the counter is reloaded from its period register, a single cycle terminal count pulse is generated.
The TC signal will always be a single clock cycle pulse. Note that it occurs during the reload
cycle. If the reload is delayed because the counter was disabled as it hit a zero count, the TC
pulse is also delayed until the counter is re-enabled and the counter is reloaded. If the counter is
forced to reload because of a reset signal, the TC pulse is not generated.
Figure 5. SW and HW Enable UDB Timer Implementation Example Waveform
The functionality of the Timer when configured for Software and Hardware enable with the PSoC
3 FF implementation is shown in Figure 6.
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Timer
®
PSoC Creator™ Component Datasheet
There is a two-clock-cycle lag between the hardware enable and the effective enable of the
counter. The result is that the counter decrements if the enable signal two clock cycles earlier
was high. This lag applies for both enabling and disabling the counter. During the cycle when the
counter is reloaded from its period register, a single-cycle terminal count pulse is generated. The
TC signal is always a single clock cycle pulse.
Note If the Timer has the enable signal low during the two cycles before the counter reaches
zero, the TC output pulse is not generated for this period of the Timer. When the Timer is reenabled it is reloaded without the generation of the TC signal. This is shown in the example
waveform.
Figure 6. SW and HW Enable PSoC 3 FF Timer Implementation Example Waveform
The functionality of the Timer when configured for Software and Hardware enable with the
PSoC 5 FF implementation is shown in Figure 7.
There is a one-clock-cycle lag between the hardware enable and the effective enable of the
counter. The result is that the counter decrements if the enable signal one clock cycle earlier was
high. This lag applies for both enabling and disabling the counter. The terminal count signal is
generated any time that the counter value is equal to zero with a one-clock-cycle lag. This occurs
at initial configuration time. The TC signal stays high if the enable signal causes the Timer to
stop while the counter is equal to zero.
Note The hardware enable signal does not function as expected if the enable is pulsed inactive
for a single cycle. A single-cycle disable pulse locks the Timer at that count until the Timer is
again disabled and then re-enabled. For this reason, a hardware disable must always be for two
or more cycles. A single-cycle enable functions as expected.
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PSoC Creator™ Component Datasheet
Timer
Figure 7. SW and HW Enable PSoC 5 FF Timer Implementation Example Waveform
One Shot Configuration
The functionality of the One Shot Run Mode varies based on the specific implementation. The
functionality of the Timer when configured for One Shot operation with the UDB implementation
is shown in Figure 8.
There is a one-clock-cycle lag between the hardware enable and the effective enable of the
counter. The result is that the counter decrements if the enable signal one clock cycle earlier was
high. This lag applies for both enabling and disabling the counter. This is a different behavior
than in Continuous Run Mode, which counts without lag.
The TC signal is always a single-clock-cycle pulse. Note that it occurs during the reload cycle. If
the reload is delayed because the counter was disabled as it hit a zero count, the TC pulse is
also delayed until the counter is re-enabled and the counter is reloaded. If the counter is forced
to reload because of a reset signal, the TC pulse is not generated.
After the One Shot period has completed, the Timer can be set up to run for another period by
using a hardware reset. The hardware reset reloads the counter from the period register. One
cycle after reset is removed, the Timer is enabled to count down again after the hardware enable
is also active.
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Timer
®
PSoC Creator™ Component Datasheet
Figure 8. One Shot Operation UDB Timer Implementation Example Waveform
The functionality of the Timer when configured for One Shot operation with the FF
implementation on PSoC 3 is shown in Figure 9.
There is a two-clock-cycle lag between the hardware enable and the effective enable of the
counter. The result is that the counter decrements if the enable signal two clock cycles earlier
was high. This lag applies for both enabling and disabling the counter. During the cycle when the
counter is reloaded from its period register, a single-cycle terminal count pulse is generated. The
TC signal is always a single-clock-cycle pulse. This is identical to the operation in Continuous
Run Mode.
An extra feature of the One Shot mode, for this implementation only, is that once the Timer starts
counting, the first time that the enable signal goes low stops the counter at that value. To start
counting again, the Timer must be reset.
After the One Shot period has completed or it has stopped because of the enable signal being
disabled, the Timer can be set up to run for another period by using a hardware reset. The
hardware reset reloads the counter from the period register. There is a two-cycle lag from
releasing reset until the Timer is enabled to count down again.
Note For this implementation, only the Timer can be restarted by using the Timer_Stop() API
followed by the Timer_Start() API. This allows the counter to continue to count, but it doesn’t
reload the counter value, so you should use this method only in the case where the counter has
already completed a period and been reloaded.
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PSoC Creator™ Component Datasheet
Timer
Figure 9. One Shot Operation FF PSoC 3 Timer Implementation Example Waveform
The functionality of the Timer when configured for One Shot operation with the FF
implementation on PSoC 5 is shown in Figure 10.
The terminal count signal is generated any time that the counter value is equal to zero with a
one-clock-cycle lag. This occurs at initial configuration time. The TC signal stays high after a one
shot period has been completed because the counter value stays at the value zero. The one
exception to the generation of the TC signal when the counter is zero is that TC is always held at
zero when the reset signal is active.
Once the One Shot period has completed, the Timer can be set up to run for another period by
using a hardware reset. The hardware reset reloads the counter with zero and configures the
Timer to run again. There is a one-cycle lag from releasing reset until the Timer is enabled to
count down again.
Note One Shot mode with a hardware enable is not supported by the PSoC 5 FF configuration.
Note Because the TC signal is held low when the reset signal is active, two TC pulses are
generated for each time the One Shot is run to completion. The first is when the counter counts
to zero. The second is after the reset is removed, but before the counter has started counting.
This is shown in the example waveform.
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Page 27 of 46
Timer
®
PSoC Creator™ Component Datasheet
Figure 10. One Shot Operation FF PSoC 5 Timer Implementation Example Waveform
UDB FIFOs
The UDB datapath FIFOs are used to capture the counter value. Each FIFO is four bytes deep.
For multi-byte configurations, each byte of the counter is captured simultaneously in the FIFO of
the associated UDB. Therefore, up to four captures can be done before the CPU must read the
capture register to avoid losing data.
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PSoC Creator™ Component Datasheet
Timer
Registers
Status Register
The status register is a read-only register that contains the status bits defined for the Timer. Use
the Timer_ReadStatusRegister() function to read the status register value. All operations on the
status register must use the following defines for the bit fields because these bit fields may be
different between FF and UDB implementations.
Some bits in the status register are sticky, meaning that after they are set to 1, they retain that
state until they are cleared when the register is read. The status data is registered at the input
clock edge of the Timer, which gives all sticky bits the timing resolution of the Timer. All
nonsticky bits are transparent and read directly from the inputs to the status register.
Timer_Status (UDB Implementation)
Bits
7
6
5
4
3
2
1
0
Name
RSVD
RSVD
RSVD
RSVD
FIFO Not
Empty
FIFO Full
Capture
TC
Sticky
N/A
N/A
N/A
N/A
FALSE
FALSE
TRUE
TRUE
Timer_Status (Fixed Function Implementation)
Bits
7
6
5
4
3
2
1
0
Name
TC
Capture
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Sticky
TRUE
TRUE
N/A
N/A
N/A
N/A
N/A
N/A
Bit Name
#define in header file
Description
TC
Timer_STATUS_TC
This bit goes to 1 when the counter value is equal to zero.
Capture
Timer_STATUS_CAPTURE
This bit goes to 1 whenever a valid capture event is triggered.
This does not include software capture.
FIFO Full
Timer_STATUS_FIFOFULL
This bit goes to 1 when the UDB FIFO reaches the full state
defined as four entries.
FIFO Not Empty Timer_STATUS_FIFONEMP
Document Number: 001-73563 Rev. **
This bit goes to 1 when the UDB FIFO contains at least one
entry.
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Timer
PSoC Creator™ Component Datasheet
Mode Register
The mode register is a read/write register that contains the interrupt mask bits defined for the
counter. Use the Timer_SetInterruptMode() function to set the mode bits. All operations on the
mode register must use the following defines for the bit fields because these bit fields may be
different between FF and UDB implementations.
The Timer component interrupt output is an OR function of all interrupt sources. Each source can
be enabled or masked by the corresponding bit in the mode register.
Timer_Mode (UDB Implementation)
Bits
7
6
5
4
3
2
1
0
Name
RSVD
RSVD
RSVD
RSVD
RSVD
FIFO Full
Catpure
TC
Timer_Mode (Fixed-Function Implementation)
Bits
7
6
5
4
3
2
1
0
Name
RSVD
RSVD
RSVD
RSVD
TC
Capture
RSVD
RSVD
Bit Name
#define in header file
Enables Interrupt Output On
TC
Timer_STATUS_TC_INT_MASK
Counter register equals 0
Capture
Timer_STATUS_CAPTURE_INT_MASK
Capture
FIFO Full
Timer_STATUS_FIFOFULL_INT_MASK
UDB FIFO full
Control Register
The Control register allows you to control the general operation of the counter. This register is
written with the Counter_WriteControlRegister() function call and read with the
Counter_ReadControlRegister() function. All operations on the control register must use the
following defines for the bit fields as these bit fields may be different between FF and UDB
implementations.
Note When writing to the control register, you must not change any of the reserved bits. All
operations must be read-modify-write with the reserved bits masked.
Timer_Control (UDB Implementation)
Bits
7
Name
Enable
Page 30 of 46
6
5
Capture Mode [1:0]
4
Trigger
Enable
3
2
Trigger Mode [1:0]
1
0
Interrupt Count [1:0]
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PSoC Creator™ Component Datasheet
Timer
Timer_Control1 (Fixed-Function Implementation)
Bits
7
6
5
4
3
2
1
0
Name
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Enable
Bit Name
#define in header file
Description / Enumerated Type
Interrupt
Count
Timer_CTRL_INTCNT_MASK
The interrupt count bits define the number of capture events to
count before an interrupt is fired.
Trigger
Mode
Timer_CTRL_TRIG_MODE_MASK
The trigger mode control bits define the expected trigger input
functionality. This bit field is configured at initialization with the
trigger mode defined in the Trigger Mode parameter.

Timer__B_TIMER__TM_NONE

Timer__B_TIMER__TM_RISINGEDGE

Timer__B_TIMER__TM_FALLINGEDGE

Timer__B_TIMER__TM_EITHEREDGE

Timer__B_TIMER__TM_SOFTWARE
Trigger
Enable
Timer_CTRL_TRIG_EN
The Trigger Enable bit allows for software control of when to
prepare for a trigger event.
Capture
Mode
Timer_CTRL_CAP_MODE_MASK
The capture mode control bits are a two-bit field used to define
the expected capture input operation. This bit field is configured
at initialization with the capture mode defined in the
Capture Mode parameter.
Enable
Timer_CTRL_ENABLE

Timer__B_TIMER__CM_NONE

Timer__B_TIMER__CM_RISINGEDGE

Timer__B_TIMER__CM_FALLINGEDGE

Timer__B_TIMER__CM_EITHEREDGE

Timer__B_TIMER__CM_SOFTWARE
Enables counting under software control. This bit is valid only if
the Enable Mode parameter is set to Software Only or
Software and Hardware.
Counter (8-, 16-, 24-, or 32-bit Based on Resolution)
The counter register contains the current counter value. This register is decremented in
response to the rising edge of all clock inputs. This register may be read at any time with the
Timer_ReadCounter() function call.
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Timer
PSoC Creator™ Component Datasheet
Capture (8-, 16-, 24-, or 32-bit Based on Resolution)
The capture register contains the captured counter value. Any capture event copies the counter
register to this register. In the UDB implementation, this register is actually a FIFO. See the UDB
FIFOs section for details.
Period (8-, 16-, 24-, or 32-bit Based on Resolution)
The period register contains the period value set with the Timer_WritePeriod() function call and
defined by the Period parameter at initialization. The period register is copied into the counter
register on a reload event.
Component Debug Window
The Timer component supports the PSoC Creator component debug window. The following
registers are displayed in the debug window. Some registers are available in the UDB
implementation (indicated by *) and some registers are only available in the fixed-function
Implementation (indicated by **). All other registers are available for either configuration.
Register:
Timer_CONTROL
Name:
Control Register
Description:
Refer to the Timer_Control register description earlier in this datasheet for bit-field definitions.
Register:
Timer_CONTROL2 **
Name:
Fixed-Function Control Register #2
Description:
The fixed-function Timer block has a second configuration register. Refer to the Technical
Reference Manual for bit field definitions.
Register:
Timer_STATUS_MASK *
Name:
Status Register Interrupt Mask Configuration
Description:
Allows you to enable any status bit as an interrupt source at the interrupt output pin of the
component. Refer to the Timer_Status register description earlier in this datasheet for one-toone correlation of bit-field definitions.
Register:
Timer_STATUS_AUX_CTRL *
Name:
Auxiliary Control Register for the Status Register
Description:
Allows you to enable the interrupt output of the internal status register through the bit field
INT_EN. Refer to the Technical Reference Manual for bit-field definitions.
Page 32 of 46
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PSoC Creator™ Component Datasheet
Timer
Register:
Timer_PERIOD
Name:
Timer Period Register
Description:
Defines the period value reloaded into the period counter at the beginning of each cycle of the
Timer.
Register:
Timer_COUNTER
Name:
Timer Counter Register
Description:
Indicates the current counter value (in clock cycles from Period down to zero) of the current
timer period cycle.
Register:
Timer_GLOBAL_ENABLE **
Name:
Fixed Function Timer Global Enable Register
Description:
Enables the Fixed-Function Timer for operation. Refer to the Technical Reference Manual for
bit-field definitions.
DC and AC Electrical Characteristics (FF Implementation)
The following values indicate expected performance and are based on initial characterization
data.
Timer DC Specifications
Parameter
Description
Min
Typ
Max
–
–
–
A
3 MHz
–
15
–
A
12 MHz
–
60
–
A
48 MHz
–
260
–
A
67 MHz
–
350
–
A
Block current
consumption
Conditions
16-bit timer, at listed input clock
frequency
Units
Timer AC Specifications
Parameter
Description
Min
Typ
Max
Operating frequency
DC
–
67
MHz
Capture pulse width (internal)
15
–
–
ns
Capture pulse width (external)
30
–
–
ns
Timer resolution
15
–
–
ns
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Conditions
Units
Page 33 of 46
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Timer
PSoC Creator™ Component Datasheet
Parameter
Description
Conditions
Min
Typ
Max
Units
Enable pulse width
15
–
–
ns
Enable pulse width (external)
30
–
–
ns
Reset pulse width
15
–
–
ns
Reset pulse width (external)
30
–
–
ns
DC and AC Electrical Characteristics for PSoC 5 (FF
Implementation)
The following values indicate expected performance and are based on initial characterization
data.
Timer DC Specifications
Parameter
Description
Min
Typ
Max
–
–
–
A
3 MHz
–
65
–
A
12 MHz
–
170
–
A
48 MHz
–
650
–
A
67 MHz
–
900
–
A
Block current
consumption
Conditions
16-bit timer, at listed input clock
frequency
Units
Timer AC Specifications
Parameter
Page 34 of 46
Description
Conditions
Min
Typ
Max
Units
Operating frequency
DC
–
67.01
MHz
Capture pulse width (internal)
13
–
–
ns
Capture pulse width (external)
30
–
–
ns
Timer resolution
13
–
–
ns
Enable pulse width
13
–
–
ns
Enable pulse width (external)
30
–
–
ns
Reset pulse width
13
–
–
ns
Reset pulse width (external)
30
–
–
ns
Document Number: 001-73563 Rev. **
®
PSoC Creator™ Component Datasheet
Timer
DC and AC Electrical Characteristics (UDB Implementation)
The following values indicate expected performance and are based on initial characterization
data.
Timing Characteristics “Maximum with Nominal Routing”
Parameter
fCLOCK
Description
Config.
Component clock frequency
tclockH
Input clock high time
tclockL
Input clock low time
4
4
Min
Typ
Max
Units
8-bit UDB Timer
–
–
40
MHz
16-bit UDB Timer
–
–
38
MHz
24-bit UDB Timer
–
–
33
MHz
32-bit UDB Timer
–
–
27
MHz
N/A
–
0.5
–
tCY_clock
N/A
–
0.5
–
tCY_clock
1
–
–
STA
2
–
–
8.5
Inputs
4
tPD_ps
Input path delay, pin to sync
tPD_ps
Input path delay, pin to sync
5
STA
6
ns
ns
6
tPD_si
Sync output to input path
5
delay (route)
1,2,3,4
–
–
ns
tI_clk
Alignment of clockX and clock
1,2,3,4
0
–
1
tCY_clock
tPD_IE
Input path delay to component 1,2
clock (edge-sensitive input)
tPD_ps +
tSYNC +
tPD_si
–
tPD_ps +
tSYNC +
tPD_si +
tI_clk
ns
tPD_IE
Input path delay to component 3,4
clock (edge-sensitive input)
tSYNC +
tPD_si
–
tSYNC +
tPD_si +
tI_clk
ns
tIH
Input high time
1,2,3,4
tCY_clock
–
–
ns
tIL
Input low time
1,2,3,4
tCY_clock
–
–
ns
tCY_clock = 1/fCLOCK. This is the cycle time of one clock period.
5
tPD_ps and tPD_si are route path delays. Because routing is dynamic, these values can change and directly affect the maximum
component clock and sync clock frequencies. The values must be found in the Static Timing Analysis results.
6
tPD_ps in configuration 2 is a fixed value defined per pin of the device. The number listed here is a nominal value of all of the pins
available on the device.
Document Number: 001-73563 Rev. **
Page 35 of 46
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Timer
PSoC Creator™ Component Datasheet
Timing Characteristics “Maximum with All Routing”
Parameter
fCLOCK
Description
Config.
Component clock frequency
tclockH
Input clock high time
tclockL
Input clock low time
8
Max
7
Min
Typ
Units
8-bit UDB Timer
–
–
20
MHz
16-bit UDB Timer
–
–
15
MHz
24-bit UDB Timer
–
–
20
MHz
32-bit UDB Timer
–
–
15
MHz
N/A
–
0.5
–
1/fclock
N/A
–
0.5
–
1/fclock
Inputs
Input path delay, pin to sync
9
1
–
–
STA
ns
tPD_ps
Input path delay, pin to sync
10
2
–
–
8.5
ns
tPD_si
Sync output to input path
9
delay (route)
1,2,3,4
–
–
STA
tI_clk
Alignment of clockX and clock
1,2,3,4
0
–
1
tCY_clock
tPD_IE
Input path delay to component
clock (edge-sensitive input)
1,2
tPD_ps +
tSYNC +
tPD_si
–
tPD_ps +
tSYNC +
tPD_si +
tI_clk
ns
tPD_IE
Input path delay to component
clock (edge-sensitive input)
3,4
tSYNC +
tPD_si
–
tSYNC +
tPD_si +
tI_clk
ns
tIH
Input high time
1,2,3,4
tCY_clock
–
–
ns
tIL
Input low time
1,2,3,4
tCY_clock
–
–
ns
tPD_ps
9
ns
7
The Maximum for All Routing timing numbers are calculated by derating the Nominal Routing timing numbers by a factor of 2. If
your component instance operates at or below these speeds, then meeting timing should not be a concern for this component.
8
tCY_clock = 1/fCLOCK. This is the cycle time of one clock period.
9
tPD_ps and tPD_si are route path delays. Because routing is dynamic, these values can change and directly affect the maximum
component clock and sync clock frequencies. The values must be found in the Static Timing Analysis results.
10
tPD_ps in configuration 2 is a fixed value defined per pin of the device. The number listed here is a nominal value of all of the
pins available on the device.
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PSoC Creator™ Component Datasheet
Timer
How to Use STA Results for Characteristics Data
Nominal route maximums are gathered through multiple test passes with Static Timing Analysis
(STA). You can calculate the maximums for your designs with the STA results using the
following methods:
fCLOCK Maximum component clock frequency appears in Timing results in the clock summary as
the named external clock. The graphic below shows an example of the clock limitations
from the _timing.html:
Input Path Delay and Pulse Width
When characterizing the functionality of inputs, all inputs, no matter how you have configured
them, look like one of four possible configurations, as shown in Figure 11.
All inputs must be synchronized. The synchronization mechanism depends on the source of the
input to the component. To fully interpret how your system will work you must understand which
input configuration you have set up for each input and the clock configuration of your system.
This section describes how to use the Static Timing Analysis (STA) results to determine the
characteristics of your system.
Document Number: 001-73563 Rev. **
Page 37 of 46
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Timer
PSoC Creator™ Component Datasheet
Figure 11. Input Configurations for Component Timing Specifications
Configuration
Component Clock
Synchronizer Clock (Frequency)
Figures
1
master_clock
master_clock
Figure 16
1
clock
master_clock
Figure 14
1
clock
clockX = clock
1
clock
clockX > clock
Figure 13
1
clock
clockX < clock
Figure 15
2
master_clock
master_clock
Figure 16
2
clock
master_clock
Figure 14
3
master_clock
master_clock
Figure 21
11
11
Figure 12
Clock frequencies are equal but alignment of rising edges is not guaranteed.
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PSoC Creator™ Component Datasheet
Configuration
3
Component Clock
clock
Timer
Synchronizer Clock (Frequency)
master_clock
Figures
Figure 19
11
3
clock
clockX = clock
Figure 17
3
clock
clockX > clock
Figure 18
3
clock
clockX < clock
Figure 20
4
master_clock
master_clock
Figure 21
4
clock
clock
Figure 17
1. The input is driven by a device pin and synchronized internally with a “sync” component. This
component is clocked using a different internal clock than the clock the component uses (all
internal clocks are derived from master_clock).
When characterizing inputs configured in this way, clockX may be faster than, equal to, or
slower than the component clock. It may also be equal to master_clock. This produces the
characterization parameters shown in Figure 12, Figure 13, Figure 15, and Figure 16.
2. The input is driven by a device pin and synchronized at the pin using master_clock.
When characterizing inputs configured in this way, master_clock is faster than or equal to the
component clock (it is never slower than). This produces the characterization parameters
shown in Figure 13 and Figure 16.
Figure 12. Input Configuration 1 and 2; Sync Clock Frequency = Component Clock
Frequency (Edge alignment of clock and clockX is not guaranteed)
Document Number: 001-73563 Rev. **
Page 39 of 46
Timer
®
PSoC Creator™ Component Datasheet
Figure 13. Input Configuration 1 and 2; Sync. Clock Frequency > Component Clock
Frequency
Figure 14. Input Configuration 1 and 2; [Sync. Clock Frequency == master_clock] >
Component Clock Frequency
Page 40 of 46
Document Number: 001-73563 Rev. **
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PSoC Creator™ Component Datasheet
Timer
Figure 15. Input Configuration 1; Sync. Clock Frequency < Component Clock Frequency
master_clock
clockX
tsync
clock
tPD_ps
Input @ pin
tPD_si
Input @ sync output
Input @ component
tPD_IE
tIH
tIL
Figure 16. Input Configuration 1 and 2; Sync. Clock = Component Clock = master_clock
3. The input is driven by logic internal to the PSoC, which is synchronous based on a clock
other than the clock the component uses (all internal clocks are derived from master_clock).
When characterizing inputs configured in this way, the synchronizer clock is faster than,
slower than, or equal to the component clock. This produces the characterization parameters
shown in Figure 17, Figure 18, and Figure 20.
4. The input is driven by logic internal to the PSoC, which is synchronous based on the same
clock the component uses.
When characterizing inputs configured in this way, the synchronizer clock is equal to the
component clock. This produces the characterization parameters as shown in Figure 21.
Document Number: 001-73563 Rev. **
Page 41 of 46
Timer
®
PSoC Creator™ Component Datasheet
Figure 17. Input Configuration 3 only; Sync. Clock Frequency = Component Clock
Frequency (Edge alignment of clock and clockX is not guaranteed)
This figure represents the information that Static Timing Analysis has about the clocks. All clocks
in the digital clock domain are synchronous to master_clock. However, it is possible that two
clocks with the same frequency are not rising-edge-aligned. Therefore, the Static Timing
Analysis tool does not know which edge the clocks are synchronous to and must assume the
minimum of one master_clock cycle. This means that t PD_si now has a limiting effect on the
system master_clock. master_clock setup time violations appear if this path delay is too long.
You must change the synchronization clocks of your system or run master_clock at a slower
frequency.
Figure 18. Input Configuration 3; Sync. Clock Frequency > Component Clock Frequency
Page 42 of 46
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PSoC Creator™ Component Datasheet
Timer
In much the same way as shown in Figure 17, all clocks are derived from master_clock. STA
indicates the tPD_si limitations on master_clock for one master_clock cycle in this configuration.
master_clock setup time violations appear if this path delay is too long. You must change the
synchronization clocks of your system or run the master_clock at a slower frequency.
Figure 19. Input Configuration 3; Synchronizer Clock Frequency = master_clock >
Component Clock Frequency
Figure 20. Input Configuration 3; Synchronizer Clock Frequency < Component Clock
Frequency
In much the same way as shown in Figure 17, all clocks are derived from master_clock. STA
indicates the tPD_si limitations on master_clock for one master_clock cycle in this configuration.
master_clock setup time violations appear if this path delay is too long. You must change the
synchronization clocks of your system or run master_clock at a slower frequency.
Document Number: 001-73563 Rev. **
Page 43 of 46
Timer
®
PSoC Creator™ Component Datasheet
Figure 21. Input Configuration 4 only; Synchronizer Clock = Component Clock
In all previous figures in this section, the most critical parameters to use to understand your
implementation are fCLOCK and tPD_IE. tPD_IE is defined by tPD_ps and tsync (for configurations 1 and 2
only), tPD_si, and tI_Clk. It is critical to note that tPD_si defines the maximum component clock
frequency. tI_Clk does not come from the STA results but is used to represent when tPD_IE is
registered. This is the margin left over after the route between the synchronizer and the
component clock.
tPD_ps and tPD_si are included in the STA results.
To find tPD_ps, look at the input setup times defined in the _timing.html file. The fanout of this input
may be more than 1 so you will need to evaluate the maximum of these paths.
tPD_si is defined in the Register-to-register times. You need to know the name of the net to use
the _timing.html file. The fanout of this path may be more than 1 so you will need to evaluate
the maximum of these paths.
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PSoC Creator™ Component Datasheet
Timer
Output Path Delays
When characterizing the path delays of outputs, you must consider where the output is going to
know where you can find the data in the STA results. For this component, all outputs are
synchronized to the component clock. Outputs fall into one of two categories. The output goes
either to another component inside the device, or to a pin to the outside of the device. In the first
case, you must look at the Register-to-register times shown for the Logic-to-input descriptions
just shown (the source clock is the component clock). For the second case, you can look at the
Clock-to-Output times in the _timing.html STA results.
Component Changes
This section lists the major changes in the component from the previous version.
Version
2.20
2.10
2.0
Description of Changes
Reason for Changes / Impact
Verilog change for UDB implementation
To fix a case where the TC output could be missed under
certain conditions when the hardware enable signal was
being used
Document that the interrupt signal is not
available for PSoC 5 FF implementation
This feature was removed because it could not be
supported by the silicon
Customizer updated to make Cancel
button always available
Under some error conditions the Cancel button had not
been available
Extensive datasheet updates
The implementation of the Timer is different for each of the
implementations (UDB, PSoC 3 FF, PSoC 5 FF) and these
differences were not adequately described. Particularly.
see the waveforms provided in the Configurations section
of the Functional Description.
Verilog update and customizer related
updates
To fix a minor issue with Trigger logic and GUI related
issues
"Interrupt on Capture" is disabled when
Capture Mode is set to None
"Interrupt on Capture" check box option was available even
when Capture Mode is set to "None" and should not be
made available
Synchronized inputs
All inputs are synchronized in the fixed-function
implementation, at the input of the block.
Timer_GetInterruptSource() function was
converted to a Macro
The Timer_GetInterruptSource() function is exactly the
same implementation as the Timer_ReadStatusRegister()
function. To save code space this was converted to a
macro substitution of the Timer_ReadStatusRegister()
function.
Outputs are now registered to the
component clock
To avoid glitches on the outputs of the component it is
required that all outputs be synchronized. This is done
inside of the datapath when possible, to avoid excess
resource use.
Document Number: 001-73563 Rev. **
Page 45 of 46
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Timer
PSoC Creator™ Component Datasheet
Version
Description of Changes
Reason for Changes / Impact
Implemented critical regions when writing
to Aux Control registers.
CyEnterCriticalSection and CyExitCriticalSections
functions are used when writing to Aux Control registers so
that it is not modified by any other process thread.
Incorrect masking rectified while setting
capture mode using SetCaptureMode()
API.
Masking used for setting capture mode has erroneous
value.
Added characterization data to datasheet
Minor datasheet edits and updates
© Cypress Semiconductor Corporation, 2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for
use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in lifesupport systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PSoC® is a registered trademark, and PSoC Creator™ and Programmable System-on-Chip™ are trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks
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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in lifesupport systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application
implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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Document Number: 001-73563 Rev. **
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